From: lkcl <lkcl@web>
Date: Fri, 1 Dec 2023 09:00:41 +0000 (+0000)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bada4c9731d40d2fee06d38cc41a0b715c09cb0f;p=libreriscv.git

---

diff --git a/meetings/sync_up/sync_up_2023-12-05.mdwn b/meetings/sync_up/sync_up_2023-12-05.mdwn
index 3fbcffe45..3ac6ffb15 100644
--- a/meetings/sync_up/sync_up_2023-12-05.mdwn
+++ b/meetings/sync_up/sync_up_2023-12-05.mdwn
@@ -13,28 +13,20 @@
 
 Meeting notes:
 
-- Deprecated SimpleV prefix format from 2019: <https://libre-soc.org/simple_v_extension/sv_prefix_proposal/>
-- RISC-V example extension: <https://github.com/riscv-software-src/riscv-isa-sim/blob/master/customext/cflush.cc>
-- The first step is to make modifications to `sv_analysis.py` to classify the RISC-V instructions.
-  <https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/sv/sv_analysis.py;hb=HEAD>
-- Standard RISC-V opcode format: <https://github.com/riscv/riscv-opcodes>
-
-- [bug #980](https://bugs.libre-soc.org/show_bug.cgi?id=980)
-  - A lot of work, need to focus on the basics
-  - Issues with current Python pseudo-code compiler:
-    - pseudocode is full of python-isms such as some variables are
-    python ints and some are selectableint and some are strings etc.
-    - plus, the parser currently has wrong operator precedence
-    [bug #1082](https://bugs.libre-soc.org/show_bug.cgi?id=1082).
-  - Suggested minimal goal for bug #980 is:
-    - Use AST (operands, flow, etc. as we already do for generated
-    Python func's) and a custom visitor function to convert to C code. 
-    - Generate C functions which can be compiled without errors.
-    - Generated functions can be run from a main function to confirm results.
-    - Jacob suggested using `maddedu` as a benchmark, since it has
-    non-trivial pseudo-code.
-    - 
+*
+*
+*
 
+# Luke
+
+* [bug #672](https://bugs.libre-soc.org/show_bug.cgi?id=672)
+  added vggb, noted to shriya to research xbitmanip draft 0.94
+  to add to [[sv/cookbook/pospopcnt/]].
+  fixed a ton of elwidth-related bugs (elwidth overrides in
+  ISACaller were started as a "stub" for Indexed REMAP 8+
+  months ago)
+
+# --- TODO below here ---
 
 # Dmitry
 
@@ -67,21 +59,6 @@ Completed the necessary bits of mmap for ELF task.
 - Check with Dmitry on git commit descriptions (bug #1126).
 Once comment made, add to [[HDL_workflow]] documentation.
 
-# Luke
-
-* [bug #672](https://bugs.libre-soc.org/show_bug.cgi?id=672)
-  long story, pospopcount needs bmatflip (aka vgbbd in VSX)
-  but also needed sv.bc fixing
-  [bug #1215](https://bugs.libre-soc.org/show_bug.cgi?id=1215)
-  which is related/similar to the DDFFirst issue on scalar source/dest
-  [bug #1183](https://bugs.libre-soc.org/show_bug.cgi?id=1183)
-  which jacob also noted for sv.cmpi/ff needed on bigmul.
-* Guide Dmitry on svanalysis.py.
-* Guide Shriya in Poly1305
-  [bug #1157](https://bugs.libre-soc.org/show_bug.cgi?id=1157)
-  and ED25519 [bug #1151](https://bugs.libre-soc.org/show_bug.cgi?id=1151)
-  to assist Sadoon.
-  
 # Shriya
 
 - Work together with Sadoon on Poly1305 and ED25519.