From: lkcl Date: Wed, 25 May 2022 18:46:06 +0000 (+0100) Subject: (no commit message) X-Git-Tag: opf_rfc_ls005_v1~2087 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bae2336043590a661f64d2d8fc8a5a7506d45365;p=libreriscv.git --- diff --git a/openpower/sv/int_fp_mv.mdwn b/openpower/sv/int_fp_mv.mdwn index b09bbd1f3..1548ab066 100644 --- a/openpower/sv/int_fp_mv.mdwn +++ b/openpower/sv/int_fp_mv.mdwn @@ -70,7 +70,7 @@ worst case, is 32 scalar instructions including seven branch instructions. All of the following instructions use the standard OpenPower conversion to/from 64-bit float format when reading/writing a 32-bit float from/to a FPR. All integers however are sourced/stored in the *GPR*. Integer operands and results being in the GPR is the key differentiator between the proposed instructions -(the entire rationale) compated to existing Scalar Power ISA. +(the entire rationale) compared to existing Scalar Power ISA. In all existing Power ISA Scalar conversion instructions, all operands are FPRs, even if the format of the source or destination data is actually a scalar integer.