From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 24 Jan 2020 11:07:33 +0000 (+0000)
Subject: de-modulify PartitionedSignal, call "set_module" to use it
X-Git-Tag: ls180-24jan2020~348
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bae6641e9bdeb9657d18169b1a453dfcd97934d6;p=ieee754fpu.git

de-modulify PartitionedSignal, call "set_module" to use it
---

diff --git a/src/ieee754/part/partsig.py b/src/ieee754/part/partsig.py
index 949bebc2..df7ad7b6 100644
--- a/src/ieee754/part/partsig.py
+++ b/src/ieee754/part/partsig.py
@@ -11,21 +11,20 @@ the class turns into a SIMD variant of Signal.  *this is dynamic*.
 http://bugs.libre-riscv.org/show_bug.cgi?id=132
 """
 
-from nmigen import (Module, Signal, Elaboratable,
-                    )
 from ieee754.part_mul_add.adder import PartitionedAdder
+from nmigen import (Signal,
+                    )
 
-class PartitionedSignal(Elaboratable):
+class PartitionedSignal:
     def __init__(self, partition_points, *args, **kwargs):
         self.partpoints = partition_points
         self.sig = Signal(*args, **kwargs)
         self.modnames = {}
         for name in ['add']:
             self.modnames[name] = 0
-        self.m = Module()
 
-    def elaborate(self, platform):
-        return self.m
+    def set_module(self, m):
+        self.m = m
 
     def get_modname(self, category):
         self.modnames[category] += 1
diff --git a/src/ieee754/part/test/test_partsig.py b/src/ieee754/part/test/test_partsig.py
index cae067dc..36ec0a41 100644
--- a/src/ieee754/part/test/test_partsig.py
+++ b/src/ieee754/part/test/test_partsig.py
@@ -30,8 +30,8 @@ class TestAddMod(Elaboratable):
 
     def elaborate(self, platform):
         m = Module()
-        m.submodules.a = self.a
-        m.submodules.b = self.b
+        self.a.set_module(m)
+        self.b.set_module(m)
         m.d.comb += self.add_output.eq(self.a + self.b)
 
         return m