From: Andreas Krebbel Date: Wed, 4 Oct 2017 16:43:09 +0000 (+0000) Subject: S/390: Fix mode in vector merge pattern. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=baf20d8df23fd33363b997a423d57bb0c3405a38;p=gcc.git S/390: Fix mode in vector merge pattern. vec_unpacks_hi_v4sf/vec_unpacks_lo_v4sf expand vec_mergeh and vec_mergel patterns also for z13 with V4SF modes so the patterns should better accept this. Fixed by changing the mode iterator to V_128_NOSINGLE which accepts V4SF unconditionally. gcc/ChangeLog: 2017-10-04 Andreas Krebbel * config/s390/vx-builtins.md ("vec_mergeh") ("vec_mergel"): Change mode iterator to V_128_NOSINGLE. From-SVN: r253420 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 5167a14788f..d8a9bc1e75b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2017-10-04 Andreas Krebbel + + * config/s390/vx-builtins.md ("vec_mergeh") + ("vec_mergel"): Change mode iterator to V_128_NOSINGLE. + 2017-10-04 Wilco Dijkstra Revert r253399: diff --git a/gcc/config/s390/vx-builtins.md b/gcc/config/s390/vx-builtins.md index 7fb176c2fa4..114935550c3 100644 --- a/gcc/config/s390/vx-builtins.md +++ b/gcc/config/s390/vx-builtins.md @@ -211,9 +211,9 @@ ; (vec_select op0) (vec_select op1) ; vmrhb, vmrhh, vmrhf, vmrhg (define_insn "vec_mergeh" - [(set (match_operand:VEC_HW 0 "register_operand" "=v") - (unspec:VEC_HW [(match_operand:VEC_HW 1 "register_operand" "v") - (match_operand:VEC_HW 2 "register_operand" "v")] + [(set (match_operand:V_128_NOSINGLE 0 "register_operand" "=v") + (unspec:V_128_NOSINGLE [(match_operand:V_128_NOSINGLE 1 "register_operand" "v") + (match_operand:V_128_NOSINGLE 2 "register_operand" "v")] UNSPEC_VEC_MERGEH))] "TARGET_VX" "vmrh\t%v0,%1,%2" @@ -221,9 +221,9 @@ ; vmrlb, vmrlh, vmrlf, vmrlg (define_insn "vec_mergel" - [(set (match_operand:VEC_HW 0 "register_operand" "=v") - (unspec:VEC_HW [(match_operand:VEC_HW 1 "register_operand" "v") - (match_operand:VEC_HW 2 "register_operand" "v")] + [(set (match_operand:V_128_NOSINGLE 0 "register_operand" "=v") + (unspec:V_128_NOSINGLE [(match_operand:V_128_NOSINGLE 1 "register_operand" "v") + (match_operand:V_128_NOSINGLE 2 "register_operand" "v")] UNSPEC_VEC_MERGEL))] "TARGET_VX" "vmrl\t%v0,%1,%2"