From: lkcl Date: Fri, 19 May 2023 23:46:23 +0000 (+0100) Subject: (no commit message) X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bb06550472f034835571654fdd80a76796d1236e;p=libreriscv.git --- diff --git a/openpower/sv/remap.mdwn b/openpower/sv/remap.mdwn index 44ea780e0..ca67cc98d 100644 --- a/openpower/sv/remap.mdwn +++ b/openpower/sv/remap.mdwn @@ -55,12 +55,6 @@ for *possible* latency alone. Commonly-used patterns such as Matrix Multiply, DCT and FFT have helper instruction options which make REMAP easier to use.* -*Future specification note: future versions of the REMAP Management instructions -will extend to EXT1xx Prefixed variants. This will overcome some of the limitations -present in the 32-bit variants of the REMAP Management instructions that at -present require direct writing to SVSHAPE0-3 SPRs. Additional -REMAP Modes may also be introduced at that time.* - There are five types of REMAP: * **Matrix**, also known as 2D and 3D reshaping, can perform in-place @@ -77,7 +71,6 @@ There are five types of REMAP: has several key Computer Science uses. Again Prefix Sum is 100% Deterministic. - Best implemented on top of a Multi-Issue Out-of-Order Micro-architecture, REMAP Schedules are 100% Deterministic **including Indexing** and are designed to be incorporated in between the Decode and Issue phases, @@ -95,6 +88,11 @@ is executed. Further details on the Deterministic Precise-Interruptible algorithms used in these Schedules is found in the [[sv/remap/appendix]]. +*Future specification note: future versions of the REMAP Management instructions +will extend to EXT1xx Prefixed variants. This will overcome some of the limitations +present in the 32-bit variants of the REMAP Management instructions that at +present require direct writing to SVSHAPE0-3 SPRs. Additional +REMAP Modes may also be introduced at that time.* ## Determining Register Hazards (hphint)