From: Andrew Waterman <waterman@s144.Millennium.Berkeley.EDU>
Date: Thu, 19 May 2011 22:27:12 +0000 (-0700)
Subject: [sim] more fp<->int fixes
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bb09521614c9cd88ce01edf0e4a5844fe1778173;p=riscv-isa-sim.git

[sim] more fp<->int fixes
---

diff --git a/riscv/insns/fcvt_d_w.h b/riscv/insns/fcvt_d_w.h
index 638a5ec..52abd75 100644
--- a/riscv/insns/fcvt_d_w.h
+++ b/riscv/insns/fcvt_d_w.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = i32_to_f64(RS1);
+FRD = i32_to_f64((int32_t)RS1);
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_d_wu.h b/riscv/insns/fcvt_d_wu.h
index 2757790..61a8a78 100644
--- a/riscv/insns/fcvt_d_wu.h
+++ b/riscv/insns/fcvt_d_wu.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = ui32_to_f64(RS1);
+FRD = ui32_to_f64((uint32_t)RS1);
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_s_w.h b/riscv/insns/fcvt_s_w.h
index 12b1e73..dedebb5 100644
--- a/riscv/insns/fcvt_s_w.h
+++ b/riscv/insns/fcvt_s_w.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = i32_to_f32(RS1);
+FRD = i32_to_f32((int32_t)RS1);
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_s_wu.h b/riscv/insns/fcvt_s_wu.h
index 4c53c01..abb782c 100644
--- a/riscv/insns/fcvt_s_wu.h
+++ b/riscv/insns/fcvt_s_wu.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = ui32_to_f32(RS1);
+FRD = ui32_to_f32((uint32_t)RS1);
 set_fp_exceptions;