From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 10 Jul 2019 21:38:13 +0000 (-0700)
Subject: Merge pull request #1180 from YosysHQ/eddie/no_abc9_retime
X-Git-Tag: working-ls180~1207
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bb2144ae733f1a2c5e629a8251bfbdcc15559aa4;p=yosys.git

Merge pull request #1180 from YosysHQ/eddie/no_abc9_retime

Error out if -abc9 and -retime specified
---

bb2144ae733f1a2c5e629a8251bfbdcc15559aa4
diff --cc techlibs/xilinx/synth_xilinx.cc
index ef7660288,22c4a1a1b..77daa745c
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@@ -207,11 -195,8 +207,11 @@@ struct SynthXilinxPass : public ScriptP
  		extra_args(args, argidx, design);
  
  		if (family != "xcup" && family != "xcu" && family != "xc7" && family != "xc6s")
- 			log_cmd_error("Invalid Xilinx -family setting: %s\n", family.c_str());
+ 			log_cmd_error("Invalid Xilinx -family setting: '%s'.\n", family.c_str());
  
 +		if (widemux != 0 && widemux < 2)
 +			log_cmd_error("-widemux value must be 0 or >= 2.\n");
 +
  		if (!design->full_selection())
  			log_cmd_error("This command only operates on fully selected designs!\n");