From: Dan Ravensloft <dan.ravensloft@gmail.com>
Date: Sun, 1 Dec 2019 00:07:48 +0000 (+0000)
Subject: vendor.intel: silence meaningless warnings in nMigen files
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bb27f249774130966275785d7d3f855951f62afa;p=nmigen.git

vendor.intel: silence meaningless warnings in nMigen files
---

diff --git a/nmigen/vendor/intel.py b/nmigen/vendor/intel.py
index c65b7c0..bc6e9b4 100644
--- a/nmigen/vendor/intel.py
+++ b/nmigen/vendor/intel.py
@@ -38,6 +38,17 @@ class IntelPlatform(TemplatedPlatform):
     speed   = abstractproperty()
     suffix  = ""
 
+    quartus_suppressed_warnings = [
+        10264,  # All case item expressions in this case statement are onehot
+        10270,  # Incomplete Verilog case statement has no default case item
+        10335,  # Unrecognized synthesis attribute
+        10763,  # Verilog case statement has overlapping case item expressions with non-constant or don't care bits
+        10935,  # Verilog casex/casez overlaps with a previous casex/vasez item expression
+        12125,  # Using design file which is not specified as a design file for the current project, but contains definitions used in project
+        18236,  # Number of processors not specified in QSF
+        292013, # Feature is only available with a valid subscription license
+    ]
+
     required_tools = [
         "quartus_map",
         "quartus_fit",
@@ -100,6 +111,11 @@ class IntelPlatform(TemplatedPlatform):
                 create_clock -period {{1000000000/frequency}} [get_nets {{signal|hierarchy("|")}}]
             {% endfor %}
         """,
+        "{{name}}.srf": r"""
+            {% for warning in platform.quartus_suppressed_warnings %}
+            { "" "" "" "{{name}}.v" {  } {  } 0 {{warning}} "" 0 0 "Design Software" 0 -1 0 ""}
+            {% endfor %}
+        """,      
     }
     command_templates = [
         r"""