From: lkcl <lkcl@web>
Date: Fri, 9 Sep 2022 12:04:46 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~558
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bb47b222815e96f8b1ca23e52a0179f6676a010b;p=libreriscv.git

---

diff --git a/openpower/sv/rfc/ls001/discussion.mdwn b/openpower/sv/rfc/ls001/discussion.mdwn
index 28e09abd6..9cc97f6e5 100644
--- a/openpower/sv/rfc/ls001/discussion.mdwn
+++ b/openpower/sv/rfc/ls001/discussion.mdwn
@@ -5,7 +5,10 @@ discussion on ways to allocate scalar and svp64 opcodes
 # major old/new scalar/vec
 
 following a similar scheme to EXT001 in Power ISA Public v3.1,
-one bit indicates "this is an entire new 32-bit scalar space"
+one bit indicates "this is an entire new 32-bit scalar space".
+although the "penalty" is that any such "escape-sequenced"
+32-bit instructions require a prefix-marker bit, it does effectively
+double the **entirety** of the 32-bit Major Opcode space.
 
 | 0-5 | 6 | 7 | 8-31 | Description               |
 |-----|---|---|------|---------------------------|