From: David Shah <davey1576@gmail.com>
Date: Tue, 19 Feb 2019 19:34:37 +0000 (+0000)
Subject: ecp5: Add DDRDLLA
X-Git-Tag: yosys-0.9~291^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bb56cb738d6586059855cc3deefad12119673157;p=yosys.git

ecp5: Add DDRDLLA

Signed-off-by: David Shah <davey1576@gmail.com>
---

diff --git a/techlibs/ecp5/cells_bb.v b/techlibs/ecp5/cells_bb.v
index bac17260f..223e19b9e 100644
--- a/techlibs/ecp5/cells_bb.v
+++ b/techlibs/ecp5/cells_bb.v
@@ -308,6 +308,15 @@ module DQSBUFM(
 	parameter GSR = "ENABLED";
 endmodule
 
+(* blackbox *)
+module DDRDLLA(
+	input CLK, RST, UDDCNTLN, FREEZE,
+	output LOCK, DDRDEL, DCNTL7, DCNTL6, DCNTL5, DCNTL4, DCNTL3, DCNTL2, DCNTL1, DCNTL0
+);
+	parameter FORCE_MAX_DELAY = "NO";
+	parameter GSR = "ENABLED";
+endmodule
+
 (* blackbox *)
 module CLKDIVF(
 	input CLKI, RST, ALIGNWD,