From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 26 Jun 2020 13:24:51 +0000 (+0100)
Subject: add test of SRAM through wishbone bus
X-Git-Tag: div_pipeline~265
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bb664403fa8d65dbaced112aae901f80399aba99;p=soc.git

add test of SRAM through wishbone bus
---

diff --git a/src/soc/bus/test/test_minerva.py b/src/soc/bus/test/test_minerva.py
index 93ed702c..eeb4a955 100644
--- a/src/soc/bus/test/test_minerva.py
+++ b/src/soc/bus/test/test_minerva.py
@@ -10,9 +10,10 @@ class TestSRAMBareLoadStoreUnit(BareLoadStoreUnit):
     def elaborate(self, platform):
         m = Module()
         comb = m.d.comb
-        m.submodules.mem = memory = Memory(width=addr_wid, depth=16)
+        # small 32-entry Memory
+        memory = Memory(width=self.addr_wid, depth=32)
         m.submodules.sram = sram = SRAM(memory=memory, granularity=8,
-                                        features=set('cti', 'bte', 'err'))
+                                        features={'cti', 'bte', 'err'})
         dbus = self.dbus
 
         # directly connect the wishbone bus of LoadStoreUnitInterface to SRAM
@@ -20,7 +21,8 @@ class TestSRAMBareLoadStoreUnit(BareLoadStoreUnit):
         fanouts = ['adr', 'dat_w', 'sel', 'cyc', 'stb', 'we', 'cti', 'bte']
         fanins = ['dat_r', 'ack', 'err']
         for fanout in fanouts:
-            comb += getattr(sram.bus, fanout).eq(getattr(dbus))
+            comb += getattr(sram.bus, fanout).eq(getattr(dbus, fanout))
         for fanin in fanins:
-            comb += getattr(dbus, fanin).eq(getattr(sram.bus))
+            comb += getattr(dbus, fanin).eq(getattr(sram.bus, fanin))
 
+        return m
diff --git a/src/soc/config/test/test_loadstore.py b/src/soc/config/test/test_loadstore.py
index b0add592..e9bf98a8 100644
--- a/src/soc/config/test/test_loadstore.py
+++ b/src/soc/config/test/test_loadstore.py
@@ -69,11 +69,11 @@ def read_byte(dut, addr):
     return (val >> (offset * 8)) & 0xff
 
 
-if __name__ == '__main__':
+def tst_lsmemtype(ifacetype):
     m = Module()
     Pspec = namedtuple('Pspec', ['ldst_ifacetype',
                                  'addr_wid', 'mask_wid', 'reg_wid'])
-    pspec = Pspec(ldst_ifacetype='testmem', addr_wid=64, mask_wid=3, reg_wid=64)
+    pspec = Pspec(ldst_ifacetype=ifacetype, addr_wid=64, mask_wid=4, reg_wid=64)
     dut = ConfigLoadStoreUnit(pspec).lsi
     m.submodules.dut = dut
 
@@ -98,6 +98,9 @@ if __name__ == '__main__':
             assert x == val
 
     sim.add_sync_process(process)
-    with sim.write_vcd("test_loadstore_tm.vcd", traces=[]):
+    with sim.write_vcd("test_loadstore_%s.vcd" % ifacetype, traces=[]):
         sim.run()
 
+if __name__ == '__main__':
+    tst_lsmemtype('testmem')
+    tst_lsmemtype('test_bare_wb')