From: Jacob Lifshay <programmerjake@gmail.com>
Date: Thu, 4 May 2023 01:04:36 +0000 (-0700)
Subject: fix non-zero assembly operands being zero
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bb7075dc62da85f092fb638c121a7324b605a502;p=openpower-isa.git

fix non-zero assembly operands being zero
---

diff --git a/src/openpower/decoder/isa/test_caller_setvl.py b/src/openpower/decoder/isa/test_caller_setvl.py
index 11c94e2f..163a5afe 100644
--- a/src/openpower/decoder/isa/test_caller_setvl.py
+++ b/src/openpower/decoder/isa/test_caller_setvl.py
@@ -802,7 +802,7 @@ class DecoderTestCase(FHDLTestCase):
         """
         isa = SVP64Asm(["setvl 0, 0, 2, 0, 1, 1",
                         'sv.add *1, *5, *9',
-                        "setvl 3, 0, 0, 0, 0, 0",
+                        "setvl 3, 0, 1, 0, 0, 0",
                         ])
         lst = list(isa)
         print("listing", lst)
@@ -832,7 +832,7 @@ class DecoderTestCase(FHDLTestCase):
                         "setvl. 0, 0, 1, 1, 0, 0",
                         'sv.add *1, *5, *9',
                         "svstep. 3, 1, 0", # svstep (Rc=1)
-                        "setvl 4, 0, 0, 0, 0, 0", # getvl
+                        "setvl 4, 0, 1, 0, 0, 0", # getvl
                         ])
         sequence is as follows:
         * setvl sets VL=2 but also "Vertical First" mode.
@@ -849,7 +849,7 @@ class DecoderTestCase(FHDLTestCase):
                         "svstep. 0, 1, 0",  # svstep (Rc=1)
                         'sv.add *1, *5, *9',
                         "svstep. 3, 1, 0",  # svstep (Rc=1)
-                        "setvl 4, 0, 0, 0, 0, 0",  # getvl
+                        "setvl 4, 0, 1, 0, 0, 0",  # getvl
                         ])
         lst = list(lst)
 
diff --git a/src/openpower/decoder/isa/test_caller_svp64_inssort.py b/src/openpower/decoder/isa/test_caller_svp64_inssort.py
index 454bf09d..86e706bb 100644
--- a/src/openpower/decoder/isa/test_caller_svp64_inssort.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_inssort.py
@@ -206,7 +206,7 @@ class DecoderTestCase(FHDLTestCase):
                         "sv.addi/m=1<<r3 12, *16, 0",  # key item to 12
                         "sv.cmp/ff=lt/m=~r10 *0, 1, *16, 12",
                         "sv.addi/m=ge *16, *17, 0",  # move down
-                        "setvl 3, 0, 0, 0, 0, 0",  # get VL into r3
+                        "setvl 3, 0, 1, 0, 0, 0",  # get VL into r3
                         "addi 3, 3, -1",
                         "setvl 13, 0, 10, 0, 1, 1",  # put VL back from CTR
                         "sv.addi/m=1<<r3 *16, 12, 0",  # restore key
diff --git a/src/openpower/decoder/isa/test_caller_svp64_parallel_reduce.py b/src/openpower/decoder/isa/test_caller_svp64_parallel_reduce.py
index 831a6353..88004682 100644
--- a/src/openpower/decoder/isa/test_caller_svp64_parallel_reduce.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_parallel_reduce.py
@@ -24,13 +24,13 @@ class DecoderTestCase(FHDLTestCase):
             self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
 
     def test_sv_remap1(self):
-        """>>> lst = ["svshape 7, 0, 0, 7, 0",
+        """>>> lst = ["svshape 7, 1, 1, 7, 0",
                         "svremap 31, 0, 1, 0, 0, 0, 0",
                        "sv.add *0, *8, *16"
                         ]
                 REMAP add RT,RA,RB
         """
-        lst = SVP64Asm(["svshape 7, 0, 0, 7, 0",
+        lst = SVP64Asm(["svshape 7, 1, 1, 7, 0",
                         "svremap 31, 0, 1, 0, 0, 0, 0",
                        "sv.add *0, *0, *0"
                         ])
@@ -63,14 +63,14 @@ class DecoderTestCase(FHDLTestCase):
                 self.assertEqual(v, expected[i])
 
     def test_sv_remap2(self):
-        """>>> lst = ["svshape 7, 0, 0, 7, 0",
+        """>>> lst = ["svshape 7, 1, 1, 7, 0",
                         "svremap 31, 1, 0, 0, 0, 0, 0", # different order
                        "sv.subf *0, *8, *16"
                         ]
                 REMAP sv.subf RT,RA,RB - inverted application of RA/RB
                                          left/right due to subf
         """
-        lst = SVP64Asm(["svshape 7, 0, 0, 7, 0",
+        lst = SVP64Asm(["svshape 7, 1, 1, 7, 0",
                         "svremap 31, 1, 0, 0, 0, 0, 0",
                        "sv.subf *0, *0, *0"
                         ])
@@ -104,14 +104,14 @@ class DecoderTestCase(FHDLTestCase):
                                  expected[i] & 0xffffffffffffffff)
 
     def test_sv_remap3(self):
-        """>>> lst = ["svshape 7, 0, 0, 7, 0",
+        """>>> lst = ["svshape 7, 1, 1, 7, 0",
                         "svremap 31, 0, 1, 0, 0, 0, 0",
                        "sv.fcpsgn *0, *8, *16"
                         ]
                 REMAP sv.subf RT,RA,RB - inverted application of RA/RB
                                          left/right due to subf
         """
-        lst = SVP64Asm(["svshape 7, 0, 0, 7, 0",
+        lst = SVP64Asm(["svshape 7, 1, 1, 7, 0",
                         "svremap 31, 0, 1, 0, 0, 0, 0",
                        "sv.fcpsgn *0, *0, *0"
                         ])