From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 16 Feb 2019 09:01:43 +0000 (+0000)
Subject: add normalise_1 function
X-Git-Tag: ls180-24jan2020~1967
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bb86ad410e26c25ab9101a5ba4d4a0004d1cddf5;p=ieee754fpu.git

add normalise_1 function
---

diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py
index 5b648b9a..19ba5a67 100644
--- a/src/add/nmigen_add_experiment.py
+++ b/src/add/nmigen_add_experiment.py
@@ -122,6 +122,18 @@ class FPADD:
         with m.Else():
             m.d.sync += op.ack.eq(1)
 
+    def normalise_1(self, m, z, of, next_state):
+        with m.If((z.m[-1] == 0) & (z.e > z.N126)):
+            m.d.sync +=[
+                z.e.eq(z.e - 1),  # DECREASE exponent
+                z.m.eq(z.m << 1), # shift mantissa UP
+                z.m[0].eq(of.guard),       # steal guard bit (was tot[2])
+                of.guard.eq(of.round_bit), # steal round_bit (was tot[1])
+                of.round_bit.eq(0),        # reset round bit
+            ]
+        with m.Else():
+            m.next = next_state
+
     def get_fragment(self, platform=None):
         m = Module()