From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 22 Jul 2018 05:17:44 +0000 (+0100)
Subject: add quart plic irqs
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bb8cde02db4d4cf8121d4fadc9b1d1939582ef12;p=pinmux.git

add quart plic irqs
---

diff --git a/src/bsv/peripheral_gen.py b/src/bsv/peripheral_gen.py
index 002a625..b75caa9 100644
--- a/src/bsv/peripheral_gen.py
+++ b/src/bsv/peripheral_gen.py
@@ -258,6 +258,27 @@ class quart(PBase):
 
         return '\n'.join(ret)
 
+    def num_irqs(self):
+        return 1
+
+    def plic_object(self, pname, idx):
+        return "{0}_interrupt.read".format(pname)
+
+    def mk_plic(self, inum, irq_offs):
+        name = "{0}{1}".format(self.name, self.mksuffix(self.name, inum))
+        ret = [uart_plic_template.format(name, irq_offs)]
+        (ret2, irq_offs) = PBase.mk_plic(self, inum, irq_offs)
+        ret.append(ret2)
+        return ('\n'.join(ret), irq_offs)
+
+uart_plic_template = """\
+         // PLIC {0} synchronisation with irq {1}
+         SyncBitIfc#(Bit#(1)) {0}_interrupt <-
+                              mkSyncBitToCC(sp_clock, uart_reset);
+         rule plic_synchronize_{0}_interrupt_{1};
+             {0}_interrupt.send({0}.irq);
+         endrule
+"""
 
 class rs232(PBase):