From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 29 Sep 2020 09:32:53 +0000 (+0000)
Subject: add cki and ck to clock settings
X-Git-Tag: partial-core-ls180-gdsii~61
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bba238c4edde927addc7af243e189cdcf032a1dc;p=soclayout.git

add cki and ck to clock settings
---

diff --git a/experiments9/coriolis2/settings.py b/experiments9/coriolis2/settings.py
index 1d24807..e964021 100644
--- a/experiments9/coriolis2/settings.py
+++ b/experiments9/coriolis2/settings.py
@@ -61,7 +61,7 @@ with CfgCache('', priority=Cfg.Parameter.Priority.UserFile) as cfg:
 env = CRL.AllianceFramework.get().getEnvironment()
 #env.setCLOCK ('^sys_clk.*|^sys_rst.*')
 #env.setCLOCK ('^clk$|^rst$|ck|cki')
-env.setCLOCK ('^sys_clk.*')
+env.setCLOCK ('^sys_clk.*|^cki$|^ck$')
 #env.setCLOCK ('clk|ck|cki')
 env.setPOWER ('vdd')
 env.setGROUND('vss')