From: Luke Kenneth Casson Leighton Date: Sun, 14 Oct 2018 05:06:43 +0000 (+0100) Subject: add shiftright X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bbac075f4d35264bb694c89a7e70d70e50200d29;p=riscv-isa-sim.git add shiftright --- diff --git a/riscv/insns/sra.h b/riscv/insns/sra.h index 403b9b7..f3b4df2 100644 --- a/riscv/insns/sra.h +++ b/riscv/insns/sra.h @@ -1 +1 @@ -WRITE_RD(sext_xlen(sext_xlen(RS1) >> (RS2 & (xlen-1)))); +WRITE_RD(sext_xlen(rv_sr(sext_xlen(RS1), (RS2 & (xlen-1))))); diff --git a/riscv/insns/srai.h b/riscv/insns/srai.h index 7ae1d4e..f089b5b 100644 --- a/riscv/insns/srai.h +++ b/riscv/insns/srai.h @@ -1,2 +1,2 @@ require(SHAMT < xlen); -WRITE_RD(sext_xlen(sext_xlen(RS1) >> SHAMT)); +WRITE_RD(sext_xlen(rv_sr(sext_xlen(RS1), SHAMT))); diff --git a/riscv/insns/sraiw.h b/riscv/insns/sraiw.h index b344459..ac9832b 100644 --- a/riscv/insns/sraiw.h +++ b/riscv/insns/sraiw.h @@ -1,2 +1,2 @@ require_rv64; -WRITE_RD(sext32(int32_t(RS1) >> SHAMT)); +WRITE_RD(sext32(rv_sr(int32_t(RS1), SHAMT))); diff --git a/riscv/insns/sraw.h b/riscv/insns/sraw.h index ca9c0c7..b197770 100644 --- a/riscv/insns/sraw.h +++ b/riscv/insns/sraw.h @@ -1,2 +1,2 @@ require_rv64; -WRITE_RD(sext32(int32_t(RS1) >> (RS2 & 0x1F))); +WRITE_RD(sext32(rv_sr(int32_t(RS1), (RS2 & 0x1F)))); diff --git a/riscv/insns/srl.h b/riscv/insns/srl.h index 0dabe9e..c6f92ac 100644 --- a/riscv/insns/srl.h +++ b/riscv/insns/srl.h @@ -1 +1 @@ -WRITE_RD(sext_xlen(zext_xlen(RS1) >> (RS2 & (xlen-1)))); +WRITE_RD(sext_xlen(rv_sr(zext_xlen(RS1), (RS2 & (xlen-1))))); diff --git a/riscv/insns/srli.h b/riscv/insns/srli.h index ea0b40d..fa4d441 100644 --- a/riscv/insns/srli.h +++ b/riscv/insns/srli.h @@ -1,2 +1,2 @@ require(SHAMT < xlen); -WRITE_RD(sext_xlen(zext_xlen(RS1) >> SHAMT)); +WRITE_RD(sext_xlen(rv_sr(zext_xlen(RS1), SHAMT))); diff --git a/riscv/insns/srliw.h b/riscv/insns/srliw.h index c657d3d..d2850e4 100644 --- a/riscv/insns/srliw.h +++ b/riscv/insns/srliw.h @@ -1,2 +1,2 @@ require_rv64; -WRITE_RD(sext32((uint32_t)RS1 >> SHAMT)); +WRITE_RD(sext32(rv_sr((uint32_t)RS1, SHAMT))); diff --git a/riscv/insns/srlw.h b/riscv/insns/srlw.h index a8eb451..45a2494 100644 --- a/riscv/insns/srlw.h +++ b/riscv/insns/srlw.h @@ -1,2 +1,2 @@ require_rv64; -WRITE_RD(sext32((uint32_t)RS1 >> (RS2 & 0x1F))); +WRITE_RD(sext32(rv_sr((uint32_t)RS1, (RS2 & 0x1F)))); diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc index 0cba560..30619dd 100644 --- a/riscv/sv_insn_redirect.cc +++ b/riscv/sv_insn_redirect.cc @@ -272,6 +272,11 @@ reg_t sv_proc_t::rv_sl(reg_t lhs, reg_t rhs) return lhs << rhs; } +reg_t sv_proc_t::rv_sr(reg_t lhs, reg_t rhs) +{ + return lhs >> rhs; +} + reg_t sv_proc_t::rv_lt(reg_t lhs, reg_t rhs) { return lhs < rhs; diff --git a/riscv/sv_insn_redirect.h b/riscv/sv_insn_redirect.h index b32d96f..81a7ee9 100644 --- a/riscv/sv_insn_redirect.h +++ b/riscv/sv_insn_redirect.h @@ -105,6 +105,7 @@ public: reg_t rv_or(reg_t lhs, reg_t rhs); reg_t rv_xor(reg_t lhs, reg_t rhs); reg_t rv_sl(reg_t lhs, reg_t rhs); + reg_t rv_sr(reg_t lhs, reg_t rhs); reg_t rv_lt(reg_t lhs, reg_t rhs); sreg_t rv_lt(sreg_t lhs, sreg_t rhs);