From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 8 Jan 2019 09:06:01 +0000 (+0000)
Subject: add overview to requirements spec
X-Git-Tag: convert-csv-opcode-to-binary~4756
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bbaf58126bf9dececfa11d11fd0ea3f73642c707;p=libreriscv.git

add overview to requirements spec
---

diff --git a/3d_gpu/requirements_specification.mdwn b/3d_gpu/requirements_specification.mdwn
index d37a4249f..9e3506d1d 100644
--- a/3d_gpu/requirements_specification.mdwn
+++ b/3d_gpu/requirements_specification.mdwn
@@ -29,7 +29,8 @@ An overview of the design is as follows:
   file.  The instruction will be scalar and will inherently and
   automatically parallelised by SV, just like all other scalar opcodes.
 * The register files will be stratified into 4-way 2R1W banks,
-  with *separate* and distinct byte-level write-enable lines on all banks.
+  with *separate* and distinct byte-level write-enable lines on all four
+  bytes of all four banks.
 * 6600-style scoreboards will be augmented with "shadow" wires
   and write hazard capability on exceptions, branch speculation,
   LD/ST and predication.