From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 5 Oct 2019 00:39:08 +0000 (-0700)
Subject: Merge remote-tracking branch 'origin/master' into xaig_dff
X-Git-Tag: working-ls180~881^2^2~182
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bbc0e06af3db4da924a3a92ced85adc87cf6abb6;p=yosys.git

Merge remote-tracking branch 'origin/master' into xaig_dff
---

bbc0e06af3db4da924a3a92ced85adc87cf6abb6
diff --cc passes/techmap/abc9.cc
index 0dbe70a68,8932e860a..6c8527811
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@@ -238,15 -243,49 +238,15 @@@ struct abc9_output_filte
  	}
  };
  
 -void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::string script_file, std::string exe_file,
 -		bool cleanup, vector<int> lut_costs, bool dff_mode, std::string clk_str,
 +void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string script_file, std::string exe_file,
 +		bool cleanup, vector<int> lut_costs, bool /*dff_mode*/, std::string /*clk_str*/,
  		bool /*keepff*/, std::string delay_target, std::string /*lutin_shared*/, bool fast_mode,
  		bool show_tempdir, std::string box_file, std::string lut_file,
- 		std::string wire_delay, const dict<int,IdString> &box_lookup
+ 		std::string wire_delay, const dict<int,IdString> &box_lookup, bool nomfs
  )
  {
 -	module = current_module;
  	map_autoidx = autoidx++;
  
 -	if (clk_str != "$")
 -	{
 -		clk_polarity = true;
 -		clk_sig = RTLIL::SigSpec();
 -
 -		en_polarity = true;
 -		en_sig = RTLIL::SigSpec();
 -	}
 -
 -	if (!clk_str.empty() && clk_str != "$")
 -	{
 -		if (clk_str.find(',') != std::string::npos) {
 -			int pos = clk_str.find(',');
 -			std::string en_str = clk_str.substr(pos+1);
 -			clk_str = clk_str.substr(0, pos);
 -			if (en_str[0] == '!') {
 -				en_polarity = false;
 -				en_str = en_str.substr(1);
 -			}
 -			if (module->wires_.count(RTLIL::escape_id(en_str)) != 0)
 -				en_sig = assign_map(RTLIL::SigSpec(module->wires_.at(RTLIL::escape_id(en_str)), 0));
 -		}
 -		if (clk_str[0] == '!') {
 -			clk_polarity = false;
 -			clk_str = clk_str.substr(1);
 -		}
 -		if (module->wires_.count(RTLIL::escape_id(clk_str)) != 0)
 -			clk_sig = assign_map(RTLIL::SigSpec(module->wires_.at(RTLIL::escape_id(clk_str)), 0));
 -	}
 -
 -	if (dff_mode && clk_sig.empty())
 -		log_cmd_error("Clock domain %s not found.\n", clk_str.c_str());
 -
  	std::string tempdir_name = "/tmp/yosys-abc-XXXXXX";
  	if (!cleanup)
  		tempdir_name[0] = tempdir_name[4] = '_';
@@@ -295,29 -334,46 +295,33 @@@
  		log_abort();
  
  	//if (script_file.empty() && !delay_target.empty())
 -	//	for (size_t pos = abc_script.find("dretime;"); pos != std::string::npos; pos = abc_script.find("dretime;", pos+1))
 -	//		abc_script = abc_script.substr(0, pos) + "dretime; retime -o {D};" + abc_script.substr(pos+8);
 +	//	for (size_t pos = abc9_script.find("dretime;"); pos != std::string::npos; pos = abc9_script.find("dretime;", pos+1))
 +	//		abc9_script = abc9_script.substr(0, pos) + "dretime; retime -o {D};" + abc9_script.substr(pos+8);
  
 -	for (size_t pos = abc_script.find("{D}"); pos != std::string::npos; pos = abc_script.find("{D}", pos))
 -		abc_script = abc_script.substr(0, pos) + delay_target + abc_script.substr(pos+3);
 +	for (size_t pos = abc9_script.find("{D}"); pos != std::string::npos; pos = abc9_script.find("{D}", pos))
 +		abc9_script = abc9_script.substr(0, pos) + delay_target + abc9_script.substr(pos+3);
  
 -	//for (size_t pos = abc_script.find("{S}"); pos != std::string::npos; pos = abc_script.find("{S}", pos))
 -	//	abc_script = abc_script.substr(0, pos) + lutin_shared + abc_script.substr(pos+3);
 +	//for (size_t pos = abc9_script.find("{S}"); pos != std::string::npos; pos = abc9_script.find("{S}", pos))
 +	//	abc9_script = abc9_script.substr(0, pos) + lutin_shared + abc9_script.substr(pos+3);
  
 -	for (size_t pos = abc_script.find("{W}"); pos != std::string::npos; pos = abc_script.find("{W}", pos))
 -		abc_script = abc_script.substr(0, pos) + wire_delay + abc_script.substr(pos+3);
 +	for (size_t pos = abc9_script.find("{W}"); pos != std::string::npos; pos = abc9_script.find("{W}", pos))
 +		abc9_script = abc9_script.substr(0, pos) + wire_delay + abc9_script.substr(pos+3);
  
+ 	if (nomfs)
 -		for (size_t pos = abc_script.find("&mfs"); pos != std::string::npos; pos = abc_script.find("&mfs", pos))
 -			abc_script = abc_script.erase(pos, strlen("&mfs"));
 -
++		for (size_t pos = abc9_script.find("&mfs"); pos != std::string::npos; pos = abc9_script.find("&mfs", pos))
++			abc9_script = abc9_script.erase(pos, strlen("&mfs"));
+ 
 -	abc_script += stringf("; &write %s/output.aig", tempdir_name.c_str());
 -	abc_script = add_echos_to_abc_cmd(abc_script);
 +	abc9_script += stringf("; &write %s/output.aig", tempdir_name.c_str());
 +	abc9_script = add_echos_to_abc9_cmd(abc9_script);
  
 -	for (size_t i = 0; i+1 < abc_script.size(); i++)
 -		if (abc_script[i] == ';' && abc_script[i+1] == ' ')
 -			abc_script[i+1] = '\n';
 +	for (size_t i = 0; i+1 < abc9_script.size(); i++)
 +		if (abc9_script[i] == ';' && abc9_script[i+1] == ' ')
 +			abc9_script[i+1] = '\n';
  
  	FILE *f = fopen(stringf("%s/abc.script", tempdir_name.c_str()).c_str(), "wt");
 -	fprintf(f, "%s\n", abc_script.c_str());
 +	fprintf(f, "%s\n", abc9_script.c_str());
  	fclose(f);
  
 -	if (dff_mode || !clk_str.empty())
 -	{
 -		if (clk_sig.size() == 0)
 -			log("No%s clock domain found. Not extracting any FF cells.\n", clk_str.empty() ? "" : " matching");
 -		else {
 -			log("Found%s %s clock domain: %s", clk_str.empty() ? "" : " matching", clk_polarity ? "posedge" : "negedge", log_signal(clk_sig));
 -			if (en_sig.size() != 0)
 -				log(", enabled by %s%s", en_polarity ? "" : "!", log_signal(en_sig));
 -			log("\n");
 -		}
 -	}
 -
  	bool count_output = false;
  	for (auto port_name : module->ports) {
  		RTLIL::Wire *port_wire = module->wire(port_name);
@@@ -866,8 -924,9 +870,9 @@@ struct Abc9Pass : public Pass 
  #endif
  		std::string script_file, clk_str, box_file, lut_file;
  		std::string delay_target, lutin_shared = "-S 1", wire_delay;
 -		bool fast_mode = false, dff_mode = false, keepff = false, cleanup = true;
 +		bool fast_mode = false, /*dff_mode = false,*/ keepff = false, cleanup = true;
  		bool show_tempdir = false;
+ 		bool nomfs = false;
  		vector<int> lut_costs;
  		markgroups = false;
  
@@@ -1232,21 -1276,24 +1241,22 @@@
  
  			log_header(design, "Summary of detected clock domains:\n");
  			for (auto &it : assigned_cells)
 -				log("  %d cells in clk=%s%s, en=%s%s\n", GetSize(it.second),
 -						std::get<0>(it.first) ? "" : "!", log_signal(std::get<1>(it.first)),
 -						std::get<2>(it.first) ? "" : "!", log_signal(std::get<3>(it.first)));
 +				log("  %d cells in clk=%s\n", GetSize(it.second), log_signal(it.first));
  
 +			design->selection_stack.emplace_back(false);
 +			design->selected_active_module = module->name.str();
  			for (auto &it : assigned_cells) {
 -				clk_polarity = std::get<0>(it.first);
 -				clk_sig = assign_map(std::get<1>(it.first));
 -				en_polarity = std::get<2>(it.first);
 -				en_sig = assign_map(std::get<3>(it.first));
 -				abc9_module(design, mod, script_file, exe_file, cleanup, lut_costs, !clk_sig.empty(), "$",
 +				RTLIL::Selection& sel = design->selection_stack.back();
 +				sel.selected_members[module->name] = std::move(it.second);
 +				abc9_module(design, module, script_file, exe_file, cleanup, lut_costs, false, "$",
  						keepff, delay_target, lutin_shared, fast_mode, show_tempdir,
- 						box_file, lut_file, wire_delay, box_lookup);
+ 						box_file, lut_file, wire_delay, box_lookup, nomfs);
+ 				assign_map.set(mod);
  			}
 +			design->selection_stack.pop_back();
 +			design->selected_active_module.clear();
  		}
  
 -		assign_map.clear();
 -
  		log_pop();
  	}
  } Abc9Pass;
diff --cc techlibs/xilinx/synth_xilinx.cc
index caeeb3266,1cddd2a92..6c598acf2
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@@ -477,14 -474,17 +477,18 @@@ struct SynthXilinxPass : public ScriptP
  				run("abc -luts 2:2,3,6:5[,10,20] [-dff]", "(option for 'nowidelut'; option for '-retime')");
  			else if (abc9) {
  				if (family != "xc7")
 -					log_warning("'synth_xilinx -abc9' currently supports '-family xc7' only.\n");
 -				run("techmap -map +/xilinx/abc_map.v -max_iter 1");
 -				run("read_verilog -icells -lib +/xilinx/abc_model.v");
 +					log_warning("'synth_xilinx -abc9' not currently supported for the '%s' family, "
-                             "will use timing for 'xc7' instead.\n", family.c_str());
++							"will use timing for 'xc7' instead.\n", family.c_str());
 +				run("techmap -map +/xilinx/abc9_map.v -max_iter 1");
 +				run("read_verilog -icells -lib +/xilinx/abc9_model.v");
+ 				std::string abc9_opts = " -box +/xilinx/abc_xc7.box";
+ 				abc9_opts += stringf(" -W %d", XC7_WIRE_DELAY);
+ 				abc9_opts += " -nomfs";
  				if (nowidelut)
- 					run("abc9 -lut +/xilinx/abc9_xc7_nowide.lut -box +/xilinx/abc9_xc7.box -W " + std::to_string(XC7_WIRE_DELAY));
+ 					abc9_opts += " -lut +/xilinx/abc_xc7_nowide.lut";
  				else
- 					run("abc9 -lut +/xilinx/abc9_xc7.lut -box +/xilinx/abc9_xc7.box -W " + std::to_string(XC7_WIRE_DELAY));
+ 					abc9_opts += " -lut +/xilinx/abc_xc7.lut";
+ 				run("abc9" + abc9_opts);
  			}
  			else {
  				if (nowidelut)