From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 12 Jul 2018 02:56:28 +0000 (+0100)
Subject: add slids
X-Git-Tag: convert-csv-opcode-to-binary~5057
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bbc68c99a8f0925a5c19e7a3186b4443df0ca973;p=libreriscv.git

add slids
---

diff --git a/shakti/m_class/libre_riscv_chennai_2018.tex b/shakti/m_class/libre_riscv_chennai_2018.tex
index a6edf26d5..c4a56725e 100644
--- a/shakti/m_class/libre_riscv_chennai_2018.tex
+++ b/shakti/m_class/libre_riscv_chennai_2018.tex
@@ -115,7 +115,7 @@
  \begin{itemize}
    \item Cover a lot of different scenarios (embedded, tablets, industrial,
          netbooks, crypto-currency mining).
-	\item Decent performance with high efficiency.  RISC-V: 40 \%
+	\item Decent performance with high efficiency.  RISC-V: 40\%
 		  more efficient than ARM / Intel.  Shakti a good
 	      candidate: 2.5ghz and 120mW per core @ 22nm.
 	\item 1080p video: y'all gotta watch cute kittens on youtube, right?
@@ -281,6 +281,30 @@
 }
 
 
+\frame{\frametitle{Challenging Stuff [4] - Power Management}
+
+ \begin{itemize}
+   \item Been done before, but not as a Libre Design.
+	   \vspace{4pt}
+   \item GPIO Banks need per-bank VREF (1.8v? to 3.3v)\\
+	      IO pads need built-in
+	     level-shifting to convert to CPU VCORE
+	   \vspace{4pt}
+   \item Each core needs independent variable-voltage capability
+	     and independent shut-down (PMIC supplies external voltage)
+	   \vspace{4pt}
+   \item DDR RAM still needs refreshing (even in sleep mode)
+	   \vspace{4pt}
+   \item Extra RV32 (PicoRV32?) always-on core for wake-up / RTC?
+	   \vspace{4pt}
+   \item PLLs are Analog.  fun fun fun in the sun sun sun...
+  \end{itemize}
+   {\it Really need help here.  PLLs, Analog stuff: very specific
+	   domain expertise.  Fall-back: license proprietary HDL.
+   }
+}
+
+
 \frame{\frametitle{TODO}
 
  \begin{itemize}