From: lkcl Date: Sat, 2 Oct 2021 22:22:46 +0000 (+0100) Subject: (no commit message) X-Git-Tag: opf_rfc_ls005_v1~3753 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bbc822e36db1cc2ff095ca7b6579083668640d7c;p=libreriscv.git --- diff --git a/3d_gpu/architecture/dynamic_simd.mdwn b/3d_gpu/architecture/dynamic_simd.mdwn index 49dd74b22..1cf9a37c9 100644 --- a/3d_gpu/architecture/dynamic_simd.mdwn +++ b/3d_gpu/architecture/dynamic_simd.mdwn @@ -132,18 +132,20 @@ Instead a suite of "partition points" identical in fashion to the Aspex Microele Basic principle: when all partition gates are open the ALU is subdivided into isolated and independent 8 bit SIMD ALUs. Whenever any one gate is opened, the relevant 8 bit "part-results" are chained together in a downstream cascade to create 16 bit, 32 bit, 64 bit and 128 bit compound results. -Pages below describe the basic features of each and track the relevant bugreports. +Pages below describe the basic features of each and track the relevant bugreports. These features here are the building blocks which lie behind +PartitionedSignal, which in turn provides "Type 1 (ast.*)" nmigen language +constructs. * [[dynamic_simd/eq]] aka `__eq__` not to be confused with nmigen eq * [[dynamic_simd/assign]] nmigen eq (assignment) -* [[dynamic_simd/gt]] +* [[dynamic_simd/gt]] aka `__gt__` in python operator terms * [[dynamic_simd/add]] * [[dynamic_simd/cat]] - limited capability * [[dynamic_simd/mul]] * [[dynamic_simd/shift]] * [[dynamic_simd/logicops]] some all xor bool -# Integration with nmigen +# Integration with nmigen: "Type 2" (dsl.Module) Dynamic partitioning of signals is not enough on its own. Normal nmigen programs involve conditional decisions, that means if statements and switch statements. @@ -168,7 +170,7 @@ A much more intelligent approach is needed. What we actually want is: with m.If(x > y): # do a partitioned compare here do something dynamic here -where behind the scenes the above laborious for-loops (conceptually) are created, hidden, looking to all intents and purposes that this is exactly like any other nmigen Signal. +where *behind the scenes* the above laborious for-loops (conceptually) are created, hidden, looking to all intents and purposes that this is exactly like any other nmigen Signal. This means one of two things: