From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 9 Jun 2021 19:29:25 +0000 (+0000)
Subject: sys_clk renamed to sys_pllclk, iopads load from copy of auto-generated
X-Git-Tag: LS180_RC3~15
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bbd0787b0f04dbc8078a4ffbfc1c203af1438ed5;p=soclayout.git

sys_clk renamed to sys_pllclk, iopads load from copy of auto-generated
pinouts in json format
---

diff --git a/experiments9/doDesign.py b/experiments9/doDesign.py
index 01866e5..33db850 100644
--- a/experiments9/doDesign.py
+++ b/experiments9/doDesign.py
@@ -28,7 +28,7 @@ def scriptMain (**kw):
     coreSize = 65000 
     cwd = os.path.split( os.path.abspath(__file__) )[0]
     ioSpecs = IoSpecs()
-    ioSpecs.loadFromPinmux( '{}/ls180/litex_pinpads.json'.format(cwd) )
+    ioSpecs.loadFromPinmux( '%s/ls180/litex_pinpads.json' % cwd )
     try:
         #helpers.setTraceLevel( 550 )
         cell, editor = plugins.kwParseMain( **kw )
diff --git a/experiments9/tsmc_c018/coriolis2/settings.py b/experiments9/tsmc_c018/coriolis2/settings.py
index 3672a32..e06b66b 100644
--- a/experiments9/tsmc_c018/coriolis2/settings.py
+++ b/experiments9/tsmc_c018/coriolis2/settings.py
@@ -131,7 +131,7 @@ with overlay.CfgCache(priority=Cfg.Parameter.Priority.UserFile) as cfg:
     cfg.etesian.spaceMargin      = 0.10
     cfg.katana.eventsLimit       = 4000000
     env = af.getEnvironment()
-    env.setCLOCK( '^sys_clk$|^ck|^jtag_tck$' )
+    env.setCLOCK( '^sys_pllclk$|^ck|^jtag_tck$' )
 
 #with overlay.UpdateSession():
 #    createSramBlackbox()
diff --git a/experiments9/tsmc_c018/doDesign.py b/experiments9/tsmc_c018/doDesign.py
index 30206b6..a48b14f 100644
--- a/experiments9/tsmc_c018/doDesign.py
+++ b/experiments9/tsmc_c018/doDesign.py
@@ -137,11 +137,20 @@ def scriptMain (**kw):
     coreSizeY  = u(56*90.0)
     chipBorder = u(2*214.0 + 8*13.0)
     ioSpecs    = IoSpecs()
-   #pinmuxFile = './non_generated/litex_pinpads.json'
-   #pinmuxFile = './coriolis2/ls180/litex_pinpads.json'
-   #ioSpecs.loadFromPinmux( pinmuxFile )
 
-   # I/O pads, East side.
+    # this should work fine, tested on nsxlib
+    cwd = os.path.split(os.path.abspath(__file__))[0]
+    pinmuxFile = '%s/non_generated/litex_pinpads.json' % cwd
+    # actual contents auto-generated and listed at:
+    # http://libre-soc.org/180nm_Oct2020/ls180/
+    ioSpecs.loadFromPinmux( pinmuxFile )
+
+    # XXX ioPadsSpec created but not used.  saves time, saves errors. see
+    # wiki page for contents: http://libre-soc.org/180nm_Oct2020/ls180/
+    # if *not* using the auto-generated ioSpecs, ioPadsSpec should, really,
+    # be made exactly the same. which is more work.
+
+    # I/O pads, East side.
     ioPadsSpec  = []
     ioPadsSpec += doIoPowerCap( IoPin.EAST|IoPin.A_BEGIN )
     ioPadsSpec += [ (IoPin.EAST, None, 'sdram_cas_n'   , 'sdram_cas_n'   , 'sdram_cas_n' )
@@ -204,8 +213,11 @@ def scriptMain (**kw):
                                     .format('ls180') ))
             sys.exit(1)
         if editor: editor.setCell( cell )
-       #ls180Conf = ChipConf( cell, ioPads=ioSpecs.ioPadsSpec )
-        ls180Conf = ChipConf( cell, ioPads=ioPadsSpec )
+        # use auto-generated (but from non_generated) io pads specs
+        # works fine with soclayout nsxlib, should work perfectly fine
+        # here, too
+        ls180Conf = ChipConf( cell, ioPads=ioSpecs.ioPadsSpec )
+        #ls180Conf = ChipConf( cell, ioPads=ioPadsSpec )
         ls180Conf.cfg.etesian.bloat = 'Flexlib'
         ls180Conf.cfg.etesian.uniformDensity = True
         ls180Conf.cfg.etesian.aspectRatio = 1.0