From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 16 Jun 2021 18:58:37 +0000 (+0100)
Subject: fix fmadds/fmsubs FPMULADD32 helper
X-Git-Tag: xlen-bcd~440
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bbdc657083b9ae012bcf1bd933dcaeee19b75111;p=openpower-isa.git

fix fmadds/fmsubs FPMULADD32 helper
---

diff --git a/src/openpower/decoder/helpers.py b/src/openpower/decoder/helpers.py
index 8b849fb8..134ef84a 100644
--- a/src/openpower/decoder/helpers.py
+++ b/src/openpower/decoder/helpers.py
@@ -295,15 +295,17 @@ def FPMULADD32(FRA, FRC, FRB, addsign, mulsign):
     #FRA = DOUBLE(SINGLE(FRA))
     #FRB = DOUBLE(SINGLE(FRB))
     if addsign == 1:
-        result = float(FRB)
+        if mulsign == 1:
+            result = float(FRA) * float(FRC) + float(FRB) # fmadds
+        elif mulsign == -1:
+            result = -(float(FRA) * float(FRC) + float(FRB))  # fnmadds
     elif addsign == -1:
-        result = -float(FRB)
+        if mulsign == 1:
+            result = float(FRA) * float(FRC) - float(FRB) # fmsubs
+        elif mulsign == -1:
+            result = -(float(FRA) * float(FRC) - float(FRB))  # fnmsubs
     elif addsign == 0:
         result = 0.0
-    if mulsign == 1:
-        result += float(FRA) * float(FRC)
-    elif mulsign == -1:
-        result -= float(FRA) * float(FRC)
     log ("FPMULADD32", FRA, FRB, FRC,
                        float(FRA), float(FRB), float(FRC),
                        result)