From: Xing GUO <higuoxing@gmail.com>
Date: Mon, 1 Feb 2021 09:33:47 +0000 (+0800)
Subject: RISC-V: Fix gcc.target/riscv/attribute-18.c
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bbe6998b227013899b001d336a0ba4de94d8d239;p=gcc.git

RISC-V: Fix gcc.target/riscv/attribute-18.c

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/attribute-18.c: Add -mriscv-attribute option.
---

diff --git a/gcc/testsuite/gcc.target/riscv/attribute-18.c b/gcc/testsuite/gcc.target/riscv/attribute-18.c
index 1fd80fed51b..492360cf7c1 100644
--- a/gcc/testsuite/gcc.target/riscv/attribute-18.c
+++ b/gcc/testsuite/gcc.target/riscv/attribute-18.c
@@ -1,4 +1,4 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64imafdcp -mabi=lp64d -misa-spec=2.2" } */
+/* { dg-options "-mriscv-attribute -march=rv64imafdcp -mabi=lp64d -misa-spec=2.2" } */
 int foo() {}
 /* { dg-final { scan-assembler ".attribute arch, \"rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_p\"" } } */