From: lkcl <lkcl@web>
Date: Sun, 3 Jul 2022 09:51:15 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1397
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bbfda4c6eed92921190abd5e37d8694cf4f9a658;p=libreriscv.git

---

diff --git a/openpower/sv/setvl.mdwn b/openpower/sv/setvl.mdwn
index 2158d8dab..d6f9eadbb 100644
--- a/openpower/sv/setvl.mdwn
+++ b/openpower/sv/setvl.mdwn
@@ -167,13 +167,18 @@ loops reach an end condition, or if VL has been reached. The immediate can
 be reinterpreted as indicating which SVSTATE (0-3)
 should be tested and placed into CR0.
 
-* setvl immediate = 1: only VL testing is enabled. CR0.SO is set
+TODO clarify/investigate
+
+* `SVi=1`: only VL testing is enabled. CR0.SO is set
   to 1 when either srcstep or dststep reach VL
-* setvl immediate = 2: also include inner middle and outer
+* `SVi=2`: also include inner middle and outer
   loop end conditions from SVSTATE0 into CR.EQ CR.LE CR.GT
-* setvl immediate = 3: test SVSTATE1
-* setvl immediate = 4: test SVSTATE2
-* setvl immediate = 5: test SVSTATE3
+* `SVi=3`: test SVSTATE1
+* `SVi=4`: test SVSTATE2
+* `SVi=5`: test SVSTATE3
+* When `SVi` is 6, `SVSTATE.srcstep` is returned.
+* When `SVi` is 7, `SVSTATE.dststep` is returned.
+
 
 Testing any end condition of any loop of any REMAP state allows branches to be used to create loops.