From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 19 Jun 2022 13:55:20 +0000 (+0100)
Subject: spelling
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bc00fd0179194c04d95b43365cc4adb54d9fb511;p=libreriscv.git

spelling
---

diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index 35d1502cc..02f78aecb 100644
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -19,7 +19,7 @@ and in GPUs, but keeps strictly to a *Simple* RISC principle of leveraging
 a *Scalar* ISA, exclusively using "Prefixing". **Not one single actual
 explicit Vector opcode exists in SV, at all**.  It is suitable for
 low-power Embedded and DSP Workloads as much as it is for power-efficient
-Suoercomputing.
+Supercomputing.
 
 Fundamental design principles: