From: Dmitry Selyutin <ghostmansd@gmail.com>
Date: Sat, 3 Sep 2022 11:08:47 +0000 (+0300)
Subject: power_insn: decouple IMM/IDX LD/ST modes
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bc3b58b501de05af146ed53ccef6a2b962a2aae3;p=openpower-isa.git

power_insn: decouple IMM/IDX LD/ST modes
---

diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py
index da843aa2..2f490c17 100644
--- a/src/openpower/decoder/power_insn.py
+++ b/src/openpower/decoder/power_insn.py
@@ -809,106 +809,104 @@ class NormalMode(Mode):
     prrc0: prrc0
 
 
-class LDSTMode(Mode):
-    class imm(Mode):
-        class normal(Mode):
-            """normal mode"""
-            zz: Mode[3]
-            els: Mode[4]
-            dz: Mode[3]
-            sz: Mode[3]
-
-        class spu(Mode):
-            """Structured Pack/Unpack"""
-            zz: Mode[3]
-            els: Mode[4]
-            dz: Mode[3]
-            sz: Mode[3]
-
-        class ffrc1(Mode):
-            """Rc=1: ffirst CR sel"""
-            inv: Mode[2]
-            CRbit: Mode[3, 4]
-
-        class ffrc0(Mode):
-            """Rc=0: ffirst z/nonz"""
-            inv: Mode[2]
-            els: Mode[3]
-            RC1: Mode[4]
-
-        class sat(Mode):
-            """sat mode: N=0/1 u/s"""
-            N: Mode[2]
-            zz: Mode[3]
-            els: Mode[4]
-            dz: Mode[3]
-            sz: Mode[3]
-
-        class prrc1(Mode):
-            """Rc=1: pred-result CR sel"""
-            inv: Mode[2]
-            CRbit: Mode[3, 4]
-
-        class prrc0(Mode):
-            """Rc=0: pred-result z/nonz"""
-            inv: Mode[2]
-            els: Mode[3]
-            RC1: Mode[4]
-
-        normal: normal
-        spu: spu
-        ffrc1: ffrc1
-        ffrc0: ffrc0
-        sat: sat
-        prrc1: prrc1
-        prrc0: prrc0
-
-    class idx(Mode):
-        class normal(Mode):
-            """normal mode"""
-            SEA: Mode[2]
-            sz: Mode[3]
-            dz: Mode[3]
-
-        class stride(Mode):
-            """strided (scalar only source)"""
-            SEA: Mode[2]
-            dz: Mode[3]
-            sz: Mode[4]
-
-        class sat(Mode):
-            """sat mode: N=0/1 u/s"""
-            N: Mode[2]
-            dz: Mode[3]
-            sz: Mode[4]
-
-        class prrc1(Mode):
-            """Rc=1: pred-result CR sel"""
-            inv: Mode[2]
-            CRbit: Mode[3, 4]
-
-        class prrc0(Mode):
-            """Rc=0: pred-result z/nonz"""
-            inv: Mode[2]
-            zz: Mode[3]
-            RC1: Mode[4]
-            dz: Mode[3]
-            sz: Mode[3]
-
-        normal: normal
-        stride: stride
-        sat: sat
-        prrc1: prrc1
-        prrc0: prrc0
-
-    imm: imm
-    idx: idx
+class LDSTImmMode(Mode):
+    class normal(Mode):
+        """normal mode"""
+        zz: Mode[3]
+        els: Mode[4]
+        dz: Mode[3]
+        sz: Mode[3]
+
+    class spu(Mode):
+        """Structured Pack/Unpack"""
+        zz: Mode[3]
+        els: Mode[4]
+        dz: Mode[3]
+        sz: Mode[3]
+
+    class ffrc1(Mode):
+        """Rc=1: ffirst CR sel"""
+        inv: Mode[2]
+        CRbit: Mode[3, 4]
+
+    class ffrc0(Mode):
+        """Rc=0: ffirst z/nonz"""
+        inv: Mode[2]
+        els: Mode[3]
+        RC1: Mode[4]
+
+    class sat(Mode):
+        """sat mode: N=0/1 u/s"""
+        N: Mode[2]
+        zz: Mode[3]
+        els: Mode[4]
+        dz: Mode[3]
+        sz: Mode[3]
+
+    class prrc1(Mode):
+        """Rc=1: pred-result CR sel"""
+        inv: Mode[2]
+        CRbit: Mode[3, 4]
+
+    class prrc0(Mode):
+        """Rc=0: pred-result z/nonz"""
+        inv: Mode[2]
+        els: Mode[3]
+        RC1: Mode[4]
+
+    normal: normal
+    spu: spu
+    ffrc1: ffrc1
+    ffrc0: ffrc0
+    sat: sat
+    prrc1: prrc1
+    prrc0: prrc0
+
+
+class LDSTIdxMode(Mode):
+    class normal(Mode):
+        """normal mode"""
+        SEA: Mode[2]
+        sz: Mode[3]
+        dz: Mode[3]
+
+    class stride(Mode):
+        """strided (scalar only source)"""
+        SEA: Mode[2]
+        dz: Mode[3]
+        sz: Mode[4]
+
+    class sat(Mode):
+        """sat mode: N=0/1 u/s"""
+        N: Mode[2]
+        dz: Mode[3]
+        sz: Mode[4]
+
+    class prrc1(Mode):
+        """Rc=1: pred-result CR sel"""
+        inv: Mode[2]
+        CRbit: Mode[3, 4]
+
+    class prrc0(Mode):
+        """Rc=0: pred-result z/nonz"""
+        inv: Mode[2]
+        zz: Mode[3]
+        RC1: Mode[4]
+        dz: Mode[3]
+        sz: Mode[3]
+
+    normal: normal
+    stride: stride
+    sat: sat
+    prrc1: prrc1
+    prrc0: prrc0
 
 
 class RM(_Mapping):
     class Mode(Mode):
         normal: NormalMode
-        ldst: LDSTMode
+        ldst_imm: LDSTImmMode
+        ldst_idx: LDSTIdxMode
 
     _: _Field = range(24)
     mmode: _Field = (0,)