From: Gabe Black <gblack@eecs.umich.edu>
Date: Fri, 22 Oct 2010 07:22:59 +0000 (-0700)
Subject: ARM: Don't pretend to writeback registers in initiateAcc.
X-Git-Tag: stable_2012_02_02~784
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bc49381287698297446da3e6f7b43b8ef4f43b27;p=gem5.git

ARM: Don't pretend to writeback registers in initiateAcc.
---

diff --git a/src/arch/arm/isa/templates/mem.isa b/src/arch/arm/isa/templates/mem.isa
index 1d0e1316c..ced7a0037 100644
--- a/src/arch/arm/isa/templates/mem.isa
+++ b/src/arch/arm/isa/templates/mem.isa
@@ -131,10 +131,6 @@ def template SwapInitiateAcc {{
                 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
                                   memAccessFlags, &memData);
             }
-
-            if (fault == NoFault) {
-                %(op_wb)s;
-            }
         } else {
             xc->setPredicate(false);
         }
@@ -393,11 +389,6 @@ def template StoreExInitiateAcc {{
                 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
                                   memAccessFlags, NULL);
             }
-
-            // Need to write back any potential address register update
-            if (fault == NoFault) {
-                %(op_wb)s;
-            }
         } else {
             xc->setPredicate(false);
         }
@@ -431,11 +422,6 @@ def template StoreInitiateAcc {{
                 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
                                   memAccessFlags, NULL);
             }
-
-            // Need to write back any potential address register update
-            if (fault == NoFault) {
-                %(op_wb)s;
-            }
         } else {
             xc->setPredicate(false);
         }
@@ -473,11 +459,6 @@ def template NeonStoreInitiateAcc {{
                 fault = xc->writeBytes(memUnion.bytes, %(size)d, EA,
                                        memAccessFlags, NULL);
             }
-
-            // Need to write back any potential address register update
-            if (fault == NoFault) {
-                %(op_wb)s;
-            }
         }
 
         if (fault == NoFault && machInst.itstateMask != 0 &&