From: lkcl <lkcl@web>
Date: Wed, 17 Mar 2021 20:50:11 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~4
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bc4f40288de20a02e1b37db16396ef39374a4c93;p=libreriscv.git

---

diff --git a/openpower/sv/implementation.mdwn b/openpower/sv/implementation.mdwn
index 38b917b1e..aff1ad04f 100644
--- a/openpower/sv/implementation.mdwn
+++ b/openpower/sv/implementation.mdwn
@@ -21,7 +21,7 @@ Links:
  (instruction form SVL-Form, field designations, pseudocode, SPR allocation)
 * <https://bugs.libre-soc.org/show_bug.cgi?id=615> agree sv assembly syntax
 * <https://bugs.libre-soc.org/show_bug.cgi?id=617> TestIssuer add single/twin Predication
-* <https://bugs.libre-soc.org/show_bug.cgi?id=617> ISACaller add single/twin Predication
+* <https://bugs.libre-soc.org/show_bug.cgi?id=618> ISACaller add single/twin Predication
 
 # Code to convert
 
@@ -188,10 +188,19 @@ At the same time the `Rc=1` CR offsets normslly CR0 and CR1 for fixed and FP sca
 
 ## Single and Twin Predication
 
-both CR and INT predication is needed
+both CR and INT predication is needed, as well as zeroing in both
+
+* INT-based single: TODO
+* CR-based single:  TODO
+* INT-based twin:   TODO
+* CR-based twin:    TODO
+* Zeroing single:   TODO
+* Zeroing twin:     TODO
+
+Progress:
 
 * TestIssuer <https://bugs.libre-soc.org/show_bug.cgi?id=617> 
-* ISACaller <https://bugs.libre-soc.org/show_bug.cgi?id=617>
+* ISACaller <https://bugs.libre-soc.org/show_bug.cgi?id=618>
 * power-gem5: TODO
 * Microwatt: TODO