From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 4 Jun 2020 18:54:36 +0000 (+0100)
Subject: add docstrings for read/write port connection
X-Git-Tag: div_pipeline~586
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bc5b63fd5ed5d2e8956a78933572097e7e7000d7;p=soc.git

add docstrings for read/write port connection
---

diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index 3846a57e..35becb01 100644
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -90,6 +90,11 @@ class NonProductionCore(Elaboratable):
         return fu_bitdict
 
     def connect_rdports(self, m, fu_bitdict):
+    """connect read ports
+
+    orders the read regspecs into a dict-of-dicts, by regfile, by regport name,
+    then connects all FUs that want that regport by way of a PriorityPicker.
+    """
         comb, sync = m.d.comb, m.d.sync
         fus = self.fus.fus
         regs = self.regs
@@ -149,6 +154,15 @@ class NonProductionCore(Elaboratable):
                     comb += src.eq(rport.data_o) # all FUs connect to same port
 
     def connect_wrports(self, m, fu_bitdict):
+    """connect write ports
+
+    orders the write regspecs into a dict-of-dicts, by regfile, by regport name,
+    then connects all FUs that want that regport by way of a PriorityPicker.
+
+    note that the write-port wen, write-port data, and go_wr_i all need to
+    be on the exact same clock cycle.  as there is a combinatorial loop bug
+    at the moment, these all use sync.
+    """
         comb, sync = m.d.comb, m.d.sync
         fus = self.fus.fus
         regs = self.regs