From: Jacob Lifshay <programmerjake@gmail.com>
Date: Wed, 27 Jul 2022 17:54:23 +0000 (-0700)
Subject: add another test and fix broken fishmv pseudocode
X-Git-Tag: sv_maxu_works-initial~210
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bc5f9cfaa3e3c25bbe11050f04d0556f114ded30;p=openpower-isa.git

add another test and fix broken fishmv pseudocode
---

diff --git a/openpower/isa/av.mdwn b/openpower/isa/av.mdwn
index 1347adcc..ffbb7e7f 100644
--- a/openpower/isa/av.mdwn
+++ b/openpower/isa/av.mdwn
@@ -230,10 +230,9 @@ DX-Form
 
 Pseudo-code:
 
-    LH   <- FRS[0:15]
-    fp32 <- LH || d0 || d1 || d2
-    n    <- DOUBLE(fp32)
-    FRS  <- LH || n[16:63]
+    fp32 <- SINGLE((FRS))
+    fp32[16:31] <- d0 || d1 || d2
+    FRS <- DOUBLE(fp32)
 
 Special Registers Altered:
 
diff --git a/openpower/isatables/RM-2P-1S1D.csv b/openpower/isatables/RM-2P-1S1D.csv
index 31d93e24..29e10d54 100644
--- a/openpower/isatables/RM-2P-1S1D.csv
+++ b/openpower/isatables/RM-2P-1S1D.csv
@@ -27,6 +27,7 @@ oris,NORMAL,,2P,EXTRA3,d:RA,s:RS,0,0,RS,0,0,RA,0,0,0
 xori,NORMAL,,2P,EXTRA3,d:RA,s:RS,0,0,RS,0,0,RA,0,0,0
 xoris,NORMAL,,2P,EXTRA3,d:RA,s:RS,0,0,RS,0,0,RA,0,0,0
 subfic,NORMAL,,2P,EXTRA3,d:RT,s:RA,0,0,RA,0,0,RT,0,0,0
+fishmv,NORMAL,,2P,EXTRA3,TODO,0,0,0,FRS,0,0,FRS,0,0,0
 cntlzw,NORMAL,,2P,EXTRA3,d:RA;d:CR0,s:RS,0,0,RS,0,0,RA,0,CR0,0
 cntlzd,NORMAL,,2P,EXTRA3,d:RA;d:CR0,s:RS,0,0,RS,0,0,RA,0,CR0,0
 subfze,NORMAL,,2P,EXTRA3,d:RT;d:CR0,s:RA,0,0,RA,0,0,RT,0,CR0,0
diff --git a/src/openpower/test/alu/fmvis_cases.py b/src/openpower/test/alu/fmvis_cases.py
index de03d8b7..4689c26f 100644
--- a/src/openpower/test/alu/fmvis_cases.py
+++ b/src/openpower/test/alu/fmvis_cases.py
@@ -37,6 +37,8 @@ class FMVISTestCase(TestAccumulatorBase):
                         "fishmv 4, 0x4000",  # 2nd half of 1.00195 in FP32 form
                         "fmvis  5, 0xC049",  # 1st half of -3.14159 in FP32 form
                         "fishmv 5, 0x0FD0",  # 2nd half of -3.14159 in FP32 form
+                        "fmvis  6, 0x89AB",  # 1st half of 0x89ABCDEF in FP32 form
+                        "fishmv 6, 0xCDEF",  # 2nd half of 0x89ABCDEF in FP32 form
                        ])
         lst = list(lst)
 
@@ -44,5 +46,6 @@ class FMVISTestCase(TestAccumulatorBase):
         expected_fprs[3] = 0x400921fa00000000 # 3.14159 in FP64 form
         expected_fprs[4] = 0x3ff0080000000000 # 1.00195 in FP64 form
         expected_fprs[5] = 0xC00921fa00000000 # -3.14159 in FP64 form
-        e = ExpectedState(pc=0x18, fp_regs=expected_fprs)
+        expected_fprs[6] = 0xB93579BDE0000000 # converted value in FP64 form
+        e = ExpectedState(pc=0x20, fp_regs=expected_fprs)
         self.add_case(Program(lst, bigendian), expected=e)