From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 14 Feb 2020 18:31:38 +0000 (-0800)
Subject: Fix tests/arch/xilinx/fsm.ys to count flops only
X-Git-Tag: working-ls180~780^2~23
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bc97e64b211ea4ff99afde7cd1f130b1b3261848;p=yosys.git

Fix tests/arch/xilinx/fsm.ys to count flops only
---

diff --git a/tests/arch/xilinx/fsm.ys b/tests/arch/xilinx/fsm.ys
index fec4c6082..70c05f2c0 100644
--- a/tests/arch/xilinx/fsm.ys
+++ b/tests/arch/xilinx/fsm.ys
@@ -15,10 +15,7 @@ stat
 select -assert-count 1 t:BUFG
 select -assert-count 4 t:FDRE
 select -assert-count 1 t:FDSE
-select -assert-count 1 t:LUT2
-select -assert-count 3 t:LUT5
-select -assert-count 1 t:LUT6
-select -assert-none t:BUFG t:FDRE t:FDSE t:LUT2 t:LUT5 t:LUT6 %% t:* %D
+select -assert-none t:BUFG t:FDRE t:FDSE t:LUT* %% t:* %D
 
 design -load orig
 
@@ -31,8 +28,5 @@ cd fsm # Constrain all select calls below inside the top module
 stat
 select -assert-count 1 t:BUFG
 select -assert-count 6 t:FDRE
-select -assert-count 1 t:LUT1
-select -assert-count 3 t:LUT3
-select -assert-count 6 t:LUT4
-select -assert-count 6 t:MUXF5
-select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT3 t:LUT4 t:MUXF5 %% t:* %D
+# FIXME: One more register than above?
+select -assert-none t:BUFG t:FDRE t:LUT* t:MUXF* %% t:* %D