From: lkcl <lkcl@web>
Date: Wed, 27 Apr 2022 15:09:46 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2556
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bc984617f86820478862438116968669ab915959;p=libreriscv.git

---

diff --git a/openpower/sv/biginteger/analysis.mdwn b/openpower/sv/biginteger/analysis.mdwn
index febdf75e7..c846fc9e0 100644
--- a/openpower/sv/biginteger/analysis.mdwn
+++ b/openpower/sv/biginteger/analysis.mdwn
@@ -137,7 +137,8 @@ and this is precisely what `adde` already does.
 For multiply and divide as shown later it is worthwhile to use
 one scalar register effectively as a full 64-bit carry/chain
 but in the case of shift, an OR may glue things together, easily,
-and in parallel.
+and in parallel, because unlike `sv.adde`, down-chain
+carry-propagation through multiple elements does not occur.
 
 With Scalar shift and rotate operations in the Power ISA already being
 complex and very comprehensive, it is hard to justify creating complex