From: lkcl <lkcl@web>
Date: Wed, 25 May 2022 11:11:03 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2102
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bcb3105807be3731260ec8b20b4f22e67a94c316;p=libreriscv.git

---

diff --git a/openpower/sv/int_fp_mv.mdwn b/openpower/sv/int_fp_mv.mdwn
index e83997d2c..3baf1fa83 100644
--- a/openpower/sv/int_fp_mv.mdwn
+++ b/openpower/sv/int_fp_mv.mdwn
@@ -79,9 +79,13 @@ work on *both* Fixed *and* Floating Point operands and results.
  The interactions with SVP64
 are explained in the  [[int_fp_mv/appendix]]
 
-# Float load immediate <a name="fmvis"></a>
+# Float load immediate
 
-This is like a variant of `fmvfg`
+These arelike a variant of `fmvfg`. Power ISA currently requires a large
+number of instructions to get Floating Point constants into registers.
+FP16 and BF16 Formats both fit into 16-bit immediates.
+
+## Load BF16 Immediate <a name="fmvis"></a>
 
 `fmvis FRT, FI`
 
@@ -118,16 +122,46 @@ change all [GPR to FPR conversion instructions](#GPR-to-FPR-conversions)
 to instead write `+0.0` if `RA` is register `0`, at least
 allowing clearing FPRs.
 
-`fmvis` fits well with DX-Form:
+`fmvis` fits with DX-Form:
 
 |  0-5   | 6-10 | 11-15 | 16-25 | 26-30 | 31  | Form |
 |--------|------|-------|-------|-------|-----|-----|
 |  Major | FRT  | d1    | d0    | XO    | d2  | DX-Form |
 
+Pseudocode:
+
     bf16 = d0 || d1 || d2
     fp32 = bf16 || [0]*16
     FRT = Single_to_Double(fp32)
 
+## Load FP16 Immediate <a name="fishmv"></a>
+
+`fishmv FRT, FI`
+
+Interprets `FI` as an IEEE754 16-bit float, which is then converted to a
+64-bit float and written to `FRT`.  This is equivalent to interpreting
+`FI` as a `FP16` and converting to 64-bit float.
+
+There is no need for an Rc=1 variant because this is an immediate loading
+instruction. This frees up one extra bit in the DX-Form format for packing
+a full `FP16`.
+
+`fishmv` fits with DX-Form:
+
+|  0-5   | 6-10 | 11-15 | 16-25 | 26-30 | 31  | Form |
+|--------|------|-------|-------|-------|-----|-----|
+|  Major | FRT  | d1    | d0    | XO    | d2  | DX-Form |
+
+Pseudocode:
+
+    fp16 = d0 || d1 || d2
+    FRT = Half_to_Double(fp16)
+
+# Moves
+
+These instructions perform a straight unaltered bit-level copy from one Register
+File to another.
+
 # FPR to GPR moves
 
 * `fmvtg RT, FRA`