From: Yunsup Lee <yunsup@cs.berkeley.edu>
Date: Sun, 2 Mar 2014 10:43:04 +0000 (-0800)
Subject: add vfmsv.{s,d} tests
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bcebb088e573ed9fc90babaf5f0eae588d605cdc;p=riscv-tests.git

add vfmsv.{s,d} tests
---

diff --git a/isa/rv64uv/Makefrag b/isa/rv64uv/Makefrag
index 978a32b..b65d7c0 100644
--- a/isa/rv64uv/Makefrag
+++ b/isa/rv64uv/Makefrag
@@ -6,7 +6,7 @@ rv64uv_sc_tests = \
 	wakeup fence \
 	vsetcfgi vsetcfg vsetvl keepcfg \
 	vmvv vmsv \
-	vfmvv vfmsv \
+	vfmvv vfmsv_d vfmsv_s \
 	utidx \
 	lb lbu lh lhu lw lwu ld \
 	sb sh sw sd \
diff --git a/isa/rv64uv/vfmsv.S b/isa/rv64uv/vfmsv.S
deleted file mode 100644
index 5a8dbeb..0000000
--- a/isa/rv64uv/vfmsv.S
+++ /dev/null
@@ -1,55 +0,0 @@
-#*****************************************************************************
-# vfmsv.S
-#-----------------------------------------------------------------------------
-#
-# Test vfmsv instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64UV
-RVTEST_CODE_BEGIN
-
-  vsetcfg 3,1
-  li a2,680
-  vsetvl a2,a2
-
-  li a3,-1
-  vfmsv vf0,a3
-  lui a0,%hi(vtcode)
-  vf %lo(vtcode)(a0)
-  la a4,dest
-  vsd vx2,a4
-  fence
-
-  li a1,0
-loop:
-  ld a0,0(a4)
-  addi x28,a1,2
-  bne a0,a1,fail
-  addi a4,a4,8
-  addi a1,a1,1
-  bne a1,a2,loop
-  j pass
-
-vtcode:
-  utidx x1
-  addi x1,x1,1
-  fmv.x.d x2, f0
-  add x2,x1,x2
-  stop
-
-  TEST_PASSFAIL
-
-RVTEST_CODE_END
-
-  .data
-RVTEST_DATA_BEGIN
-
-  TEST_DATA
-
-dest:
-  .skip 16384
-
-RVTEST_DATA_END
diff --git a/isa/rv64uv/vfmsv_d.S b/isa/rv64uv/vfmsv_d.S
new file mode 100644
index 0000000..e355eb8
--- /dev/null
+++ b/isa/rv64uv/vfmsv_d.S
@@ -0,0 +1,55 @@
+#*****************************************************************************
+# vfmsv_d.S
+#-----------------------------------------------------------------------------
+#
+# Test vfmsv.d instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UV
+RVTEST_CODE_BEGIN
+
+  vsetcfg 3,1
+  li a2,680
+  vsetvl a2,a2
+
+  li a3,-1
+  vfmsv.d vf0,a3
+  lui a0,%hi(vtcode)
+  vf %lo(vtcode)(a0)
+  la a4,dest
+  vsd vx2,a4
+  fence
+
+  li a1,0
+loop:
+  ld a0,0(a4)
+  addi TESTNUM,a1,2
+  bne a0,a1,fail
+  addi a4,a4,8
+  addi a1,a1,1
+  bne a1,a2,loop
+  j pass
+
+vtcode:
+  utidx x1
+  addi x1,x1,1
+  fmv.x.d x2, f0
+  add x2,x1,x2
+  stop
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+dest:
+  .skip 16384
+
+RVTEST_DATA_END
diff --git a/isa/rv64uv/vfmsv_s.S b/isa/rv64uv/vfmsv_s.S
new file mode 100644
index 0000000..8b566fd
--- /dev/null
+++ b/isa/rv64uv/vfmsv_s.S
@@ -0,0 +1,55 @@
+#*****************************************************************************
+# vfmsv_s.S
+#-----------------------------------------------------------------------------
+#
+# Test vfmsv.s instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UV
+RVTEST_CODE_BEGIN
+
+  vsetcfg 3,1
+  li a2,680
+  vsetvl a2,a2
+
+  li a3,-1
+  vfmsv.s vf0,a3
+  lui a0,%hi(vtcode)
+  vf %lo(vtcode)(a0)
+  la a4,dest
+  vsd vx2,a4
+  fence
+
+  li a1,0
+loop:
+  ld a0,0(a4)
+  addi TESTNUM,a1,2
+  bne a0,a1,fail
+  addi a4,a4,8
+  addi a1,a1,1
+  bne a1,a2,loop
+  j pass
+
+vtcode:
+  utidx x1
+  addi x1,x1,1
+  fmv.x.s x2, f0
+  add x2,x1,x2
+  stop
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+dest:
+  .skip 16384
+
+RVTEST_DATA_END