From: Luke Kenneth Casson Leighton Date: Sat, 30 May 2020 13:27:06 +0000 (+0100) Subject: order of XER so/ca wrong way round from regspec X-Git-Tag: div_pipeline~736 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bcec0e66c9d6fd8bcb7b5d0ce6a9837a50e0fc96;p=soc.git order of XER so/ca wrong way round from regspec --- diff --git a/src/soc/fu/compunits/test/test_alu_compunit.py b/src/soc/fu/compunits/test/test_alu_compunit.py index c765af1d..22c0ee48 100644 --- a/src/soc/fu/compunits/test/test_alu_compunit.py +++ b/src/soc/fu/compunits/test/test_alu_compunit.py @@ -92,9 +92,9 @@ def set_operand(cu, dec2, sim): def set_extra_cu_inputs(cu, dec2, sim): carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0 carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0 - yield from set_cu_input(cu, 2, carry | (carry32<<1)) + yield from set_cu_input(cu, 3, carry | (carry32<<1)) so = 1 if sim.spr['XER'][XER_bits['SO']] else 0 - yield from set_cu_input(cu, 3, so) + yield from set_cu_input(cu, 2, so)