From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 15 Oct 2020 14:58:09 +0000 (+0100)
Subject: syntax error
X-Git-Tag: 24jan2021_ls180~149
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bd16ecbddd613773e12b67d2406085528b65cd0e;p=soc.git

syntax error
---

diff --git a/libreriscv b/libreriscv
index f0f302d8..1f4b308f 160000
--- a/libreriscv
+++ b/libreriscv
@@ -1 +1 @@
-Subproject commit f0f302d80683c9b68fc9b13dac9f590ae1937232
+Subproject commit 1f4b308f975418595a0858cd37e7e66f2fe7244d
diff --git a/src/soc/litex/florent/versa_ecp5.py b/src/soc/litex/florent/versa_ecp5.py
index c9938fea..bd565b0b 100755
--- a/src/soc/litex/florent/versa_ecp5.py
+++ b/src/soc/litex/florent/versa_ecp5.py
@@ -29,7 +29,6 @@ class VersaECP5TestSoC(versa_ecp5.BaseSoC):
             sys_clk_freq = sys_clk_freq,
             cpu_type     = "external",
             cpu_cls      = LibreSoC,
-            cpu_variant  = "standardjtag",
             cpu_variant = "standardjtagnoirq",
             #cpu_cls      = Microwatt,
             device       = "LFE5UM",