From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 26 Nov 2018 03:00:17 +0000 (+0000)
Subject: add counters (TODO)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bd2c1c1d66e3d82d1080f77382e8af2c41559db6;p=rv32.git

add counters (TODO)
---

diff --git a/cpu.py b/cpu.py
index c8dafde..eabe9d8 100644
--- a/cpu.py
+++ b/cpu.py
@@ -622,6 +622,11 @@ class CPU(Module):
         self.comb += self.get_csr_op_is_valid(csr_op_is_valid, csr_number,
                                               csr_reads, csr_writes)
 
+        # TODO
+        cycle_counter   = Signal(64); # TODO: implement cycle_counter
+        time_counter    = Signal(64); # TODO: implement time_counter
+        instret_counter = Signal(64); # TODO: implement instret_counter
+
 if __name__ == "__main__":
     example = CPU()
     print(verilog.convert(example,