From: Luke Kenneth Casson Leighton Date: Tue, 29 Sep 2020 09:32:13 +0000 (+0000) Subject: updated ls180 (no core, testing) X-Git-Tag: partial-core-ls180-gdsii~62 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bd4e7438840af1788670f9b68fb85bb00a3fa931;p=soclayout.git updated ls180 (no core, testing) --- diff --git a/experiments9/non_generated/ls180.il b/experiments9/non_generated/ls180.il index 107e41d..4f9c4b8 100644 --- a/experiments9/non_generated/ls180.il +++ b/experiments9/non_generated/ls180.il @@ -1,5 +1,5 @@ # Generated by Yosys 0.9+3578 (git sha1 c6ff947f, clang 9.0.1-12 -fPIC -Os) -autoidx 3705 +autoidx 3702 attribute \src "libresoc.v:5.1-277.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.jtag._fsm" @@ -68455,2456 +68455,2452 @@ module \jtag connect \io_shift \$21 connect \io_capture \$7 end -attribute \src "ls180.v:4.1-10286.10" +attribute \src "ls180.v:4.1-10282.10" attribute \cells_not_processed 1 module \ls180 - attribute \src "ls180.v:9981.1-9991.4" - wire width 7 $0$memwr$\mem$ls180.v:9983$1_ADDR[6:0]$2685 - attribute \src "ls180.v:9981.1-9991.4" - wire width 32 $0$memwr$\mem$ls180.v:9983$1_DATA[31:0]$2686 - attribute \src "ls180.v:9981.1-9991.4" - wire width 32 $0$memwr$\mem$ls180.v:9983$1_EN[31:0]$2687 - attribute \src "ls180.v:9981.1-9991.4" - wire width 7 $0$memwr$\mem$ls180.v:9985$2_ADDR[6:0]$2688 - attribute \src "ls180.v:9981.1-9991.4" - wire width 32 $0$memwr$\mem$ls180.v:9985$2_DATA[31:0]$2689 - attribute \src "ls180.v:9981.1-9991.4" - wire width 32 $0$memwr$\mem$ls180.v:9985$2_EN[31:0]$2690 - attribute \src "ls180.v:9981.1-9991.4" - wire width 7 $0$memwr$\mem$ls180.v:9987$3_ADDR[6:0]$2691 - attribute \src "ls180.v:9981.1-9991.4" - wire width 32 $0$memwr$\mem$ls180.v:9987$3_DATA[31:0]$2692 - attribute \src "ls180.v:9981.1-9991.4" - wire width 32 $0$memwr$\mem$ls180.v:9987$3_EN[31:0]$2693 - attribute \src "ls180.v:9981.1-9991.4" - wire width 7 $0$memwr$\mem$ls180.v:9989$4_ADDR[6:0]$2694 - attribute \src "ls180.v:9981.1-9991.4" - wire width 32 $0$memwr$\mem$ls180.v:9989$4_DATA[31:0]$2695 - attribute \src "ls180.v:9981.1-9991.4" - wire width 32 $0$memwr$\mem$ls180.v:9989$4_EN[31:0]$2696 - attribute \src "ls180.v:10001.1-10005.4" - wire width 3 $0$memwr$\storage$ls180.v:10003$5_ADDR[2:0]$2699 - attribute \src "ls180.v:10001.1-10005.4" - wire width 25 $0$memwr$\storage$ls180.v:10003$5_DATA[24:0]$2700 - attribute \src "ls180.v:10001.1-10005.4" - wire width 25 $0$memwr$\storage$ls180.v:10003$5_EN[24:0]$2701 - attribute \src "ls180.v:10015.1-10019.4" - wire width 3 $0$memwr$\storage_1$ls180.v:10017$6_ADDR[2:0]$2706 - attribute \src "ls180.v:10015.1-10019.4" - wire width 25 $0$memwr$\storage_1$ls180.v:10017$6_DATA[24:0]$2707 - attribute \src "ls180.v:10015.1-10019.4" - wire width 25 $0$memwr$\storage_1$ls180.v:10017$6_EN[24:0]$2708 - attribute \src "ls180.v:10029.1-10033.4" - wire width 3 $0$memwr$\storage_2$ls180.v:10031$7_ADDR[2:0]$2713 - attribute \src "ls180.v:10029.1-10033.4" - wire width 25 $0$memwr$\storage_2$ls180.v:10031$7_DATA[24:0]$2714 - attribute \src "ls180.v:10029.1-10033.4" - wire width 25 $0$memwr$\storage_2$ls180.v:10031$7_EN[24:0]$2715 - attribute \src "ls180.v:10043.1-10047.4" - wire width 3 $0$memwr$\storage_3$ls180.v:10045$8_ADDR[2:0]$2720 - attribute \src "ls180.v:10043.1-10047.4" - wire width 25 $0$memwr$\storage_3$ls180.v:10045$8_DATA[24:0]$2721 - attribute \src "ls180.v:10043.1-10047.4" - wire width 25 $0$memwr$\storage_3$ls180.v:10045$8_EN[24:0]$2722 - attribute \src "ls180.v:10058.1-10062.4" - wire width 4 $0$memwr$\storage_4$ls180.v:10060$9_ADDR[3:0]$2727 - attribute \src "ls180.v:10058.1-10062.4" - wire width 10 $0$memwr$\storage_4$ls180.v:10060$9_DATA[9:0]$2728 - attribute \src "ls180.v:10058.1-10062.4" - wire width 10 $0$memwr$\storage_4$ls180.v:10060$9_EN[9:0]$2729 - attribute \src "ls180.v:10075.1-10079.4" - wire width 4 $0$memwr$\storage_5$ls180.v:10077$10_ADDR[3:0]$2734 - attribute \src "ls180.v:10075.1-10079.4" - wire width 10 $0$memwr$\storage_5$ls180.v:10077$10_DATA[9:0]$2735 - attribute \src "ls180.v:10075.1-10079.4" - wire width 10 $0$memwr$\storage_5$ls180.v:10077$10_EN[9:0]$2736 - attribute \src "ls180.v:10091.1-10095.4" - wire width 5 $0$memwr$\storage_6$ls180.v:10093$11_ADDR[4:0]$2741 - attribute \src "ls180.v:10091.1-10095.4" - wire width 10 $0$memwr$\storage_6$ls180.v:10093$11_DATA[9:0]$2742 - attribute \src "ls180.v:10091.1-10095.4" - wire width 10 $0$memwr$\storage_6$ls180.v:10093$11_EN[9:0]$2743 - attribute \src "ls180.v:10105.1-10109.4" - wire width 5 $0$memwr$\storage_7$ls180.v:10107$12_ADDR[4:0]$2748 - attribute \src "ls180.v:10105.1-10109.4" - wire width 10 $0$memwr$\storage_7$ls180.v:10107$12_DATA[9:0]$2749 - attribute \src "ls180.v:10105.1-10109.4" - wire width 10 $0$memwr$\storage_7$ls180.v:10107$12_EN[9:0]$2750 - attribute \src "ls180.v:3179.1-3272.4" + attribute \src "ls180.v:9977.1-9987.4" + wire width 7 $0$memwr$\mem$ls180.v:9979$1_ADDR[6:0]$2683 + attribute \src "ls180.v:9977.1-9987.4" + wire width 32 $0$memwr$\mem$ls180.v:9979$1_DATA[31:0]$2684 + attribute \src "ls180.v:9977.1-9987.4" + wire width 32 $0$memwr$\mem$ls180.v:9979$1_EN[31:0]$2685 + attribute \src "ls180.v:9977.1-9987.4" + wire width 7 $0$memwr$\mem$ls180.v:9981$2_ADDR[6:0]$2686 + attribute \src "ls180.v:9977.1-9987.4" + wire width 32 $0$memwr$\mem$ls180.v:9981$2_DATA[31:0]$2687 + attribute \src "ls180.v:9977.1-9987.4" + wire width 32 $0$memwr$\mem$ls180.v:9981$2_EN[31:0]$2688 + attribute \src "ls180.v:9977.1-9987.4" + wire width 7 $0$memwr$\mem$ls180.v:9983$3_ADDR[6:0]$2689 + attribute \src "ls180.v:9977.1-9987.4" + wire width 32 $0$memwr$\mem$ls180.v:9983$3_DATA[31:0]$2690 + attribute \src "ls180.v:9977.1-9987.4" + wire width 32 $0$memwr$\mem$ls180.v:9983$3_EN[31:0]$2691 + attribute \src "ls180.v:9977.1-9987.4" + wire width 7 $0$memwr$\mem$ls180.v:9985$4_ADDR[6:0]$2692 + attribute \src "ls180.v:9977.1-9987.4" + wire width 32 $0$memwr$\mem$ls180.v:9985$4_DATA[31:0]$2693 + attribute \src "ls180.v:9977.1-9987.4" + wire width 32 $0$memwr$\mem$ls180.v:9985$4_EN[31:0]$2694 + attribute \src "ls180.v:9997.1-10001.4" + wire width 3 $0$memwr$\storage$ls180.v:9999$5_ADDR[2:0]$2697 + attribute \src "ls180.v:9997.1-10001.4" + wire width 25 $0$memwr$\storage$ls180.v:9999$5_DATA[24:0]$2698 + attribute \src "ls180.v:9997.1-10001.4" + wire width 25 $0$memwr$\storage$ls180.v:9999$5_EN[24:0]$2699 + attribute \src "ls180.v:10011.1-10015.4" + wire width 3 $0$memwr$\storage_1$ls180.v:10013$6_ADDR[2:0]$2704 + attribute \src "ls180.v:10011.1-10015.4" + wire width 25 $0$memwr$\storage_1$ls180.v:10013$6_DATA[24:0]$2705 + attribute \src "ls180.v:10011.1-10015.4" + wire width 25 $0$memwr$\storage_1$ls180.v:10013$6_EN[24:0]$2706 + attribute \src "ls180.v:10025.1-10029.4" + wire width 3 $0$memwr$\storage_2$ls180.v:10027$7_ADDR[2:0]$2711 + attribute \src "ls180.v:10025.1-10029.4" + wire width 25 $0$memwr$\storage_2$ls180.v:10027$7_DATA[24:0]$2712 + attribute \src "ls180.v:10025.1-10029.4" + wire width 25 $0$memwr$\storage_2$ls180.v:10027$7_EN[24:0]$2713 + attribute \src "ls180.v:10039.1-10043.4" + wire width 3 $0$memwr$\storage_3$ls180.v:10041$8_ADDR[2:0]$2718 + attribute \src "ls180.v:10039.1-10043.4" + wire width 25 $0$memwr$\storage_3$ls180.v:10041$8_DATA[24:0]$2719 + attribute \src "ls180.v:10039.1-10043.4" + wire width 25 $0$memwr$\storage_3$ls180.v:10041$8_EN[24:0]$2720 + attribute \src "ls180.v:10054.1-10058.4" + wire width 4 $0$memwr$\storage_4$ls180.v:10056$9_ADDR[3:0]$2725 + attribute \src "ls180.v:10054.1-10058.4" + wire width 10 $0$memwr$\storage_4$ls180.v:10056$9_DATA[9:0]$2726 + attribute \src "ls180.v:10054.1-10058.4" + wire width 10 $0$memwr$\storage_4$ls180.v:10056$9_EN[9:0]$2727 + attribute \src "ls180.v:10071.1-10075.4" + wire width 4 $0$memwr$\storage_5$ls180.v:10073$10_ADDR[3:0]$2732 + attribute \src "ls180.v:10071.1-10075.4" + wire width 10 $0$memwr$\storage_5$ls180.v:10073$10_DATA[9:0]$2733 + attribute \src "ls180.v:10071.1-10075.4" + wire width 10 $0$memwr$\storage_5$ls180.v:10073$10_EN[9:0]$2734 + attribute \src "ls180.v:10087.1-10091.4" + wire width 5 $0$memwr$\storage_6$ls180.v:10089$11_ADDR[4:0]$2739 + attribute \src "ls180.v:10087.1-10091.4" + wire width 10 $0$memwr$\storage_6$ls180.v:10089$11_DATA[9:0]$2740 + attribute \src "ls180.v:10087.1-10091.4" + wire width 10 $0$memwr$\storage_6$ls180.v:10089$11_EN[9:0]$2741 + attribute \src "ls180.v:10101.1-10105.4" + wire width 5 $0$memwr$\storage_7$ls180.v:10103$12_ADDR[4:0]$2746 + attribute \src "ls180.v:10101.1-10105.4" + wire width 10 $0$memwr$\storage_7$ls180.v:10103$12_DATA[9:0]$2747 + attribute \src "ls180.v:10101.1-10105.4" + wire width 10 $0$memwr$\storage_7$ls180.v:10103$12_EN[9:0]$2748 + attribute \src "ls180.v:3175.1-3268.4" wire width 3 $0\builder_bankmachine0_next_state[2:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 3 $0\builder_bankmachine0_state[2:0] - attribute \src "ls180.v:3336.1-3429.4" + attribute \src "ls180.v:3332.1-3425.4" wire width 3 $0\builder_bankmachine1_next_state[2:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 3 $0\builder_bankmachine1_state[2:0] - attribute \src "ls180.v:3493.1-3586.4" + attribute \src "ls180.v:3489.1-3582.4" wire width 3 $0\builder_bankmachine2_next_state[2:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 3 $0\builder_bankmachine2_state[2:0] - attribute \src "ls180.v:3650.1-3743.4" + attribute \src "ls180.v:3646.1-3739.4" wire width 3 $0\builder_bankmachine3_next_state[2:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 3 $0\builder_bankmachine3_state[2:0] - attribute \src "ls180.v:6452.1-6468.4" + attribute \src "ls180.v:6448.1-6464.4" wire $0\builder_comb_rhs_array_muxed0[0:0] - attribute \src "ls180.v:6673.1-6689.4" + attribute \src "ls180.v:6669.1-6685.4" wire $0\builder_comb_rhs_array_muxed10[0:0] - attribute \src "ls180.v:6690.1-6706.4" + attribute \src "ls180.v:6686.1-6702.4" wire $0\builder_comb_rhs_array_muxed11[0:0] - attribute \src "ls180.v:6758.1-6765.4" + attribute \src "ls180.v:6754.1-6761.4" wire width 22 $0\builder_comb_rhs_array_muxed12[21:0] - attribute \src "ls180.v:6766.1-6773.4" + attribute \src "ls180.v:6762.1-6769.4" wire $0\builder_comb_rhs_array_muxed13[0:0] - attribute \src "ls180.v:6774.1-6781.4" + attribute \src "ls180.v:6770.1-6777.4" wire $0\builder_comb_rhs_array_muxed14[0:0] - attribute \src "ls180.v:6782.1-6789.4" + attribute \src "ls180.v:6778.1-6785.4" wire width 22 $0\builder_comb_rhs_array_muxed15[21:0] - attribute \src "ls180.v:6790.1-6797.4" + attribute \src "ls180.v:6786.1-6793.4" wire $0\builder_comb_rhs_array_muxed16[0:0] - attribute \src "ls180.v:6798.1-6805.4" + attribute \src "ls180.v:6794.1-6801.4" wire $0\builder_comb_rhs_array_muxed17[0:0] - attribute \src "ls180.v:6806.1-6813.4" + attribute \src "ls180.v:6802.1-6809.4" wire width 22 $0\builder_comb_rhs_array_muxed18[21:0] - attribute \src "ls180.v:6814.1-6821.4" + attribute \src "ls180.v:6810.1-6817.4" wire $0\builder_comb_rhs_array_muxed19[0:0] - attribute \src "ls180.v:6469.1-6485.4" + attribute \src "ls180.v:6465.1-6481.4" wire width 13 $0\builder_comb_rhs_array_muxed1[12:0] - attribute \src "ls180.v:6822.1-6829.4" + attribute \src "ls180.v:6818.1-6825.4" wire $0\builder_comb_rhs_array_muxed20[0:0] - attribute \src "ls180.v:6830.1-6837.4" + attribute \src "ls180.v:6826.1-6833.4" wire width 22 $0\builder_comb_rhs_array_muxed21[21:0] - attribute \src "ls180.v:6838.1-6845.4" + attribute \src "ls180.v:6834.1-6841.4" wire $0\builder_comb_rhs_array_muxed22[0:0] - attribute \src "ls180.v:6846.1-6853.4" + attribute \src "ls180.v:6842.1-6849.4" wire $0\builder_comb_rhs_array_muxed23[0:0] - attribute \src "ls180.v:6854.1-6873.4" + attribute \src "ls180.v:6850.1-6869.4" wire width 32 $0\builder_comb_rhs_array_muxed24[31:0] - attribute \src "ls180.v:6874.1-6893.4" + attribute \src "ls180.v:6870.1-6889.4" wire width 32 $0\builder_comb_rhs_array_muxed25[31:0] - attribute \src "ls180.v:6894.1-6913.4" + attribute \src "ls180.v:6890.1-6909.4" wire width 4 $0\builder_comb_rhs_array_muxed26[3:0] - attribute \src "ls180.v:6914.1-6933.4" + attribute \src "ls180.v:6910.1-6929.4" wire $0\builder_comb_rhs_array_muxed27[0:0] - attribute \src "ls180.v:6934.1-6953.4" + attribute \src "ls180.v:6930.1-6949.4" wire $0\builder_comb_rhs_array_muxed28[0:0] - attribute \src "ls180.v:6954.1-6973.4" + attribute \src "ls180.v:6950.1-6969.4" wire $0\builder_comb_rhs_array_muxed29[0:0] - attribute \src "ls180.v:6486.1-6502.4" + attribute \src "ls180.v:6482.1-6498.4" wire width 2 $0\builder_comb_rhs_array_muxed2[1:0] - attribute \src "ls180.v:6974.1-6993.4" + attribute \src "ls180.v:6970.1-6989.4" wire width 3 $0\builder_comb_rhs_array_muxed30[2:0] - attribute \src "ls180.v:6994.1-7013.4" + attribute \src "ls180.v:6990.1-7009.4" wire width 2 $0\builder_comb_rhs_array_muxed31[1:0] - attribute \src "ls180.v:6503.1-6519.4" + attribute \src "ls180.v:6499.1-6515.4" wire $0\builder_comb_rhs_array_muxed3[0:0] - attribute \src "ls180.v:6520.1-6536.4" + attribute \src "ls180.v:6516.1-6532.4" wire $0\builder_comb_rhs_array_muxed4[0:0] - attribute \src "ls180.v:6537.1-6553.4" + attribute \src "ls180.v:6533.1-6549.4" wire $0\builder_comb_rhs_array_muxed5[0:0] - attribute \src "ls180.v:6605.1-6621.4" + attribute \src "ls180.v:6601.1-6617.4" wire $0\builder_comb_rhs_array_muxed6[0:0] - attribute \src "ls180.v:6622.1-6638.4" + attribute \src "ls180.v:6618.1-6634.4" wire width 13 $0\builder_comb_rhs_array_muxed7[12:0] - attribute \src "ls180.v:6639.1-6655.4" + attribute \src "ls180.v:6635.1-6651.4" wire width 2 $0\builder_comb_rhs_array_muxed8[1:0] - attribute \src "ls180.v:6656.1-6672.4" + attribute \src "ls180.v:6652.1-6668.4" wire $0\builder_comb_rhs_array_muxed9[0:0] - attribute \src "ls180.v:6554.1-6570.4" + attribute \src "ls180.v:6550.1-6566.4" wire $0\builder_comb_t_array_muxed0[0:0] - attribute \src "ls180.v:6571.1-6587.4" + attribute \src "ls180.v:6567.1-6583.4" wire $0\builder_comb_t_array_muxed1[0:0] - attribute \src "ls180.v:6588.1-6604.4" + attribute \src "ls180.v:6584.1-6600.4" wire $0\builder_comb_t_array_muxed2[0:0] - attribute \src "ls180.v:6707.1-6723.4" + attribute \src "ls180.v:6703.1-6719.4" wire $0\builder_comb_t_array_muxed3[0:0] - attribute \src "ls180.v:6724.1-6740.4" + attribute \src "ls180.v:6720.1-6736.4" wire $0\builder_comb_t_array_muxed4[0:0] - attribute \src "ls180.v:6741.1-6757.4" + attribute \src "ls180.v:6737.1-6753.4" wire $0\builder_comb_t_array_muxed5[0:0] - attribute \src "ls180.v:2738.1-2784.4" + attribute \src "ls180.v:2739.1-2785.4" wire $0\builder_converter0_next_state[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\builder_converter0_state[0:0] - attribute \src "ls180.v:2798.1-2844.4" + attribute \src "ls180.v:2799.1-2845.4" wire $0\builder_converter1_next_state[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\builder_converter1_state[0:0] - attribute \src "ls180.v:2858.1-2904.4" + attribute \src "ls180.v:2859.1-2905.4" wire $0\builder_converter2_next_state[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\builder_converter2_state[0:0] - attribute \src "ls180.v:3996.1-4042.4" + attribute \src "ls180.v:3992.1-4038.4" wire $0\builder_converter_next_state[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\builder_converter_state[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 20 $0\builder_count[19:0] - attribute \src "ls180.v:5709.1-5720.4" + attribute \src "ls180.v:5705.1-5716.4" wire $0\builder_error[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 3 $0\builder_grant[2:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 8 $0\builder_interface0_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 8 $0\builder_interface10_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 8 $0\builder_interface11_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 8 $0\builder_interface12_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 8 $0\builder_interface13_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 8 $0\builder_interface1_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 8 $0\builder_interface2_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 8 $0\builder_interface3_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 8 $0\builder_interface4_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 8 $0\builder_interface5_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 8 $0\builder_interface6_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 8 $0\builder_interface7_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 8 $0\builder_interface8_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 8 $0\builder_interface9_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 14 $0\builder_libresocsim_adr[13:0] - attribute \src "ls180.v:5598.1-5634.4" + attribute \src "ls180.v:5594.1-5630.4" wire width 14 $0\builder_libresocsim_adr_next_value1[13:0] - attribute \src "ls180.v:5598.1-5634.4" + attribute \src "ls180.v:5594.1-5630.4" wire $0\builder_libresocsim_adr_next_value_ce1[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 8 $0\builder_libresocsim_dat_w[7:0] - attribute \src "ls180.v:5598.1-5634.4" + attribute \src "ls180.v:5594.1-5630.4" wire width 8 $0\builder_libresocsim_dat_w_next_value0[7:0] - attribute \src "ls180.v:5598.1-5634.4" + attribute \src "ls180.v:5594.1-5630.4" wire $0\builder_libresocsim_dat_w_next_value_ce0[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\builder_libresocsim_we[0:0] - attribute \src "ls180.v:5598.1-5634.4" + attribute \src "ls180.v:5594.1-5630.4" wire $0\builder_libresocsim_we_next_value2[0:0] - attribute \src "ls180.v:5598.1-5634.4" + attribute \src "ls180.v:5594.1-5630.4" wire $0\builder_libresocsim_we_next_value_ce2[0:0] - attribute \src "ls180.v:5598.1-5634.4" + attribute \src "ls180.v:5594.1-5630.4" wire $0\builder_libresocsim_wishbone_ack[0:0] - attribute \src "ls180.v:5598.1-5634.4" + attribute \src "ls180.v:5594.1-5630.4" wire width 32 $0\builder_libresocsim_wishbone_dat_r[31:0] - attribute \src "ls180.v:1842.5-1842.44" + attribute \src "ls180.v:1841.5-1841.44" wire $0\builder_libresocsim_wishbone_err[0:0] - attribute \src "ls180.v:1731.5-1731.27" + attribute \src "ls180.v:1730.5-1730.27" wire $0\builder_locked0[0:0] - attribute \src "ls180.v:1732.5-1732.27" + attribute \src "ls180.v:1731.5-1731.27" wire $0\builder_locked1[0:0] - attribute \src "ls180.v:1733.5-1733.27" + attribute \src "ls180.v:1732.5-1732.27" wire $0\builder_locked2[0:0] - attribute \src "ls180.v:1734.5-1734.27" + attribute \src "ls180.v:1733.5-1733.27" wire $0\builder_locked3[0:0] - attribute \src "ls180.v:3868.1-3940.4" + attribute \src "ls180.v:3864.1-3936.4" wire width 3 $0\builder_multiplexer_next_state[2:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 3 $0\builder_multiplexer_state[2:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\builder_multiregimpl0_regs0[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\builder_multiregimpl0_regs1[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\builder_multiregimpl10_regs0[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\builder_multiregimpl10_regs1[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\builder_multiregimpl11_regs0[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\builder_multiregimpl11_regs1[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\builder_multiregimpl12_regs0[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\builder_multiregimpl12_regs1[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\builder_multiregimpl13_regs0[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\builder_multiregimpl13_regs1[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\builder_multiregimpl14_regs0[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\builder_multiregimpl14_regs1[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\builder_multiregimpl15_regs0[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\builder_multiregimpl15_regs1[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\builder_multiregimpl16_regs0[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\builder_multiregimpl16_regs1[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\builder_multiregimpl1_regs0[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\builder_multiregimpl1_regs1[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\builder_multiregimpl2_regs0[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\builder_multiregimpl2_regs1[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\builder_multiregimpl3_regs0[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\builder_multiregimpl3_regs1[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\builder_multiregimpl4_regs0[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\builder_multiregimpl4_regs1[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\builder_multiregimpl5_regs0[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\builder_multiregimpl5_regs1[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\builder_multiregimpl6_regs0[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\builder_multiregimpl6_regs1[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\builder_multiregimpl7_regs0[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\builder_multiregimpl7_regs1[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\builder_multiregimpl8_regs0[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\builder_multiregimpl8_regs1[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\builder_multiregimpl9_regs0[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\builder_multiregimpl9_regs1[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\builder_new_master_rdata_valid0[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\builder_new_master_rdata_valid1[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\builder_new_master_rdata_valid2[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\builder_new_master_rdata_valid3[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\builder_new_master_wdata_ready[0:0] - attribute \src "ls180.v:5598.1-5634.4" + attribute \src "ls180.v:5594.1-5630.4" wire width 2 $0\builder_next_state[1:0] - attribute \src "ls180.v:3085.1-3115.4" + attribute \src "ls180.v:3081.1-3111.4" wire width 2 $0\builder_refresher_next_state[1:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 2 $0\builder_refresher_state[1:0] - attribute \src "ls180.v:5349.1-5388.4" + attribute \src "ls180.v:5345.1-5384.4" wire width 2 $0\builder_sdblock2memdma_next_state[1:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 2 $0\builder_sdblock2memdma_state[1:0] - attribute \src "ls180.v:4916.1-4995.4" + attribute \src "ls180.v:4912.1-4991.4" wire $0\builder_sdcore_crcupstreaminserter_next_state[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\builder_sdcore_crcupstreaminserter_state[0:0] - attribute \src "ls180.v:5098.1-5288.4" + attribute \src "ls180.v:5094.1-5284.4" wire width 3 $0\builder_sdcore_fsm_next_state[2:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 3 $0\builder_sdcore_fsm_state[2:0] - attribute \src "ls180.v:5408.1-5445.4" + attribute \src "ls180.v:5404.1-5441.4" wire $0\builder_sdmem2blockdma_fsm_next_state[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\builder_sdmem2blockdma_fsm_state[0:0] - attribute \src "ls180.v:5446.1-5482.4" + attribute \src "ls180.v:5442.1-5478.4" wire width 2 $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 2 $0\builder_sdmem2blockdma_resetinserter_state[1:0] - attribute \src "ls180.v:4591.1-4663.4" + attribute \src "ls180.v:4587.1-4659.4" wire width 3 $0\builder_sdphy_fsm_next_state[2:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 3 $0\builder_sdphy_fsm_state[2:0] - attribute \src "ls180.v:4436.1-4529.4" + attribute \src "ls180.v:4432.1-4525.4" wire width 3 $0\builder_sdphy_sdphycmdr_next_state[2:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 3 $0\builder_sdphy_sdphycmdr_state[2:0] - attribute \src "ls180.v:4326.1-4402.4" + attribute \src "ls180.v:4322.1-4398.4" wire width 2 $0\builder_sdphy_sdphycmdw_next_state[1:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 2 $0\builder_sdphy_sdphycmdw_state[1:0] - attribute \src "ls180.v:4563.1-4590.4" + attribute \src "ls180.v:4559.1-4586.4" wire $0\builder_sdphy_sdphycrcr_next_state[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\builder_sdphy_sdphycrcr_state[0:0] - attribute \src "ls180.v:4697.1-4798.4" + attribute \src "ls180.v:4693.1-4794.4" wire width 3 $0\builder_sdphy_sdphydatar_next_state[2:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 3 $0\builder_sdphy_sdphydatar_state[2:0] - attribute \src "ls180.v:4292.1-4325.4" + attribute \src "ls180.v:4288.1-4321.4" wire $0\builder_sdphy_sdphyinit_next_state[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\builder_sdphy_sdphyinit_state[0:0] - attribute \src "ls180.v:5709.1-5720.4" + attribute \src "ls180.v:5705.1-5716.4" wire $0\builder_shared_ack[0:0] - attribute \src "ls180.v:5709.1-5720.4" + attribute \src "ls180.v:5705.1-5716.4" wire width 32 $0\builder_shared_dat_r[31:0] - attribute \src "ls180.v:5659.1-5666.4" + attribute \src "ls180.v:5655.1-5662.4" wire width 5 $0\builder_slave_sel[4:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 5 $0\builder_slave_sel_r[4:0] - attribute \src "ls180.v:4186.1-4234.4" + attribute \src "ls180.v:4182.1-4230.4" wire width 2 $0\builder_spimaster0_next_state[1:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 2 $0\builder_spimaster0_state[1:0] - attribute \src "ls180.v:5549.1-5597.4" + attribute \src "ls180.v:5545.1-5593.4" wire width 2 $0\builder_spimaster1_next_state[1:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 2 $0\builder_spimaster1_state[1:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 2 $0\builder_state[1:0] - attribute \src "ls180.v:7133.1-7161.4" + attribute \src "ls180.v:7129.1-7157.4" wire $0\builder_sync_f_array_muxed0[0:0] - attribute \src "ls180.v:7162.1-7190.4" + attribute \src "ls180.v:7158.1-7186.4" wire $0\builder_sync_f_array_muxed1[0:0] - attribute \src "ls180.v:7014.1-7030.4" + attribute \src "ls180.v:7010.1-7026.4" wire width 2 $0\builder_sync_rhs_array_muxed0[1:0] - attribute \src "ls180.v:7031.1-7047.4" + attribute \src "ls180.v:7027.1-7043.4" wire width 13 $0\builder_sync_rhs_array_muxed1[12:0] - attribute \src "ls180.v:7048.1-7064.4" + attribute \src "ls180.v:7044.1-7060.4" wire $0\builder_sync_rhs_array_muxed2[0:0] - attribute \src "ls180.v:7065.1-7081.4" + attribute \src "ls180.v:7061.1-7077.4" wire $0\builder_sync_rhs_array_muxed3[0:0] - attribute \src "ls180.v:7082.1-7098.4" + attribute \src "ls180.v:7078.1-7094.4" wire $0\builder_sync_rhs_array_muxed4[0:0] - attribute \src "ls180.v:7099.1-7115.4" + attribute \src "ls180.v:7095.1-7111.4" wire $0\builder_sync_rhs_array_muxed5[0:0] - attribute \src "ls180.v:7116.1-7132.4" + attribute \src "ls180.v:7112.1-7128.4" wire $0\builder_sync_rhs_array_muxed6[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 16 $0\libresocsim_clk_divider1[15:0] - attribute \src "ls180.v:5549.1-5597.4" + attribute \src "ls180.v:5545.1-5593.4" wire $0\libresocsim_clk_enable[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\libresocsim_control_re[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 16 $0\libresocsim_control_storage[15:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 3 $0\libresocsim_count[2:0] - attribute \src "ls180.v:5549.1-5597.4" + attribute \src "ls180.v:5545.1-5593.4" wire width 3 $0\libresocsim_count_spimaster1_next_value[2:0] - attribute \src "ls180.v:5549.1-5597.4" + attribute \src "ls180.v:5545.1-5593.4" wire $0\libresocsim_count_spimaster1_next_value_ce[0:0] - attribute \src "ls180.v:5549.1-5597.4" + attribute \src "ls180.v:5545.1-5593.4" wire $0\libresocsim_cs_enable[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\libresocsim_cs_re[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\libresocsim_cs_storage[0:0] - attribute \src "ls180.v:5549.1-5597.4" + attribute \src "ls180.v:5545.1-5593.4" wire $0\libresocsim_done0[0:0] - attribute \src "ls180.v:5549.1-5597.4" + attribute \src "ls180.v:5545.1-5593.4" wire $0\libresocsim_irq[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\libresocsim_loopback_re[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\libresocsim_loopback_storage[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 8 $0\libresocsim_miso[7:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 8 $0\libresocsim_miso_data[7:0] - attribute \src "ls180.v:5549.1-5597.4" + attribute \src "ls180.v:5545.1-5593.4" wire $0\libresocsim_miso_latch[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 8 $0\libresocsim_mosi_data[7:0] - attribute \src "ls180.v:5549.1-5597.4" + attribute \src "ls180.v:5545.1-5593.4" wire $0\libresocsim_mosi_latch[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\libresocsim_mosi_re[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 3 $0\libresocsim_mosi_sel[2:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 8 $0\libresocsim_mosi_storage[7:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\libresocsim_re[0:0] - attribute \src "ls180.v:6266.1-6271.4" + attribute \src "ls180.v:6262.1-6267.4" wire $0\libresocsim_start1[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 16 $0\libresocsim_storage[15:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_cmd_consumed[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_converter_counter[0:0] - attribute \src "ls180.v:3996.1-4042.4" + attribute \src "ls180.v:3992.1-4038.4" wire $0\main_converter_counter_converter_next_value[0:0] - attribute \src "ls180.v:3996.1-4042.4" + attribute \src "ls180.v:3992.1-4038.4" wire $0\main_converter_counter_converter_next_value_ce[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 32 $0\main_converter_dat_r[31:0] - attribute \src "ls180.v:3996.1-4042.4" + attribute \src "ls180.v:3992.1-4038.4" wire $0\main_converter_skip[0:0] - attribute \src "ls180.v:7289.1-7357.4" + attribute \src "ls180.v:7287.1-7357.4" wire width 16 $0\main_dfi_p0_rddata[15:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_dfi_p0_rddata_valid[0:0] - attribute \src "ls180.v:2931.1-2935.4" - wire width 2 $0\main_dm[1:0] - attribute \src "ls180.v:7359.1-9977.4" - wire width 43 $0\main_dummy[42:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" + wire width 42 $0\main_dummy[41:0] + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_gpio_oe_re[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 16 $0\main_gpio_oe_storage[15:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_gpio_out_re[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 16 $0\main_gpio_out_storage[15:0] - attribute \src "ls180.v:7246.1-7264.4" + attribute \src "ls180.v:7244.1-7262.4" wire width 16 $0\main_gpio_status[15:0] - attribute \src "ls180.v:7285.1-7287.4" + attribute \src "ls180.v:7283.1-7285.4" wire $0\main_int_rst[0:0] - attribute \src "ls180.v:1481.11-1481.41" - wire width 2 $0\main_interface0_bus_bte[1:0] attribute \src "ls180.v:1480.11-1480.41" + wire width 2 $0\main_interface0_bus_bte[1:0] + attribute \src "ls180.v:1479.11-1479.41" wire width 3 $0\main_interface0_bus_cti[2:0] - attribute \src "ls180.v:5408.1-5445.4" + attribute \src "ls180.v:5404.1-5441.4" wire width 32 $0\main_interface1_bus_adr[31:0] - attribute \src "ls180.v:1572.11-1572.41" - wire width 2 $0\main_interface1_bus_bte[1:0] attribute \src "ls180.v:1571.11-1571.41" + wire width 2 $0\main_interface1_bus_bte[1:0] + attribute \src "ls180.v:1570.11-1570.41" wire width 3 $0\main_interface1_bus_cti[2:0] - attribute \src "ls180.v:5408.1-5445.4" + attribute \src "ls180.v:5404.1-5441.4" wire $0\main_interface1_bus_cyc[0:0] - attribute \src "ls180.v:1564.12-1564.45" + attribute \src "ls180.v:1563.12-1563.45" wire width 32 $0\main_interface1_bus_dat_w[31:0] - attribute \src "ls180.v:5408.1-5445.4" + attribute \src "ls180.v:5404.1-5441.4" wire width 4 $0\main_interface1_bus_sel[3:0] - attribute \src "ls180.v:5408.1-5445.4" + attribute \src "ls180.v:5404.1-5441.4" wire $0\main_interface1_bus_stb[0:0] - attribute \src "ls180.v:5408.1-5445.4" + attribute \src "ls180.v:5404.1-5441.4" wire $0\main_interface1_bus_we[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 32 $0\main_libresocsim_bus_errors[31:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_libresocsim_converter0_counter[0:0] - attribute \src "ls180.v:2738.1-2784.4" + attribute \src "ls180.v:2739.1-2785.4" wire $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] - attribute \src "ls180.v:2738.1-2784.4" + attribute \src "ls180.v:2739.1-2785.4" wire $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 64 $0\main_libresocsim_converter0_dat_r[63:0] - attribute \src "ls180.v:2738.1-2784.4" + attribute \src "ls180.v:2739.1-2785.4" wire $0\main_libresocsim_converter0_skip[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_libresocsim_converter1_counter[0:0] - attribute \src "ls180.v:2798.1-2844.4" + attribute \src "ls180.v:2799.1-2845.4" wire $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] - attribute \src "ls180.v:2798.1-2844.4" + attribute \src "ls180.v:2799.1-2845.4" wire $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 64 $0\main_libresocsim_converter1_dat_r[63:0] - attribute \src "ls180.v:2798.1-2844.4" + attribute \src "ls180.v:2799.1-2845.4" wire $0\main_libresocsim_converter1_skip[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_libresocsim_converter2_counter[0:0] - attribute \src "ls180.v:2858.1-2904.4" + attribute \src "ls180.v:2859.1-2905.4" wire $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] - attribute \src "ls180.v:2858.1-2904.4" + attribute \src "ls180.v:2859.1-2905.4" wire $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 64 $0\main_libresocsim_converter2_dat_r[63:0] - attribute \src "ls180.v:2858.1-2904.4" + attribute \src "ls180.v:2859.1-2905.4" wire $0\main_libresocsim_converter2_skip[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_libresocsim_en_re[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_libresocsim_en_storage[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_libresocsim_eventmanager_re[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_libresocsim_eventmanager_storage[0:0] - attribute \src "ls180.v:2738.1-2784.4" + attribute \src "ls180.v:2739.1-2785.4" wire width 30 $0\main_libresocsim_interface0_converted_interface_adr[29:0] attribute \src "ls180.v:139.11-139.69" wire width 2 $0\main_libresocsim_interface0_converted_interface_bte[1:0] attribute \src "ls180.v:138.11-138.69" wire width 3 $0\main_libresocsim_interface0_converted_interface_cti[2:0] - attribute \src "ls180.v:2738.1-2784.4" + attribute \src "ls180.v:2739.1-2785.4" wire $0\main_libresocsim_interface0_converted_interface_cyc[0:0] - attribute \src "ls180.v:2726.1-2736.4" + attribute \src "ls180.v:2727.1-2737.4" wire width 32 $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] - attribute \src "ls180.v:2738.1-2784.4" + attribute \src "ls180.v:2739.1-2785.4" wire width 4 $0\main_libresocsim_interface0_converted_interface_sel[3:0] - attribute \src "ls180.v:2738.1-2784.4" + attribute \src "ls180.v:2739.1-2785.4" wire $0\main_libresocsim_interface0_converted_interface_stb[0:0] - attribute \src "ls180.v:2738.1-2784.4" + attribute \src "ls180.v:2739.1-2785.4" wire $0\main_libresocsim_interface0_converted_interface_we[0:0] - attribute \src "ls180.v:2798.1-2844.4" + attribute \src "ls180.v:2799.1-2845.4" wire width 30 $0\main_libresocsim_interface1_converted_interface_adr[29:0] attribute \src "ls180.v:154.11-154.69" wire width 2 $0\main_libresocsim_interface1_converted_interface_bte[1:0] attribute \src "ls180.v:153.11-153.69" wire width 3 $0\main_libresocsim_interface1_converted_interface_cti[2:0] - attribute \src "ls180.v:2798.1-2844.4" + attribute \src "ls180.v:2799.1-2845.4" wire $0\main_libresocsim_interface1_converted_interface_cyc[0:0] - attribute \src "ls180.v:2786.1-2796.4" + attribute \src "ls180.v:2787.1-2797.4" wire width 32 $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] - attribute \src "ls180.v:2798.1-2844.4" + attribute \src "ls180.v:2799.1-2845.4" wire width 4 $0\main_libresocsim_interface1_converted_interface_sel[3:0] - attribute \src "ls180.v:2798.1-2844.4" + attribute \src "ls180.v:2799.1-2845.4" wire $0\main_libresocsim_interface1_converted_interface_stb[0:0] - attribute \src "ls180.v:2798.1-2844.4" + attribute \src "ls180.v:2799.1-2845.4" wire $0\main_libresocsim_interface1_converted_interface_we[0:0] - attribute \src "ls180.v:2858.1-2904.4" + attribute \src "ls180.v:2859.1-2905.4" wire width 30 $0\main_libresocsim_interface2_converted_interface_adr[29:0] attribute \src "ls180.v:169.11-169.69" wire width 2 $0\main_libresocsim_interface2_converted_interface_bte[1:0] attribute \src "ls180.v:168.11-168.69" wire width 3 $0\main_libresocsim_interface2_converted_interface_cti[2:0] - attribute \src "ls180.v:2858.1-2904.4" + attribute \src "ls180.v:2859.1-2905.4" wire $0\main_libresocsim_interface2_converted_interface_cyc[0:0] - attribute \src "ls180.v:2846.1-2856.4" + attribute \src "ls180.v:2847.1-2857.4" wire width 32 $0\main_libresocsim_interface2_converted_interface_dat_w[31:0] - attribute \src "ls180.v:2858.1-2904.4" + attribute \src "ls180.v:2859.1-2905.4" wire width 4 $0\main_libresocsim_interface2_converted_interface_sel[3:0] - attribute \src "ls180.v:2858.1-2904.4" + attribute \src "ls180.v:2859.1-2905.4" wire $0\main_libresocsim_interface2_converted_interface_stb[0:0] - attribute \src "ls180.v:2858.1-2904.4" + attribute \src "ls180.v:2859.1-2905.4" wire $0\main_libresocsim_interface2_converted_interface_we[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] - attribute \src "ls180.v:2798.1-2844.4" + attribute \src "ls180.v:2799.1-2845.4" wire $0\main_libresocsim_libresoc_dbus_ack[0:0] attribute \src "ls180.v:70.5-70.46" wire $0\main_libresocsim_libresoc_dbus_err[0:0] - attribute \src "ls180.v:2738.1-2784.4" + attribute \src "ls180.v:2739.1-2785.4" wire $0\main_libresocsim_libresoc_ibus_ack[0:0] attribute \src "ls180.v:81.5-81.46" wire $0\main_libresocsim_libresoc_ibus_err[0:0] - attribute \src "ls180.v:2719.1-2724.4" + attribute \src "ls180.v:2720.1-2725.4" wire width 16 $0\main_libresocsim_libresoc_interrupt[15:0] - attribute \src "ls180.v:2858.1-2904.4" + attribute \src "ls180.v:2859.1-2905.4" wire $0\main_libresocsim_libresoc_jtag_wb_ack[0:0] attribute \src "ls180.v:112.5-112.49" wire $0\main_libresocsim_libresoc_jtag_wb_err[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_libresocsim_load_re[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 32 $0\main_libresocsim_load_storage[31:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_libresocsim_ram_bus_ack[0:0] attribute \src "ls180.v:185.5-185.40" wire $0\main_libresocsim_ram_bus_err[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_libresocsim_reload_re[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 32 $0\main_libresocsim_reload_storage[31:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_libresocsim_reset_re[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_libresocsim_reset_storage[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_libresocsim_scratch_re[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 32 $0\main_libresocsim_scratch_storage[31:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_libresocsim_update_value_re[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_libresocsim_update_value_storage[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 32 $0\main_libresocsim_value[31:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 32 $0\main_libresocsim_value_status[31:0] - attribute \src "ls180.v:2907.1-2913.4" + attribute \src "ls180.v:2908.1-2914.4" wire width 4 $0\main_libresocsim_we[3:0] - attribute \src "ls180.v:2919.1-2924.4" + attribute \src "ls180.v:2920.1-2925.4" wire $0\main_libresocsim_zero_clear[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_libresocsim_zero_old_trigger[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_libresocsim_zero_pending[0:0] - attribute \src "ls180.v:3996.1-4042.4" + attribute \src "ls180.v:3992.1-4038.4" wire width 30 $0\main_litedram_wb_adr[29:0] - attribute \src "ls180.v:3996.1-4042.4" + attribute \src "ls180.v:3992.1-4038.4" wire $0\main_litedram_wb_cyc[0:0] - attribute \src "ls180.v:3984.1-3994.4" + attribute \src "ls180.v:3980.1-3990.4" wire width 16 $0\main_litedram_wb_dat_w[15:0] - attribute \src "ls180.v:3996.1-4042.4" + attribute \src "ls180.v:3992.1-4038.4" wire width 2 $0\main_litedram_wb_sel[1:0] - attribute \src "ls180.v:3996.1-4042.4" + attribute \src "ls180.v:3992.1-4038.4" wire $0\main_litedram_wb_stb[0:0] - attribute \src "ls180.v:3996.1-4042.4" + attribute \src "ls180.v:3992.1-4038.4" wire $0\main_litedram_wb_we[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 32 $0\main_phase_accumulator_rx[31:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 32 $0\main_phase_accumulator_tx[31:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 32 $0\main_pwm0_counter[31:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_pwm0_enable_re[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_pwm0_enable_storage[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_pwm0_period_re[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 32 $0\main_pwm0_period_storage[31:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_pwm0_width_re[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 32 $0\main_pwm0_width_storage[31:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 32 $0\main_pwm1_counter[31:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_pwm1_enable_re[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_pwm1_enable_storage[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_pwm1_period_re[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 32 $0\main_pwm1_period_storage[31:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_pwm1_width_re[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 32 $0\main_pwm1_width_storage[31:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 3 $0\main_rddata_en[2:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_re[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 4 $0\main_rx_bitcount[3:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_rx_busy[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_rx_r[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 8 $0\main_rx_reg[7:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 2 $0\main_sdblock2mem_converter_demux[1:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdblock2mem_converter_source_first[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdblock2mem_converter_source_last[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 32 $0\main_sdblock2mem_converter_source_payload_data[31:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 3 $0\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdblock2mem_converter_strobe_all[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 5 $0\main_sdblock2mem_fifo_consume[4:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 6 $0\main_sdblock2mem_fifo_level[5:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 5 $0\main_sdblock2mem_fifo_produce[4:0] - attribute \src "ls180.v:1505.5-1505.41" + attribute \src "ls180.v:1504.5-1504.41" wire $0\main_sdblock2mem_fifo_replace[0:0] - attribute \src "ls180.v:5316.1-5323.4" + attribute \src "ls180.v:5312.1-5319.4" wire width 5 $0\main_sdblock2mem_fifo_wrport_adr[4:0] - attribute \src "ls180.v:5349.1-5388.4" + attribute \src "ls180.v:5345.1-5384.4" wire width 32 $0\main_sdblock2mem_sink_sink_payload_address[31:0] - attribute \src "ls180.v:5349.1-5388.4" + attribute \src "ls180.v:5345.1-5384.4" wire width 32 $0\main_sdblock2mem_sink_sink_payload_data1[31:0] - attribute \src "ls180.v:5349.1-5388.4" + attribute \src "ls180.v:5345.1-5384.4" wire $0\main_sdblock2mem_sink_sink_valid1[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 64 $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 32 $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 32 $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] - attribute \src "ls180.v:5349.1-5388.4" + attribute \src "ls180.v:5345.1-5384.4" wire width 32 $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] - attribute \src "ls180.v:5349.1-5388.4" + attribute \src "ls180.v:5345.1-5384.4" wire $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] - attribute \src "ls180.v:5349.1-5388.4" + attribute \src "ls180.v:5345.1-5384.4" wire $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] - attribute \src "ls180.v:5349.1-5388.4" + attribute \src "ls180.v:5345.1-5384.4" wire $0\main_sdblock2mem_wishbonedmawriter_status[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdcore_block_count_re[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 32 $0\main_sdcore_block_count_storage[31:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdcore_block_length_re[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 10 $0\main_sdcore_block_length_storage[9:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdcore_cmd_argument_re[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 32 $0\main_sdcore_cmd_argument_storage[31:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdcore_cmd_command_re[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 32 $0\main_sdcore_cmd_command_storage[31:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 3 $0\main_sdcore_cmd_count[2:0] - attribute \src "ls180.v:5098.1-5288.4" + attribute \src "ls180.v:5094.1-5284.4" wire width 3 $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] - attribute \src "ls180.v:5098.1-5288.4" + attribute \src "ls180.v:5094.1-5284.4" wire $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdcore_cmd_done[0:0] - attribute \src "ls180.v:5098.1-5288.4" + attribute \src "ls180.v:5094.1-5284.4" wire $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] - attribute \src "ls180.v:5098.1-5288.4" + attribute \src "ls180.v:5094.1-5284.4" wire $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdcore_cmd_error[0:0] - attribute \src "ls180.v:5098.1-5288.4" + attribute \src "ls180.v:5094.1-5284.4" wire $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] - attribute \src "ls180.v:5098.1-5288.4" + attribute \src "ls180.v:5094.1-5284.4" wire $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 128 $0\main_sdcore_cmd_response_status[127:0] - attribute \src "ls180.v:5098.1-5288.4" + attribute \src "ls180.v:5094.1-5284.4" wire width 128 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] - attribute \src "ls180.v:5098.1-5288.4" + attribute \src "ls180.v:5094.1-5284.4" wire $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] - attribute \src "ls180.v:1314.5-1314.34" + attribute \src "ls180.v:1313.5-1313.34" wire $0\main_sdcore_cmd_send_w[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdcore_cmd_timeout[0:0] - attribute \src "ls180.v:5098.1-5288.4" + attribute \src "ls180.v:5094.1-5284.4" wire $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] - attribute \src "ls180.v:5098.1-5288.4" + attribute \src "ls180.v:5094.1-5284.4" wire $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 4 $0\main_sdcore_crc16_checker_cnt[3:0] - attribute \src "ls180.v:5004.1-5011.4" + attribute \src "ls180.v:5000.1-5007.4" wire $0\main_sdcore_crc16_checker_crc0_clr[0:0] - attribute \src "ls180.v:5060.1-5067.4" + attribute \src "ls180.v:5056.1-5063.4" wire width 16 $0\main_sdcore_crc16_checker_crc0_crc[15:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 16 $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] - attribute \src "ls180.v:5014.1-5021.4" + attribute \src "ls180.v:5010.1-5017.4" wire $0\main_sdcore_crc16_checker_crc1_clr[0:0] - attribute \src "ls180.v:5070.1-5077.4" + attribute \src "ls180.v:5066.1-5073.4" wire width 16 $0\main_sdcore_crc16_checker_crc1_crc[15:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 16 $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] - attribute \src "ls180.v:5024.1-5031.4" + attribute \src "ls180.v:5020.1-5027.4" wire $0\main_sdcore_crc16_checker_crc2_clr[0:0] - attribute \src "ls180.v:5080.1-5087.4" + attribute \src "ls180.v:5076.1-5083.4" wire width 16 $0\main_sdcore_crc16_checker_crc2_crc[15:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 16 $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] - attribute \src "ls180.v:5034.1-5041.4" + attribute \src "ls180.v:5030.1-5037.4" wire $0\main_sdcore_crc16_checker_crc3_clr[0:0] - attribute \src "ls180.v:5090.1-5097.4" + attribute \src "ls180.v:5086.1-5093.4" wire width 16 $0\main_sdcore_crc16_checker_crc3_crc[15:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 16 $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 16 $0\main_sdcore_crc16_checker_crctmp0[15:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 16 $0\main_sdcore_crc16_checker_crctmp1[15:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 16 $0\main_sdcore_crc16_checker_crctmp2[15:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 16 $0\main_sdcore_crc16_checker_crctmp3[15:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 16 $0\main_sdcore_crc16_checker_fifo0[15:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 16 $0\main_sdcore_crc16_checker_fifo1[15:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 16 $0\main_sdcore_crc16_checker_fifo2[15:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 16 $0\main_sdcore_crc16_checker_fifo3[15:0] - attribute \src "ls180.v:5098.1-5288.4" + attribute \src "ls180.v:5094.1-5284.4" wire $0\main_sdcore_crc16_checker_sink_first[0:0] - attribute \src "ls180.v:5098.1-5288.4" + attribute \src "ls180.v:5094.1-5284.4" wire $0\main_sdcore_crc16_checker_sink_last[0:0] - attribute \src "ls180.v:5098.1-5288.4" + attribute \src "ls180.v:5094.1-5284.4" wire width 8 $0\main_sdcore_crc16_checker_sink_payload_data[7:0] - attribute \src "ls180.v:5049.1-5056.4" + attribute \src "ls180.v:5045.1-5052.4" wire $0\main_sdcore_crc16_checker_sink_ready[0:0] - attribute \src "ls180.v:5098.1-5288.4" + attribute \src "ls180.v:5094.1-5284.4" wire $0\main_sdcore_crc16_checker_sink_valid[0:0] - attribute \src "ls180.v:1420.5-1420.50" + attribute \src "ls180.v:1419.5-1419.50" wire $0\main_sdcore_crc16_checker_source_first[0:0] - attribute \src "ls180.v:5043.1-5048.4" + attribute \src "ls180.v:5039.1-5044.4" wire $0\main_sdcore_crc16_checker_source_valid[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 8 $0\main_sdcore_crc16_checker_val[7:0] - attribute \src "ls180.v:4996.1-5001.4" + attribute \src "ls180.v:4992.1-4997.4" wire $0\main_sdcore_crc16_checker_valid[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 3 $0\main_sdcore_crc16_inserter_cnt[2:0] - attribute \src "ls180.v:4916.1-4995.4" + attribute \src "ls180.v:4912.1-4991.4" wire width 3 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] - attribute \src "ls180.v:4916.1-4995.4" + attribute \src "ls180.v:4912.1-4991.4" wire $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] - attribute \src "ls180.v:4878.1-4885.4" + attribute \src "ls180.v:4874.1-4881.4" wire width 16 $0\main_sdcore_crc16_inserter_crc0_crc[15:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 16 $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] - attribute \src "ls180.v:4888.1-4895.4" + attribute \src "ls180.v:4884.1-4891.4" wire width 16 $0\main_sdcore_crc16_inserter_crc1_crc[15:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 16 $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] - attribute \src "ls180.v:4898.1-4905.4" + attribute \src "ls180.v:4894.1-4901.4" wire width 16 $0\main_sdcore_crc16_inserter_crc2_crc[15:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 16 $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] - attribute \src "ls180.v:4908.1-4915.4" + attribute \src "ls180.v:4904.1-4911.4" wire width 16 $0\main_sdcore_crc16_inserter_crc3_crc[15:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 16 $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 16 $0\main_sdcore_crc16_inserter_crctmp0[15:0] - attribute \src "ls180.v:4916.1-4995.4" + attribute \src "ls180.v:4912.1-4991.4" wire width 16 $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] - attribute \src "ls180.v:4916.1-4995.4" + attribute \src "ls180.v:4912.1-4991.4" wire $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 16 $0\main_sdcore_crc16_inserter_crctmp1[15:0] - attribute \src "ls180.v:4916.1-4995.4" + attribute \src "ls180.v:4912.1-4991.4" wire width 16 $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] - attribute \src "ls180.v:4916.1-4995.4" + attribute \src "ls180.v:4912.1-4991.4" wire $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 16 $0\main_sdcore_crc16_inserter_crctmp2[15:0] - attribute \src "ls180.v:4916.1-4995.4" + attribute \src "ls180.v:4912.1-4991.4" wire width 16 $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] - attribute \src "ls180.v:4916.1-4995.4" + attribute \src "ls180.v:4912.1-4991.4" wire $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 16 $0\main_sdcore_crc16_inserter_crctmp3[15:0] - attribute \src "ls180.v:4916.1-4995.4" + attribute \src "ls180.v:4912.1-4991.4" wire width 16 $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] - attribute \src "ls180.v:4916.1-4995.4" + attribute \src "ls180.v:4912.1-4991.4" wire $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] - attribute \src "ls180.v:4916.1-4995.4" + attribute \src "ls180.v:4912.1-4991.4" wire $0\main_sdcore_crc16_inserter_sink_ready[0:0] - attribute \src "ls180.v:1377.5-1377.51" + attribute \src "ls180.v:1376.5-1376.51" wire $0\main_sdcore_crc16_inserter_source_first[0:0] - attribute \src "ls180.v:4916.1-4995.4" + attribute \src "ls180.v:4912.1-4991.4" wire $0\main_sdcore_crc16_inserter_source_last[0:0] - attribute \src "ls180.v:4916.1-4995.4" + attribute \src "ls180.v:4912.1-4991.4" wire width 8 $0\main_sdcore_crc16_inserter_source_payload_data[7:0] - attribute \src "ls180.v:5098.1-5288.4" + attribute \src "ls180.v:5094.1-5284.4" wire $0\main_sdcore_crc16_inserter_source_ready[0:0] - attribute \src "ls180.v:4916.1-4995.4" + attribute \src "ls180.v:4912.1-4991.4" wire $0\main_sdcore_crc16_inserter_source_valid[0:0] - attribute \src "ls180.v:4856.1-4863.4" + attribute \src "ls180.v:4852.1-4859.4" wire width 7 $0\main_sdcore_crc7_inserter_crc[6:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 7 $0\main_sdcore_crc7_inserter_crcreg0[6:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 32 $0\main_sdcore_data_count[31:0] - attribute \src "ls180.v:5098.1-5288.4" + attribute \src "ls180.v:5094.1-5284.4" wire width 32 $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] - attribute \src "ls180.v:5098.1-5288.4" + attribute \src "ls180.v:5094.1-5284.4" wire $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdcore_data_done[0:0] - attribute \src "ls180.v:5098.1-5288.4" + attribute \src "ls180.v:5094.1-5284.4" wire $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] - attribute \src "ls180.v:5098.1-5288.4" + attribute \src "ls180.v:5094.1-5284.4" wire $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdcore_data_error[0:0] - attribute \src "ls180.v:5098.1-5288.4" + attribute \src "ls180.v:5094.1-5284.4" wire $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] - attribute \src "ls180.v:5098.1-5288.4" + attribute \src "ls180.v:5094.1-5284.4" wire $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdcore_data_timeout[0:0] - attribute \src "ls180.v:5098.1-5288.4" + attribute \src "ls180.v:5094.1-5284.4" wire $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] - attribute \src "ls180.v:5098.1-5288.4" + attribute \src "ls180.v:5094.1-5284.4" wire $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 2 $0\main_sdmem2block_converter_mux[1:0] - attribute \src "ls180.v:5494.1-5510.4" + attribute \src "ls180.v:5490.1-5506.4" wire width 8 $0\main_sdmem2block_converter_source_payload_data[7:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdmem2block_dma_base_re[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 64 $0\main_sdmem2block_dma_base_storage[63:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 32 $0\main_sdmem2block_dma_data[31:0] - attribute \src "ls180.v:5408.1-5445.4" + attribute \src "ls180.v:5404.1-5441.4" wire width 32 $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] - attribute \src "ls180.v:5408.1-5445.4" + attribute \src "ls180.v:5404.1-5441.4" wire $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] - attribute \src "ls180.v:5446.1-5482.4" + attribute \src "ls180.v:5442.1-5478.4" wire $0\main_sdmem2block_dma_done_status[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdmem2block_dma_enable_re[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdmem2block_dma_enable_storage[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdmem2block_dma_length_re[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 32 $0\main_sdmem2block_dma_length_storage[31:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdmem2block_dma_loop_re[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdmem2block_dma_loop_storage[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 32 $0\main_sdmem2block_dma_offset[31:0] - attribute \src "ls180.v:5446.1-5482.4" + attribute \src "ls180.v:5442.1-5478.4" wire width 32 $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] - attribute \src "ls180.v:5446.1-5482.4" + attribute \src "ls180.v:5442.1-5478.4" wire $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] - attribute \src "ls180.v:5446.1-5482.4" + attribute \src "ls180.v:5442.1-5478.4" wire $0\main_sdmem2block_dma_sink_last[0:0] - attribute \src "ls180.v:5446.1-5482.4" + attribute \src "ls180.v:5442.1-5478.4" wire width 32 $0\main_sdmem2block_dma_sink_payload_address[31:0] - attribute \src "ls180.v:5408.1-5445.4" + attribute \src "ls180.v:5404.1-5441.4" wire $0\main_sdmem2block_dma_sink_ready[0:0] - attribute \src "ls180.v:5446.1-5482.4" + attribute \src "ls180.v:5442.1-5478.4" wire $0\main_sdmem2block_dma_sink_valid[0:0] - attribute \src "ls180.v:1585.5-1585.45" + attribute \src "ls180.v:1584.5-1584.45" wire $0\main_sdmem2block_dma_source_first[0:0] - attribute \src "ls180.v:5408.1-5445.4" + attribute \src "ls180.v:5404.1-5441.4" wire $0\main_sdmem2block_dma_source_last[0:0] - attribute \src "ls180.v:5408.1-5445.4" + attribute \src "ls180.v:5404.1-5441.4" wire width 32 $0\main_sdmem2block_dma_source_payload_data[31:0] - attribute \src "ls180.v:5408.1-5445.4" + attribute \src "ls180.v:5404.1-5441.4" wire $0\main_sdmem2block_dma_source_valid[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 5 $0\main_sdmem2block_fifo_consume[4:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 6 $0\main_sdmem2block_fifo_level[5:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 5 $0\main_sdmem2block_fifo_produce[4:0] - attribute \src "ls180.v:1641.5-1641.41" + attribute \src "ls180.v:1640.5-1640.41" wire $0\main_sdmem2block_fifo_replace[0:0] - attribute \src "ls180.v:5524.1-5531.4" + attribute \src "ls180.v:5520.1-5527.4" wire width 5 $0\main_sdmem2block_fifo_wrport_adr[4:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdphy_clocker_clk0[0:0] - attribute \src "ls180.v:4262.1-4290.4" + attribute \src "ls180.v:4258.1-4286.4" wire $0\main_sdphy_clocker_clk1[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdphy_clocker_clk_d[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 9 $0\main_sdphy_clocker_clks[8:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdphy_clocker_re[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 9 $0\main_sdphy_clocker_storage[8:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 8 $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 3 $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] - attribute \src "ls180.v:1106.5-1106.53" + attribute \src "ls180.v:1105.5-1105.53" wire $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] - attribute \src "ls180.v:1107.5-1107.52" + attribute \src "ls180.v:1106.5-1106.52" wire $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 8 $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 4 $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] - attribute \src "ls180.v:1087.5-1087.46" + attribute \src "ls180.v:1086.5-1086.46" wire $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdphy_cmdr_cmdr_reset[0:0] - attribute \src "ls180.v:4436.1-4529.4" + attribute \src "ls180.v:4432.1-4525.4" wire $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] - attribute \src "ls180.v:4436.1-4529.4" + attribute \src "ls180.v:4432.1-4525.4" wire $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdphy_cmdr_cmdr_run[0:0] - attribute \src "ls180.v:4436.1-4529.4" + attribute \src "ls180.v:4432.1-4525.4" wire $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 8 $0\main_sdphy_cmdr_count[7:0] - attribute \src "ls180.v:4436.1-4529.4" + attribute \src "ls180.v:4432.1-4525.4" wire width 8 $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] - attribute \src "ls180.v:4436.1-4529.4" + attribute \src "ls180.v:4432.1-4525.4" wire $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] - attribute \src "ls180.v:1060.5-1060.49" + attribute \src "ls180.v:1059.5-1059.49" wire $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] - attribute \src "ls180.v:1061.5-1061.48" + attribute \src "ls180.v:1060.5-1060.48" wire $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] - attribute \src "ls180.v:1062.5-1062.55" + attribute \src "ls180.v:1061.5-1061.55" wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] - attribute \src "ls180.v:1064.5-1064.57" + attribute \src "ls180.v:1063.5-1063.57" wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] - attribute \src "ls180.v:1065.5-1065.58" + attribute \src "ls180.v:1064.5-1064.58" wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] - attribute \src "ls180.v:1067.11-1067.64" + attribute \src "ls180.v:1066.11-1066.64" wire width 4 $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] - attribute \src "ls180.v:1068.5-1068.59" + attribute \src "ls180.v:1067.5-1067.59" wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] - attribute \src "ls180.v:4436.1-4529.4" + attribute \src "ls180.v:4432.1-4525.4" wire $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] - attribute \src "ls180.v:4436.1-4529.4" + attribute \src "ls180.v:4432.1-4525.4" wire $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:4436.1-4529.4" + attribute \src "ls180.v:4432.1-4525.4" wire $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1073.11-1073.57" + attribute \src "ls180.v:1072.11-1072.57" wire width 4 $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:1074.5-1074.52" + attribute \src "ls180.v:1073.5-1073.52" wire $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:5098.1-5288.4" + attribute \src "ls180.v:5094.1-5284.4" wire $0\main_sdphy_cmdr_sink_last[0:0] - attribute \src "ls180.v:5098.1-5288.4" + attribute \src "ls180.v:5094.1-5284.4" wire width 8 $0\main_sdphy_cmdr_sink_payload_length[7:0] - attribute \src "ls180.v:4436.1-4529.4" + attribute \src "ls180.v:4432.1-4525.4" wire $0\main_sdphy_cmdr_sink_ready[0:0] - attribute \src "ls180.v:5098.1-5288.4" + attribute \src "ls180.v:5094.1-5284.4" wire $0\main_sdphy_cmdr_sink_valid[0:0] - attribute \src "ls180.v:4436.1-4529.4" + attribute \src "ls180.v:4432.1-4525.4" wire $0\main_sdphy_cmdr_source_last[0:0] - attribute \src "ls180.v:4436.1-4529.4" + attribute \src "ls180.v:4432.1-4525.4" wire width 8 $0\main_sdphy_cmdr_source_payload_data[7:0] - attribute \src "ls180.v:4436.1-4529.4" + attribute \src "ls180.v:4432.1-4525.4" wire width 3 $0\main_sdphy_cmdr_source_payload_status[2:0] - attribute \src "ls180.v:5098.1-5288.4" + attribute \src "ls180.v:5094.1-5284.4" wire $0\main_sdphy_cmdr_source_ready[0:0] - attribute \src "ls180.v:4436.1-4529.4" + attribute \src "ls180.v:4432.1-4525.4" wire $0\main_sdphy_cmdr_source_valid[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 32 $0\main_sdphy_cmdr_timeout[31:0] - attribute \src "ls180.v:4436.1-4529.4" + attribute \src "ls180.v:4432.1-4525.4" wire width 32 $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] - attribute \src "ls180.v:4436.1-4529.4" + attribute \src "ls180.v:4432.1-4525.4" wire $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 8 $0\main_sdphy_cmdw_count[7:0] - attribute \src "ls180.v:4326.1-4402.4" + attribute \src "ls180.v:4322.1-4398.4" wire width 8 $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] - attribute \src "ls180.v:4326.1-4402.4" + attribute \src "ls180.v:4322.1-4398.4" wire $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] - attribute \src "ls180.v:4326.1-4402.4" + attribute \src "ls180.v:4322.1-4398.4" wire $0\main_sdphy_cmdw_done[0:0] - attribute \src "ls180.v:4326.1-4402.4" + attribute \src "ls180.v:4322.1-4398.4" wire $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] - attribute \src "ls180.v:4326.1-4402.4" + attribute \src "ls180.v:4322.1-4398.4" wire $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:4326.1-4402.4" + attribute \src "ls180.v:4322.1-4398.4" wire $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1050.11-1050.57" + attribute \src "ls180.v:1049.11-1049.57" wire width 4 $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:1051.5-1051.52" + attribute \src "ls180.v:1050.5-1050.52" wire $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:5098.1-5288.4" + attribute \src "ls180.v:5094.1-5284.4" wire $0\main_sdphy_cmdw_sink_last[0:0] - attribute \src "ls180.v:5098.1-5288.4" + attribute \src "ls180.v:5094.1-5284.4" wire width 8 $0\main_sdphy_cmdw_sink_payload_data[7:0] - attribute \src "ls180.v:4326.1-4402.4" + attribute \src "ls180.v:4322.1-4398.4" wire $0\main_sdphy_cmdw_sink_ready[0:0] - attribute \src "ls180.v:5098.1-5288.4" + attribute \src "ls180.v:5094.1-5284.4" wire $0\main_sdphy_cmdw_sink_valid[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 10 $0\main_sdphy_datar_count[9:0] - attribute \src "ls180.v:4697.1-4798.4" + attribute \src "ls180.v:4693.1-4794.4" wire width 10 $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] - attribute \src "ls180.v:4697.1-4798.4" + attribute \src "ls180.v:4693.1-4794.4" wire $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdphy_datar_datar_buf_source_first[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdphy_datar_datar_buf_source_last[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 8 $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdphy_datar_datar_buf_source_valid[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdphy_datar_datar_converter_demux[0:0] - attribute \src "ls180.v:1262.5-1262.55" + attribute \src "ls180.v:1261.5-1261.55" wire $0\main_sdphy_datar_datar_converter_sink_first[0:0] - attribute \src "ls180.v:1263.5-1263.54" + attribute \src "ls180.v:1262.5-1262.54" wire $0\main_sdphy_datar_datar_converter_sink_last[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdphy_datar_datar_converter_source_first[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdphy_datar_datar_converter_source_last[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 8 $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 2 $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdphy_datar_datar_converter_strobe_all[0:0] - attribute \src "ls180.v:1243.5-1243.48" + attribute \src "ls180.v:1242.5-1242.48" wire $0\main_sdphy_datar_datar_pads_in_ready[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdphy_datar_datar_reset[0:0] - attribute \src "ls180.v:4697.1-4798.4" + attribute \src "ls180.v:4693.1-4794.4" wire $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] - attribute \src "ls180.v:4697.1-4798.4" + attribute \src "ls180.v:4693.1-4794.4" wire $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdphy_datar_datar_run[0:0] - attribute \src "ls180.v:4697.1-4798.4" + attribute \src "ls180.v:4693.1-4794.4" wire $0\main_sdphy_datar_datar_source_source_ready0[0:0] - attribute \src "ls180.v:1214.5-1214.50" + attribute \src "ls180.v:1213.5-1213.50" wire $0\main_sdphy_datar_pads_in_pads_in_first[0:0] - attribute \src "ls180.v:1215.5-1215.49" + attribute \src "ls180.v:1214.5-1214.49" wire $0\main_sdphy_datar_pads_in_pads_in_last[0:0] - attribute \src "ls180.v:1216.5-1216.56" + attribute \src "ls180.v:1215.5-1215.56" wire $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] - attribute \src "ls180.v:1218.5-1218.58" + attribute \src "ls180.v:1217.5-1217.58" wire $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] - attribute \src "ls180.v:1219.5-1219.59" + attribute \src "ls180.v:1218.5-1218.59" wire $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] - attribute \src "ls180.v:1221.11-1221.65" + attribute \src "ls180.v:1220.11-1220.65" wire width 4 $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] - attribute \src "ls180.v:1222.5-1222.60" + attribute \src "ls180.v:1221.5-1221.60" wire $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] - attribute \src "ls180.v:4697.1-4798.4" + attribute \src "ls180.v:4693.1-4794.4" wire $0\main_sdphy_datar_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1225.5-1225.51" + attribute \src "ls180.v:1224.5-1224.51" wire $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:1226.5-1226.52" + attribute \src "ls180.v:1225.5-1225.52" wire $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1227.11-1227.58" + attribute \src "ls180.v:1226.11-1226.58" wire width 4 $0\main_sdphy_datar_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:1228.5-1228.53" + attribute \src "ls180.v:1227.5-1227.53" wire $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:5098.1-5288.4" + attribute \src "ls180.v:5094.1-5284.4" wire $0\main_sdphy_datar_sink_last[0:0] - attribute \src "ls180.v:5098.1-5288.4" + attribute \src "ls180.v:5094.1-5284.4" wire width 10 $0\main_sdphy_datar_sink_payload_block_length[9:0] - attribute \src "ls180.v:4697.1-4798.4" + attribute \src "ls180.v:4693.1-4794.4" wire $0\main_sdphy_datar_sink_ready[0:0] - attribute \src "ls180.v:5098.1-5288.4" + attribute \src "ls180.v:5094.1-5284.4" wire $0\main_sdphy_datar_sink_valid[0:0] - attribute \src "ls180.v:1235.5-1235.41" + attribute \src "ls180.v:1234.5-1234.41" wire $0\main_sdphy_datar_source_first[0:0] - attribute \src "ls180.v:4697.1-4798.4" + attribute \src "ls180.v:4693.1-4794.4" wire $0\main_sdphy_datar_source_last[0:0] - attribute \src "ls180.v:4697.1-4798.4" + attribute \src "ls180.v:4693.1-4794.4" wire width 8 $0\main_sdphy_datar_source_payload_data[7:0] - attribute \src "ls180.v:4697.1-4798.4" + attribute \src "ls180.v:4693.1-4794.4" wire width 3 $0\main_sdphy_datar_source_payload_status[2:0] - attribute \src "ls180.v:5098.1-5288.4" + attribute \src "ls180.v:5094.1-5284.4" wire $0\main_sdphy_datar_source_ready[0:0] - attribute \src "ls180.v:4697.1-4798.4" + attribute \src "ls180.v:4693.1-4794.4" wire $0\main_sdphy_datar_source_valid[0:0] - attribute \src "ls180.v:4697.1-4798.4" + attribute \src "ls180.v:4693.1-4794.4" wire $0\main_sdphy_datar_stop[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 32 $0\main_sdphy_datar_timeout[31:0] - attribute \src "ls180.v:4697.1-4798.4" + attribute \src "ls180.v:4693.1-4794.4" wire width 32 $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] - attribute \src "ls180.v:4697.1-4798.4" + attribute \src "ls180.v:4693.1-4794.4" wire $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 8 $0\main_sdphy_dataw_count[7:0] - attribute \src "ls180.v:4591.1-4663.4" + attribute \src "ls180.v:4587.1-4659.4" wire width 8 $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] - attribute \src "ls180.v:4591.1-4663.4" + attribute \src "ls180.v:4587.1-4659.4" wire $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdphy_dataw_crcr_buf_source_first[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdphy_dataw_crcr_buf_source_last[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 8 $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 3 $0\main_sdphy_dataw_crcr_converter_demux[2:0] - attribute \src "ls180.v:1184.5-1184.54" + attribute \src "ls180.v:1183.5-1183.54" wire $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] - attribute \src "ls180.v:1185.5-1185.53" + attribute \src "ls180.v:1184.5-1184.53" wire $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdphy_dataw_crcr_converter_source_first[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdphy_dataw_crcr_converter_source_last[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 8 $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 4 $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] - attribute \src "ls180.v:1165.5-1165.47" + attribute \src "ls180.v:1164.5-1164.47" wire $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdphy_dataw_crcr_reset[0:0] - attribute \src "ls180.v:4563.1-4590.4" + attribute \src "ls180.v:4559.1-4586.4" wire $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] - attribute \src "ls180.v:4563.1-4590.4" + attribute \src "ls180.v:4559.1-4586.4" wire $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdphy_dataw_crcr_run[0:0] - attribute \src "ls180.v:4563.1-4590.4" + attribute \src "ls180.v:4559.1-4586.4" wire $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] - attribute \src "ls180.v:4563.1-4590.4" + attribute \src "ls180.v:4559.1-4586.4" wire $0\main_sdphy_dataw_error[0:0] - attribute \src "ls180.v:1152.5-1152.50" + attribute \src "ls180.v:1151.5-1151.50" wire $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] - attribute \src "ls180.v:1153.5-1153.49" + attribute \src "ls180.v:1152.5-1152.49" wire $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] - attribute \src "ls180.v:1154.5-1154.56" + attribute \src "ls180.v:1153.5-1153.56" wire $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] - attribute \src "ls180.v:1155.5-1155.58" + attribute \src "ls180.v:1154.5-1154.58" wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] - attribute \src "ls180.v:1156.5-1156.58" + attribute \src "ls180.v:1155.5-1155.58" wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] - attribute \src "ls180.v:1157.5-1157.59" + attribute \src "ls180.v:1156.5-1156.59" wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] - attribute \src "ls180.v:1158.11-1158.65" + attribute \src "ls180.v:1157.11-1157.65" wire width 4 $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] - attribute \src "ls180.v:1159.11-1159.65" + attribute \src "ls180.v:1158.11-1158.65" wire width 4 $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] - attribute \src "ls180.v:1160.5-1160.60" + attribute \src "ls180.v:1159.5-1159.60" wire $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] - attribute \src "ls180.v:1150.5-1150.50" + attribute \src "ls180.v:1149.5-1149.50" wire $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] - attribute \src "ls180.v:4591.1-4663.4" + attribute \src "ls180.v:4587.1-4659.4" wire $0\main_sdphy_dataw_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1139.5-1139.51" + attribute \src "ls180.v:1138.5-1138.51" wire $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:1140.5-1140.52" + attribute \src "ls180.v:1139.5-1139.52" wire $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:4591.1-4663.4" + attribute \src "ls180.v:4587.1-4659.4" wire width 4 $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:4591.1-4663.4" + attribute \src "ls180.v:4587.1-4659.4" wire $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:5098.1-5288.4" + attribute \src "ls180.v:5094.1-5284.4" wire $0\main_sdphy_dataw_sink_first[0:0] - attribute \src "ls180.v:5098.1-5288.4" + attribute \src "ls180.v:5094.1-5284.4" wire $0\main_sdphy_dataw_sink_last[0:0] - attribute \src "ls180.v:5098.1-5288.4" + attribute \src "ls180.v:5094.1-5284.4" wire width 8 $0\main_sdphy_dataw_sink_payload_data[7:0] - attribute \src "ls180.v:4591.1-4663.4" + attribute \src "ls180.v:4587.1-4659.4" wire $0\main_sdphy_dataw_sink_ready[0:0] - attribute \src "ls180.v:5098.1-5288.4" + attribute \src "ls180.v:5094.1-5284.4" wire $0\main_sdphy_dataw_sink_valid[0:0] - attribute \src "ls180.v:4591.1-4663.4" + attribute \src "ls180.v:4587.1-4659.4" wire $0\main_sdphy_dataw_start[0:0] - attribute \src "ls180.v:4591.1-4663.4" + attribute \src "ls180.v:4587.1-4659.4" wire $0\main_sdphy_dataw_stop[0:0] - attribute \src "ls180.v:4563.1-4590.4" + attribute \src "ls180.v:4559.1-4586.4" wire $0\main_sdphy_dataw_valid[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 8 $0\main_sdphy_init_count[7:0] - attribute \src "ls180.v:4292.1-4325.4" + attribute \src "ls180.v:4288.1-4321.4" wire width 8 $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] - attribute \src "ls180.v:4292.1-4325.4" + attribute \src "ls180.v:4288.1-4321.4" wire $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] - attribute \src "ls180.v:1032.5-1032.40" + attribute \src "ls180.v:1031.5-1031.40" wire $0\main_sdphy_init_initialize_w[0:0] - attribute \src "ls180.v:4292.1-4325.4" + attribute \src "ls180.v:4288.1-4321.4" wire $0\main_sdphy_init_pads_out_payload_clk[0:0] - attribute \src "ls180.v:4292.1-4325.4" + attribute \src "ls180.v:4288.1-4321.4" wire $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:4292.1-4325.4" + attribute \src "ls180.v:4288.1-4321.4" wire $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:4292.1-4325.4" + attribute \src "ls180.v:4288.1-4321.4" wire width 4 $0\main_sdphy_init_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:4292.1-4325.4" + attribute \src "ls180.v:4288.1-4321.4" wire $0\main_sdphy_init_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:7289.1-7357.4" + attribute \src "ls180.v:7287.1-7357.4" wire $0\main_sdphy_sdpads_cmd_i[0:0] - attribute \src "ls180.v:7289.1-7357.4" + attribute \src "ls180.v:7287.1-7357.4" wire width 4 $0\main_sdphy_sdpads_data_i[3:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdram_address_re[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 13 $0\main_sdram_address_storage[12:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdram_baddress_re[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 2 $0\main_sdram_baddress_storage[1:0] - attribute \src "ls180.v:3141.1-3148.4" + attribute \src "ls180.v:3137.1-3144.4" wire $0\main_sdram_bankmachine0_auto_precharge[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 4 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:418.5-418.64" + attribute \src "ls180.v:417.5-417.64" wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] - attribute \src "ls180.v:401.5-401.67" + attribute \src "ls180.v:400.5-400.67" wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] - attribute \src "ls180.v:402.5-402.66" + attribute \src "ls180.v:401.5-401.66" wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] - attribute \src "ls180.v:3163.1-3170.4" + attribute \src "ls180.v:3159.1-3166.4" wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 22 $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:3130.1-3137.4" + attribute \src "ls180.v:3126.1-3133.4" wire width 13 $0\main_sdram_bankmachine0_cmd_payload_a[12:0] - attribute \src "ls180.v:3179.1-3272.4" + attribute \src "ls180.v:3175.1-3268.4" wire $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] - attribute \src "ls180.v:3179.1-3272.4" + attribute \src "ls180.v:3175.1-3268.4" wire $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:3179.1-3272.4" + attribute \src "ls180.v:3175.1-3268.4" wire $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] - attribute \src "ls180.v:3179.1-3272.4" + attribute \src "ls180.v:3175.1-3268.4" wire $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] - attribute \src "ls180.v:3179.1-3272.4" + attribute \src "ls180.v:3175.1-3268.4" wire $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] - attribute \src "ls180.v:3179.1-3272.4" + attribute \src "ls180.v:3175.1-3268.4" wire $0\main_sdram_bankmachine0_cmd_payload_we[0:0] - attribute \src "ls180.v:3828.1-3836.4" + attribute \src "ls180.v:3824.1-3832.4" wire $0\main_sdram_bankmachine0_cmd_ready[0:0] - attribute \src "ls180.v:3179.1-3272.4" + attribute \src "ls180.v:3175.1-3268.4" wire $0\main_sdram_bankmachine0_cmd_valid[0:0] - attribute \src "ls180.v:3179.1-3272.4" + attribute \src "ls180.v:3175.1-3268.4" wire $0\main_sdram_bankmachine0_refresh_gnt[0:0] - attribute \src "ls180.v:3179.1-3272.4" + attribute \src "ls180.v:3175.1-3268.4" wire $0\main_sdram_bankmachine0_req_rdata_valid[0:0] - attribute \src "ls180.v:3179.1-3272.4" + attribute \src "ls180.v:3175.1-3268.4" wire $0\main_sdram_bankmachine0_req_wdata_ready[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 13 $0\main_sdram_bankmachine0_row[12:0] - attribute \src "ls180.v:3179.1-3272.4" + attribute \src "ls180.v:3175.1-3268.4" wire $0\main_sdram_bankmachine0_row_close[0:0] - attribute \src "ls180.v:3179.1-3272.4" + attribute \src "ls180.v:3175.1-3268.4" wire $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:3179.1-3272.4" + attribute \src "ls180.v:3175.1-3268.4" wire $0\main_sdram_bankmachine0_row_open[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdram_bankmachine0_row_opened[0:0] - attribute \src "ls180.v:460.32-460.76" + attribute \src "ls180.v:459.32-459.76" wire $0\main_sdram_bankmachine0_trascon_ready[0:0] - attribute \src "ls180.v:458.32-458.75" + attribute \src "ls180.v:457.32-457.75" wire $0\main_sdram_bankmachine0_trccon_ready[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 3 $0\main_sdram_bankmachine0_twtpcon_count[2:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdram_bankmachine0_twtpcon_ready[0:0] - attribute \src "ls180.v:3298.1-3305.4" + attribute \src "ls180.v:3294.1-3301.4" wire $0\main_sdram_bankmachine1_auto_precharge[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 4 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:500.5-500.64" + attribute \src "ls180.v:499.5-499.64" wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] - attribute \src "ls180.v:483.5-483.67" + attribute \src "ls180.v:482.5-482.67" wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] - attribute \src "ls180.v:484.5-484.66" + attribute \src "ls180.v:483.5-483.66" wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] - attribute \src "ls180.v:3320.1-3327.4" + attribute \src "ls180.v:3316.1-3323.4" wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 22 $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:3287.1-3294.4" + attribute \src "ls180.v:3283.1-3290.4" wire width 13 $0\main_sdram_bankmachine1_cmd_payload_a[12:0] - attribute \src "ls180.v:3336.1-3429.4" + attribute \src "ls180.v:3332.1-3425.4" wire $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] - attribute \src "ls180.v:3336.1-3429.4" + attribute \src "ls180.v:3332.1-3425.4" wire $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:3336.1-3429.4" + attribute \src "ls180.v:3332.1-3425.4" wire $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] - attribute \src "ls180.v:3336.1-3429.4" + attribute \src "ls180.v:3332.1-3425.4" wire $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] - attribute \src "ls180.v:3336.1-3429.4" + attribute \src "ls180.v:3332.1-3425.4" wire $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] - attribute \src "ls180.v:3336.1-3429.4" + attribute \src "ls180.v:3332.1-3425.4" wire $0\main_sdram_bankmachine1_cmd_payload_we[0:0] - attribute \src "ls180.v:3837.1-3845.4" + attribute \src "ls180.v:3833.1-3841.4" wire $0\main_sdram_bankmachine1_cmd_ready[0:0] - attribute \src "ls180.v:3336.1-3429.4" + attribute \src "ls180.v:3332.1-3425.4" wire $0\main_sdram_bankmachine1_cmd_valid[0:0] - attribute \src "ls180.v:3336.1-3429.4" + attribute \src "ls180.v:3332.1-3425.4" wire $0\main_sdram_bankmachine1_refresh_gnt[0:0] - attribute \src "ls180.v:3336.1-3429.4" + attribute \src "ls180.v:3332.1-3425.4" wire $0\main_sdram_bankmachine1_req_rdata_valid[0:0] - attribute \src "ls180.v:3336.1-3429.4" + attribute \src "ls180.v:3332.1-3425.4" wire $0\main_sdram_bankmachine1_req_wdata_ready[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 13 $0\main_sdram_bankmachine1_row[12:0] - attribute \src "ls180.v:3336.1-3429.4" + attribute \src "ls180.v:3332.1-3425.4" wire $0\main_sdram_bankmachine1_row_close[0:0] - attribute \src "ls180.v:3336.1-3429.4" + attribute \src "ls180.v:3332.1-3425.4" wire $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:3336.1-3429.4" + attribute \src "ls180.v:3332.1-3425.4" wire $0\main_sdram_bankmachine1_row_open[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdram_bankmachine1_row_opened[0:0] - attribute \src "ls180.v:542.32-542.76" + attribute \src "ls180.v:541.32-541.76" wire $0\main_sdram_bankmachine1_trascon_ready[0:0] - attribute \src "ls180.v:540.32-540.75" + attribute \src "ls180.v:539.32-539.75" wire $0\main_sdram_bankmachine1_trccon_ready[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 3 $0\main_sdram_bankmachine1_twtpcon_count[2:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdram_bankmachine1_twtpcon_ready[0:0] - attribute \src "ls180.v:3455.1-3462.4" + attribute \src "ls180.v:3451.1-3458.4" wire $0\main_sdram_bankmachine2_auto_precharge[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 4 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:582.5-582.64" + attribute \src "ls180.v:581.5-581.64" wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] - attribute \src "ls180.v:565.5-565.67" + attribute \src "ls180.v:564.5-564.67" wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] - attribute \src "ls180.v:566.5-566.66" + attribute \src "ls180.v:565.5-565.66" wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] - attribute \src "ls180.v:3477.1-3484.4" + attribute \src "ls180.v:3473.1-3480.4" wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 22 $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:3444.1-3451.4" + attribute \src "ls180.v:3440.1-3447.4" wire width 13 $0\main_sdram_bankmachine2_cmd_payload_a[12:0] - attribute \src "ls180.v:3493.1-3586.4" + attribute \src "ls180.v:3489.1-3582.4" wire $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] - attribute \src "ls180.v:3493.1-3586.4" + attribute \src "ls180.v:3489.1-3582.4" wire $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:3493.1-3586.4" + attribute \src "ls180.v:3489.1-3582.4" wire $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] - attribute \src "ls180.v:3493.1-3586.4" + attribute \src "ls180.v:3489.1-3582.4" wire $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] - attribute \src "ls180.v:3493.1-3586.4" + attribute \src "ls180.v:3489.1-3582.4" wire $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] - attribute \src "ls180.v:3493.1-3586.4" + attribute \src "ls180.v:3489.1-3582.4" wire $0\main_sdram_bankmachine2_cmd_payload_we[0:0] - attribute \src "ls180.v:3846.1-3854.4" + attribute \src "ls180.v:3842.1-3850.4" wire $0\main_sdram_bankmachine2_cmd_ready[0:0] - attribute \src "ls180.v:3493.1-3586.4" + attribute \src "ls180.v:3489.1-3582.4" wire $0\main_sdram_bankmachine2_cmd_valid[0:0] - attribute \src "ls180.v:3493.1-3586.4" + attribute \src "ls180.v:3489.1-3582.4" wire $0\main_sdram_bankmachine2_refresh_gnt[0:0] - attribute \src "ls180.v:3493.1-3586.4" + attribute \src "ls180.v:3489.1-3582.4" wire $0\main_sdram_bankmachine2_req_rdata_valid[0:0] - attribute \src "ls180.v:3493.1-3586.4" + attribute \src "ls180.v:3489.1-3582.4" wire $0\main_sdram_bankmachine2_req_wdata_ready[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 13 $0\main_sdram_bankmachine2_row[12:0] - attribute \src "ls180.v:3493.1-3586.4" + attribute \src "ls180.v:3489.1-3582.4" wire $0\main_sdram_bankmachine2_row_close[0:0] - attribute \src "ls180.v:3493.1-3586.4" + attribute \src "ls180.v:3489.1-3582.4" wire $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:3493.1-3586.4" + attribute \src "ls180.v:3489.1-3582.4" wire $0\main_sdram_bankmachine2_row_open[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdram_bankmachine2_row_opened[0:0] - attribute \src "ls180.v:624.32-624.76" + attribute \src "ls180.v:623.32-623.76" wire $0\main_sdram_bankmachine2_trascon_ready[0:0] - attribute \src "ls180.v:622.32-622.75" + attribute \src "ls180.v:621.32-621.75" wire $0\main_sdram_bankmachine2_trccon_ready[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 3 $0\main_sdram_bankmachine2_twtpcon_count[2:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdram_bankmachine2_twtpcon_ready[0:0] - attribute \src "ls180.v:3612.1-3619.4" + attribute \src "ls180.v:3608.1-3615.4" wire $0\main_sdram_bankmachine3_auto_precharge[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 4 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:664.5-664.64" + attribute \src "ls180.v:663.5-663.64" wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] - attribute \src "ls180.v:647.5-647.67" + attribute \src "ls180.v:646.5-646.67" wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] - attribute \src "ls180.v:648.5-648.66" + attribute \src "ls180.v:647.5-647.66" wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] - attribute \src "ls180.v:3634.1-3641.4" + attribute \src "ls180.v:3630.1-3637.4" wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 22 $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:3601.1-3608.4" + attribute \src "ls180.v:3597.1-3604.4" wire width 13 $0\main_sdram_bankmachine3_cmd_payload_a[12:0] - attribute \src "ls180.v:3650.1-3743.4" + attribute \src "ls180.v:3646.1-3739.4" wire $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] - attribute \src "ls180.v:3650.1-3743.4" + attribute \src "ls180.v:3646.1-3739.4" wire $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:3650.1-3743.4" + attribute \src "ls180.v:3646.1-3739.4" wire $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] - attribute \src "ls180.v:3650.1-3743.4" + attribute \src "ls180.v:3646.1-3739.4" wire $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] - attribute \src "ls180.v:3650.1-3743.4" + attribute \src "ls180.v:3646.1-3739.4" wire $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] - attribute \src "ls180.v:3650.1-3743.4" + attribute \src "ls180.v:3646.1-3739.4" wire $0\main_sdram_bankmachine3_cmd_payload_we[0:0] - attribute \src "ls180.v:3855.1-3863.4" + attribute \src "ls180.v:3851.1-3859.4" wire $0\main_sdram_bankmachine3_cmd_ready[0:0] - attribute \src "ls180.v:3650.1-3743.4" + attribute \src "ls180.v:3646.1-3739.4" wire $0\main_sdram_bankmachine3_cmd_valid[0:0] - attribute \src "ls180.v:3650.1-3743.4" + attribute \src "ls180.v:3646.1-3739.4" wire $0\main_sdram_bankmachine3_refresh_gnt[0:0] - attribute \src "ls180.v:3650.1-3743.4" + attribute \src "ls180.v:3646.1-3739.4" wire $0\main_sdram_bankmachine3_req_rdata_valid[0:0] - attribute \src "ls180.v:3650.1-3743.4" + attribute \src "ls180.v:3646.1-3739.4" wire $0\main_sdram_bankmachine3_req_wdata_ready[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 13 $0\main_sdram_bankmachine3_row[12:0] - attribute \src "ls180.v:3650.1-3743.4" + attribute \src "ls180.v:3646.1-3739.4" wire $0\main_sdram_bankmachine3_row_close[0:0] - attribute \src "ls180.v:3650.1-3743.4" + attribute \src "ls180.v:3646.1-3739.4" wire $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:3650.1-3743.4" + attribute \src "ls180.v:3646.1-3739.4" wire $0\main_sdram_bankmachine3_row_open[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdram_bankmachine3_row_opened[0:0] - attribute \src "ls180.v:706.32-706.76" + attribute \src "ls180.v:705.32-705.76" wire $0\main_sdram_bankmachine3_trascon_ready[0:0] - attribute \src "ls180.v:704.32-704.75" + attribute \src "ls180.v:703.32-703.75" wire $0\main_sdram_bankmachine3_trccon_ready[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 3 $0\main_sdram_bankmachine3_twtpcon_count[2:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdram_bankmachine3_twtpcon_ready[0:0] - attribute \src "ls180.v:3777.1-3782.4" + attribute \src "ls180.v:3773.1-3778.4" wire $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] - attribute \src "ls180.v:3783.1-3788.4" + attribute \src "ls180.v:3779.1-3784.4" wire $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] - attribute \src "ls180.v:3789.1-3794.4" + attribute \src "ls180.v:3785.1-3790.4" wire $0\main_sdram_choose_cmd_cmd_payload_we[0:0] - attribute \src "ls180.v:714.5-714.43" + attribute \src "ls180.v:713.5-713.43" wire $0\main_sdram_choose_cmd_cmd_ready[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 2 $0\main_sdram_choose_cmd_grant[1:0] - attribute \src "ls180.v:3763.1-3769.4" + attribute \src "ls180.v:3759.1-3765.4" wire width 4 $0\main_sdram_choose_cmd_valids[3:0] - attribute \src "ls180.v:712.5-712.48" + attribute \src "ls180.v:711.5-711.48" wire $0\main_sdram_choose_cmd_want_activates[0:0] - attribute \src "ls180.v:711.5-711.43" + attribute \src "ls180.v:710.5-710.43" wire $0\main_sdram_choose_cmd_want_cmds[0:0] - attribute \src "ls180.v:709.5-709.44" + attribute \src "ls180.v:708.5-708.44" wire $0\main_sdram_choose_cmd_want_reads[0:0] - attribute \src "ls180.v:710.5-710.45" + attribute \src "ls180.v:709.5-709.45" wire $0\main_sdram_choose_cmd_want_writes[0:0] - attribute \src "ls180.v:3810.1-3815.4" + attribute \src "ls180.v:3806.1-3811.4" wire $0\main_sdram_choose_req_cmd_payload_cas[0:0] - attribute \src "ls180.v:3816.1-3821.4" + attribute \src "ls180.v:3812.1-3817.4" wire $0\main_sdram_choose_req_cmd_payload_ras[0:0] - attribute \src "ls180.v:3822.1-3827.4" + attribute \src "ls180.v:3818.1-3823.4" wire $0\main_sdram_choose_req_cmd_payload_we[0:0] - attribute \src "ls180.v:3868.1-3940.4" + attribute \src "ls180.v:3864.1-3936.4" wire $0\main_sdram_choose_req_cmd_ready[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 2 $0\main_sdram_choose_req_grant[1:0] - attribute \src "ls180.v:3796.1-3802.4" + attribute \src "ls180.v:3792.1-3798.4" wire width 4 $0\main_sdram_choose_req_valids[3:0] - attribute \src "ls180.v:3868.1-3940.4" + attribute \src "ls180.v:3864.1-3936.4" wire $0\main_sdram_choose_req_want_activates[0:0] - attribute \src "ls180.v:3868.1-3940.4" + attribute \src "ls180.v:3864.1-3936.4" wire $0\main_sdram_choose_req_want_reads[0:0] - attribute \src "ls180.v:3868.1-3940.4" + attribute \src "ls180.v:3864.1-3936.4" wire $0\main_sdram_choose_req_want_writes[0:0] - attribute \src "ls180.v:3085.1-3115.4" + attribute \src "ls180.v:3081.1-3111.4" wire $0\main_sdram_cmd_last[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 13 $0\main_sdram_cmd_payload_a[12:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 2 $0\main_sdram_cmd_payload_ba[1:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdram_cmd_payload_cas[0:0] - attribute \src "ls180.v:362.5-362.42" + attribute \src "ls180.v:361.5-361.42" wire $0\main_sdram_cmd_payload_is_read[0:0] - attribute \src "ls180.v:363.5-363.43" + attribute \src "ls180.v:362.5-362.43" wire $0\main_sdram_cmd_payload_is_write[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdram_cmd_payload_ras[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdram_cmd_payload_we[0:0] - attribute \src "ls180.v:3868.1-3940.4" + attribute \src "ls180.v:3864.1-3936.4" wire $0\main_sdram_cmd_ready[0:0] - attribute \src "ls180.v:3085.1-3115.4" + attribute \src "ls180.v:3081.1-3111.4" wire $0\main_sdram_cmd_valid[0:0] - attribute \src "ls180.v:298.5-298.38" + attribute \src "ls180.v:297.5-297.38" wire $0\main_sdram_command_issue_w[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdram_command_re[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 6 $0\main_sdram_command_storage[5:0] - attribute \src "ls180.v:347.5-347.35" + attribute \src "ls180.v:346.5-346.35" wire $0\main_sdram_dfi_p0_act_n[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 13 $0\main_sdram_dfi_p0_address[12:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 2 $0\main_sdram_dfi_p0_bank[1:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdram_dfi_p0_cas_n[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdram_dfi_p0_cs_n[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdram_dfi_p0_ras_n[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdram_dfi_p0_rddata_en[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdram_dfi_p0_we_n[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdram_dfi_p0_wrdata_en[0:0] - attribute \src "ls180.v:3868.1-3940.4" + attribute \src "ls180.v:3864.1-3936.4" wire $0\main_sdram_en0[0:0] - attribute \src "ls180.v:3868.1-3940.4" + attribute \src "ls180.v:3864.1-3936.4" wire $0\main_sdram_en1[0:0] - attribute \src "ls180.v:3964.1-3977.4" + attribute \src "ls180.v:3960.1-3973.4" wire width 16 $0\main_sdram_interface_wdata[15:0] - attribute \src "ls180.v:3964.1-3977.4" + attribute \src "ls180.v:3960.1-3973.4" wire width 2 $0\main_sdram_interface_wdata_we[1:0] - attribute \src "ls180.v:248.5-248.36" + attribute \src "ls180.v:247.5-247.36" wire $0\main_sdram_inti_p0_act_n[0:0] - attribute \src "ls180.v:3026.1-3042.4" + attribute \src "ls180.v:3022.1-3038.4" wire $0\main_sdram_inti_p0_cas_n[0:0] - attribute \src "ls180.v:3026.1-3042.4" + attribute \src "ls180.v:3022.1-3038.4" wire $0\main_sdram_inti_p0_cs_n[0:0] - attribute \src "ls180.v:3026.1-3042.4" + attribute \src "ls180.v:3022.1-3038.4" wire $0\main_sdram_inti_p0_ras_n[0:0] - attribute \src "ls180.v:2968.1-3022.4" + attribute \src "ls180.v:2964.1-3018.4" wire width 16 $0\main_sdram_inti_p0_rddata[15:0] - attribute \src "ls180.v:2968.1-3022.4" + attribute \src "ls180.v:2964.1-3018.4" wire $0\main_sdram_inti_p0_rddata_valid[0:0] - attribute \src "ls180.v:3026.1-3042.4" + attribute \src "ls180.v:3022.1-3038.4" wire $0\main_sdram_inti_p0_we_n[0:0] - attribute \src "ls180.v:2968.1-3022.4" + attribute \src "ls180.v:2964.1-3018.4" wire $0\main_sdram_master_p0_act_n[0:0] - attribute \src "ls180.v:2968.1-3022.4" + attribute \src "ls180.v:2964.1-3018.4" wire width 13 $0\main_sdram_master_p0_address[12:0] - attribute \src "ls180.v:2968.1-3022.4" + attribute \src "ls180.v:2964.1-3018.4" wire width 2 $0\main_sdram_master_p0_bank[1:0] - attribute \src "ls180.v:2968.1-3022.4" + attribute \src "ls180.v:2964.1-3018.4" wire $0\main_sdram_master_p0_cas_n[0:0] - attribute \src "ls180.v:2968.1-3022.4" + attribute \src "ls180.v:2964.1-3018.4" wire $0\main_sdram_master_p0_cke[0:0] - attribute \src "ls180.v:2968.1-3022.4" + attribute \src "ls180.v:2964.1-3018.4" wire $0\main_sdram_master_p0_cs_n[0:0] - attribute \src "ls180.v:2968.1-3022.4" + attribute \src "ls180.v:2964.1-3018.4" wire $0\main_sdram_master_p0_odt[0:0] - attribute \src "ls180.v:2968.1-3022.4" + attribute \src "ls180.v:2964.1-3018.4" wire $0\main_sdram_master_p0_ras_n[0:0] - attribute \src "ls180.v:2968.1-3022.4" + attribute \src "ls180.v:2964.1-3018.4" wire $0\main_sdram_master_p0_rddata_en[0:0] - attribute \src "ls180.v:2968.1-3022.4" + attribute \src "ls180.v:2964.1-3018.4" wire $0\main_sdram_master_p0_reset_n[0:0] - attribute \src "ls180.v:2968.1-3022.4" + attribute \src "ls180.v:2964.1-3018.4" wire $0\main_sdram_master_p0_we_n[0:0] - attribute \src "ls180.v:2968.1-3022.4" + attribute \src "ls180.v:2964.1-3018.4" wire width 16 $0\main_sdram_master_p0_wrdata[15:0] - attribute \src "ls180.v:2968.1-3022.4" + attribute \src "ls180.v:2964.1-3018.4" wire $0\main_sdram_master_p0_wrdata_en[0:0] - attribute \src "ls180.v:2968.1-3022.4" + attribute \src "ls180.v:2964.1-3018.4" wire width 2 $0\main_sdram_master_p0_wrdata_mask[1:0] - attribute \src "ls180.v:745.12-745.36" + attribute \src "ls180.v:744.12-744.36" wire width 13 $0\main_sdram_nop_a[12:0] - attribute \src "ls180.v:746.11-746.35" + attribute \src "ls180.v:745.11-745.35" wire width 2 $0\main_sdram_nop_ba[1:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdram_postponer_count[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdram_postponer_req_o[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdram_re[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdram_sequencer_count[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 4 $0\main_sdram_sequencer_counter[3:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdram_sequencer_done1[0:0] - attribute \src "ls180.v:3085.1-3115.4" + attribute \src "ls180.v:3081.1-3111.4" wire $0\main_sdram_sequencer_start0[0:0] - attribute \src "ls180.v:2968.1-3022.4" + attribute \src "ls180.v:2964.1-3018.4" wire width 16 $0\main_sdram_slave_p0_rddata[15:0] - attribute \src "ls180.v:2968.1-3022.4" + attribute \src "ls180.v:2964.1-3018.4" wire $0\main_sdram_slave_p0_rddata_valid[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 16 $0\main_sdram_status[15:0] - attribute \src "ls180.v:748.5-748.31" + attribute \src "ls180.v:747.5-747.31" wire $0\main_sdram_steerer0[0:0] - attribute \src "ls180.v:749.5-749.31" + attribute \src "ls180.v:748.5-748.31" wire $0\main_sdram_steerer1[0:0] - attribute \src "ls180.v:3868.1-3940.4" + attribute \src "ls180.v:3864.1-3936.4" wire width 2 $0\main_sdram_steerer_sel[1:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 4 $0\main_sdram_storage[3:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdram_tccdcon_count[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdram_tccdcon_ready[0:0] - attribute \src "ls180.v:753.32-753.63" + attribute \src "ls180.v:752.32-752.63" wire $0\main_sdram_tfawcon_ready[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 5 $0\main_sdram_time0[4:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 4 $0\main_sdram_time1[3:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 10 $0\main_sdram_timer_count1[9:0] - attribute \src "ls180.v:751.32-751.63" + attribute \src "ls180.v:750.32-750.63" wire $0\main_sdram_trrdcon_ready[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 3 $0\main_sdram_twtrcon_count[2:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdram_twtrcon_ready[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sdram_wrdata_re[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 16 $0\main_sdram_wrdata_storage[15:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_sink_ready[0:0] - attribute \src "ls180.v:824.5-824.29" + attribute \src "ls180.v:823.5-823.29" wire $0\main_source_first[0:0] - attribute \src "ls180.v:825.5-825.28" + attribute \src "ls180.v:824.5-824.28" wire $0\main_source_last[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 8 $0\main_source_payload_data[7:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_source_valid[0:0] - attribute \src "ls180.v:969.12-969.48" + attribute \src "ls180.v:968.12-968.48" wire width 16 $0\main_spi_master_clk_divider0[15:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 16 $0\main_spi_master_clk_divider1[15:0] - attribute \src "ls180.v:4186.1-4234.4" + attribute \src "ls180.v:4182.1-4230.4" wire $0\main_spi_master_clk_enable[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_spi_master_control_re[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 16 $0\main_spi_master_control_storage[15:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 3 $0\main_spi_master_count[2:0] - attribute \src "ls180.v:4186.1-4234.4" + attribute \src "ls180.v:4182.1-4230.4" wire width 3 $0\main_spi_master_count_spimaster0_next_value[2:0] - attribute \src "ls180.v:4186.1-4234.4" + attribute \src "ls180.v:4182.1-4230.4" wire $0\main_spi_master_count_spimaster0_next_value_ce[0:0] - attribute \src "ls180.v:4186.1-4234.4" + attribute \src "ls180.v:4182.1-4230.4" wire $0\main_spi_master_cs_enable[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_spi_master_cs_re[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_spi_master_cs_storage[0:0] - attribute \src "ls180.v:4186.1-4234.4" + attribute \src "ls180.v:4182.1-4230.4" wire $0\main_spi_master_done0[0:0] - attribute \src "ls180.v:4186.1-4234.4" + attribute \src "ls180.v:4182.1-4230.4" wire $0\main_spi_master_irq[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_spi_master_loopback_re[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_spi_master_loopback_storage[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 8 $0\main_spi_master_miso[7:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 8 $0\main_spi_master_miso_data[7:0] - attribute \src "ls180.v:4186.1-4234.4" + attribute \src "ls180.v:4182.1-4230.4" wire $0\main_spi_master_miso_latch[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 8 $0\main_spi_master_mosi_data[7:0] - attribute \src "ls180.v:4186.1-4234.4" + attribute \src "ls180.v:4182.1-4230.4" wire $0\main_spi_master_mosi_latch[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_spi_master_mosi_re[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 3 $0\main_spi_master_mosi_sel[2:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 8 $0\main_spi_master_mosi_storage[7:0] - attribute \src "ls180.v:6220.1-6225.4" + attribute \src "ls180.v:6216.1-6221.4" wire $0\main_spi_master_start1[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 32 $0\main_storage[31:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 4 $0\main_tx_bitcount[3:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_tx_busy[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 8 $0\main_tx_reg[7:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_uart_clk_rxen[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_uart_clk_txen[0:0] - attribute \src "ls180.v:4104.1-4108.4" + attribute \src "ls180.v:4100.1-4104.4" wire width 2 $0\main_uart_eventmanager_pending_w[1:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_uart_eventmanager_re[0:0] - attribute \src "ls180.v:4093.1-4097.4" + attribute \src "ls180.v:4089.1-4093.4" wire width 2 $0\main_uart_eventmanager_status_w[1:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 2 $0\main_uart_eventmanager_storage[1:0] - attribute \src "ls180.v:951.5-951.27" + attribute \src "ls180.v:950.5-950.27" wire $0\main_uart_reset[0:0] - attribute \src "ls180.v:4098.1-4103.4" + attribute \src "ls180.v:4094.1-4099.4" wire $0\main_uart_rx_clear[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 4 $0\main_uart_rx_fifo_consume[3:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 5 $0\main_uart_rx_fifo_level0[4:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 4 $0\main_uart_rx_fifo_produce[3:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_uart_rx_fifo_readable[0:0] - attribute \src "ls180.v:933.5-933.37" + attribute \src "ls180.v:932.5-932.37" wire $0\main_uart_rx_fifo_replace[0:0] - attribute \src "ls180.v:4156.1-4163.4" + attribute \src "ls180.v:4152.1-4159.4" wire width 4 $0\main_uart_rx_fifo_wrport_adr[3:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_uart_rx_old_trigger[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_uart_rx_pending[0:0] - attribute \src "ls180.v:4087.1-4092.4" + attribute \src "ls180.v:4083.1-4088.4" wire $0\main_uart_tx_clear[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 4 $0\main_uart_tx_fifo_consume[3:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 5 $0\main_uart_tx_fifo_level0[4:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire width 4 $0\main_uart_tx_fifo_produce[3:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_uart_tx_fifo_readable[0:0] - attribute \src "ls180.v:896.5-896.37" + attribute \src "ls180.v:895.5-895.37" wire $0\main_uart_tx_fifo_replace[0:0] - attribute \src "ls180.v:879.5-879.40" + attribute \src "ls180.v:878.5-878.40" wire $0\main_uart_tx_fifo_sink_first[0:0] - attribute \src "ls180.v:880.5-880.39" + attribute \src "ls180.v:879.5-879.39" wire $0\main_uart_tx_fifo_sink_last[0:0] - attribute \src "ls180.v:4126.1-4133.4" + attribute \src "ls180.v:4122.1-4129.4" wire width 4 $0\main_uart_tx_fifo_wrport_adr[3:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_uart_tx_old_trigger[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_uart_tx_pending[0:0] - attribute \src "ls180.v:3996.1-4042.4" + attribute \src "ls180.v:3992.1-4038.4" wire $0\main_wb_sdram_ack[0:0] - attribute \src "ls180.v:792.5-792.29" + attribute \src "ls180.v:791.5-791.29" wire $0\main_wb_sdram_err[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\main_wdata_consumed[0:0] - attribute \src "ls180.v:9981.1-9991.4" + attribute \src "ls180.v:9977.1-9987.4" wire width 7 $0\memadr[6:0] - attribute \src "ls180.v:10001.1-10005.4" + attribute \src "ls180.v:9997.1-10001.4" wire width 25 $0\memdat[24:0] - attribute \src "ls180.v:10015.1-10019.4" + attribute \src "ls180.v:10011.1-10015.4" wire width 25 $0\memdat_1[24:0] - attribute \src "ls180.v:10029.1-10033.4" + attribute \src "ls180.v:10025.1-10029.4" wire width 25 $0\memdat_2[24:0] - attribute \src "ls180.v:10043.1-10047.4" + attribute \src "ls180.v:10039.1-10043.4" wire width 25 $0\memdat_3[24:0] - attribute \src "ls180.v:10058.1-10062.4" + attribute \src "ls180.v:10054.1-10058.4" wire width 10 $0\memdat_4[9:0] - attribute \src "ls180.v:10064.1-10067.4" + attribute \src "ls180.v:10060.1-10063.4" wire width 10 $0\memdat_5[9:0] - attribute \src "ls180.v:10075.1-10079.4" + attribute \src "ls180.v:10071.1-10075.4" wire width 10 $0\memdat_6[9:0] - attribute \src "ls180.v:10081.1-10084.4" + attribute \src "ls180.v:10077.1-10080.4" wire width 10 $0\memdat_7[9:0] - attribute \src "ls180.v:10091.1-10095.4" + attribute \src "ls180.v:10087.1-10091.4" wire width 10 $0\memdat_8[9:0] - attribute \src "ls180.v:10105.1-10109.4" + attribute \src "ls180.v:10101.1-10105.4" wire width 10 $0\memdat_9[9:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\pwm0[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\pwm1[0:0] - attribute \src "ls180.v:7289.1-7357.4" + attribute \src "ls180.v:7287.1-7357.4" wire $0\sdcard_clk[0:0] - attribute \src "ls180.v:7289.1-7357.4" + attribute \src "ls180.v:7287.1-7357.4" wire $0\sdcard_cmd_o[0:0] - attribute \src "ls180.v:7289.1-7357.4" + attribute \src "ls180.v:7287.1-7357.4" wire $0\sdcard_cmd_oe[0:0] - attribute \src "ls180.v:7289.1-7357.4" + attribute \src "ls180.v:7287.1-7357.4" wire width 4 $0\sdcard_data_o[3:0] - attribute \src "ls180.v:7289.1-7357.4" + attribute \src "ls180.v:7287.1-7357.4" wire $0\sdcard_data_oe[0:0] - attribute \src "ls180.v:7289.1-7357.4" + attribute \src "ls180.v:7287.1-7357.4" wire width 13 $0\sdram_a[12:0] - attribute \src "ls180.v:7289.1-7357.4" + attribute \src "ls180.v:7287.1-7357.4" wire width 2 $0\sdram_ba[1:0] - attribute \src "ls180.v:7289.1-7357.4" + attribute \src "ls180.v:7287.1-7357.4" wire $0\sdram_cas_n[0:0] - attribute \src "ls180.v:7289.1-7357.4" + attribute \src "ls180.v:7287.1-7357.4" wire $0\sdram_cke[0:0] - attribute \src "ls180.v:7289.1-7357.4" + attribute \src "ls180.v:7287.1-7357.4" wire $0\sdram_clock[0:0] - attribute \src "ls180.v:7289.1-7357.4" + attribute \src "ls180.v:7287.1-7357.4" wire $0\sdram_cs_n[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7287.1-7357.4" wire width 2 $0\sdram_dm[1:0] - attribute \src "ls180.v:7289.1-7357.4" + attribute \src "ls180.v:7287.1-7357.4" wire width 16 $0\sdram_dq_o[15:0] - attribute \src "ls180.v:7289.1-7357.4" + attribute \src "ls180.v:7287.1-7357.4" wire $0\sdram_dq_oe[0:0] - attribute \src "ls180.v:7289.1-7357.4" + attribute \src "ls180.v:7287.1-7357.4" wire $0\sdram_ras_n[0:0] - attribute \src "ls180.v:7289.1-7357.4" + attribute \src "ls180.v:7287.1-7357.4" wire $0\sdram_we_n[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\spi_master_clk[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\spi_master_cs_n[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\spi_master_mosi[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\spisdcard_clk[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\spisdcard_cs_n[0:0] - attribute \src "ls180.v:7359.1-9977.4" + attribute \src "ls180.v:7359.1-9973.4" wire $0\spisdcard_mosi[0:0] - attribute \src "ls180.v:1710.11-1710.49" + attribute \src "ls180.v:1709.11-1709.49" wire width 3 $1\builder_bankmachine0_next_state[2:0] - attribute \src "ls180.v:1709.11-1709.44" + attribute \src "ls180.v:1708.11-1708.44" wire width 3 $1\builder_bankmachine0_state[2:0] - attribute \src "ls180.v:1712.11-1712.49" + attribute \src "ls180.v:1711.11-1711.49" wire width 3 $1\builder_bankmachine1_next_state[2:0] - attribute \src "ls180.v:1711.11-1711.44" + attribute \src "ls180.v:1710.11-1710.44" wire width 3 $1\builder_bankmachine1_state[2:0] - attribute \src "ls180.v:1714.11-1714.49" + attribute \src "ls180.v:1713.11-1713.49" wire width 3 $1\builder_bankmachine2_next_state[2:0] - attribute \src "ls180.v:1713.11-1713.44" + attribute \src "ls180.v:1712.11-1712.44" wire width 3 $1\builder_bankmachine2_state[2:0] - attribute \src "ls180.v:1716.11-1716.49" + attribute \src "ls180.v:1715.11-1715.49" wire width 3 $1\builder_bankmachine3_next_state[2:0] - attribute \src "ls180.v:1715.11-1715.44" + attribute \src "ls180.v:1714.11-1714.44" wire width 3 $1\builder_bankmachine3_state[2:0] - attribute \src "ls180.v:2548.5-2548.41" + attribute \src "ls180.v:2547.5-2547.41" wire $1\builder_comb_rhs_array_muxed0[0:0] - attribute \src "ls180.v:2561.5-2561.42" + attribute \src "ls180.v:2560.5-2560.42" wire $1\builder_comb_rhs_array_muxed10[0:0] - attribute \src "ls180.v:2562.5-2562.42" + attribute \src "ls180.v:2561.5-2561.42" wire $1\builder_comb_rhs_array_muxed11[0:0] - attribute \src "ls180.v:2566.12-2566.50" + attribute \src "ls180.v:2565.12-2565.50" wire width 22 $1\builder_comb_rhs_array_muxed12[21:0] - attribute \src "ls180.v:2567.5-2567.42" + attribute \src "ls180.v:2566.5-2566.42" wire $1\builder_comb_rhs_array_muxed13[0:0] - attribute \src "ls180.v:2568.5-2568.42" + attribute \src "ls180.v:2567.5-2567.42" wire $1\builder_comb_rhs_array_muxed14[0:0] - attribute \src "ls180.v:2569.12-2569.50" + attribute \src "ls180.v:2568.12-2568.50" wire width 22 $1\builder_comb_rhs_array_muxed15[21:0] - attribute \src "ls180.v:2570.5-2570.42" + attribute \src "ls180.v:2569.5-2569.42" wire $1\builder_comb_rhs_array_muxed16[0:0] - attribute \src "ls180.v:2571.5-2571.42" + attribute \src "ls180.v:2570.5-2570.42" wire $1\builder_comb_rhs_array_muxed17[0:0] - attribute \src "ls180.v:2572.12-2572.50" + attribute \src "ls180.v:2571.12-2571.50" wire width 22 $1\builder_comb_rhs_array_muxed18[21:0] - attribute \src "ls180.v:2573.5-2573.42" + attribute \src "ls180.v:2572.5-2572.42" wire $1\builder_comb_rhs_array_muxed19[0:0] - attribute \src "ls180.v:2549.12-2549.49" + attribute \src "ls180.v:2548.12-2548.49" wire width 13 $1\builder_comb_rhs_array_muxed1[12:0] - attribute \src "ls180.v:2574.5-2574.42" + attribute \src "ls180.v:2573.5-2573.42" wire $1\builder_comb_rhs_array_muxed20[0:0] - attribute \src "ls180.v:2575.12-2575.50" + attribute \src "ls180.v:2574.12-2574.50" wire width 22 $1\builder_comb_rhs_array_muxed21[21:0] - attribute \src "ls180.v:2576.5-2576.42" + attribute \src "ls180.v:2575.5-2575.42" wire $1\builder_comb_rhs_array_muxed22[0:0] - attribute \src "ls180.v:2577.5-2577.42" + attribute \src "ls180.v:2576.5-2576.42" wire $1\builder_comb_rhs_array_muxed23[0:0] - attribute \src "ls180.v:2578.12-2578.50" + attribute \src "ls180.v:2577.12-2577.50" wire width 32 $1\builder_comb_rhs_array_muxed24[31:0] - attribute \src "ls180.v:2579.12-2579.50" + attribute \src "ls180.v:2578.12-2578.50" wire width 32 $1\builder_comb_rhs_array_muxed25[31:0] - attribute \src "ls180.v:2580.11-2580.48" + attribute \src "ls180.v:2579.11-2579.48" wire width 4 $1\builder_comb_rhs_array_muxed26[3:0] - attribute \src "ls180.v:2581.5-2581.42" + attribute \src "ls180.v:2580.5-2580.42" wire $1\builder_comb_rhs_array_muxed27[0:0] - attribute \src "ls180.v:2582.5-2582.42" + attribute \src "ls180.v:2581.5-2581.42" wire $1\builder_comb_rhs_array_muxed28[0:0] - attribute \src "ls180.v:2583.5-2583.42" + attribute \src "ls180.v:2582.5-2582.42" wire $1\builder_comb_rhs_array_muxed29[0:0] - attribute \src "ls180.v:2550.11-2550.47" + attribute \src "ls180.v:2549.11-2549.47" wire width 2 $1\builder_comb_rhs_array_muxed2[1:0] - attribute \src "ls180.v:2584.11-2584.48" + attribute \src "ls180.v:2583.11-2583.48" wire width 3 $1\builder_comb_rhs_array_muxed30[2:0] - attribute \src "ls180.v:2585.11-2585.48" + attribute \src "ls180.v:2584.11-2584.48" wire width 2 $1\builder_comb_rhs_array_muxed31[1:0] - attribute \src "ls180.v:2551.5-2551.41" + attribute \src "ls180.v:2550.5-2550.41" wire $1\builder_comb_rhs_array_muxed3[0:0] - attribute \src "ls180.v:2552.5-2552.41" + attribute \src "ls180.v:2551.5-2551.41" wire $1\builder_comb_rhs_array_muxed4[0:0] - attribute \src "ls180.v:2553.5-2553.41" + attribute \src "ls180.v:2552.5-2552.41" wire $1\builder_comb_rhs_array_muxed5[0:0] - attribute \src "ls180.v:2557.5-2557.41" + attribute \src "ls180.v:2556.5-2556.41" wire $1\builder_comb_rhs_array_muxed6[0:0] - attribute \src "ls180.v:2558.12-2558.49" + attribute \src "ls180.v:2557.12-2557.49" wire width 13 $1\builder_comb_rhs_array_muxed7[12:0] - attribute \src "ls180.v:2559.11-2559.47" + attribute \src "ls180.v:2558.11-2558.47" wire width 2 $1\builder_comb_rhs_array_muxed8[1:0] - attribute \src "ls180.v:2560.5-2560.41" + attribute \src "ls180.v:2559.5-2559.41" wire $1\builder_comb_rhs_array_muxed9[0:0] - attribute \src "ls180.v:2554.5-2554.39" + attribute \src "ls180.v:2553.5-2553.39" wire $1\builder_comb_t_array_muxed0[0:0] - attribute \src "ls180.v:2555.5-2555.39" + attribute \src "ls180.v:2554.5-2554.39" wire $1\builder_comb_t_array_muxed1[0:0] - attribute \src "ls180.v:2556.5-2556.39" + attribute \src "ls180.v:2555.5-2555.39" wire $1\builder_comb_t_array_muxed2[0:0] - attribute \src "ls180.v:2563.5-2563.39" + attribute \src "ls180.v:2562.5-2562.39" wire $1\builder_comb_t_array_muxed3[0:0] - attribute \src "ls180.v:2564.5-2564.39" + attribute \src "ls180.v:2563.5-2563.39" wire $1\builder_comb_t_array_muxed4[0:0] - attribute \src "ls180.v:2565.5-2565.39" + attribute \src "ls180.v:2564.5-2564.39" wire $1\builder_comb_t_array_muxed5[0:0] - attribute \src "ls180.v:1696.5-1696.41" + attribute \src "ls180.v:1695.5-1695.41" wire $1\builder_converter0_next_state[0:0] - attribute \src "ls180.v:1695.5-1695.36" + attribute \src "ls180.v:1694.5-1694.36" wire $1\builder_converter0_state[0:0] - attribute \src "ls180.v:1700.5-1700.41" + attribute \src "ls180.v:1699.5-1699.41" wire $1\builder_converter1_next_state[0:0] - attribute \src "ls180.v:1699.5-1699.36" + attribute \src "ls180.v:1698.5-1698.36" wire $1\builder_converter1_state[0:0] - attribute \src "ls180.v:1704.5-1704.41" + attribute \src "ls180.v:1703.5-1703.41" wire $1\builder_converter2_next_state[0:0] - attribute \src "ls180.v:1703.5-1703.36" + attribute \src "ls180.v:1702.5-1702.36" wire $1\builder_converter2_state[0:0] - attribute \src "ls180.v:1741.5-1741.40" + attribute \src "ls180.v:1740.5-1740.40" wire $1\builder_converter_next_state[0:0] - attribute \src "ls180.v:1740.5-1740.35" + attribute \src "ls180.v:1739.5-1739.35" wire $1\builder_converter_state[0:0] - attribute \src "ls180.v:1861.12-1861.39" + attribute \src "ls180.v:1860.12-1860.39" wire width 20 $1\builder_count[19:0] - attribute \src "ls180.v:1858.5-1858.25" + attribute \src "ls180.v:1857.5-1857.25" wire $1\builder_error[0:0] - attribute \src "ls180.v:1855.11-1855.31" + attribute \src "ls180.v:1854.11-1854.31" wire width 3 $1\builder_grant[2:0] - attribute \src "ls180.v:1865.11-1865.51" + attribute \src "ls180.v:1864.11-1864.51" wire width 8 $1\builder_interface0_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2387.11-2387.52" + attribute \src "ls180.v:2386.11-2386.52" wire width 8 $1\builder_interface10_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2428.11-2428.52" + attribute \src "ls180.v:2427.11-2427.52" wire width 8 $1\builder_interface11_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2493.11-2493.52" + attribute \src "ls180.v:2492.11-2492.52" wire width 8 $1\builder_interface12_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2518.11-2518.52" + attribute \src "ls180.v:2517.11-2517.52" wire width 8 $1\builder_interface13_bank_bus_dat_r[7:0] - attribute \src "ls180.v:1906.11-1906.51" + attribute \src "ls180.v:1905.11-1905.51" wire width 8 $1\builder_interface1_bank_bus_dat_r[7:0] - attribute \src "ls180.v:1935.11-1935.51" + attribute \src "ls180.v:1934.11-1934.51" wire width 8 $1\builder_interface2_bank_bus_dat_r[7:0] - attribute \src "ls180.v:1976.11-1976.51" + attribute \src "ls180.v:1975.11-1975.51" wire width 8 $1\builder_interface3_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2017.11-2017.51" + attribute \src "ls180.v:2016.11-2016.51" wire width 8 $1\builder_interface4_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2082.11-2082.51" + attribute \src "ls180.v:2081.11-2081.51" wire width 8 $1\builder_interface5_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2215.11-2215.51" + attribute \src "ls180.v:2214.11-2214.51" wire width 8 $1\builder_interface6_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2296.11-2296.51" + attribute \src "ls180.v:2295.11-2295.51" wire width 8 $1\builder_interface7_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2313.11-2313.51" + attribute \src "ls180.v:2312.11-2312.51" wire width 8 $1\builder_interface8_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2354.11-2354.51" + attribute \src "ls180.v:2353.11-2353.51" wire width 8 $1\builder_interface9_bank_bus_dat_r[7:0] - attribute \src "ls180.v:1828.12-1828.43" + attribute \src "ls180.v:1827.12-1827.43" wire width 14 $1\builder_libresocsim_adr[13:0] - attribute \src "ls180.v:2544.12-2544.55" + attribute \src "ls180.v:2543.12-2543.55" wire width 14 $1\builder_libresocsim_adr_next_value1[13:0] - attribute \src "ls180.v:2545.5-2545.50" + attribute \src "ls180.v:2544.5-2544.50" wire $1\builder_libresocsim_adr_next_value_ce1[0:0] - attribute \src "ls180.v:1830.11-1830.43" + attribute \src "ls180.v:1829.11-1829.43" wire width 8 $1\builder_libresocsim_dat_w[7:0] - attribute \src "ls180.v:2542.11-2542.55" + attribute \src "ls180.v:2541.11-2541.55" wire width 8 $1\builder_libresocsim_dat_w_next_value0[7:0] - attribute \src "ls180.v:2543.5-2543.52" + attribute \src "ls180.v:2542.5-2542.52" wire $1\builder_libresocsim_dat_w_next_value_ce0[0:0] - attribute \src "ls180.v:1829.5-1829.34" + attribute \src "ls180.v:1828.5-1828.34" wire $1\builder_libresocsim_we[0:0] - attribute \src "ls180.v:2546.5-2546.46" + attribute \src "ls180.v:2545.5-2545.46" wire $1\builder_libresocsim_we_next_value2[0:0] - attribute \src "ls180.v:2547.5-2547.49" + attribute \src "ls180.v:2546.5-2546.49" wire $1\builder_libresocsim_we_next_value_ce2[0:0] - attribute \src "ls180.v:1838.5-1838.44" + attribute \src "ls180.v:1837.5-1837.44" wire $1\builder_libresocsim_wishbone_ack[0:0] - attribute \src "ls180.v:1834.12-1834.54" + attribute \src "ls180.v:1833.12-1833.54" wire width 32 $1\builder_libresocsim_wishbone_dat_r[31:0] - attribute \src "ls180.v:1718.11-1718.48" + attribute \src "ls180.v:1717.11-1717.48" wire width 3 $1\builder_multiplexer_next_state[2:0] - attribute \src "ls180.v:1717.11-1717.43" + attribute \src "ls180.v:1716.11-1716.43" wire width 3 $1\builder_multiplexer_state[2:0] - attribute \src "ls180.v:2649.32-2649.66" - wire $1\builder_multiregimpl0_regs0[0:0] attribute \src "ls180.v:2650.32-2650.66" + wire $1\builder_multiregimpl0_regs0[0:0] + attribute \src "ls180.v:2651.32-2651.66" wire $1\builder_multiregimpl0_regs1[0:0] - attribute \src "ls180.v:2669.32-2669.67" - wire $1\builder_multiregimpl10_regs0[0:0] attribute \src "ls180.v:2670.32-2670.67" - wire $1\builder_multiregimpl10_regs1[0:0] + wire $1\builder_multiregimpl10_regs0[0:0] attribute \src "ls180.v:2671.32-2671.67" - wire $1\builder_multiregimpl11_regs0[0:0] + wire $1\builder_multiregimpl10_regs1[0:0] attribute \src "ls180.v:2672.32-2672.67" - wire $1\builder_multiregimpl11_regs1[0:0] + wire $1\builder_multiregimpl11_regs0[0:0] attribute \src "ls180.v:2673.32-2673.67" - wire $1\builder_multiregimpl12_regs0[0:0] + wire $1\builder_multiregimpl11_regs1[0:0] attribute \src "ls180.v:2674.32-2674.67" - wire $1\builder_multiregimpl12_regs1[0:0] + wire $1\builder_multiregimpl12_regs0[0:0] attribute \src "ls180.v:2675.32-2675.67" - wire $1\builder_multiregimpl13_regs0[0:0] + wire $1\builder_multiregimpl12_regs1[0:0] attribute \src "ls180.v:2676.32-2676.67" - wire $1\builder_multiregimpl13_regs1[0:0] + wire $1\builder_multiregimpl13_regs0[0:0] attribute \src "ls180.v:2677.32-2677.67" - wire $1\builder_multiregimpl14_regs0[0:0] + wire $1\builder_multiregimpl13_regs1[0:0] attribute \src "ls180.v:2678.32-2678.67" - wire $1\builder_multiregimpl14_regs1[0:0] + wire $1\builder_multiregimpl14_regs0[0:0] attribute \src "ls180.v:2679.32-2679.67" - wire $1\builder_multiregimpl15_regs0[0:0] + wire $1\builder_multiregimpl14_regs1[0:0] attribute \src "ls180.v:2680.32-2680.67" - wire $1\builder_multiregimpl15_regs1[0:0] + wire $1\builder_multiregimpl15_regs0[0:0] attribute \src "ls180.v:2681.32-2681.67" - wire $1\builder_multiregimpl16_regs0[0:0] + wire $1\builder_multiregimpl15_regs1[0:0] attribute \src "ls180.v:2682.32-2682.67" + wire $1\builder_multiregimpl16_regs0[0:0] + attribute \src "ls180.v:2683.32-2683.67" wire $1\builder_multiregimpl16_regs1[0:0] - attribute \src "ls180.v:2651.32-2651.66" - wire $1\builder_multiregimpl1_regs0[0:0] attribute \src "ls180.v:2652.32-2652.66" - wire $1\builder_multiregimpl1_regs1[0:0] + wire $1\builder_multiregimpl1_regs0[0:0] attribute \src "ls180.v:2653.32-2653.66" - wire $1\builder_multiregimpl2_regs0[0:0] + wire $1\builder_multiregimpl1_regs1[0:0] attribute \src "ls180.v:2654.32-2654.66" - wire $1\builder_multiregimpl2_regs1[0:0] + wire $1\builder_multiregimpl2_regs0[0:0] attribute \src "ls180.v:2655.32-2655.66" - wire $1\builder_multiregimpl3_regs0[0:0] + wire $1\builder_multiregimpl2_regs1[0:0] attribute \src "ls180.v:2656.32-2656.66" - wire $1\builder_multiregimpl3_regs1[0:0] + wire $1\builder_multiregimpl3_regs0[0:0] attribute \src "ls180.v:2657.32-2657.66" - wire $1\builder_multiregimpl4_regs0[0:0] + wire $1\builder_multiregimpl3_regs1[0:0] attribute \src "ls180.v:2658.32-2658.66" - wire $1\builder_multiregimpl4_regs1[0:0] + wire $1\builder_multiregimpl4_regs0[0:0] attribute \src "ls180.v:2659.32-2659.66" - wire $1\builder_multiregimpl5_regs0[0:0] + wire $1\builder_multiregimpl4_regs1[0:0] attribute \src "ls180.v:2660.32-2660.66" - wire $1\builder_multiregimpl5_regs1[0:0] + wire $1\builder_multiregimpl5_regs0[0:0] attribute \src "ls180.v:2661.32-2661.66" - wire $1\builder_multiregimpl6_regs0[0:0] + wire $1\builder_multiregimpl5_regs1[0:0] attribute \src "ls180.v:2662.32-2662.66" - wire $1\builder_multiregimpl6_regs1[0:0] + wire $1\builder_multiregimpl6_regs0[0:0] attribute \src "ls180.v:2663.32-2663.66" - wire $1\builder_multiregimpl7_regs0[0:0] + wire $1\builder_multiregimpl6_regs1[0:0] attribute \src "ls180.v:2664.32-2664.66" - wire $1\builder_multiregimpl7_regs1[0:0] + wire $1\builder_multiregimpl7_regs0[0:0] attribute \src "ls180.v:2665.32-2665.66" - wire $1\builder_multiregimpl8_regs0[0:0] + wire $1\builder_multiregimpl7_regs1[0:0] attribute \src "ls180.v:2666.32-2666.66" - wire $1\builder_multiregimpl8_regs1[0:0] + wire $1\builder_multiregimpl8_regs0[0:0] attribute \src "ls180.v:2667.32-2667.66" - wire $1\builder_multiregimpl9_regs0[0:0] + wire $1\builder_multiregimpl8_regs1[0:0] attribute \src "ls180.v:2668.32-2668.66" + wire $1\builder_multiregimpl9_regs0[0:0] + attribute \src "ls180.v:2669.32-2669.66" wire $1\builder_multiregimpl9_regs1[0:0] - attribute \src "ls180.v:1736.5-1736.43" + attribute \src "ls180.v:1735.5-1735.43" wire $1\builder_new_master_rdata_valid0[0:0] - attribute \src "ls180.v:1737.5-1737.43" + attribute \src "ls180.v:1736.5-1736.43" wire $1\builder_new_master_rdata_valid1[0:0] - attribute \src "ls180.v:1738.5-1738.43" + attribute \src "ls180.v:1737.5-1737.43" wire $1\builder_new_master_rdata_valid2[0:0] - attribute \src "ls180.v:1739.5-1739.43" + attribute \src "ls180.v:1738.5-1738.43" wire $1\builder_new_master_rdata_valid3[0:0] - attribute \src "ls180.v:1735.5-1735.42" + attribute \src "ls180.v:1734.5-1734.42" wire $1\builder_new_master_wdata_ready[0:0] - attribute \src "ls180.v:2541.11-2541.36" + attribute \src "ls180.v:2540.11-2540.36" wire width 2 $1\builder_next_state[1:0] - attribute \src "ls180.v:1708.11-1708.46" + attribute \src "ls180.v:1707.11-1707.46" wire width 2 $1\builder_refresher_next_state[1:0] - attribute \src "ls180.v:1707.11-1707.41" + attribute \src "ls180.v:1706.11-1706.41" wire width 2 $1\builder_refresher_state[1:0] - attribute \src "ls180.v:1813.11-1813.51" + attribute \src "ls180.v:1812.11-1812.51" wire width 2 $1\builder_sdblock2memdma_next_state[1:0] - attribute \src "ls180.v:1812.11-1812.46" + attribute \src "ls180.v:1811.11-1811.46" wire width 2 $1\builder_sdblock2memdma_state[1:0] - attribute \src "ls180.v:1781.5-1781.57" + attribute \src "ls180.v:1780.5-1780.57" wire $1\builder_sdcore_crcupstreaminserter_next_state[0:0] - attribute \src "ls180.v:1780.5-1780.52" + attribute \src "ls180.v:1779.5-1779.52" wire $1\builder_sdcore_crcupstreaminserter_state[0:0] - attribute \src "ls180.v:1793.11-1793.47" + attribute \src "ls180.v:1792.11-1792.47" wire width 3 $1\builder_sdcore_fsm_next_state[2:0] - attribute \src "ls180.v:1792.11-1792.42" + attribute \src "ls180.v:1791.11-1791.42" wire width 3 $1\builder_sdcore_fsm_state[2:0] - attribute \src "ls180.v:1817.5-1817.49" + attribute \src "ls180.v:1816.5-1816.49" wire $1\builder_sdmem2blockdma_fsm_next_state[0:0] - attribute \src "ls180.v:1816.5-1816.44" + attribute \src "ls180.v:1815.5-1815.44" wire $1\builder_sdmem2blockdma_fsm_state[0:0] - attribute \src "ls180.v:1821.11-1821.65" + attribute \src "ls180.v:1820.11-1820.65" wire width 2 $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] - attribute \src "ls180.v:1820.11-1820.60" + attribute \src "ls180.v:1819.11-1819.60" wire width 2 $1\builder_sdmem2blockdma_resetinserter_state[1:0] - attribute \src "ls180.v:1769.11-1769.46" + attribute \src "ls180.v:1768.11-1768.46" wire width 3 $1\builder_sdphy_fsm_next_state[2:0] - attribute \src "ls180.v:1768.11-1768.41" + attribute \src "ls180.v:1767.11-1767.41" wire width 3 $1\builder_sdphy_fsm_state[2:0] - attribute \src "ls180.v:1757.11-1757.52" + attribute \src "ls180.v:1756.11-1756.52" wire width 3 $1\builder_sdphy_sdphycmdr_next_state[2:0] - attribute \src "ls180.v:1756.11-1756.47" + attribute \src "ls180.v:1755.11-1755.47" wire width 3 $1\builder_sdphy_sdphycmdr_state[2:0] - attribute \src "ls180.v:1753.11-1753.52" + attribute \src "ls180.v:1752.11-1752.52" wire width 2 $1\builder_sdphy_sdphycmdw_next_state[1:0] - attribute \src "ls180.v:1752.11-1752.47" + attribute \src "ls180.v:1751.11-1751.47" wire width 2 $1\builder_sdphy_sdphycmdw_state[1:0] - attribute \src "ls180.v:1765.5-1765.46" + attribute \src "ls180.v:1764.5-1764.46" wire $1\builder_sdphy_sdphycrcr_next_state[0:0] - attribute \src "ls180.v:1764.5-1764.41" + attribute \src "ls180.v:1763.5-1763.41" wire $1\builder_sdphy_sdphycrcr_state[0:0] - attribute \src "ls180.v:1773.11-1773.53" + attribute \src "ls180.v:1772.11-1772.53" wire width 3 $1\builder_sdphy_sdphydatar_next_state[2:0] - attribute \src "ls180.v:1772.11-1772.48" + attribute \src "ls180.v:1771.11-1771.48" wire width 3 $1\builder_sdphy_sdphydatar_state[2:0] - attribute \src "ls180.v:1749.5-1749.46" + attribute \src "ls180.v:1748.5-1748.46" wire $1\builder_sdphy_sdphyinit_next_state[0:0] - attribute \src "ls180.v:1748.5-1748.41" + attribute \src "ls180.v:1747.5-1747.41" wire $1\builder_sdphy_sdphyinit_state[0:0] - attribute \src "ls180.v:1849.5-1849.30" + attribute \src "ls180.v:1848.5-1848.30" wire $1\builder_shared_ack[0:0] - attribute \src "ls180.v:1845.12-1845.40" + attribute \src "ls180.v:1844.12-1844.40" wire width 32 $1\builder_shared_dat_r[31:0] - attribute \src "ls180.v:1856.11-1856.35" + attribute \src "ls180.v:1855.11-1855.35" wire width 5 $1\builder_slave_sel[4:0] - attribute \src "ls180.v:1857.11-1857.37" + attribute \src "ls180.v:1856.11-1856.37" wire width 5 $1\builder_slave_sel_r[4:0] - attribute \src "ls180.v:1745.11-1745.47" + attribute \src "ls180.v:1744.11-1744.47" wire width 2 $1\builder_spimaster0_next_state[1:0] - attribute \src "ls180.v:1744.11-1744.42" + attribute \src "ls180.v:1743.11-1743.42" wire width 2 $1\builder_spimaster0_state[1:0] - attribute \src "ls180.v:1825.11-1825.47" + attribute \src "ls180.v:1824.11-1824.47" wire width 2 $1\builder_spimaster1_next_state[1:0] - attribute \src "ls180.v:1824.11-1824.42" + attribute \src "ls180.v:1823.11-1823.42" wire width 2 $1\builder_spimaster1_state[1:0] - attribute \src "ls180.v:2540.11-2540.31" + attribute \src "ls180.v:2539.11-2539.31" wire width 2 $1\builder_state[1:0] - attribute \src "ls180.v:2593.5-2593.39" + attribute \src "ls180.v:2592.5-2592.39" wire $1\builder_sync_f_array_muxed0[0:0] - attribute \src "ls180.v:2594.5-2594.39" + attribute \src "ls180.v:2593.5-2593.39" wire $1\builder_sync_f_array_muxed1[0:0] - attribute \src "ls180.v:2586.11-2586.47" + attribute \src "ls180.v:2585.11-2585.47" wire width 2 $1\builder_sync_rhs_array_muxed0[1:0] - attribute \src "ls180.v:2587.12-2587.49" + attribute \src "ls180.v:2586.12-2586.49" wire width 13 $1\builder_sync_rhs_array_muxed1[12:0] - attribute \src "ls180.v:2588.5-2588.41" + attribute \src "ls180.v:2587.5-2587.41" wire $1\builder_sync_rhs_array_muxed2[0:0] - attribute \src "ls180.v:2589.5-2589.41" + attribute \src "ls180.v:2588.5-2588.41" wire $1\builder_sync_rhs_array_muxed3[0:0] - attribute \src "ls180.v:2590.5-2590.41" + attribute \src "ls180.v:2589.5-2589.41" wire $1\builder_sync_rhs_array_muxed4[0:0] - attribute \src "ls180.v:2591.5-2591.41" + attribute \src "ls180.v:2590.5-2590.41" wire $1\builder_sync_rhs_array_muxed5[0:0] - attribute \src "ls180.v:2592.5-2592.41" + attribute \src "ls180.v:2591.5-2591.41" wire $1\builder_sync_rhs_array_muxed6[0:0] - attribute \src "ls180.v:1687.12-1687.44" + attribute \src "ls180.v:1686.12-1686.44" wire width 16 $1\libresocsim_clk_divider1[15:0] - attribute \src "ls180.v:1682.5-1682.34" + attribute \src "ls180.v:1681.5-1681.34" wire $1\libresocsim_clk_enable[0:0] - attribute \src "ls180.v:1669.5-1669.34" + attribute \src "ls180.v:1668.5-1668.34" wire $1\libresocsim_control_re[0:0] - attribute \src "ls180.v:1668.12-1668.47" + attribute \src "ls180.v:1667.12-1667.47" wire width 16 $1\libresocsim_control_storage[15:0] - attribute \src "ls180.v:1684.11-1684.35" + attribute \src "ls180.v:1683.11-1683.35" wire width 3 $1\libresocsim_count[2:0] - attribute \src "ls180.v:1826.11-1826.57" + attribute \src "ls180.v:1825.11-1825.57" wire width 3 $1\libresocsim_count_spimaster1_next_value[2:0] - attribute \src "ls180.v:1827.5-1827.54" + attribute \src "ls180.v:1826.5-1826.54" wire $1\libresocsim_count_spimaster1_next_value_ce[0:0] - attribute \src "ls180.v:1683.5-1683.33" + attribute \src "ls180.v:1682.5-1682.33" wire $1\libresocsim_cs_enable[0:0] - attribute \src "ls180.v:1679.5-1679.29" + attribute \src "ls180.v:1678.5-1678.29" wire $1\libresocsim_cs_re[0:0] - attribute \src "ls180.v:1678.5-1678.34" + attribute \src "ls180.v:1677.5-1677.34" wire $1\libresocsim_cs_storage[0:0] - attribute \src "ls180.v:1659.5-1659.29" + attribute \src "ls180.v:1658.5-1658.29" wire $1\libresocsim_done0[0:0] - attribute \src "ls180.v:1660.5-1660.27" + attribute \src "ls180.v:1659.5-1659.27" wire $1\libresocsim_irq[0:0] - attribute \src "ls180.v:1681.5-1681.35" + attribute \src "ls180.v:1680.5-1680.35" wire $1\libresocsim_loopback_re[0:0] - attribute \src "ls180.v:1680.5-1680.40" + attribute \src "ls180.v:1679.5-1679.40" wire $1\libresocsim_loopback_storage[0:0] - attribute \src "ls180.v:1662.11-1662.34" + attribute \src "ls180.v:1661.11-1661.34" wire width 8 $1\libresocsim_miso[7:0] - attribute \src "ls180.v:1692.11-1692.39" + attribute \src "ls180.v:1691.11-1691.39" wire width 8 $1\libresocsim_miso_data[7:0] - attribute \src "ls180.v:1686.5-1686.34" + attribute \src "ls180.v:1685.5-1685.34" wire $1\libresocsim_miso_latch[0:0] - attribute \src "ls180.v:1690.11-1690.39" + attribute \src "ls180.v:1689.11-1689.39" wire width 8 $1\libresocsim_mosi_data[7:0] - attribute \src "ls180.v:1685.5-1685.34" + attribute \src "ls180.v:1684.5-1684.34" wire $1\libresocsim_mosi_latch[0:0] - attribute \src "ls180.v:1674.5-1674.31" + attribute \src "ls180.v:1673.5-1673.31" wire $1\libresocsim_mosi_re[0:0] - attribute \src "ls180.v:1691.11-1691.38" + attribute \src "ls180.v:1690.11-1690.38" wire width 3 $1\libresocsim_mosi_sel[2:0] - attribute \src "ls180.v:1673.11-1673.42" + attribute \src "ls180.v:1672.11-1672.42" wire width 8 $1\libresocsim_mosi_storage[7:0] - attribute \src "ls180.v:1694.5-1694.26" + attribute \src "ls180.v:1693.5-1693.26" wire $1\libresocsim_re[0:0] - attribute \src "ls180.v:1666.5-1666.30" + attribute \src "ls180.v:1665.5-1665.30" wire $1\libresocsim_start1[0:0] - attribute \src "ls180.v:1693.12-1693.41" + attribute \src "ls180.v:1692.12-1692.41" wire width 16 $1\libresocsim_storage[15:0] - attribute \src "ls180.v:805.5-805.29" + attribute \src "ls180.v:804.5-804.29" wire $1\main_cmd_consumed[0:0] - attribute \src "ls180.v:802.5-802.34" + attribute \src "ls180.v:801.5-801.34" wire $1\main_converter_counter[0:0] - attribute \src "ls180.v:1742.5-1742.55" + attribute \src "ls180.v:1741.5-1741.55" wire $1\main_converter_counter_converter_next_value[0:0] - attribute \src "ls180.v:1743.5-1743.58" + attribute \src "ls180.v:1742.5-1742.58" wire $1\main_converter_counter_converter_next_value_ce[0:0] - attribute \src "ls180.v:804.12-804.40" + attribute \src "ls180.v:803.12-803.40" wire width 32 $1\main_converter_dat_r[31:0] - attribute \src "ls180.v:801.5-801.31" + attribute \src "ls180.v:800.5-800.31" wire $1\main_converter_skip[0:0] attribute \src "ls180.v:235.12-235.38" wire width 16 $1\main_dfi_p0_rddata[15:0] attribute \src "ls180.v:236.5-236.36" wire $1\main_dfi_p0_rddata_valid[0:0] - attribute \src "ls180.v:237.11-237.25" - wire width 2 $1\main_dm[1:0] - attribute \src "ls180.v:998.12-998.30" - wire width 43 $1\main_dummy[42:0] - attribute \src "ls180.v:953.5-953.27" + attribute \src "ls180.v:997.12-997.30" + wire width 42 $1\main_dummy[41:0] + attribute \src "ls180.v:952.5-952.27" wire $1\main_gpio_oe_re[0:0] - attribute \src "ls180.v:952.12-952.40" + attribute \src "ls180.v:951.12-951.40" wire width 16 $1\main_gpio_oe_storage[15:0] - attribute \src "ls180.v:957.5-957.28" + attribute \src "ls180.v:956.5-956.28" wire $1\main_gpio_out_re[0:0] - attribute \src "ls180.v:956.12-956.41" + attribute \src "ls180.v:955.12-955.41" wire width 16 $1\main_gpio_out_storage[15:0] - attribute \src "ls180.v:954.12-954.36" + attribute \src "ls180.v:953.12-953.36" wire width 16 $1\main_gpio_status[15:0] attribute \src "ls180.v:220.5-220.24" wire $1\main_int_rst[0:0] - attribute \src "ls180.v:1563.12-1563.43" + attribute \src "ls180.v:1562.12-1562.43" wire width 32 $1\main_interface1_bus_adr[31:0] - attribute \src "ls180.v:1567.5-1567.35" + attribute \src "ls180.v:1566.5-1566.35" wire $1\main_interface1_bus_cyc[0:0] - attribute \src "ls180.v:1566.11-1566.41" + attribute \src "ls180.v:1565.11-1565.41" wire width 4 $1\main_interface1_bus_sel[3:0] - attribute \src "ls180.v:1568.5-1568.35" + attribute \src "ls180.v:1567.5-1567.35" wire $1\main_interface1_bus_stb[0:0] - attribute \src "ls180.v:1570.5-1570.34" + attribute \src "ls180.v:1569.5-1569.34" wire $1\main_interface1_bus_we[0:0] attribute \src "ls180.v:57.12-57.47" wire width 32 $1\main_libresocsim_bus_errors[31:0] attribute \src "ls180.v:142.5-142.47" wire $1\main_libresocsim_converter0_counter[0:0] - attribute \src "ls180.v:1697.5-1697.69" + attribute \src "ls180.v:1696.5-1696.69" wire $1\main_libresocsim_converter0_counter_converter0_next_value[0:0] - attribute \src "ls180.v:1698.5-1698.72" + attribute \src "ls180.v:1697.5-1697.72" wire $1\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] attribute \src "ls180.v:144.12-144.53" wire width 64 $1\main_libresocsim_converter0_dat_r[63:0] @@ -70912,9 +70908,9 @@ module \ls180 wire $1\main_libresocsim_converter0_skip[0:0] attribute \src "ls180.v:157.5-157.47" wire $1\main_libresocsim_converter1_counter[0:0] - attribute \src "ls180.v:1701.5-1701.69" + attribute \src "ls180.v:1700.5-1700.69" wire $1\main_libresocsim_converter1_counter_converter1_next_value[0:0] - attribute \src "ls180.v:1702.5-1702.72" + attribute \src "ls180.v:1701.5-1701.72" wire $1\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] attribute \src "ls180.v:159.12-159.53" wire width 64 $1\main_libresocsim_converter1_dat_r[63:0] @@ -70922,9 +70918,9 @@ module \ls180 wire $1\main_libresocsim_converter1_skip[0:0] attribute \src "ls180.v:172.5-172.47" wire $1\main_libresocsim_converter2_counter[0:0] - attribute \src "ls180.v:1705.5-1705.69" + attribute \src "ls180.v:1704.5-1704.69" wire $1\main_libresocsim_converter2_counter_converter2_next_value[0:0] - attribute \src "ls180.v:1706.5-1706.72" + attribute \src "ls180.v:1705.5-1705.72" wire $1\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] attribute \src "ls180.v:174.12-174.53" wire width 64 $1\main_libresocsim_converter2_dat_r[63:0] @@ -71018,8043 +71014,8041 @@ module \ls180 wire $1\main_libresocsim_zero_old_trigger[0:0] attribute \src "ls180.v:202.5-202.41" wire $1\main_libresocsim_zero_pending[0:0] - attribute \src "ls180.v:793.12-793.40" + attribute \src "ls180.v:792.12-792.40" wire width 30 $1\main_litedram_wb_adr[29:0] - attribute \src "ls180.v:797.5-797.32" + attribute \src "ls180.v:796.5-796.32" wire $1\main_litedram_wb_cyc[0:0] - attribute \src "ls180.v:794.12-794.42" + attribute \src "ls180.v:793.12-793.42" wire width 16 $1\main_litedram_wb_dat_w[15:0] - attribute \src "ls180.v:796.11-796.38" + attribute \src "ls180.v:795.11-795.38" wire width 2 $1\main_litedram_wb_sel[1:0] - attribute \src "ls180.v:798.5-798.32" + attribute \src "ls180.v:797.5-797.32" wire $1\main_litedram_wb_stb[0:0] - attribute \src "ls180.v:800.5-800.31" + attribute \src "ls180.v:799.5-799.31" wire $1\main_litedram_wb_we[0:0] - attribute \src "ls180.v:828.12-828.45" + attribute \src "ls180.v:827.12-827.45" wire width 32 $1\main_phase_accumulator_rx[31:0] - attribute \src "ls180.v:818.12-818.45" + attribute \src "ls180.v:817.12-817.45" wire width 32 $1\main_phase_accumulator_tx[31:0] - attribute \src "ls180.v:1002.12-1002.37" + attribute \src "ls180.v:1001.12-1001.37" wire width 32 $1\main_pwm0_counter[31:0] - attribute \src "ls180.v:1004.5-1004.31" + attribute \src "ls180.v:1003.5-1003.31" wire $1\main_pwm0_enable_re[0:0] - attribute \src "ls180.v:1003.5-1003.36" + attribute \src "ls180.v:1002.5-1002.36" wire $1\main_pwm0_enable_storage[0:0] - attribute \src "ls180.v:1008.5-1008.31" + attribute \src "ls180.v:1007.5-1007.31" wire $1\main_pwm0_period_re[0:0] - attribute \src "ls180.v:1007.12-1007.44" + attribute \src "ls180.v:1006.12-1006.44" wire width 32 $1\main_pwm0_period_storage[31:0] - attribute \src "ls180.v:1006.5-1006.30" + attribute \src "ls180.v:1005.5-1005.30" wire $1\main_pwm0_width_re[0:0] - attribute \src "ls180.v:1005.12-1005.43" + attribute \src "ls180.v:1004.12-1004.43" wire width 32 $1\main_pwm0_width_storage[31:0] - attribute \src "ls180.v:1012.12-1012.37" + attribute \src "ls180.v:1011.12-1011.37" wire width 32 $1\main_pwm1_counter[31:0] - attribute \src "ls180.v:1014.5-1014.31" + attribute \src "ls180.v:1013.5-1013.31" wire $1\main_pwm1_enable_re[0:0] - attribute \src "ls180.v:1013.5-1013.36" + attribute \src "ls180.v:1012.5-1012.36" wire $1\main_pwm1_enable_storage[0:0] - attribute \src "ls180.v:1018.5-1018.31" + attribute \src "ls180.v:1017.5-1017.31" wire $1\main_pwm1_period_re[0:0] - attribute \src "ls180.v:1017.12-1017.44" + attribute \src "ls180.v:1016.12-1016.44" wire width 32 $1\main_pwm1_period_storage[31:0] - attribute \src "ls180.v:1016.5-1016.30" + attribute \src "ls180.v:1015.5-1015.30" wire $1\main_pwm1_width_re[0:0] - attribute \src "ls180.v:1015.12-1015.43" + attribute \src "ls180.v:1014.12-1014.43" wire width 32 $1\main_pwm1_width_storage[31:0] - attribute \src "ls180.v:238.11-238.32" + attribute \src "ls180.v:237.11-237.32" wire width 3 $1\main_rddata_en[2:0] - attribute \src "ls180.v:811.5-811.19" + attribute \src "ls180.v:810.5-810.19" wire $1\main_re[0:0] - attribute \src "ls180.v:832.11-832.34" + attribute \src "ls180.v:831.11-831.34" wire width 4 $1\main_rx_bitcount[3:0] - attribute \src "ls180.v:833.5-833.24" + attribute \src "ls180.v:832.5-832.24" wire $1\main_rx_busy[0:0] - attribute \src "ls180.v:830.5-830.21" + attribute \src "ls180.v:829.5-829.21" wire $1\main_rx_r[0:0] - attribute \src "ls180.v:831.11-831.29" + attribute \src "ls180.v:830.11-830.29" wire width 8 $1\main_rx_reg[7:0] - attribute \src "ls180.v:1532.11-1532.50" + attribute \src "ls180.v:1531.11-1531.50" wire width 2 $1\main_sdblock2mem_converter_demux[1:0] - attribute \src "ls180.v:1528.5-1528.51" + attribute \src "ls180.v:1527.5-1527.51" wire $1\main_sdblock2mem_converter_source_first[0:0] - attribute \src "ls180.v:1529.5-1529.50" + attribute \src "ls180.v:1528.5-1528.50" wire $1\main_sdblock2mem_converter_source_last[0:0] - attribute \src "ls180.v:1530.12-1530.66" + attribute \src "ls180.v:1529.12-1529.66" wire width 32 $1\main_sdblock2mem_converter_source_payload_data[31:0] - attribute \src "ls180.v:1531.11-1531.77" + attribute \src "ls180.v:1530.11-1530.77" wire width 3 $1\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] - attribute \src "ls180.v:1534.5-1534.49" + attribute \src "ls180.v:1533.5-1533.49" wire $1\main_sdblock2mem_converter_strobe_all[0:0] - attribute \src "ls180.v:1507.11-1507.47" + attribute \src "ls180.v:1506.11-1506.47" wire width 5 $1\main_sdblock2mem_fifo_consume[4:0] - attribute \src "ls180.v:1504.11-1504.45" + attribute \src "ls180.v:1503.11-1503.45" wire width 6 $1\main_sdblock2mem_fifo_level[5:0] - attribute \src "ls180.v:1506.11-1506.47" + attribute \src "ls180.v:1505.11-1505.47" wire width 5 $1\main_sdblock2mem_fifo_produce[4:0] - attribute \src "ls180.v:1508.11-1508.50" + attribute \src "ls180.v:1507.11-1507.50" wire width 5 $1\main_sdblock2mem_fifo_wrport_adr[4:0] - attribute \src "ls180.v:1542.12-1542.62" + attribute \src "ls180.v:1541.12-1541.62" wire width 32 $1\main_sdblock2mem_sink_sink_payload_address[31:0] - attribute \src "ls180.v:1543.12-1543.60" + attribute \src "ls180.v:1542.12-1542.60" wire width 32 $1\main_sdblock2mem_sink_sink_payload_data1[31:0] - attribute \src "ls180.v:1540.5-1540.45" + attribute \src "ls180.v:1539.5-1539.45" wire $1\main_sdblock2mem_sink_sink_valid1[0:0] - attribute \src "ls180.v:1550.5-1550.54" + attribute \src "ls180.v:1549.5-1549.54" wire $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] - attribute \src "ls180.v:1549.12-1549.67" + attribute \src "ls180.v:1548.12-1548.67" wire width 64 $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] - attribute \src "ls180.v:1554.5-1554.56" + attribute \src "ls180.v:1553.5-1553.56" wire $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] - attribute \src "ls180.v:1553.5-1553.61" + attribute \src "ls180.v:1552.5-1552.61" wire $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] - attribute \src "ls180.v:1552.5-1552.56" + attribute \src "ls180.v:1551.5-1551.56" wire $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] - attribute \src "ls180.v:1551.12-1551.69" + attribute \src "ls180.v:1550.12-1550.69" wire width 32 $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] - attribute \src "ls180.v:1558.5-1558.54" + attribute \src "ls180.v:1557.5-1557.54" wire $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] - attribute \src "ls180.v:1557.5-1557.59" + attribute \src "ls180.v:1556.5-1556.59" wire $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] - attribute \src "ls180.v:1560.12-1560.61" + attribute \src "ls180.v:1559.12-1559.61" wire width 32 $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] - attribute \src "ls180.v:1814.12-1814.87" + attribute \src "ls180.v:1813.12-1813.87" wire width 32 $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] - attribute \src "ls180.v:1815.5-1815.82" + attribute \src "ls180.v:1814.5-1814.82" wire $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] - attribute \src "ls180.v:1545.5-1545.57" + attribute \src "ls180.v:1544.5-1544.57" wire $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] - attribute \src "ls180.v:1555.5-1555.53" + attribute \src "ls180.v:1554.5-1554.53" wire $1\main_sdblock2mem_wishbonedmawriter_status[0:0] - attribute \src "ls180.v:1324.5-1324.38" + attribute \src "ls180.v:1323.5-1323.38" wire $1\main_sdcore_block_count_re[0:0] - attribute \src "ls180.v:1323.12-1323.51" + attribute \src "ls180.v:1322.12-1322.51" wire width 32 $1\main_sdcore_block_count_storage[31:0] - attribute \src "ls180.v:1322.5-1322.39" + attribute \src "ls180.v:1321.5-1321.39" wire $1\main_sdcore_block_length_re[0:0] - attribute \src "ls180.v:1321.11-1321.51" + attribute \src "ls180.v:1320.11-1320.51" wire width 10 $1\main_sdcore_block_length_storage[9:0] - attribute \src "ls180.v:1308.5-1308.39" + attribute \src "ls180.v:1307.5-1307.39" wire $1\main_sdcore_cmd_argument_re[0:0] - attribute \src "ls180.v:1307.12-1307.52" + attribute \src "ls180.v:1306.12-1306.52" wire width 32 $1\main_sdcore_cmd_argument_storage[31:0] - attribute \src "ls180.v:1310.5-1310.38" + attribute \src "ls180.v:1309.5-1309.38" wire $1\main_sdcore_cmd_command_re[0:0] - attribute \src "ls180.v:1309.12-1309.51" + attribute \src "ls180.v:1308.12-1308.51" wire width 32 $1\main_sdcore_cmd_command_storage[31:0] - attribute \src "ls180.v:1463.11-1463.39" + attribute \src "ls180.v:1462.11-1462.39" wire width 3 $1\main_sdcore_cmd_count[2:0] - attribute \src "ls180.v:1798.11-1798.62" + attribute \src "ls180.v:1797.11-1797.62" wire width 3 $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] - attribute \src "ls180.v:1799.5-1799.59" + attribute \src "ls180.v:1798.5-1798.59" wire $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] - attribute \src "ls180.v:1464.5-1464.32" + attribute \src "ls180.v:1463.5-1463.32" wire $1\main_sdcore_cmd_done[0:0] - attribute \src "ls180.v:1794.5-1794.55" + attribute \src "ls180.v:1793.5-1793.55" wire $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] - attribute \src "ls180.v:1795.5-1795.58" + attribute \src "ls180.v:1794.5-1794.58" wire $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] - attribute \src "ls180.v:1465.5-1465.33" + attribute \src "ls180.v:1464.5-1464.33" wire $1\main_sdcore_cmd_error[0:0] - attribute \src "ls180.v:1802.5-1802.56" + attribute \src "ls180.v:1801.5-1801.56" wire $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] - attribute \src "ls180.v:1803.5-1803.59" + attribute \src "ls180.v:1802.5-1802.59" wire $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] - attribute \src "ls180.v:1315.13-1315.53" + attribute \src "ls180.v:1314.13-1314.53" wire width 128 $1\main_sdcore_cmd_response_status[127:0] - attribute \src "ls180.v:1810.13-1810.76" + attribute \src "ls180.v:1809.13-1809.76" wire width 128 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] - attribute \src "ls180.v:1811.5-1811.69" + attribute \src "ls180.v:1810.5-1810.69" wire $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] - attribute \src "ls180.v:1466.5-1466.35" + attribute \src "ls180.v:1465.5-1465.35" wire $1\main_sdcore_cmd_timeout[0:0] - attribute \src "ls180.v:1804.5-1804.58" + attribute \src "ls180.v:1803.5-1803.58" wire $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] - attribute \src "ls180.v:1805.5-1805.61" + attribute \src "ls180.v:1804.5-1804.61" wire $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] - attribute \src "ls180.v:1424.11-1424.47" + attribute \src "ls180.v:1423.11-1423.47" wire width 4 $1\main_sdcore_crc16_checker_cnt[3:0] - attribute \src "ls180.v:1430.5-1430.46" + attribute \src "ls180.v:1429.5-1429.46" wire $1\main_sdcore_crc16_checker_crc0_clr[0:0] - attribute \src "ls180.v:1429.12-1429.54" + attribute \src "ls180.v:1428.12-1428.54" wire width 16 $1\main_sdcore_crc16_checker_crc0_crc[15:0] - attribute \src "ls180.v:1425.12-1425.58" + attribute \src "ls180.v:1424.12-1424.58" wire width 16 $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] - attribute \src "ls180.v:1437.5-1437.46" + attribute \src "ls180.v:1436.5-1436.46" wire $1\main_sdcore_crc16_checker_crc1_clr[0:0] - attribute \src "ls180.v:1436.12-1436.54" + attribute \src "ls180.v:1435.12-1435.54" wire width 16 $1\main_sdcore_crc16_checker_crc1_crc[15:0] - attribute \src "ls180.v:1432.12-1432.58" + attribute \src "ls180.v:1431.12-1431.58" wire width 16 $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] - attribute \src "ls180.v:1444.5-1444.46" + attribute \src "ls180.v:1443.5-1443.46" wire $1\main_sdcore_crc16_checker_crc2_clr[0:0] - attribute \src "ls180.v:1443.12-1443.54" + attribute \src "ls180.v:1442.12-1442.54" wire width 16 $1\main_sdcore_crc16_checker_crc2_crc[15:0] - attribute \src "ls180.v:1439.12-1439.58" + attribute \src "ls180.v:1438.12-1438.58" wire width 16 $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] - attribute \src "ls180.v:1451.5-1451.46" + attribute \src "ls180.v:1450.5-1450.46" wire $1\main_sdcore_crc16_checker_crc3_clr[0:0] - attribute \src "ls180.v:1450.12-1450.54" + attribute \src "ls180.v:1449.12-1449.54" wire width 16 $1\main_sdcore_crc16_checker_crc3_crc[15:0] - attribute \src "ls180.v:1446.12-1446.58" + attribute \src "ls180.v:1445.12-1445.58" wire width 16 $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] - attribute \src "ls180.v:1453.12-1453.53" + attribute \src "ls180.v:1452.12-1452.53" wire width 16 $1\main_sdcore_crc16_checker_crctmp0[15:0] - attribute \src "ls180.v:1454.12-1454.53" + attribute \src "ls180.v:1453.12-1453.53" wire width 16 $1\main_sdcore_crc16_checker_crctmp1[15:0] - attribute \src "ls180.v:1455.12-1455.53" + attribute \src "ls180.v:1454.12-1454.53" wire width 16 $1\main_sdcore_crc16_checker_crctmp2[15:0] - attribute \src "ls180.v:1456.12-1456.53" + attribute \src "ls180.v:1455.12-1455.53" wire width 16 $1\main_sdcore_crc16_checker_crctmp3[15:0] - attribute \src "ls180.v:1458.12-1458.51" + attribute \src "ls180.v:1457.12-1457.51" wire width 16 $1\main_sdcore_crc16_checker_fifo0[15:0] - attribute \src "ls180.v:1459.12-1459.51" + attribute \src "ls180.v:1458.12-1458.51" wire width 16 $1\main_sdcore_crc16_checker_fifo1[15:0] - attribute \src "ls180.v:1460.12-1460.51" + attribute \src "ls180.v:1459.12-1459.51" wire width 16 $1\main_sdcore_crc16_checker_fifo2[15:0] - attribute \src "ls180.v:1461.12-1461.51" + attribute \src "ls180.v:1460.12-1460.51" wire width 16 $1\main_sdcore_crc16_checker_fifo3[15:0] - attribute \src "ls180.v:1415.5-1415.48" + attribute \src "ls180.v:1414.5-1414.48" wire $1\main_sdcore_crc16_checker_sink_first[0:0] - attribute \src "ls180.v:1416.5-1416.47" + attribute \src "ls180.v:1415.5-1415.47" wire $1\main_sdcore_crc16_checker_sink_last[0:0] - attribute \src "ls180.v:1417.11-1417.61" + attribute \src "ls180.v:1416.11-1416.61" wire width 8 $1\main_sdcore_crc16_checker_sink_payload_data[7:0] - attribute \src "ls180.v:1414.5-1414.48" - wire $1\main_sdcore_crc16_checker_sink_ready[0:0] attribute \src "ls180.v:1413.5-1413.48" + wire $1\main_sdcore_crc16_checker_sink_ready[0:0] + attribute \src "ls180.v:1412.5-1412.48" wire $1\main_sdcore_crc16_checker_sink_valid[0:0] - attribute \src "ls180.v:1418.5-1418.50" + attribute \src "ls180.v:1417.5-1417.50" wire $1\main_sdcore_crc16_checker_source_valid[0:0] - attribute \src "ls180.v:1423.11-1423.47" + attribute \src "ls180.v:1422.11-1422.47" wire width 8 $1\main_sdcore_crc16_checker_val[7:0] - attribute \src "ls180.v:1457.5-1457.43" + attribute \src "ls180.v:1456.5-1456.43" wire $1\main_sdcore_crc16_checker_valid[0:0] - attribute \src "ls180.v:1380.11-1380.48" + attribute \src "ls180.v:1379.11-1379.48" wire width 3 $1\main_sdcore_crc16_inserter_cnt[2:0] - attribute \src "ls180.v:1790.11-1790.87" + attribute \src "ls180.v:1789.11-1789.87" wire width 3 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] - attribute \src "ls180.v:1791.5-1791.84" + attribute \src "ls180.v:1790.5-1790.84" wire $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] - attribute \src "ls180.v:1385.12-1385.55" + attribute \src "ls180.v:1384.12-1384.55" wire width 16 $1\main_sdcore_crc16_inserter_crc0_crc[15:0] - attribute \src "ls180.v:1381.12-1381.59" + attribute \src "ls180.v:1380.12-1380.59" wire width 16 $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] - attribute \src "ls180.v:1392.12-1392.55" + attribute \src "ls180.v:1391.12-1391.55" wire width 16 $1\main_sdcore_crc16_inserter_crc1_crc[15:0] - attribute \src "ls180.v:1388.12-1388.59" + attribute \src "ls180.v:1387.12-1387.59" wire width 16 $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] - attribute \src "ls180.v:1399.12-1399.55" + attribute \src "ls180.v:1398.12-1398.55" wire width 16 $1\main_sdcore_crc16_inserter_crc2_crc[15:0] - attribute \src "ls180.v:1395.12-1395.59" + attribute \src "ls180.v:1394.12-1394.59" wire width 16 $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] - attribute \src "ls180.v:1406.12-1406.55" + attribute \src "ls180.v:1405.12-1405.55" wire width 16 $1\main_sdcore_crc16_inserter_crc3_crc[15:0] - attribute \src "ls180.v:1402.12-1402.59" + attribute \src "ls180.v:1401.12-1401.59" wire width 16 $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] - attribute \src "ls180.v:1409.12-1409.54" + attribute \src "ls180.v:1408.12-1408.54" wire width 16 $1\main_sdcore_crc16_inserter_crctmp0[15:0] - attribute \src "ls180.v:1782.12-1782.93" + attribute \src "ls180.v:1781.12-1781.93" wire width 16 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] - attribute \src "ls180.v:1783.5-1783.88" + attribute \src "ls180.v:1782.5-1782.88" wire $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] - attribute \src "ls180.v:1410.12-1410.54" + attribute \src "ls180.v:1409.12-1409.54" wire width 16 $1\main_sdcore_crc16_inserter_crctmp1[15:0] - attribute \src "ls180.v:1784.12-1784.93" + attribute \src "ls180.v:1783.12-1783.93" wire width 16 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] - attribute \src "ls180.v:1785.5-1785.88" + attribute \src "ls180.v:1784.5-1784.88" wire $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] - attribute \src "ls180.v:1411.12-1411.54" + attribute \src "ls180.v:1410.12-1410.54" wire width 16 $1\main_sdcore_crc16_inserter_crctmp2[15:0] - attribute \src "ls180.v:1786.12-1786.93" + attribute \src "ls180.v:1785.12-1785.93" wire width 16 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] - attribute \src "ls180.v:1787.5-1787.88" + attribute \src "ls180.v:1786.5-1786.88" wire $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] - attribute \src "ls180.v:1412.12-1412.54" + attribute \src "ls180.v:1411.12-1411.54" wire width 16 $1\main_sdcore_crc16_inserter_crctmp3[15:0] - attribute \src "ls180.v:1788.12-1788.93" + attribute \src "ls180.v:1787.12-1787.93" wire width 16 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] - attribute \src "ls180.v:1789.5-1789.88" + attribute \src "ls180.v:1788.5-1788.88" wire $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] - attribute \src "ls180.v:1371.5-1371.49" + attribute \src "ls180.v:1370.5-1370.49" wire $1\main_sdcore_crc16_inserter_sink_ready[0:0] - attribute \src "ls180.v:1378.5-1378.50" + attribute \src "ls180.v:1377.5-1377.50" wire $1\main_sdcore_crc16_inserter_source_last[0:0] - attribute \src "ls180.v:1379.11-1379.64" + attribute \src "ls180.v:1378.11-1378.64" wire width 8 $1\main_sdcore_crc16_inserter_source_payload_data[7:0] - attribute \src "ls180.v:1376.5-1376.51" - wire $1\main_sdcore_crc16_inserter_source_ready[0:0] attribute \src "ls180.v:1375.5-1375.51" + wire $1\main_sdcore_crc16_inserter_source_ready[0:0] + attribute \src "ls180.v:1374.5-1374.51" wire $1\main_sdcore_crc16_inserter_source_valid[0:0] - attribute \src "ls180.v:1367.11-1367.47" + attribute \src "ls180.v:1366.11-1366.47" wire width 7 $1\main_sdcore_crc7_inserter_crc[6:0] - attribute \src "ls180.v:1325.11-1325.51" + attribute \src "ls180.v:1324.11-1324.51" wire width 7 $1\main_sdcore_crc7_inserter_crcreg0[6:0] - attribute \src "ls180.v:1468.12-1468.42" + attribute \src "ls180.v:1467.12-1467.42" wire width 32 $1\main_sdcore_data_count[31:0] - attribute \src "ls180.v:1800.12-1800.65" + attribute \src "ls180.v:1799.12-1799.65" wire width 32 $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] - attribute \src "ls180.v:1801.5-1801.60" + attribute \src "ls180.v:1800.5-1800.60" wire $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] - attribute \src "ls180.v:1469.5-1469.33" + attribute \src "ls180.v:1468.5-1468.33" wire $1\main_sdcore_data_done[0:0] - attribute \src "ls180.v:1796.5-1796.56" + attribute \src "ls180.v:1795.5-1795.56" wire $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] - attribute \src "ls180.v:1797.5-1797.59" + attribute \src "ls180.v:1796.5-1796.59" wire $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] - attribute \src "ls180.v:1470.5-1470.34" + attribute \src "ls180.v:1469.5-1469.34" wire $1\main_sdcore_data_error[0:0] - attribute \src "ls180.v:1806.5-1806.57" + attribute \src "ls180.v:1805.5-1805.57" wire $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] - attribute \src "ls180.v:1807.5-1807.60" + attribute \src "ls180.v:1806.5-1806.60" wire $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] - attribute \src "ls180.v:1471.5-1471.36" + attribute \src "ls180.v:1470.5-1470.36" wire $1\main_sdcore_data_timeout[0:0] - attribute \src "ls180.v:1808.5-1808.59" + attribute \src "ls180.v:1807.5-1807.59" wire $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] - attribute \src "ls180.v:1809.5-1809.62" + attribute \src "ls180.v:1808.5-1808.62" wire $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] - attribute \src "ls180.v:1616.11-1616.48" + attribute \src "ls180.v:1615.11-1615.48" wire width 2 $1\main_sdmem2block_converter_mux[1:0] - attribute \src "ls180.v:1614.11-1614.64" + attribute \src "ls180.v:1613.11-1613.64" wire width 8 $1\main_sdmem2block_converter_source_payload_data[7:0] - attribute \src "ls180.v:1590.5-1590.40" + attribute \src "ls180.v:1589.5-1589.40" wire $1\main_sdmem2block_dma_base_re[0:0] - attribute \src "ls180.v:1589.12-1589.53" + attribute \src "ls180.v:1588.12-1588.53" wire width 64 $1\main_sdmem2block_dma_base_storage[63:0] - attribute \src "ls180.v:1588.12-1588.45" + attribute \src "ls180.v:1587.12-1587.45" wire width 32 $1\main_sdmem2block_dma_data[31:0] - attribute \src "ls180.v:1818.12-1818.75" + attribute \src "ls180.v:1817.12-1817.75" wire width 32 $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] - attribute \src "ls180.v:1819.5-1819.70" + attribute \src "ls180.v:1818.5-1818.70" wire $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] - attribute \src "ls180.v:1595.5-1595.44" + attribute \src "ls180.v:1594.5-1594.44" wire $1\main_sdmem2block_dma_done_status[0:0] - attribute \src "ls180.v:1594.5-1594.42" + attribute \src "ls180.v:1593.5-1593.42" wire $1\main_sdmem2block_dma_enable_re[0:0] - attribute \src "ls180.v:1593.5-1593.47" + attribute \src "ls180.v:1592.5-1592.47" wire $1\main_sdmem2block_dma_enable_storage[0:0] - attribute \src "ls180.v:1592.5-1592.42" + attribute \src "ls180.v:1591.5-1591.42" wire $1\main_sdmem2block_dma_length_re[0:0] - attribute \src "ls180.v:1591.12-1591.55" + attribute \src "ls180.v:1590.12-1590.55" wire width 32 $1\main_sdmem2block_dma_length_storage[31:0] - attribute \src "ls180.v:1598.5-1598.40" + attribute \src "ls180.v:1597.5-1597.40" wire $1\main_sdmem2block_dma_loop_re[0:0] - attribute \src "ls180.v:1597.5-1597.45" + attribute \src "ls180.v:1596.5-1596.45" wire $1\main_sdmem2block_dma_loop_storage[0:0] - attribute \src "ls180.v:1602.12-1602.47" + attribute \src "ls180.v:1601.12-1601.47" wire width 32 $1\main_sdmem2block_dma_offset[31:0] - attribute \src "ls180.v:1822.12-1822.87" + attribute \src "ls180.v:1821.12-1821.87" wire width 32 $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] - attribute \src "ls180.v:1823.5-1823.82" + attribute \src "ls180.v:1822.5-1822.82" wire $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] - attribute \src "ls180.v:1581.5-1581.42" + attribute \src "ls180.v:1580.5-1580.42" wire $1\main_sdmem2block_dma_sink_last[0:0] - attribute \src "ls180.v:1582.12-1582.61" + attribute \src "ls180.v:1581.12-1581.61" wire width 32 $1\main_sdmem2block_dma_sink_payload_address[31:0] - attribute \src "ls180.v:1580.5-1580.43" - wire $1\main_sdmem2block_dma_sink_ready[0:0] attribute \src "ls180.v:1579.5-1579.43" + wire $1\main_sdmem2block_dma_sink_ready[0:0] + attribute \src "ls180.v:1578.5-1578.43" wire $1\main_sdmem2block_dma_sink_valid[0:0] - attribute \src "ls180.v:1586.5-1586.44" + attribute \src "ls180.v:1585.5-1585.44" wire $1\main_sdmem2block_dma_source_last[0:0] - attribute \src "ls180.v:1587.12-1587.60" + attribute \src "ls180.v:1586.12-1586.60" wire width 32 $1\main_sdmem2block_dma_source_payload_data[31:0] - attribute \src "ls180.v:1583.5-1583.45" + attribute \src "ls180.v:1582.5-1582.45" wire $1\main_sdmem2block_dma_source_valid[0:0] - attribute \src "ls180.v:1643.11-1643.47" + attribute \src "ls180.v:1642.11-1642.47" wire width 5 $1\main_sdmem2block_fifo_consume[4:0] - attribute \src "ls180.v:1640.11-1640.45" + attribute \src "ls180.v:1639.11-1639.45" wire width 6 $1\main_sdmem2block_fifo_level[5:0] - attribute \src "ls180.v:1642.11-1642.47" + attribute \src "ls180.v:1641.11-1641.47" wire width 5 $1\main_sdmem2block_fifo_produce[4:0] - attribute \src "ls180.v:1644.11-1644.50" + attribute \src "ls180.v:1643.11-1643.50" wire width 5 $1\main_sdmem2block_fifo_wrport_adr[4:0] - attribute \src "ls180.v:1024.5-1024.35" + attribute \src "ls180.v:1023.5-1023.35" wire $1\main_sdphy_clocker_clk0[0:0] - attribute \src "ls180.v:1027.5-1027.35" + attribute \src "ls180.v:1026.5-1026.35" wire $1\main_sdphy_clocker_clk1[0:0] - attribute \src "ls180.v:1028.5-1028.36" + attribute \src "ls180.v:1027.5-1027.36" wire $1\main_sdphy_clocker_clk_d[0:0] - attribute \src "ls180.v:1026.11-1026.41" + attribute \src "ls180.v:1025.11-1025.41" wire width 9 $1\main_sdphy_clocker_clks[8:0] - attribute \src "ls180.v:1022.5-1022.33" + attribute \src "ls180.v:1021.5-1021.33" wire $1\main_sdphy_clocker_re[0:0] - attribute \src "ls180.v:1021.11-1021.46" + attribute \src "ls180.v:1020.11-1020.46" wire width 9 $1\main_sdphy_clocker_storage[8:0] - attribute \src "ls180.v:1130.5-1130.49" + attribute \src "ls180.v:1129.5-1129.49" wire $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] - attribute \src "ls180.v:1131.5-1131.48" + attribute \src "ls180.v:1130.5-1130.48" wire $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] - attribute \src "ls180.v:1132.11-1132.62" + attribute \src "ls180.v:1131.11-1131.62" wire width 8 $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] - attribute \src "ls180.v:1128.5-1128.49" + attribute \src "ls180.v:1127.5-1127.49" wire $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] - attribute \src "ls180.v:1115.11-1115.54" + attribute \src "ls180.v:1114.11-1114.54" wire width 3 $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] - attribute \src "ls180.v:1111.5-1111.55" + attribute \src "ls180.v:1110.5-1110.55" wire $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] - attribute \src "ls180.v:1112.5-1112.54" + attribute \src "ls180.v:1111.5-1111.54" wire $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] - attribute \src "ls180.v:1113.11-1113.68" + attribute \src "ls180.v:1112.11-1112.68" wire width 8 $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] - attribute \src "ls180.v:1114.11-1114.81" + attribute \src "ls180.v:1113.11-1113.81" wire width 4 $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] - attribute \src "ls180.v:1117.5-1117.53" + attribute \src "ls180.v:1116.5-1116.53" wire $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] - attribute \src "ls180.v:1133.5-1133.38" + attribute \src "ls180.v:1132.5-1132.38" wire $1\main_sdphy_cmdr_cmdr_reset[0:0] - attribute \src "ls180.v:1762.5-1762.66" + attribute \src "ls180.v:1761.5-1761.66" wire $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] - attribute \src "ls180.v:1763.5-1763.69" + attribute \src "ls180.v:1762.5-1762.69" wire $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] - attribute \src "ls180.v:1103.5-1103.36" + attribute \src "ls180.v:1102.5-1102.36" wire $1\main_sdphy_cmdr_cmdr_run[0:0] - attribute \src "ls180.v:1098.5-1098.53" + attribute \src "ls180.v:1097.5-1097.53" wire $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] - attribute \src "ls180.v:1085.11-1085.39" + attribute \src "ls180.v:1084.11-1084.39" wire width 8 $1\main_sdphy_cmdr_count[7:0] - attribute \src "ls180.v:1758.11-1758.67" + attribute \src "ls180.v:1757.11-1757.67" wire width 8 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] - attribute \src "ls180.v:1759.5-1759.64" + attribute \src "ls180.v:1758.5-1758.64" wire $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] - attribute \src "ls180.v:1070.5-1070.48" + attribute \src "ls180.v:1069.5-1069.48" wire $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1071.5-1071.50" + attribute \src "ls180.v:1070.5-1070.50" wire $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:1072.5-1072.51" + attribute \src "ls180.v:1071.5-1071.51" wire $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1077.5-1077.37" + attribute \src "ls180.v:1076.5-1076.37" wire $1\main_sdphy_cmdr_sink_last[0:0] - attribute \src "ls180.v:1078.11-1078.53" + attribute \src "ls180.v:1077.11-1077.53" wire width 8 $1\main_sdphy_cmdr_sink_payload_length[7:0] - attribute \src "ls180.v:1076.5-1076.38" - wire $1\main_sdphy_cmdr_sink_ready[0:0] attribute \src "ls180.v:1075.5-1075.38" + wire $1\main_sdphy_cmdr_sink_ready[0:0] + attribute \src "ls180.v:1074.5-1074.38" wire $1\main_sdphy_cmdr_sink_valid[0:0] - attribute \src "ls180.v:1081.5-1081.39" + attribute \src "ls180.v:1080.5-1080.39" wire $1\main_sdphy_cmdr_source_last[0:0] - attribute \src "ls180.v:1082.11-1082.53" + attribute \src "ls180.v:1081.11-1081.53" wire width 8 $1\main_sdphy_cmdr_source_payload_data[7:0] - attribute \src "ls180.v:1083.11-1083.55" + attribute \src "ls180.v:1082.11-1082.55" wire width 3 $1\main_sdphy_cmdr_source_payload_status[2:0] - attribute \src "ls180.v:1080.5-1080.40" - wire $1\main_sdphy_cmdr_source_ready[0:0] attribute \src "ls180.v:1079.5-1079.40" + wire $1\main_sdphy_cmdr_source_ready[0:0] + attribute \src "ls180.v:1078.5-1078.40" wire $1\main_sdphy_cmdr_source_valid[0:0] - attribute \src "ls180.v:1084.12-1084.48" + attribute \src "ls180.v:1083.12-1083.48" wire width 32 $1\main_sdphy_cmdr_timeout[31:0] - attribute \src "ls180.v:1760.12-1760.71" + attribute \src "ls180.v:1759.12-1759.71" wire width 32 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] - attribute \src "ls180.v:1761.5-1761.66" + attribute \src "ls180.v:1760.5-1760.66" wire $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] - attribute \src "ls180.v:1057.11-1057.39" + attribute \src "ls180.v:1056.11-1056.39" wire width 8 $1\main_sdphy_cmdw_count[7:0] - attribute \src "ls180.v:1754.11-1754.66" + attribute \src "ls180.v:1753.11-1753.66" wire width 8 $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] - attribute \src "ls180.v:1755.5-1755.63" + attribute \src "ls180.v:1754.5-1754.63" wire $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] - attribute \src "ls180.v:1056.5-1056.32" + attribute \src "ls180.v:1055.5-1055.32" wire $1\main_sdphy_cmdw_done[0:0] - attribute \src "ls180.v:1047.5-1047.48" + attribute \src "ls180.v:1046.5-1046.48" wire $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1048.5-1048.50" + attribute \src "ls180.v:1047.5-1047.50" wire $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:1049.5-1049.51" + attribute \src "ls180.v:1048.5-1048.51" wire $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1054.5-1054.37" + attribute \src "ls180.v:1053.5-1053.37" wire $1\main_sdphy_cmdw_sink_last[0:0] - attribute \src "ls180.v:1055.11-1055.51" + attribute \src "ls180.v:1054.11-1054.51" wire width 8 $1\main_sdphy_cmdw_sink_payload_data[7:0] - attribute \src "ls180.v:1053.5-1053.38" - wire $1\main_sdphy_cmdw_sink_ready[0:0] attribute \src "ls180.v:1052.5-1052.38" + wire $1\main_sdphy_cmdw_sink_ready[0:0] + attribute \src "ls180.v:1051.5-1051.38" wire $1\main_sdphy_cmdw_sink_valid[0:0] - attribute \src "ls180.v:1241.11-1241.41" + attribute \src "ls180.v:1240.11-1240.41" wire width 10 $1\main_sdphy_datar_count[9:0] - attribute \src "ls180.v:1774.11-1774.70" + attribute \src "ls180.v:1773.11-1773.70" wire width 10 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] - attribute \src "ls180.v:1775.5-1775.66" + attribute \src "ls180.v:1774.5-1774.66" wire $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] - attribute \src "ls180.v:1286.5-1286.51" + attribute \src "ls180.v:1285.5-1285.51" wire $1\main_sdphy_datar_datar_buf_source_first[0:0] - attribute \src "ls180.v:1287.5-1287.50" + attribute \src "ls180.v:1286.5-1286.50" wire $1\main_sdphy_datar_datar_buf_source_last[0:0] - attribute \src "ls180.v:1288.11-1288.64" + attribute \src "ls180.v:1287.11-1287.64" wire width 8 $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] - attribute \src "ls180.v:1284.5-1284.51" + attribute \src "ls180.v:1283.5-1283.51" wire $1\main_sdphy_datar_datar_buf_source_valid[0:0] - attribute \src "ls180.v:1271.5-1271.50" + attribute \src "ls180.v:1270.5-1270.50" wire $1\main_sdphy_datar_datar_converter_demux[0:0] - attribute \src "ls180.v:1267.5-1267.57" + attribute \src "ls180.v:1266.5-1266.57" wire $1\main_sdphy_datar_datar_converter_source_first[0:0] - attribute \src "ls180.v:1268.5-1268.56" + attribute \src "ls180.v:1267.5-1267.56" wire $1\main_sdphy_datar_datar_converter_source_last[0:0] - attribute \src "ls180.v:1269.11-1269.70" + attribute \src "ls180.v:1268.11-1268.70" wire width 8 $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] - attribute \src "ls180.v:1270.11-1270.83" + attribute \src "ls180.v:1269.11-1269.83" wire width 2 $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] - attribute \src "ls180.v:1273.5-1273.55" + attribute \src "ls180.v:1272.5-1272.55" wire $1\main_sdphy_datar_datar_converter_strobe_all[0:0] - attribute \src "ls180.v:1289.5-1289.40" + attribute \src "ls180.v:1288.5-1288.40" wire $1\main_sdphy_datar_datar_reset[0:0] - attribute \src "ls180.v:1778.5-1778.69" + attribute \src "ls180.v:1777.5-1777.69" wire $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] - attribute \src "ls180.v:1779.5-1779.72" + attribute \src "ls180.v:1778.5-1778.72" wire $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] - attribute \src "ls180.v:1259.5-1259.38" + attribute \src "ls180.v:1258.5-1258.38" wire $1\main_sdphy_datar_datar_run[0:0] - attribute \src "ls180.v:1254.5-1254.55" + attribute \src "ls180.v:1253.5-1253.55" wire $1\main_sdphy_datar_datar_source_source_ready0[0:0] - attribute \src "ls180.v:1224.5-1224.49" + attribute \src "ls180.v:1223.5-1223.49" wire $1\main_sdphy_datar_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1231.5-1231.38" + attribute \src "ls180.v:1230.5-1230.38" wire $1\main_sdphy_datar_sink_last[0:0] - attribute \src "ls180.v:1232.11-1232.61" + attribute \src "ls180.v:1231.11-1231.61" wire width 10 $1\main_sdphy_datar_sink_payload_block_length[9:0] - attribute \src "ls180.v:1230.5-1230.39" - wire $1\main_sdphy_datar_sink_ready[0:0] attribute \src "ls180.v:1229.5-1229.39" + wire $1\main_sdphy_datar_sink_ready[0:0] + attribute \src "ls180.v:1228.5-1228.39" wire $1\main_sdphy_datar_sink_valid[0:0] - attribute \src "ls180.v:1236.5-1236.40" + attribute \src "ls180.v:1235.5-1235.40" wire $1\main_sdphy_datar_source_last[0:0] - attribute \src "ls180.v:1237.11-1237.54" + attribute \src "ls180.v:1236.11-1236.54" wire width 8 $1\main_sdphy_datar_source_payload_data[7:0] - attribute \src "ls180.v:1238.11-1238.56" + attribute \src "ls180.v:1237.11-1237.56" wire width 3 $1\main_sdphy_datar_source_payload_status[2:0] - attribute \src "ls180.v:1234.5-1234.41" - wire $1\main_sdphy_datar_source_ready[0:0] attribute \src "ls180.v:1233.5-1233.41" + wire $1\main_sdphy_datar_source_ready[0:0] + attribute \src "ls180.v:1232.5-1232.41" wire $1\main_sdphy_datar_source_valid[0:0] - attribute \src "ls180.v:1239.5-1239.33" + attribute \src "ls180.v:1238.5-1238.33" wire $1\main_sdphy_datar_stop[0:0] - attribute \src "ls180.v:1240.12-1240.49" + attribute \src "ls180.v:1239.12-1239.49" wire width 32 $1\main_sdphy_datar_timeout[31:0] - attribute \src "ls180.v:1776.12-1776.73" + attribute \src "ls180.v:1775.12-1775.73" wire width 32 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] - attribute \src "ls180.v:1777.5-1777.68" + attribute \src "ls180.v:1776.5-1776.68" wire $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] - attribute \src "ls180.v:1149.11-1149.40" + attribute \src "ls180.v:1148.11-1148.40" wire width 8 $1\main_sdphy_dataw_count[7:0] - attribute \src "ls180.v:1770.11-1770.61" + attribute \src "ls180.v:1769.11-1769.61" wire width 8 $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] - attribute \src "ls180.v:1771.5-1771.58" + attribute \src "ls180.v:1770.5-1770.58" wire $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] - attribute \src "ls180.v:1208.5-1208.50" + attribute \src "ls180.v:1207.5-1207.50" wire $1\main_sdphy_dataw_crcr_buf_source_first[0:0] - attribute \src "ls180.v:1209.5-1209.49" + attribute \src "ls180.v:1208.5-1208.49" wire $1\main_sdphy_dataw_crcr_buf_source_last[0:0] - attribute \src "ls180.v:1210.11-1210.63" + attribute \src "ls180.v:1209.11-1209.63" wire width 8 $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] - attribute \src "ls180.v:1206.5-1206.50" + attribute \src "ls180.v:1205.5-1205.50" wire $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] - attribute \src "ls180.v:1193.11-1193.55" + attribute \src "ls180.v:1192.11-1192.55" wire width 3 $1\main_sdphy_dataw_crcr_converter_demux[2:0] - attribute \src "ls180.v:1189.5-1189.56" + attribute \src "ls180.v:1188.5-1188.56" wire $1\main_sdphy_dataw_crcr_converter_source_first[0:0] - attribute \src "ls180.v:1190.5-1190.55" + attribute \src "ls180.v:1189.5-1189.55" wire $1\main_sdphy_dataw_crcr_converter_source_last[0:0] - attribute \src "ls180.v:1191.11-1191.69" + attribute \src "ls180.v:1190.11-1190.69" wire width 8 $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] - attribute \src "ls180.v:1192.11-1192.82" + attribute \src "ls180.v:1191.11-1191.82" wire width 4 $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] - attribute \src "ls180.v:1195.5-1195.54" + attribute \src "ls180.v:1194.5-1194.54" wire $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] - attribute \src "ls180.v:1211.5-1211.39" + attribute \src "ls180.v:1210.5-1210.39" wire $1\main_sdphy_dataw_crcr_reset[0:0] - attribute \src "ls180.v:1766.5-1766.66" + attribute \src "ls180.v:1765.5-1765.66" wire $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] - attribute \src "ls180.v:1767.5-1767.69" + attribute \src "ls180.v:1766.5-1766.69" wire $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] - attribute \src "ls180.v:1181.5-1181.37" + attribute \src "ls180.v:1180.5-1180.37" wire $1\main_sdphy_dataw_crcr_run[0:0] - attribute \src "ls180.v:1176.5-1176.54" + attribute \src "ls180.v:1175.5-1175.54" wire $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] - attribute \src "ls180.v:1163.5-1163.34" + attribute \src "ls180.v:1162.5-1162.34" wire $1\main_sdphy_dataw_error[0:0] - attribute \src "ls180.v:1138.5-1138.49" + attribute \src "ls180.v:1137.5-1137.49" wire $1\main_sdphy_dataw_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1141.11-1141.58" + attribute \src "ls180.v:1140.11-1140.58" wire width 4 $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:1142.5-1142.53" + attribute \src "ls180.v:1141.5-1141.53" wire $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:1145.5-1145.39" + attribute \src "ls180.v:1144.5-1144.39" wire $1\main_sdphy_dataw_sink_first[0:0] - attribute \src "ls180.v:1146.5-1146.38" + attribute \src "ls180.v:1145.5-1145.38" wire $1\main_sdphy_dataw_sink_last[0:0] - attribute \src "ls180.v:1147.11-1147.52" + attribute \src "ls180.v:1146.11-1146.52" wire width 8 $1\main_sdphy_dataw_sink_payload_data[7:0] - attribute \src "ls180.v:1144.5-1144.39" - wire $1\main_sdphy_dataw_sink_ready[0:0] attribute \src "ls180.v:1143.5-1143.39" + wire $1\main_sdphy_dataw_sink_ready[0:0] + attribute \src "ls180.v:1142.5-1142.39" wire $1\main_sdphy_dataw_sink_valid[0:0] - attribute \src "ls180.v:1161.5-1161.34" + attribute \src "ls180.v:1160.5-1160.34" wire $1\main_sdphy_dataw_start[0:0] - attribute \src "ls180.v:1148.5-1148.33" + attribute \src "ls180.v:1147.5-1147.33" wire $1\main_sdphy_dataw_stop[0:0] - attribute \src "ls180.v:1162.5-1162.34" + attribute \src "ls180.v:1161.5-1161.34" wire $1\main_sdphy_dataw_valid[0:0] - attribute \src "ls180.v:1042.11-1042.39" + attribute \src "ls180.v:1041.11-1041.39" wire width 8 $1\main_sdphy_init_count[7:0] - attribute \src "ls180.v:1750.11-1750.66" + attribute \src "ls180.v:1749.11-1749.66" wire width 8 $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] - attribute \src "ls180.v:1751.5-1751.63" + attribute \src "ls180.v:1750.5-1750.63" wire $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] - attribute \src "ls180.v:1037.5-1037.48" + attribute \src "ls180.v:1036.5-1036.48" wire $1\main_sdphy_init_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1038.5-1038.50" + attribute \src "ls180.v:1037.5-1037.50" wire $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:1039.5-1039.51" + attribute \src "ls180.v:1038.5-1038.51" wire $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1040.11-1040.57" + attribute \src "ls180.v:1039.11-1039.57" wire width 4 $1\main_sdphy_init_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:1041.5-1041.52" + attribute \src "ls180.v:1040.5-1040.52" wire $1\main_sdphy_init_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:1291.5-1291.35" + attribute \src "ls180.v:1290.5-1290.35" wire $1\main_sdphy_sdpads_cmd_i[0:0] - attribute \src "ls180.v:1294.11-1294.42" + attribute \src "ls180.v:1293.11-1293.42" wire width 4 $1\main_sdphy_sdpads_data_i[3:0] - attribute \src "ls180.v:300.5-300.33" + attribute \src "ls180.v:299.5-299.33" wire $1\main_sdram_address_re[0:0] - attribute \src "ls180.v:299.12-299.46" + attribute \src "ls180.v:298.12-298.46" wire width 13 $1\main_sdram_address_storage[12:0] - attribute \src "ls180.v:302.5-302.34" + attribute \src "ls180.v:301.5-301.34" wire $1\main_sdram_baddress_re[0:0] - attribute \src "ls180.v:301.11-301.45" + attribute \src "ls180.v:300.11-300.45" wire width 2 $1\main_sdram_baddress_storage[1:0] - attribute \src "ls180.v:398.5-398.50" + attribute \src "ls180.v:397.5-397.50" wire $1\main_sdram_bankmachine0_auto_precharge[0:0] - attribute \src "ls180.v:420.11-420.70" + attribute \src "ls180.v:419.11-419.70" wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:417.11-417.68" + attribute \src "ls180.v:416.11-416.68" wire width 4 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:419.11-419.70" + attribute \src "ls180.v:418.11-418.70" wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:421.11-421.73" + attribute \src "ls180.v:420.11-420.73" wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:444.5-444.59" + attribute \src "ls180.v:443.5-443.59" wire $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:445.5-445.58" + attribute \src "ls180.v:444.5-444.58" wire $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:447.12-447.74" + attribute \src "ls180.v:446.12-446.74" wire width 22 $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:446.5-446.64" + attribute \src "ls180.v:445.5-445.64" wire $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:442.5-442.59" + attribute \src "ls180.v:441.5-441.59" wire $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:390.12-390.57" + attribute \src "ls180.v:389.12-389.57" wire width 13 $1\main_sdram_bankmachine0_cmd_payload_a[12:0] - attribute \src "ls180.v:392.5-392.51" + attribute \src "ls180.v:391.5-391.51" wire $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] - attribute \src "ls180.v:395.5-395.54" + attribute \src "ls180.v:394.5-394.54" wire $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:396.5-396.55" + attribute \src "ls180.v:395.5-395.55" wire $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] - attribute \src "ls180.v:397.5-397.56" + attribute \src "ls180.v:396.5-396.56" wire $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] - attribute \src "ls180.v:393.5-393.51" + attribute \src "ls180.v:392.5-392.51" wire $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] - attribute \src "ls180.v:394.5-394.50" + attribute \src "ls180.v:393.5-393.50" wire $1\main_sdram_bankmachine0_cmd_payload_we[0:0] - attribute \src "ls180.v:389.5-389.45" - wire $1\main_sdram_bankmachine0_cmd_ready[0:0] attribute \src "ls180.v:388.5-388.45" + wire $1\main_sdram_bankmachine0_cmd_ready[0:0] + attribute \src "ls180.v:387.5-387.45" wire $1\main_sdram_bankmachine0_cmd_valid[0:0] - attribute \src "ls180.v:387.5-387.47" + attribute \src "ls180.v:386.5-386.47" wire $1\main_sdram_bankmachine0_refresh_gnt[0:0] - attribute \src "ls180.v:385.5-385.51" - wire $1\main_sdram_bankmachine0_req_rdata_valid[0:0] attribute \src "ls180.v:384.5-384.51" + wire $1\main_sdram_bankmachine0_req_rdata_valid[0:0] + attribute \src "ls180.v:383.5-383.51" wire $1\main_sdram_bankmachine0_req_wdata_ready[0:0] - attribute \src "ls180.v:448.12-448.47" + attribute \src "ls180.v:447.12-447.47" wire width 13 $1\main_sdram_bankmachine0_row[12:0] - attribute \src "ls180.v:452.5-452.45" + attribute \src "ls180.v:451.5-451.45" wire $1\main_sdram_bankmachine0_row_close[0:0] - attribute \src "ls180.v:453.5-453.54" + attribute \src "ls180.v:452.5-452.54" wire $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:451.5-451.44" + attribute \src "ls180.v:450.5-450.44" wire $1\main_sdram_bankmachine0_row_open[0:0] - attribute \src "ls180.v:449.5-449.46" + attribute \src "ls180.v:448.5-448.46" wire $1\main_sdram_bankmachine0_row_opened[0:0] - attribute \src "ls180.v:456.11-456.55" + attribute \src "ls180.v:455.11-455.55" wire width 3 $1\main_sdram_bankmachine0_twtpcon_count[2:0] - attribute \src "ls180.v:455.32-455.76" + attribute \src "ls180.v:454.32-454.76" wire $1\main_sdram_bankmachine0_twtpcon_ready[0:0] - attribute \src "ls180.v:480.5-480.50" + attribute \src "ls180.v:479.5-479.50" wire $1\main_sdram_bankmachine1_auto_precharge[0:0] - attribute \src "ls180.v:502.11-502.70" + attribute \src "ls180.v:501.11-501.70" wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:499.11-499.68" + attribute \src "ls180.v:498.11-498.68" wire width 4 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:501.11-501.70" + attribute \src "ls180.v:500.11-500.70" wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:503.11-503.73" + attribute \src "ls180.v:502.11-502.73" wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:526.5-526.59" + attribute \src "ls180.v:525.5-525.59" wire $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:527.5-527.58" + attribute \src "ls180.v:526.5-526.58" wire $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:529.12-529.74" + attribute \src "ls180.v:528.12-528.74" wire width 22 $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:528.5-528.64" + attribute \src "ls180.v:527.5-527.64" wire $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:524.5-524.59" + attribute \src "ls180.v:523.5-523.59" wire $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:472.12-472.57" + attribute \src "ls180.v:471.12-471.57" wire width 13 $1\main_sdram_bankmachine1_cmd_payload_a[12:0] - attribute \src "ls180.v:474.5-474.51" + attribute \src "ls180.v:473.5-473.51" wire $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] - attribute \src "ls180.v:477.5-477.54" + attribute \src "ls180.v:476.5-476.54" wire $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:478.5-478.55" + attribute \src "ls180.v:477.5-477.55" wire $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] - attribute \src "ls180.v:479.5-479.56" + attribute \src "ls180.v:478.5-478.56" wire $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] - attribute \src "ls180.v:475.5-475.51" + attribute \src "ls180.v:474.5-474.51" wire $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] - attribute \src "ls180.v:476.5-476.50" + attribute \src "ls180.v:475.5-475.50" wire $1\main_sdram_bankmachine1_cmd_payload_we[0:0] - attribute \src "ls180.v:471.5-471.45" - wire $1\main_sdram_bankmachine1_cmd_ready[0:0] attribute \src "ls180.v:470.5-470.45" + wire $1\main_sdram_bankmachine1_cmd_ready[0:0] + attribute \src "ls180.v:469.5-469.45" wire $1\main_sdram_bankmachine1_cmd_valid[0:0] - attribute \src "ls180.v:469.5-469.47" + attribute \src "ls180.v:468.5-468.47" wire $1\main_sdram_bankmachine1_refresh_gnt[0:0] - attribute \src "ls180.v:467.5-467.51" - wire $1\main_sdram_bankmachine1_req_rdata_valid[0:0] attribute \src "ls180.v:466.5-466.51" + wire $1\main_sdram_bankmachine1_req_rdata_valid[0:0] + attribute \src "ls180.v:465.5-465.51" wire $1\main_sdram_bankmachine1_req_wdata_ready[0:0] - attribute \src "ls180.v:530.12-530.47" + attribute \src "ls180.v:529.12-529.47" wire width 13 $1\main_sdram_bankmachine1_row[12:0] - attribute \src "ls180.v:534.5-534.45" + attribute \src "ls180.v:533.5-533.45" wire $1\main_sdram_bankmachine1_row_close[0:0] - attribute \src "ls180.v:535.5-535.54" + attribute \src "ls180.v:534.5-534.54" wire $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:533.5-533.44" + attribute \src "ls180.v:532.5-532.44" wire $1\main_sdram_bankmachine1_row_open[0:0] - attribute \src "ls180.v:531.5-531.46" + attribute \src "ls180.v:530.5-530.46" wire $1\main_sdram_bankmachine1_row_opened[0:0] - attribute \src "ls180.v:538.11-538.55" + attribute \src "ls180.v:537.11-537.55" wire width 3 $1\main_sdram_bankmachine1_twtpcon_count[2:0] - attribute \src "ls180.v:537.32-537.76" + attribute \src "ls180.v:536.32-536.76" wire $1\main_sdram_bankmachine1_twtpcon_ready[0:0] - attribute \src "ls180.v:562.5-562.50" + attribute \src "ls180.v:561.5-561.50" wire $1\main_sdram_bankmachine2_auto_precharge[0:0] - attribute \src "ls180.v:584.11-584.70" + attribute \src "ls180.v:583.11-583.70" wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:581.11-581.68" + attribute \src "ls180.v:580.11-580.68" wire width 4 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:583.11-583.70" + attribute \src "ls180.v:582.11-582.70" wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:585.11-585.73" + attribute \src "ls180.v:584.11-584.73" wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:608.5-608.59" + attribute \src "ls180.v:607.5-607.59" wire $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:609.5-609.58" + attribute \src "ls180.v:608.5-608.58" wire $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:611.12-611.74" + attribute \src "ls180.v:610.12-610.74" wire width 22 $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:610.5-610.64" + attribute \src "ls180.v:609.5-609.64" wire $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:606.5-606.59" + attribute \src "ls180.v:605.5-605.59" wire $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:554.12-554.57" + attribute \src "ls180.v:553.12-553.57" wire width 13 $1\main_sdram_bankmachine2_cmd_payload_a[12:0] - attribute \src "ls180.v:556.5-556.51" + attribute \src "ls180.v:555.5-555.51" wire $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] - attribute \src "ls180.v:559.5-559.54" + attribute \src "ls180.v:558.5-558.54" wire $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:560.5-560.55" + attribute \src "ls180.v:559.5-559.55" wire $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] - attribute \src "ls180.v:561.5-561.56" + attribute \src "ls180.v:560.5-560.56" wire $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] - attribute \src "ls180.v:557.5-557.51" + attribute \src "ls180.v:556.5-556.51" wire $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] - attribute \src "ls180.v:558.5-558.50" + attribute \src "ls180.v:557.5-557.50" wire $1\main_sdram_bankmachine2_cmd_payload_we[0:0] - attribute \src "ls180.v:553.5-553.45" - wire $1\main_sdram_bankmachine2_cmd_ready[0:0] attribute \src "ls180.v:552.5-552.45" + wire $1\main_sdram_bankmachine2_cmd_ready[0:0] + attribute \src "ls180.v:551.5-551.45" wire $1\main_sdram_bankmachine2_cmd_valid[0:0] - attribute \src "ls180.v:551.5-551.47" + attribute \src "ls180.v:550.5-550.47" wire $1\main_sdram_bankmachine2_refresh_gnt[0:0] - attribute \src "ls180.v:549.5-549.51" - wire $1\main_sdram_bankmachine2_req_rdata_valid[0:0] attribute \src "ls180.v:548.5-548.51" + wire $1\main_sdram_bankmachine2_req_rdata_valid[0:0] + attribute \src "ls180.v:547.5-547.51" wire $1\main_sdram_bankmachine2_req_wdata_ready[0:0] - attribute \src "ls180.v:612.12-612.47" + attribute \src "ls180.v:611.12-611.47" wire width 13 $1\main_sdram_bankmachine2_row[12:0] - attribute \src "ls180.v:616.5-616.45" + attribute \src "ls180.v:615.5-615.45" wire $1\main_sdram_bankmachine2_row_close[0:0] - attribute \src "ls180.v:617.5-617.54" + attribute \src "ls180.v:616.5-616.54" wire $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:615.5-615.44" + attribute \src "ls180.v:614.5-614.44" wire $1\main_sdram_bankmachine2_row_open[0:0] - attribute \src "ls180.v:613.5-613.46" + attribute \src "ls180.v:612.5-612.46" wire $1\main_sdram_bankmachine2_row_opened[0:0] - attribute \src "ls180.v:620.11-620.55" + attribute \src "ls180.v:619.11-619.55" wire width 3 $1\main_sdram_bankmachine2_twtpcon_count[2:0] - attribute \src "ls180.v:619.32-619.76" + attribute \src "ls180.v:618.32-618.76" wire $1\main_sdram_bankmachine2_twtpcon_ready[0:0] - attribute \src "ls180.v:644.5-644.50" + attribute \src "ls180.v:643.5-643.50" wire $1\main_sdram_bankmachine3_auto_precharge[0:0] - attribute \src "ls180.v:666.11-666.70" + attribute \src "ls180.v:665.11-665.70" wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:663.11-663.68" + attribute \src "ls180.v:662.11-662.68" wire width 4 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:665.11-665.70" + attribute \src "ls180.v:664.11-664.70" wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:667.11-667.73" + attribute \src "ls180.v:666.11-666.73" wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:690.5-690.59" + attribute \src "ls180.v:689.5-689.59" wire $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:691.5-691.58" + attribute \src "ls180.v:690.5-690.58" wire $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:693.12-693.74" + attribute \src "ls180.v:692.12-692.74" wire width 22 $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:692.5-692.64" + attribute \src "ls180.v:691.5-691.64" wire $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:688.5-688.59" + attribute \src "ls180.v:687.5-687.59" wire $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:636.12-636.57" + attribute \src "ls180.v:635.12-635.57" wire width 13 $1\main_sdram_bankmachine3_cmd_payload_a[12:0] - attribute \src "ls180.v:638.5-638.51" + attribute \src "ls180.v:637.5-637.51" wire $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] - attribute \src "ls180.v:641.5-641.54" + attribute \src "ls180.v:640.5-640.54" wire $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:642.5-642.55" + attribute \src "ls180.v:641.5-641.55" wire $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] - attribute \src "ls180.v:643.5-643.56" + attribute \src "ls180.v:642.5-642.56" wire $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] - attribute \src "ls180.v:639.5-639.51" + attribute \src "ls180.v:638.5-638.51" wire $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] - attribute \src "ls180.v:640.5-640.50" + attribute \src "ls180.v:639.5-639.50" wire $1\main_sdram_bankmachine3_cmd_payload_we[0:0] - attribute \src "ls180.v:635.5-635.45" - wire $1\main_sdram_bankmachine3_cmd_ready[0:0] attribute \src "ls180.v:634.5-634.45" + wire $1\main_sdram_bankmachine3_cmd_ready[0:0] + attribute \src "ls180.v:633.5-633.45" wire $1\main_sdram_bankmachine3_cmd_valid[0:0] - attribute \src "ls180.v:633.5-633.47" + attribute \src "ls180.v:632.5-632.47" wire $1\main_sdram_bankmachine3_refresh_gnt[0:0] - attribute \src "ls180.v:631.5-631.51" - wire $1\main_sdram_bankmachine3_req_rdata_valid[0:0] attribute \src "ls180.v:630.5-630.51" + wire $1\main_sdram_bankmachine3_req_rdata_valid[0:0] + attribute \src "ls180.v:629.5-629.51" wire $1\main_sdram_bankmachine3_req_wdata_ready[0:0] - attribute \src "ls180.v:694.12-694.47" + attribute \src "ls180.v:693.12-693.47" wire width 13 $1\main_sdram_bankmachine3_row[12:0] - attribute \src "ls180.v:698.5-698.45" + attribute \src "ls180.v:697.5-697.45" wire $1\main_sdram_bankmachine3_row_close[0:0] - attribute \src "ls180.v:699.5-699.54" + attribute \src "ls180.v:698.5-698.54" wire $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:697.5-697.44" + attribute \src "ls180.v:696.5-696.44" wire $1\main_sdram_bankmachine3_row_open[0:0] - attribute \src "ls180.v:695.5-695.46" + attribute \src "ls180.v:694.5-694.46" wire $1\main_sdram_bankmachine3_row_opened[0:0] - attribute \src "ls180.v:702.11-702.55" + attribute \src "ls180.v:701.11-701.55" wire width 3 $1\main_sdram_bankmachine3_twtpcon_count[2:0] - attribute \src "ls180.v:701.32-701.76" + attribute \src "ls180.v:700.32-700.76" wire $1\main_sdram_bankmachine3_twtpcon_ready[0:0] - attribute \src "ls180.v:717.5-717.49" + attribute \src "ls180.v:716.5-716.49" wire $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] - attribute \src "ls180.v:718.5-718.49" + attribute \src "ls180.v:717.5-717.49" wire $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] - attribute \src "ls180.v:719.5-719.48" + attribute \src "ls180.v:718.5-718.48" wire $1\main_sdram_choose_cmd_cmd_payload_we[0:0] - attribute \src "ls180.v:725.11-725.45" + attribute \src "ls180.v:724.11-724.45" wire width 2 $1\main_sdram_choose_cmd_grant[1:0] - attribute \src "ls180.v:723.11-723.46" + attribute \src "ls180.v:722.11-722.46" wire width 4 $1\main_sdram_choose_cmd_valids[3:0] - attribute \src "ls180.v:735.5-735.49" + attribute \src "ls180.v:734.5-734.49" wire $1\main_sdram_choose_req_cmd_payload_cas[0:0] - attribute \src "ls180.v:736.5-736.49" + attribute \src "ls180.v:735.5-735.49" wire $1\main_sdram_choose_req_cmd_payload_ras[0:0] - attribute \src "ls180.v:737.5-737.48" + attribute \src "ls180.v:736.5-736.48" wire $1\main_sdram_choose_req_cmd_payload_we[0:0] - attribute \src "ls180.v:732.5-732.43" + attribute \src "ls180.v:731.5-731.43" wire $1\main_sdram_choose_req_cmd_ready[0:0] - attribute \src "ls180.v:743.11-743.45" + attribute \src "ls180.v:742.11-742.45" wire width 2 $1\main_sdram_choose_req_grant[1:0] - attribute \src "ls180.v:741.11-741.46" + attribute \src "ls180.v:740.11-740.46" wire width 4 $1\main_sdram_choose_req_valids[3:0] - attribute \src "ls180.v:730.5-730.48" + attribute \src "ls180.v:729.5-729.48" wire $1\main_sdram_choose_req_want_activates[0:0] - attribute \src "ls180.v:727.5-727.44" + attribute \src "ls180.v:726.5-726.44" wire $1\main_sdram_choose_req_want_reads[0:0] - attribute \src "ls180.v:728.5-728.45" + attribute \src "ls180.v:727.5-727.45" wire $1\main_sdram_choose_req_want_writes[0:0] - attribute \src "ls180.v:356.5-356.31" + attribute \src "ls180.v:355.5-355.31" wire $1\main_sdram_cmd_last[0:0] - attribute \src "ls180.v:357.12-357.44" + attribute \src "ls180.v:356.12-356.44" wire width 13 $1\main_sdram_cmd_payload_a[12:0] - attribute \src "ls180.v:358.11-358.43" + attribute \src "ls180.v:357.11-357.43" wire width 2 $1\main_sdram_cmd_payload_ba[1:0] - attribute \src "ls180.v:359.5-359.38" + attribute \src "ls180.v:358.5-358.38" wire $1\main_sdram_cmd_payload_cas[0:0] - attribute \src "ls180.v:360.5-360.38" + attribute \src "ls180.v:359.5-359.38" wire $1\main_sdram_cmd_payload_ras[0:0] - attribute \src "ls180.v:361.5-361.37" + attribute \src "ls180.v:360.5-360.37" wire $1\main_sdram_cmd_payload_we[0:0] - attribute \src "ls180.v:355.5-355.32" - wire $1\main_sdram_cmd_ready[0:0] attribute \src "ls180.v:354.5-354.32" + wire $1\main_sdram_cmd_ready[0:0] + attribute \src "ls180.v:353.5-353.32" wire $1\main_sdram_cmd_valid[0:0] - attribute \src "ls180.v:294.5-294.33" + attribute \src "ls180.v:293.5-293.33" wire $1\main_sdram_command_re[0:0] - attribute \src "ls180.v:293.11-293.44" + attribute \src "ls180.v:292.11-292.44" wire width 6 $1\main_sdram_command_storage[5:0] - attribute \src "ls180.v:338.12-338.45" + attribute \src "ls180.v:337.12-337.45" wire width 13 $1\main_sdram_dfi_p0_address[12:0] - attribute \src "ls180.v:339.11-339.40" + attribute \src "ls180.v:338.11-338.40" wire width 2 $1\main_sdram_dfi_p0_bank[1:0] - attribute \src "ls180.v:340.5-340.35" + attribute \src "ls180.v:339.5-339.35" wire $1\main_sdram_dfi_p0_cas_n[0:0] - attribute \src "ls180.v:341.5-341.34" + attribute \src "ls180.v:340.5-340.34" wire $1\main_sdram_dfi_p0_cs_n[0:0] - attribute \src "ls180.v:342.5-342.35" + attribute \src "ls180.v:341.5-341.35" wire $1\main_sdram_dfi_p0_ras_n[0:0] - attribute \src "ls180.v:351.5-351.39" + attribute \src "ls180.v:350.5-350.39" wire $1\main_sdram_dfi_p0_rddata_en[0:0] - attribute \src "ls180.v:343.5-343.34" + attribute \src "ls180.v:342.5-342.34" wire $1\main_sdram_dfi_p0_we_n[0:0] - attribute \src "ls180.v:349.5-349.39" + attribute \src "ls180.v:348.5-348.39" wire $1\main_sdram_dfi_p0_wrdata_en[0:0] - attribute \src "ls180.v:762.5-762.26" + attribute \src "ls180.v:761.5-761.26" wire $1\main_sdram_en0[0:0] - attribute \src "ls180.v:765.5-765.26" + attribute \src "ls180.v:764.5-764.26" wire $1\main_sdram_en1[0:0] - attribute \src "ls180.v:335.12-335.46" + attribute \src "ls180.v:334.12-334.46" wire width 16 $1\main_sdram_interface_wdata[15:0] - attribute \src "ls180.v:336.11-336.47" + attribute \src "ls180.v:335.11-335.47" wire width 2 $1\main_sdram_interface_wdata_we[1:0] - attribute \src "ls180.v:241.5-241.36" + attribute \src "ls180.v:240.5-240.36" wire $1\main_sdram_inti_p0_cas_n[0:0] - attribute \src "ls180.v:242.5-242.35" + attribute \src "ls180.v:241.5-241.35" wire $1\main_sdram_inti_p0_cs_n[0:0] - attribute \src "ls180.v:243.5-243.36" + attribute \src "ls180.v:242.5-242.36" wire $1\main_sdram_inti_p0_ras_n[0:0] - attribute \src "ls180.v:253.12-253.45" + attribute \src "ls180.v:252.12-252.45" wire width 16 $1\main_sdram_inti_p0_rddata[15:0] - attribute \src "ls180.v:254.5-254.43" + attribute \src "ls180.v:253.5-253.43" wire $1\main_sdram_inti_p0_rddata_valid[0:0] - attribute \src "ls180.v:244.5-244.35" + attribute \src "ls180.v:243.5-243.35" wire $1\main_sdram_inti_p0_we_n[0:0] - attribute \src "ls180.v:280.5-280.38" + attribute \src "ls180.v:279.5-279.38" wire $1\main_sdram_master_p0_act_n[0:0] - attribute \src "ls180.v:271.12-271.48" + attribute \src "ls180.v:270.12-270.48" wire width 13 $1\main_sdram_master_p0_address[12:0] - attribute \src "ls180.v:272.11-272.43" + attribute \src "ls180.v:271.11-271.43" wire width 2 $1\main_sdram_master_p0_bank[1:0] - attribute \src "ls180.v:273.5-273.38" + attribute \src "ls180.v:272.5-272.38" wire $1\main_sdram_master_p0_cas_n[0:0] - attribute \src "ls180.v:277.5-277.36" + attribute \src "ls180.v:276.5-276.36" wire $1\main_sdram_master_p0_cke[0:0] - attribute \src "ls180.v:274.5-274.37" + attribute \src "ls180.v:273.5-273.37" wire $1\main_sdram_master_p0_cs_n[0:0] - attribute \src "ls180.v:278.5-278.36" + attribute \src "ls180.v:277.5-277.36" wire $1\main_sdram_master_p0_odt[0:0] - attribute \src "ls180.v:275.5-275.38" + attribute \src "ls180.v:274.5-274.38" wire $1\main_sdram_master_p0_ras_n[0:0] - attribute \src "ls180.v:284.5-284.42" + attribute \src "ls180.v:283.5-283.42" wire $1\main_sdram_master_p0_rddata_en[0:0] - attribute \src "ls180.v:279.5-279.40" + attribute \src "ls180.v:278.5-278.40" wire $1\main_sdram_master_p0_reset_n[0:0] - attribute \src "ls180.v:276.5-276.37" + attribute \src "ls180.v:275.5-275.37" wire $1\main_sdram_master_p0_we_n[0:0] - attribute \src "ls180.v:281.12-281.47" + attribute \src "ls180.v:280.12-280.47" wire width 16 $1\main_sdram_master_p0_wrdata[15:0] - attribute \src "ls180.v:282.5-282.42" + attribute \src "ls180.v:281.5-281.42" wire $1\main_sdram_master_p0_wrdata_en[0:0] - attribute \src "ls180.v:283.11-283.50" + attribute \src "ls180.v:282.11-282.50" wire width 2 $1\main_sdram_master_p0_wrdata_mask[1:0] - attribute \src "ls180.v:372.5-372.38" - wire $1\main_sdram_postponer_count[0:0] attribute \src "ls180.v:371.5-371.38" + wire $1\main_sdram_postponer_count[0:0] + attribute \src "ls180.v:370.5-370.38" wire $1\main_sdram_postponer_req_o[0:0] - attribute \src "ls180.v:292.5-292.25" + attribute \src "ls180.v:291.5-291.25" wire $1\main_sdram_re[0:0] - attribute \src "ls180.v:378.5-378.38" + attribute \src "ls180.v:377.5-377.38" wire $1\main_sdram_sequencer_count[0:0] - attribute \src "ls180.v:377.11-377.46" + attribute \src "ls180.v:376.11-376.46" wire width 4 $1\main_sdram_sequencer_counter[3:0] - attribute \src "ls180.v:376.5-376.38" + attribute \src "ls180.v:375.5-375.38" wire $1\main_sdram_sequencer_done1[0:0] - attribute \src "ls180.v:373.5-373.39" + attribute \src "ls180.v:372.5-372.39" wire $1\main_sdram_sequencer_start0[0:0] - attribute \src "ls180.v:269.12-269.46" + attribute \src "ls180.v:268.12-268.46" wire width 16 $1\main_sdram_slave_p0_rddata[15:0] - attribute \src "ls180.v:270.5-270.44" + attribute \src "ls180.v:269.5-269.44" wire $1\main_sdram_slave_p0_rddata_valid[0:0] - attribute \src "ls180.v:305.12-305.37" + attribute \src "ls180.v:304.12-304.37" wire width 16 $1\main_sdram_status[15:0] - attribute \src "ls180.v:747.11-747.40" + attribute \src "ls180.v:746.11-746.40" wire width 2 $1\main_sdram_steerer_sel[1:0] - attribute \src "ls180.v:291.11-291.36" + attribute \src "ls180.v:290.11-290.36" wire width 4 $1\main_sdram_storage[3:0] - attribute \src "ls180.v:756.5-756.36" + attribute \src "ls180.v:755.5-755.36" wire $1\main_sdram_tccdcon_count[0:0] - attribute \src "ls180.v:755.32-755.63" + attribute \src "ls180.v:754.32-754.63" wire $1\main_sdram_tccdcon_ready[0:0] - attribute \src "ls180.v:764.11-764.34" + attribute \src "ls180.v:763.11-763.34" wire width 5 $1\main_sdram_time0[4:0] - attribute \src "ls180.v:767.11-767.34" + attribute \src "ls180.v:766.11-766.34" wire width 4 $1\main_sdram_time1[3:0] - attribute \src "ls180.v:369.11-369.44" + attribute \src "ls180.v:368.11-368.44" wire width 10 $1\main_sdram_timer_count1[9:0] - attribute \src "ls180.v:759.11-759.42" + attribute \src "ls180.v:758.11-758.42" wire width 3 $1\main_sdram_twtrcon_count[2:0] - attribute \src "ls180.v:758.32-758.63" + attribute \src "ls180.v:757.32-757.63" wire $1\main_sdram_twtrcon_ready[0:0] - attribute \src "ls180.v:304.5-304.32" + attribute \src "ls180.v:303.5-303.32" wire $1\main_sdram_wrdata_re[0:0] - attribute \src "ls180.v:303.12-303.45" + attribute \src "ls180.v:302.12-302.45" wire width 16 $1\main_sdram_wrdata_storage[15:0] - attribute \src "ls180.v:813.5-813.27" + attribute \src "ls180.v:812.5-812.27" wire $1\main_sink_ready[0:0] - attribute \src "ls180.v:826.11-826.42" + attribute \src "ls180.v:825.11-825.42" wire width 8 $1\main_source_payload_data[7:0] - attribute \src "ls180.v:822.5-822.29" + attribute \src "ls180.v:821.5-821.29" wire $1\main_source_valid[0:0] - attribute \src "ls180.v:991.12-991.48" + attribute \src "ls180.v:990.12-990.48" wire width 16 $1\main_spi_master_clk_divider1[15:0] - attribute \src "ls180.v:986.5-986.38" + attribute \src "ls180.v:985.5-985.38" wire $1\main_spi_master_clk_enable[0:0] - attribute \src "ls180.v:973.5-973.38" + attribute \src "ls180.v:972.5-972.38" wire $1\main_spi_master_control_re[0:0] - attribute \src "ls180.v:972.12-972.51" + attribute \src "ls180.v:971.12-971.51" wire width 16 $1\main_spi_master_control_storage[15:0] - attribute \src "ls180.v:988.11-988.39" + attribute \src "ls180.v:987.11-987.39" wire width 3 $1\main_spi_master_count[2:0] - attribute \src "ls180.v:1746.11-1746.61" + attribute \src "ls180.v:1745.11-1745.61" wire width 3 $1\main_spi_master_count_spimaster0_next_value[2:0] - attribute \src "ls180.v:1747.5-1747.58" + attribute \src "ls180.v:1746.5-1746.58" wire $1\main_spi_master_count_spimaster0_next_value_ce[0:0] - attribute \src "ls180.v:987.5-987.37" + attribute \src "ls180.v:986.5-986.37" wire $1\main_spi_master_cs_enable[0:0] - attribute \src "ls180.v:983.5-983.33" + attribute \src "ls180.v:982.5-982.33" wire $1\main_spi_master_cs_re[0:0] - attribute \src "ls180.v:982.5-982.38" + attribute \src "ls180.v:981.5-981.38" wire $1\main_spi_master_cs_storage[0:0] - attribute \src "ls180.v:963.5-963.33" + attribute \src "ls180.v:962.5-962.33" wire $1\main_spi_master_done0[0:0] - attribute \src "ls180.v:964.5-964.31" + attribute \src "ls180.v:963.5-963.31" wire $1\main_spi_master_irq[0:0] - attribute \src "ls180.v:985.5-985.39" + attribute \src "ls180.v:984.5-984.39" wire $1\main_spi_master_loopback_re[0:0] - attribute \src "ls180.v:984.5-984.44" + attribute \src "ls180.v:983.5-983.44" wire $1\main_spi_master_loopback_storage[0:0] - attribute \src "ls180.v:966.11-966.38" + attribute \src "ls180.v:965.11-965.38" wire width 8 $1\main_spi_master_miso[7:0] - attribute \src "ls180.v:996.11-996.43" + attribute \src "ls180.v:995.11-995.43" wire width 8 $1\main_spi_master_miso_data[7:0] - attribute \src "ls180.v:990.5-990.38" + attribute \src "ls180.v:989.5-989.38" wire $1\main_spi_master_miso_latch[0:0] - attribute \src "ls180.v:994.11-994.43" + attribute \src "ls180.v:993.11-993.43" wire width 8 $1\main_spi_master_mosi_data[7:0] - attribute \src "ls180.v:989.5-989.38" + attribute \src "ls180.v:988.5-988.38" wire $1\main_spi_master_mosi_latch[0:0] - attribute \src "ls180.v:978.5-978.35" + attribute \src "ls180.v:977.5-977.35" wire $1\main_spi_master_mosi_re[0:0] - attribute \src "ls180.v:995.11-995.42" + attribute \src "ls180.v:994.11-994.42" wire width 3 $1\main_spi_master_mosi_sel[2:0] - attribute \src "ls180.v:977.11-977.46" + attribute \src "ls180.v:976.11-976.46" wire width 8 $1\main_spi_master_mosi_storage[7:0] - attribute \src "ls180.v:970.5-970.34" + attribute \src "ls180.v:969.5-969.34" wire $1\main_spi_master_start1[0:0] - attribute \src "ls180.v:810.12-810.38" + attribute \src "ls180.v:809.12-809.38" wire width 32 $1\main_storage[31:0] - attribute \src "ls180.v:820.11-820.34" + attribute \src "ls180.v:819.11-819.34" wire width 4 $1\main_tx_bitcount[3:0] - attribute \src "ls180.v:821.5-821.24" + attribute \src "ls180.v:820.5-820.24" wire $1\main_tx_busy[0:0] - attribute \src "ls180.v:819.11-819.29" + attribute \src "ls180.v:818.11-818.29" wire width 8 $1\main_tx_reg[7:0] - attribute \src "ls180.v:827.5-827.30" + attribute \src "ls180.v:826.5-826.30" wire $1\main_uart_clk_rxen[0:0] - attribute \src "ls180.v:817.5-817.30" + attribute \src "ls180.v:816.5-816.30" wire $1\main_uart_clk_txen[0:0] - attribute \src "ls180.v:860.11-860.50" + attribute \src "ls180.v:859.11-859.50" wire width 2 $1\main_uart_eventmanager_pending_w[1:0] - attribute \src "ls180.v:862.5-862.37" + attribute \src "ls180.v:861.5-861.37" wire $1\main_uart_eventmanager_re[0:0] - attribute \src "ls180.v:856.11-856.49" + attribute \src "ls180.v:855.11-855.49" wire width 2 $1\main_uart_eventmanager_status_w[1:0] - attribute \src "ls180.v:861.11-861.48" + attribute \src "ls180.v:860.11-860.48" wire width 2 $1\main_uart_eventmanager_storage[1:0] - attribute \src "ls180.v:851.5-851.30" + attribute \src "ls180.v:850.5-850.30" wire $1\main_uart_rx_clear[0:0] - attribute \src "ls180.v:935.11-935.43" + attribute \src "ls180.v:934.11-934.43" wire width 4 $1\main_uart_rx_fifo_consume[3:0] - attribute \src "ls180.v:932.11-932.42" + attribute \src "ls180.v:931.11-931.42" wire width 5 $1\main_uart_rx_fifo_level0[4:0] - attribute \src "ls180.v:934.11-934.43" + attribute \src "ls180.v:933.11-933.43" wire width 4 $1\main_uart_rx_fifo_produce[3:0] - attribute \src "ls180.v:925.5-925.38" + attribute \src "ls180.v:924.5-924.38" wire $1\main_uart_rx_fifo_readable[0:0] - attribute \src "ls180.v:936.11-936.46" + attribute \src "ls180.v:935.11-935.46" wire width 4 $1\main_uart_rx_fifo_wrport_adr[3:0] - attribute \src "ls180.v:852.5-852.36" + attribute \src "ls180.v:851.5-851.36" wire $1\main_uart_rx_old_trigger[0:0] - attribute \src "ls180.v:849.5-849.32" + attribute \src "ls180.v:848.5-848.32" wire $1\main_uart_rx_pending[0:0] - attribute \src "ls180.v:846.5-846.30" + attribute \src "ls180.v:845.5-845.30" wire $1\main_uart_tx_clear[0:0] - attribute \src "ls180.v:898.11-898.43" + attribute \src "ls180.v:897.11-897.43" wire width 4 $1\main_uart_tx_fifo_consume[3:0] - attribute \src "ls180.v:895.11-895.42" + attribute \src "ls180.v:894.11-894.42" wire width 5 $1\main_uart_tx_fifo_level0[4:0] - attribute \src "ls180.v:897.11-897.43" + attribute \src "ls180.v:896.11-896.43" wire width 4 $1\main_uart_tx_fifo_produce[3:0] - attribute \src "ls180.v:888.5-888.38" + attribute \src "ls180.v:887.5-887.38" wire $1\main_uart_tx_fifo_readable[0:0] - attribute \src "ls180.v:899.11-899.46" + attribute \src "ls180.v:898.11-898.46" wire width 4 $1\main_uart_tx_fifo_wrport_adr[3:0] - attribute \src "ls180.v:847.5-847.36" + attribute \src "ls180.v:846.5-846.36" wire $1\main_uart_tx_old_trigger[0:0] - attribute \src "ls180.v:844.5-844.32" + attribute \src "ls180.v:843.5-843.32" wire $1\main_uart_tx_pending[0:0] - attribute \src "ls180.v:788.5-788.29" + attribute \src "ls180.v:787.5-787.29" wire $1\main_wb_sdram_ack[0:0] - attribute \src "ls180.v:806.5-806.31" + attribute \src "ls180.v:805.5-805.31" wire $1\main_wdata_consumed[0:0] - attribute \src "ls180.v:2767.68-2767.110" - wire $add$ls180.v:2767$22_Y - attribute \src "ls180.v:2827.68-2827.110" - wire $add$ls180.v:2827$33_Y - attribute \src "ls180.v:2887.68-2887.110" - wire $add$ls180.v:2887$44_Y - attribute \src "ls180.v:4025.54-4025.83" - wire $add$ls180.v:4025$538_Y - attribute \src "ls180.v:4125.36-4125.89" - wire width 5 $add$ls180.v:4125$584_Y - attribute \src "ls180.v:4155.36-4155.89" - wire width 5 $add$ls180.v:4155$595_Y - attribute \src "ls180.v:4210.53-4210.81" - wire width 3 $add$ls180.v:4210$608_Y - attribute \src "ls180.v:4310.58-4310.86" - wire width 8 $add$ls180.v:4310$636_Y - attribute \src "ls180.v:4367.58-4367.86" - wire width 8 $add$ls180.v:4367$639_Y - attribute \src "ls180.v:4384.58-4384.86" - wire width 8 $add$ls180.v:4384$641_Y - attribute \src "ls180.v:4477.59-4477.87" - wire width 8 $add$ls180.v:4477$658_Y - attribute \src "ls180.v:4502.59-4502.87" - wire width 8 $add$ls180.v:4502$661_Y - attribute \src "ls180.v:4624.53-4624.82" - wire width 8 $add$ls180.v:4624$678_Y - attribute \src "ls180.v:4735.65-4735.114" - wire width 10 $add$ls180.v:4735$692_Y - attribute \src "ls180.v:4740.62-4740.91" - wire width 10 $add$ls180.v:4740$695_Y - attribute \src "ls180.v:4766.61-4766.90" - wire width 10 $add$ls180.v:4766$698_Y - attribute \src "ls180.v:4970.80-4970.117" - wire width 3 $add$ls180.v:4970$883_Y - attribute \src "ls180.v:5164.54-5164.82" - wire width 3 $add$ls180.v:5164$958_Y - attribute \src "ls180.v:5216.55-5216.84" - wire width 32 $add$ls180.v:5216$968_Y - attribute \src "ls180.v:5242.57-5242.86" - wire width 32 $add$ls180.v:5242$976_Y - attribute \src "ls180.v:5363.51-5363.134" - wire width 32 $add$ls180.v:5363$992_Y - attribute \src "ls180.v:5366.77-5366.125" - wire width 32 $add$ls180.v:5366$994_Y - attribute \src "ls180.v:5459.50-5459.105" - wire width 32 $add$ls180.v:5459$1003_Y - attribute \src "ls180.v:5461.77-5461.111" - wire width 32 $add$ls180.v:5461$1004_Y - attribute \src "ls180.v:5573.49-5573.73" - wire width 3 $add$ls180.v:5573$1023_Y - attribute \src "ls180.v:7438.36-7438.70" - wire width 32 $add$ls180.v:7438$2407_Y - attribute \src "ls180.v:7525.37-7525.72" - wire width 4 $add$ls180.v:7525$2428_Y + attribute \src "ls180.v:2768.68-2768.110" + wire $add$ls180.v:2768$22_Y + attribute \src "ls180.v:2828.68-2828.110" + wire $add$ls180.v:2828$33_Y + attribute \src "ls180.v:2888.68-2888.110" + wire $add$ls180.v:2888$44_Y + attribute \src "ls180.v:4021.54-4021.83" + wire $add$ls180.v:4021$537_Y + attribute \src "ls180.v:4121.36-4121.89" + wire width 5 $add$ls180.v:4121$583_Y + attribute \src "ls180.v:4151.36-4151.89" + wire width 5 $add$ls180.v:4151$594_Y + attribute \src "ls180.v:4206.53-4206.81" + wire width 3 $add$ls180.v:4206$607_Y + attribute \src "ls180.v:4306.58-4306.86" + wire width 8 $add$ls180.v:4306$635_Y + attribute \src "ls180.v:4363.58-4363.86" + wire width 8 $add$ls180.v:4363$638_Y + attribute \src "ls180.v:4380.58-4380.86" + wire width 8 $add$ls180.v:4380$640_Y + attribute \src "ls180.v:4473.59-4473.87" + wire width 8 $add$ls180.v:4473$657_Y + attribute \src "ls180.v:4498.59-4498.87" + wire width 8 $add$ls180.v:4498$660_Y + attribute \src "ls180.v:4620.53-4620.82" + wire width 8 $add$ls180.v:4620$677_Y + attribute \src "ls180.v:4731.65-4731.114" + wire width 10 $add$ls180.v:4731$691_Y + attribute \src "ls180.v:4736.62-4736.91" + wire width 10 $add$ls180.v:4736$694_Y + attribute \src "ls180.v:4762.61-4762.90" + wire width 10 $add$ls180.v:4762$697_Y + attribute \src "ls180.v:4966.80-4966.117" + wire width 3 $add$ls180.v:4966$882_Y + attribute \src "ls180.v:5160.54-5160.82" + wire width 3 $add$ls180.v:5160$957_Y + attribute \src "ls180.v:5212.55-5212.84" + wire width 32 $add$ls180.v:5212$967_Y + attribute \src "ls180.v:5238.57-5238.86" + wire width 32 $add$ls180.v:5238$975_Y + attribute \src "ls180.v:5359.51-5359.134" + wire width 32 $add$ls180.v:5359$991_Y + attribute \src "ls180.v:5362.77-5362.125" + wire width 32 $add$ls180.v:5362$993_Y + attribute \src "ls180.v:5455.50-5455.105" + wire width 32 $add$ls180.v:5455$1002_Y + attribute \src "ls180.v:5457.77-5457.111" + wire width 32 $add$ls180.v:5457$1003_Y + attribute \src "ls180.v:5569.49-5569.73" + wire width 3 $add$ls180.v:5569$1022_Y + attribute \src "ls180.v:7437.36-7437.70" + wire width 32 $add$ls180.v:7437$2405_Y + attribute \src "ls180.v:7522.37-7522.72" + wire width 4 $add$ls180.v:7522$2426_Y + attribute \src "ls180.v:7539.60-7539.119" + wire width 3 $add$ls180.v:7539$2430_Y attribute \src "ls180.v:7542.60-7542.119" - wire width 3 $add$ls180.v:7542$2432_Y - attribute \src "ls180.v:7545.60-7545.119" - wire width 3 $add$ls180.v:7545$2433_Y - attribute \src "ls180.v:7549.59-7549.116" - wire width 4 $add$ls180.v:7549$2438_Y + wire width 3 $add$ls180.v:7542$2431_Y + attribute \src "ls180.v:7546.59-7546.116" + wire width 4 $add$ls180.v:7546$2436_Y + attribute \src "ls180.v:7585.60-7585.119" + wire width 3 $add$ls180.v:7585$2446_Y attribute \src "ls180.v:7588.60-7588.119" - wire width 3 $add$ls180.v:7588$2448_Y - attribute \src "ls180.v:7591.60-7591.119" - wire width 3 $add$ls180.v:7591$2449_Y - attribute \src "ls180.v:7595.59-7595.116" - wire width 4 $add$ls180.v:7595$2454_Y + wire width 3 $add$ls180.v:7588$2447_Y + attribute \src "ls180.v:7592.59-7592.116" + wire width 4 $add$ls180.v:7592$2452_Y + attribute \src "ls180.v:7631.60-7631.119" + wire width 3 $add$ls180.v:7631$2462_Y attribute \src "ls180.v:7634.60-7634.119" - wire width 3 $add$ls180.v:7634$2464_Y - attribute \src "ls180.v:7637.60-7637.119" - wire width 3 $add$ls180.v:7637$2465_Y - attribute \src "ls180.v:7641.59-7641.116" - wire width 4 $add$ls180.v:7641$2470_Y + wire width 3 $add$ls180.v:7634$2463_Y + attribute \src "ls180.v:7638.59-7638.116" + wire width 4 $add$ls180.v:7638$2468_Y + attribute \src "ls180.v:7677.60-7677.119" + wire width 3 $add$ls180.v:7677$2478_Y attribute \src "ls180.v:7680.60-7680.119" - wire width 3 $add$ls180.v:7680$2480_Y - attribute \src "ls180.v:7683.60-7683.119" - wire width 3 $add$ls180.v:7683$2481_Y - attribute \src "ls180.v:7687.59-7687.116" - wire width 4 $add$ls180.v:7687$2486_Y - attribute \src "ls180.v:7917.25-7917.48" - wire width 4 $add$ls180.v:7917$2540_Y - attribute \src "ls180.v:7933.55-7933.95" - wire width 33 $add$ls180.v:7933$2543_Y - attribute \src "ls180.v:7946.25-7946.48" - wire width 4 $add$ls180.v:7946$2547_Y - attribute \src "ls180.v:7965.55-7965.95" - wire width 33 $add$ls180.v:7965$2550_Y + wire width 3 $add$ls180.v:7680$2479_Y + attribute \src "ls180.v:7684.59-7684.116" + wire width 4 $add$ls180.v:7684$2484_Y + attribute \src "ls180.v:7914.25-7914.48" + wire width 4 $add$ls180.v:7914$2538_Y + attribute \src "ls180.v:7930.55-7930.95" + wire width 33 $add$ls180.v:7930$2541_Y + attribute \src "ls180.v:7943.25-7943.48" + wire width 4 $add$ls180.v:7943$2545_Y + attribute \src "ls180.v:7962.55-7962.95" + wire width 33 $add$ls180.v:7962$2548_Y + attribute \src "ls180.v:7988.33-7988.65" + wire width 4 $add$ls180.v:7988$2556_Y attribute \src "ls180.v:7991.33-7991.65" - wire width 4 $add$ls180.v:7991$2558_Y - attribute \src "ls180.v:7994.33-7994.65" - wire width 4 $add$ls180.v:7994$2559_Y - attribute \src "ls180.v:7998.33-7998.64" - wire width 5 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"ls180.v:8209.46-8209.90" - wire width 3 $add$ls180.v:8209$2607_Y - attribute \src "ls180.v:8255.72-8255.116" - wire width 4 $add$ls180.v:8255$2613_Y - attribute \src "ls180.v:8288.47-8288.92" - wire $add$ls180.v:8288$2619_Y - attribute \src "ls180.v:8316.73-8316.118" - wire width 2 $add$ls180.v:8316$2625_Y - attribute \src "ls180.v:8428.39-8428.75" - wire width 4 $add$ls180.v:8428$2638_Y + wire width 4 $add$ls180.v:8013$2568_Y + attribute \src "ls180.v:8017.33-8017.64" + wire width 5 $add$ls180.v:8017$2573_Y + attribute \src "ls180.v:8038.35-8038.70" + wire width 16 $add$ls180.v:8038$2575_Y + attribute \src "ls180.v:8074.25-8074.49" + wire width 32 $add$ls180.v:8074$2580_Y + attribute \src "ls180.v:8088.25-8088.49" + wire width 32 $add$ls180.v:8088$2584_Y + attribute \src "ls180.v:8102.31-8102.61" + wire width 9 $add$ls180.v:8102$2589_Y + attribute \src "ls180.v:8125.45-8125.88" + wire width 3 $add$ls180.v:8125$2593_Y + attribute \src "ls180.v:8171.71-8171.114" + wire width 4 $add$ls180.v:8171$2599_Y + attribute \src "ls180.v:8206.46-8206.90" + wire width 3 $add$ls180.v:8206$2605_Y + attribute \src "ls180.v:8252.72-8252.116" + wire width 4 $add$ls180.v:8252$2611_Y + attribute \src "ls180.v:8285.47-8285.92" + wire $add$ls180.v:8285$2617_Y + attribute \src "ls180.v:8313.73-8313.118" + wire width 2 $add$ls180.v:8313$2623_Y + attribute \src "ls180.v:8425.39-8425.75" + wire width 4 $add$ls180.v:8425$2636_Y + attribute \src "ls180.v:8486.37-8486.73" + wire width 5 $add$ls180.v:8486$2640_Y attribute \src "ls180.v:8489.37-8489.73" - wire width 5 $add$ls180.v:8489$2642_Y - attribute \src "ls180.v:8492.37-8492.73" - wire width 5 $add$ls180.v:8492$2643_Y - attribute \src "ls180.v:8496.36-8496.70" - wire width 6 $add$ls180.v:8496$2648_Y - attribute \src "ls180.v:8511.41-8511.80" - wire width 2 $add$ls180.v:8511$2652_Y - attribute \src "ls180.v:8545.67-8545.106" - wire width 3 $add$ls180.v:8545$2658_Y - attribute \src "ls180.v:8571.39-8571.76" - wire width 2 $add$ls180.v:8571$2660_Y + wire width 5 $add$ls180.v:8489$2641_Y + attribute \src "ls180.v:8493.36-8493.70" + wire width 6 $add$ls180.v:8493$2646_Y + attribute \src "ls180.v:8508.41-8508.80" + wire width 2 $add$ls180.v:8508$2650_Y + attribute \src "ls180.v:8542.67-8542.106" + wire width 3 $add$ls180.v:8542$2656_Y + attribute \src "ls180.v:8568.39-8568.76" + wire width 2 $add$ls180.v:8568$2658_Y + attribute \src "ls180.v:8572.37-8572.73" + wire width 5 $add$ls180.v:8572$2662_Y attribute \src "ls180.v:8575.37-8575.73" - wire width 5 $add$ls180.v:8575$2664_Y - attribute \src "ls180.v:8578.37-8578.73" - wire width 5 $add$ls180.v:8578$2665_Y - attribute \src "ls180.v:8582.36-8582.70" - wire width 6 $add$ls180.v:8582$2670_Y - attribute \src "ls180.v:8589.31-8589.62" - wire width 16 $add$ls180.v:8589$2672_Y - attribute \src "ls180.v:2761.9-2761.80" - wire $and$ls180.v:2761$17_Y - attribute \src "ls180.v:2779.9-2779.80" - wire $and$ls180.v:2779$24_Y - attribute \src "ls180.v:2821.9-2821.80" - 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$eq$ls180.v:6320$2091_Y + attribute \src "ls180.v:6321.103-6321.149" + wire $eq$ls180.v:6321$2095_Y + attribute \src "ls180.v:6323.100-6323.146" + wire $eq$ls180.v:6323$2098_Y + attribute \src "ls180.v:6324.103-6324.149" + wire $eq$ls180.v:6324$2102_Y + attribute \src "ls180.v:6326.112-6326.158" + wire $eq$ls180.v:6326$2105_Y + attribute \src "ls180.v:6327.115-6327.161" + wire $eq$ls180.v:6327$2109_Y + attribute \src "ls180.v:6329.113-6329.159" + wire $eq$ls180.v:6329$2112_Y + attribute \src "ls180.v:6330.116-6330.162" + wire $eq$ls180.v:6330$2116_Y + attribute \src "ls180.v:6332.104-6332.150" + wire $eq$ls180.v:6332$2119_Y + attribute \src "ls180.v:6333.107-6333.153" + wire $eq$ls180.v:6333$2123_Y + attribute \src "ls180.v:6350.33-6350.79" + wire $eq$ls180.v:6350$2125_Y + attribute \src "ls180.v:6352.90-6352.135" + wire $eq$ls180.v:6352$2127_Y + attribute \src "ls180.v:6353.93-6353.138" + wire $eq$ls180.v:6353$2131_Y + attribute \src "ls180.v:6355.100-6355.145" + wire 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attribute \src "ls180.v:4837.205-4837.278" - wire $xor$ls180.v:4837$767_Y + wire $xor$ls180.v:4837$778_Y attribute \src "ls180.v:4837.164-4837.279" - wire $xor$ls180.v:4837$768_Y + wire $xor$ls180.v:4837$779_Y attribute \src "ls180.v:4838.361-4838.434" - wire $xor$ls180.v:4838$769_Y + wire $xor$ls180.v:4838$780_Y attribute \src "ls180.v:4838.205-4838.278" - wire $xor$ls180.v:4838$770_Y + wire $xor$ls180.v:4838$781_Y attribute \src "ls180.v:4838.164-4838.279" - wire $xor$ls180.v:4838$771_Y + wire $xor$ls180.v:4838$782_Y attribute \src "ls180.v:4839.361-4839.434" - wire $xor$ls180.v:4839$772_Y + wire $xor$ls180.v:4839$783_Y attribute \src "ls180.v:4839.205-4839.278" - wire $xor$ls180.v:4839$773_Y + wire $xor$ls180.v:4839$784_Y attribute \src "ls180.v:4839.164-4839.279" - wire $xor$ls180.v:4839$774_Y + wire $xor$ls180.v:4839$785_Y attribute \src "ls180.v:4840.361-4840.434" - wire $xor$ls180.v:4840$775_Y + wire $xor$ls180.v:4840$786_Y attribute \src "ls180.v:4840.205-4840.278" - wire $xor$ls180.v:4840$776_Y + wire $xor$ls180.v:4840$787_Y attribute \src "ls180.v:4840.164-4840.279" - wire $xor$ls180.v:4840$777_Y + wire $xor$ls180.v:4840$788_Y attribute \src "ls180.v:4841.361-4841.434" - wire $xor$ls180.v:4841$778_Y + wire $xor$ls180.v:4841$789_Y attribute \src "ls180.v:4841.205-4841.278" - wire $xor$ls180.v:4841$779_Y + wire $xor$ls180.v:4841$790_Y attribute \src "ls180.v:4841.164-4841.279" - wire $xor$ls180.v:4841$780_Y - attribute \src "ls180.v:4842.361-4842.434" - wire $xor$ls180.v:4842$781_Y - attribute \src "ls180.v:4842.205-4842.278" - wire $xor$ls180.v:4842$782_Y - attribute \src "ls180.v:4842.164-4842.279" - wire $xor$ls180.v:4842$783_Y - attribute \src "ls180.v:4843.361-4843.434" - wire $xor$ls180.v:4843$784_Y - attribute \src "ls180.v:4843.205-4843.278" - wire $xor$ls180.v:4843$785_Y - attribute \src "ls180.v:4843.164-4843.279" - wire $xor$ls180.v:4843$786_Y - attribute \src "ls180.v:4844.361-4844.434" - wire $xor$ls180.v:4844$787_Y - attribute \src "ls180.v:4844.205-4844.278" - wire $xor$ls180.v:4844$788_Y - attribute \src "ls180.v:4844.164-4844.279" - wire $xor$ls180.v:4844$789_Y - attribute \src "ls180.v:4845.361-4845.434" - wire $xor$ls180.v:4845$790_Y - attribute \src "ls180.v:4845.205-4845.278" - wire $xor$ls180.v:4845$791_Y - attribute \src "ls180.v:4845.164-4845.279" - wire $xor$ls180.v:4845$792_Y + wire $xor$ls180.v:4841$791_Y + attribute \src "ls180.v:4842.360-4842.432" + wire $xor$ls180.v:4842$792_Y + attribute \src "ls180.v:4842.205-4842.277" + wire $xor$ls180.v:4842$793_Y + attribute \src "ls180.v:4842.164-4842.278" + wire $xor$ls180.v:4842$794_Y + attribute \src "ls180.v:4843.360-4843.432" + wire $xor$ls180.v:4843$795_Y + attribute \src "ls180.v:4843.205-4843.277" + wire $xor$ls180.v:4843$796_Y + attribute \src "ls180.v:4843.164-4843.278" + wire $xor$ls180.v:4843$797_Y + attribute \src "ls180.v:4844.360-4844.432" + wire $xor$ls180.v:4844$798_Y + attribute \src "ls180.v:4844.205-4844.277" + wire $xor$ls180.v:4844$799_Y + attribute \src "ls180.v:4844.164-4844.278" + wire $xor$ls180.v:4844$800_Y + attribute \src "ls180.v:4845.360-4845.432" + wire $xor$ls180.v:4845$801_Y + attribute \src "ls180.v:4845.205-4845.277" + wire $xor$ls180.v:4845$802_Y + attribute \src "ls180.v:4845.164-4845.278" + wire $xor$ls180.v:4845$803_Y attribute \src "ls180.v:4846.360-4846.432" - wire $xor$ls180.v:4846$793_Y + wire $xor$ls180.v:4846$804_Y attribute \src "ls180.v:4846.205-4846.277" - wire $xor$ls180.v:4846$794_Y + wire $xor$ls180.v:4846$805_Y attribute \src "ls180.v:4846.164-4846.278" - wire $xor$ls180.v:4846$795_Y + wire $xor$ls180.v:4846$806_Y attribute \src "ls180.v:4847.360-4847.432" - wire $xor$ls180.v:4847$796_Y + wire $xor$ls180.v:4847$807_Y attribute \src "ls180.v:4847.205-4847.277" - wire $xor$ls180.v:4847$797_Y + wire $xor$ls180.v:4847$808_Y attribute \src "ls180.v:4847.164-4847.278" - wire $xor$ls180.v:4847$798_Y + wire $xor$ls180.v:4847$809_Y attribute \src "ls180.v:4848.360-4848.432" - wire $xor$ls180.v:4848$799_Y + wire $xor$ls180.v:4848$810_Y attribute \src "ls180.v:4848.205-4848.277" - wire $xor$ls180.v:4848$800_Y + wire $xor$ls180.v:4848$811_Y attribute \src "ls180.v:4848.164-4848.278" - wire $xor$ls180.v:4848$801_Y + wire $xor$ls180.v:4848$812_Y attribute \src "ls180.v:4849.360-4849.432" - wire $xor$ls180.v:4849$802_Y + wire $xor$ls180.v:4849$813_Y attribute \src "ls180.v:4849.205-4849.277" - wire $xor$ls180.v:4849$803_Y + wire $xor$ls180.v:4849$814_Y attribute \src "ls180.v:4849.164-4849.278" - wire $xor$ls180.v:4849$804_Y + wire $xor$ls180.v:4849$815_Y attribute \src "ls180.v:4850.360-4850.432" - wire $xor$ls180.v:4850$805_Y + wire $xor$ls180.v:4850$816_Y attribute \src "ls180.v:4850.205-4850.277" - wire $xor$ls180.v:4850$806_Y + wire $xor$ls180.v:4850$817_Y attribute \src "ls180.v:4850.164-4850.278" - wire $xor$ls180.v:4850$807_Y + wire $xor$ls180.v:4850$818_Y attribute \src "ls180.v:4851.360-4851.432" - wire $xor$ls180.v:4851$808_Y + wire $xor$ls180.v:4851$819_Y attribute \src "ls180.v:4851.205-4851.277" - wire $xor$ls180.v:4851$809_Y + wire $xor$ls180.v:4851$820_Y attribute \src "ls180.v:4851.164-4851.278" - wire $xor$ls180.v:4851$810_Y - attribute \src "ls180.v:4852.360-4852.432" - wire $xor$ls180.v:4852$811_Y - attribute \src "ls180.v:4852.205-4852.277" - wire $xor$ls180.v:4852$812_Y - attribute \src "ls180.v:4852.164-4852.278" - wire $xor$ls180.v:4852$813_Y - attribute \src "ls180.v:4853.360-4853.432" - wire $xor$ls180.v:4853$814_Y - attribute \src "ls180.v:4853.205-4853.277" - wire $xor$ls180.v:4853$815_Y - attribute \src "ls180.v:4853.164-4853.278" - wire $xor$ls180.v:4853$816_Y - attribute \src "ls180.v:4854.360-4854.432" - wire $xor$ls180.v:4854$817_Y - attribute \src "ls180.v:4854.205-4854.277" - wire $xor$ls180.v:4854$818_Y - attribute \src "ls180.v:4854.164-4854.278" - wire $xor$ls180.v:4854$819_Y - attribute \src "ls180.v:4855.360-4855.432" - wire $xor$ls180.v:4855$820_Y - attribute \src "ls180.v:4855.205-4855.277" - wire $xor$ls180.v:4855$821_Y - attribute \src "ls180.v:4855.164-4855.278" - wire $xor$ls180.v:4855$822_Y - attribute \src "ls180.v:4876.899-4876.983" - wire $xor$ls180.v:4876$836_Y - attribute \src "ls180.v:4876.634-4876.718" - wire $xor$ls180.v:4876$837_Y - attribute \src "ls180.v:4876.588-4876.719" - wire $xor$ls180.v:4876$838_Y - attribute \src "ls180.v:4876.234-4876.318" - wire $xor$ls180.v:4876$839_Y - attribute \src "ls180.v:4876.187-4876.319" - wire $xor$ls180.v:4876$840_Y - attribute \src "ls180.v:4877.899-4877.983" - wire $xor$ls180.v:4877$841_Y - attribute \src "ls180.v:4877.634-4877.718" - wire $xor$ls180.v:4877$842_Y - attribute \src "ls180.v:4877.588-4877.719" - wire $xor$ls180.v:4877$843_Y - attribute \src "ls180.v:4877.234-4877.318" - wire $xor$ls180.v:4877$844_Y - attribute \src "ls180.v:4877.187-4877.319" - wire $xor$ls180.v:4877$845_Y - attribute \src "ls180.v:4886.899-4886.983" - wire $xor$ls180.v:4886$847_Y - attribute \src "ls180.v:4886.634-4886.718" - wire $xor$ls180.v:4886$848_Y - attribute \src "ls180.v:4886.588-4886.719" - wire $xor$ls180.v:4886$849_Y - attribute \src "ls180.v:4886.234-4886.318" - wire $xor$ls180.v:4886$850_Y - attribute \src "ls180.v:4886.187-4886.319" - wire $xor$ls180.v:4886$851_Y - attribute \src "ls180.v:4887.899-4887.983" - wire $xor$ls180.v:4887$852_Y - attribute \src "ls180.v:4887.634-4887.718" - wire $xor$ls180.v:4887$853_Y - attribute \src "ls180.v:4887.588-4887.719" - wire $xor$ls180.v:4887$854_Y - attribute \src "ls180.v:4887.234-4887.318" - wire $xor$ls180.v:4887$855_Y - attribute \src "ls180.v:4887.187-4887.319" - wire $xor$ls180.v:4887$856_Y - attribute \src "ls180.v:4896.899-4896.983" - wire $xor$ls180.v:4896$858_Y - attribute \src "ls180.v:4896.634-4896.718" - wire $xor$ls180.v:4896$859_Y - attribute \src "ls180.v:4896.588-4896.719" - wire $xor$ls180.v:4896$860_Y - attribute \src "ls180.v:4896.234-4896.318" - wire $xor$ls180.v:4896$861_Y - attribute \src "ls180.v:4896.187-4896.319" - wire $xor$ls180.v:4896$862_Y - attribute \src "ls180.v:4897.899-4897.983" - wire $xor$ls180.v:4897$863_Y - attribute \src "ls180.v:4897.634-4897.718" - wire $xor$ls180.v:4897$864_Y - attribute \src "ls180.v:4897.588-4897.719" - wire $xor$ls180.v:4897$865_Y - attribute \src "ls180.v:4897.234-4897.318" - wire $xor$ls180.v:4897$866_Y - attribute \src "ls180.v:4897.187-4897.319" - wire $xor$ls180.v:4897$867_Y - attribute \src "ls180.v:4906.899-4906.983" - wire $xor$ls180.v:4906$869_Y - attribute \src "ls180.v:4906.634-4906.718" - wire $xor$ls180.v:4906$870_Y - attribute \src "ls180.v:4906.588-4906.719" - wire $xor$ls180.v:4906$871_Y - attribute \src "ls180.v:4906.234-4906.318" - wire $xor$ls180.v:4906$872_Y - attribute \src "ls180.v:4906.187-4906.319" - wire $xor$ls180.v:4906$873_Y - attribute \src "ls180.v:4907.899-4907.983" - wire $xor$ls180.v:4907$874_Y - attribute \src "ls180.v:4907.634-4907.718" - wire $xor$ls180.v:4907$875_Y - attribute \src "ls180.v:4907.588-4907.719" - wire $xor$ls180.v:4907$876_Y - attribute \src "ls180.v:4907.234-4907.318" - wire $xor$ls180.v:4907$877_Y - attribute \src "ls180.v:4907.187-4907.319" - wire $xor$ls180.v:4907$878_Y - attribute \src "ls180.v:5058.879-5058.961" - wire $xor$ls180.v:5058$911_Y - attribute \src "ls180.v:5058.620-5058.702" - wire $xor$ls180.v:5058$912_Y - attribute \src "ls180.v:5058.575-5058.703" - wire $xor$ls180.v:5058$913_Y - attribute \src "ls180.v:5058.229-5058.311" - wire $xor$ls180.v:5058$914_Y - attribute \src "ls180.v:5058.183-5058.312" - wire $xor$ls180.v:5058$915_Y - attribute \src "ls180.v:5059.879-5059.961" - wire $xor$ls180.v:5059$916_Y - attribute \src "ls180.v:5059.620-5059.702" - wire $xor$ls180.v:5059$917_Y - attribute \src "ls180.v:5059.575-5059.703" - wire $xor$ls180.v:5059$918_Y - attribute \src "ls180.v:5059.229-5059.311" - wire $xor$ls180.v:5059$919_Y - attribute \src "ls180.v:5059.183-5059.312" - wire $xor$ls180.v:5059$920_Y - attribute \src "ls180.v:5068.879-5068.961" - wire $xor$ls180.v:5068$922_Y - attribute \src "ls180.v:5068.620-5068.702" - wire $xor$ls180.v:5068$923_Y - attribute \src "ls180.v:5068.575-5068.703" - wire $xor$ls180.v:5068$924_Y - attribute \src "ls180.v:5068.229-5068.311" - wire $xor$ls180.v:5068$925_Y - attribute \src "ls180.v:5068.183-5068.312" - wire $xor$ls180.v:5068$926_Y - attribute \src "ls180.v:5069.879-5069.961" - wire $xor$ls180.v:5069$927_Y - attribute \src "ls180.v:5069.620-5069.702" - wire $xor$ls180.v:5069$928_Y - attribute \src "ls180.v:5069.575-5069.703" - wire $xor$ls180.v:5069$929_Y - attribute \src "ls180.v:5069.229-5069.311" - wire $xor$ls180.v:5069$930_Y - attribute \src "ls180.v:5069.183-5069.312" - wire $xor$ls180.v:5069$931_Y - attribute \src "ls180.v:5078.879-5078.961" - wire $xor$ls180.v:5078$933_Y - attribute \src "ls180.v:5078.620-5078.702" - wire $xor$ls180.v:5078$934_Y - attribute \src "ls180.v:5078.575-5078.703" - wire $xor$ls180.v:5078$935_Y - attribute \src "ls180.v:5078.229-5078.311" - wire $xor$ls180.v:5078$936_Y - attribute \src "ls180.v:5078.183-5078.312" - wire $xor$ls180.v:5078$937_Y - attribute \src "ls180.v:5079.879-5079.961" - wire $xor$ls180.v:5079$938_Y - attribute \src "ls180.v:5079.620-5079.702" - wire $xor$ls180.v:5079$939_Y - attribute \src "ls180.v:5079.575-5079.703" - wire $xor$ls180.v:5079$940_Y - attribute \src "ls180.v:5079.229-5079.311" - wire $xor$ls180.v:5079$941_Y - attribute \src "ls180.v:5079.183-5079.312" - wire $xor$ls180.v:5079$942_Y - attribute \src "ls180.v:5088.879-5088.961" - wire $xor$ls180.v:5088$944_Y - attribute \src "ls180.v:5088.620-5088.702" - wire $xor$ls180.v:5088$945_Y - attribute \src "ls180.v:5088.575-5088.703" - wire $xor$ls180.v:5088$946_Y - attribute \src "ls180.v:5088.229-5088.311" - wire $xor$ls180.v:5088$947_Y - attribute \src "ls180.v:5088.183-5088.312" - wire $xor$ls180.v:5088$948_Y - attribute \src "ls180.v:5089.879-5089.961" - wire $xor$ls180.v:5089$949_Y - attribute \src "ls180.v:5089.620-5089.702" - wire $xor$ls180.v:5089$950_Y - attribute \src "ls180.v:5089.575-5089.703" - wire $xor$ls180.v:5089$951_Y - attribute \src "ls180.v:5089.229-5089.311" - wire $xor$ls180.v:5089$952_Y - attribute \src "ls180.v:5089.183-5089.312" - wire $xor$ls180.v:5089$953_Y - attribute \src "ls180.v:1710.11-1710.42" + wire $xor$ls180.v:4851$821_Y + attribute \src "ls180.v:4872.899-4872.983" + wire $xor$ls180.v:4872$835_Y + attribute \src "ls180.v:4872.634-4872.718" + wire $xor$ls180.v:4872$836_Y + attribute \src "ls180.v:4872.588-4872.719" + wire $xor$ls180.v:4872$837_Y + attribute \src "ls180.v:4872.234-4872.318" + wire $xor$ls180.v:4872$838_Y + attribute \src "ls180.v:4872.187-4872.319" + wire $xor$ls180.v:4872$839_Y + attribute \src "ls180.v:4873.899-4873.983" + wire $xor$ls180.v:4873$840_Y + attribute \src "ls180.v:4873.634-4873.718" + wire $xor$ls180.v:4873$841_Y + attribute \src "ls180.v:4873.588-4873.719" + wire $xor$ls180.v:4873$842_Y + attribute \src "ls180.v:4873.234-4873.318" + wire $xor$ls180.v:4873$843_Y + attribute \src "ls180.v:4873.187-4873.319" + wire $xor$ls180.v:4873$844_Y + attribute \src "ls180.v:4882.899-4882.983" + wire $xor$ls180.v:4882$846_Y + attribute \src "ls180.v:4882.634-4882.718" + wire $xor$ls180.v:4882$847_Y + attribute \src "ls180.v:4882.588-4882.719" + wire $xor$ls180.v:4882$848_Y + attribute \src "ls180.v:4882.234-4882.318" + wire $xor$ls180.v:4882$849_Y + attribute \src "ls180.v:4882.187-4882.319" + wire $xor$ls180.v:4882$850_Y + attribute \src "ls180.v:4883.899-4883.983" + wire $xor$ls180.v:4883$851_Y + attribute \src "ls180.v:4883.634-4883.718" + wire $xor$ls180.v:4883$852_Y + attribute \src "ls180.v:4883.588-4883.719" + wire $xor$ls180.v:4883$853_Y + attribute \src "ls180.v:4883.234-4883.318" + wire $xor$ls180.v:4883$854_Y + attribute \src "ls180.v:4883.187-4883.319" + wire $xor$ls180.v:4883$855_Y + attribute \src "ls180.v:4892.899-4892.983" + wire $xor$ls180.v:4892$857_Y + attribute \src "ls180.v:4892.634-4892.718" + wire $xor$ls180.v:4892$858_Y + attribute \src "ls180.v:4892.588-4892.719" + wire $xor$ls180.v:4892$859_Y + attribute \src "ls180.v:4892.234-4892.318" + wire $xor$ls180.v:4892$860_Y + attribute \src "ls180.v:4892.187-4892.319" + wire $xor$ls180.v:4892$861_Y + attribute \src "ls180.v:4893.899-4893.983" + wire $xor$ls180.v:4893$862_Y + attribute \src "ls180.v:4893.634-4893.718" + wire $xor$ls180.v:4893$863_Y + attribute \src "ls180.v:4893.588-4893.719" + wire $xor$ls180.v:4893$864_Y + attribute \src "ls180.v:4893.234-4893.318" + wire $xor$ls180.v:4893$865_Y + attribute \src "ls180.v:4893.187-4893.319" + wire $xor$ls180.v:4893$866_Y + attribute \src "ls180.v:4902.899-4902.983" + wire $xor$ls180.v:4902$868_Y + attribute \src "ls180.v:4902.634-4902.718" + wire $xor$ls180.v:4902$869_Y + attribute \src "ls180.v:4902.588-4902.719" + wire $xor$ls180.v:4902$870_Y + attribute \src "ls180.v:4902.234-4902.318" + wire $xor$ls180.v:4902$871_Y + attribute \src "ls180.v:4902.187-4902.319" + wire $xor$ls180.v:4902$872_Y + attribute \src "ls180.v:4903.899-4903.983" + wire $xor$ls180.v:4903$873_Y + attribute \src "ls180.v:4903.634-4903.718" + wire $xor$ls180.v:4903$874_Y + attribute \src "ls180.v:4903.588-4903.719" + wire $xor$ls180.v:4903$875_Y + attribute \src "ls180.v:4903.234-4903.318" + wire $xor$ls180.v:4903$876_Y + attribute \src "ls180.v:4903.187-4903.319" + wire $xor$ls180.v:4903$877_Y + attribute \src "ls180.v:5054.879-5054.961" + wire $xor$ls180.v:5054$910_Y + attribute \src "ls180.v:5054.620-5054.702" + wire $xor$ls180.v:5054$911_Y + attribute \src "ls180.v:5054.575-5054.703" + wire $xor$ls180.v:5054$912_Y + attribute \src "ls180.v:5054.229-5054.311" + wire $xor$ls180.v:5054$913_Y + attribute \src "ls180.v:5054.183-5054.312" + wire $xor$ls180.v:5054$914_Y + attribute \src "ls180.v:5055.879-5055.961" + wire $xor$ls180.v:5055$915_Y + attribute \src "ls180.v:5055.620-5055.702" + wire $xor$ls180.v:5055$916_Y + attribute \src "ls180.v:5055.575-5055.703" + wire $xor$ls180.v:5055$917_Y + attribute \src "ls180.v:5055.229-5055.311" + wire $xor$ls180.v:5055$918_Y + attribute \src "ls180.v:5055.183-5055.312" + wire $xor$ls180.v:5055$919_Y + attribute \src "ls180.v:5064.879-5064.961" + wire $xor$ls180.v:5064$921_Y + attribute \src "ls180.v:5064.620-5064.702" + wire $xor$ls180.v:5064$922_Y + attribute \src "ls180.v:5064.575-5064.703" + wire $xor$ls180.v:5064$923_Y + attribute \src "ls180.v:5064.229-5064.311" + wire $xor$ls180.v:5064$924_Y + attribute \src "ls180.v:5064.183-5064.312" + wire $xor$ls180.v:5064$925_Y + attribute \src "ls180.v:5065.879-5065.961" + wire $xor$ls180.v:5065$926_Y + attribute \src "ls180.v:5065.620-5065.702" + wire $xor$ls180.v:5065$927_Y + attribute \src "ls180.v:5065.575-5065.703" + wire $xor$ls180.v:5065$928_Y + attribute \src "ls180.v:5065.229-5065.311" + wire $xor$ls180.v:5065$929_Y + attribute \src "ls180.v:5065.183-5065.312" + wire $xor$ls180.v:5065$930_Y + attribute \src "ls180.v:5074.879-5074.961" + wire $xor$ls180.v:5074$932_Y + attribute \src "ls180.v:5074.620-5074.702" + wire $xor$ls180.v:5074$933_Y + attribute \src "ls180.v:5074.575-5074.703" + wire $xor$ls180.v:5074$934_Y + attribute \src "ls180.v:5074.229-5074.311" + wire $xor$ls180.v:5074$935_Y + attribute \src "ls180.v:5074.183-5074.312" + wire $xor$ls180.v:5074$936_Y + attribute \src "ls180.v:5075.879-5075.961" + wire $xor$ls180.v:5075$937_Y + attribute \src "ls180.v:5075.620-5075.702" + wire $xor$ls180.v:5075$938_Y + attribute \src "ls180.v:5075.575-5075.703" + wire $xor$ls180.v:5075$939_Y + attribute \src "ls180.v:5075.229-5075.311" + wire $xor$ls180.v:5075$940_Y + attribute \src "ls180.v:5075.183-5075.312" + wire $xor$ls180.v:5075$941_Y + attribute \src "ls180.v:5084.879-5084.961" + wire $xor$ls180.v:5084$943_Y + attribute \src "ls180.v:5084.620-5084.702" + wire $xor$ls180.v:5084$944_Y + attribute \src "ls180.v:5084.575-5084.703" + wire $xor$ls180.v:5084$945_Y + attribute \src "ls180.v:5084.229-5084.311" + wire $xor$ls180.v:5084$946_Y + attribute \src "ls180.v:5084.183-5084.312" + wire $xor$ls180.v:5084$947_Y + attribute \src "ls180.v:5085.879-5085.961" + wire $xor$ls180.v:5085$948_Y + attribute \src "ls180.v:5085.620-5085.702" + wire $xor$ls180.v:5085$949_Y + attribute \src "ls180.v:5085.575-5085.703" + wire $xor$ls180.v:5085$950_Y + attribute \src "ls180.v:5085.229-5085.311" + wire $xor$ls180.v:5085$951_Y + attribute \src "ls180.v:5085.183-5085.312" + wire $xor$ls180.v:5085$952_Y + attribute \src "ls180.v:1709.11-1709.42" wire width 3 \builder_bankmachine0_next_state - attribute \src "ls180.v:1709.11-1709.37" + attribute \src "ls180.v:1708.11-1708.37" wire width 3 \builder_bankmachine0_state - attribute \src "ls180.v:1712.11-1712.42" + attribute \src "ls180.v:1711.11-1711.42" wire width 3 \builder_bankmachine1_next_state - attribute \src "ls180.v:1711.11-1711.37" + attribute \src "ls180.v:1710.11-1710.37" wire width 3 \builder_bankmachine1_state - attribute \src "ls180.v:1714.11-1714.42" + attribute \src "ls180.v:1713.11-1713.42" wire width 3 \builder_bankmachine2_next_state - attribute \src "ls180.v:1713.11-1713.37" + attribute \src "ls180.v:1712.11-1712.37" wire width 3 \builder_bankmachine2_state - attribute \src "ls180.v:1716.11-1716.42" + attribute \src "ls180.v:1715.11-1715.42" wire width 3 \builder_bankmachine3_next_state - attribute \src "ls180.v:1715.11-1715.37" + attribute \src "ls180.v:1714.11-1714.37" wire width 3 \builder_bankmachine3_state - attribute \src "ls180.v:2548.5-2548.34" + attribute \src "ls180.v:2547.5-2547.34" wire \builder_comb_rhs_array_muxed0 - attribute \src "ls180.v:2549.12-2549.41" + attribute \src "ls180.v:2548.12-2548.41" wire width 13 \builder_comb_rhs_array_muxed1 - attribute \src "ls180.v:2561.5-2561.35" + attribute \src "ls180.v:2560.5-2560.35" wire \builder_comb_rhs_array_muxed10 - attribute \src "ls180.v:2562.5-2562.35" + attribute \src "ls180.v:2561.5-2561.35" wire \builder_comb_rhs_array_muxed11 - attribute \src "ls180.v:2566.12-2566.42" + attribute \src "ls180.v:2565.12-2565.42" wire width 22 \builder_comb_rhs_array_muxed12 - attribute \src "ls180.v:2567.5-2567.35" + attribute \src "ls180.v:2566.5-2566.35" wire \builder_comb_rhs_array_muxed13 - attribute \src "ls180.v:2568.5-2568.35" + attribute \src "ls180.v:2567.5-2567.35" wire \builder_comb_rhs_array_muxed14 - attribute \src "ls180.v:2569.12-2569.42" + attribute \src "ls180.v:2568.12-2568.42" wire width 22 \builder_comb_rhs_array_muxed15 - attribute \src "ls180.v:2570.5-2570.35" + attribute \src "ls180.v:2569.5-2569.35" wire \builder_comb_rhs_array_muxed16 - attribute \src "ls180.v:2571.5-2571.35" + attribute \src "ls180.v:2570.5-2570.35" wire \builder_comb_rhs_array_muxed17 - attribute \src "ls180.v:2572.12-2572.42" + attribute \src "ls180.v:2571.12-2571.42" wire width 22 \builder_comb_rhs_array_muxed18 - attribute \src "ls180.v:2573.5-2573.35" + attribute \src "ls180.v:2572.5-2572.35" wire \builder_comb_rhs_array_muxed19 - attribute \src "ls180.v:2550.11-2550.40" + attribute \src "ls180.v:2549.11-2549.40" wire width 2 \builder_comb_rhs_array_muxed2 - attribute \src "ls180.v:2574.5-2574.35" + attribute \src "ls180.v:2573.5-2573.35" wire \builder_comb_rhs_array_muxed20 - attribute \src "ls180.v:2575.12-2575.42" + attribute \src "ls180.v:2574.12-2574.42" wire width 22 \builder_comb_rhs_array_muxed21 - attribute \src "ls180.v:2576.5-2576.35" + attribute \src "ls180.v:2575.5-2575.35" wire \builder_comb_rhs_array_muxed22 - attribute \src "ls180.v:2577.5-2577.35" + attribute \src "ls180.v:2576.5-2576.35" wire \builder_comb_rhs_array_muxed23 - attribute \src "ls180.v:2578.12-2578.42" + attribute \src "ls180.v:2577.12-2577.42" wire width 32 \builder_comb_rhs_array_muxed24 - attribute \src "ls180.v:2579.12-2579.42" + attribute \src "ls180.v:2578.12-2578.42" wire width 32 \builder_comb_rhs_array_muxed25 - attribute \src "ls180.v:2580.11-2580.41" + attribute \src "ls180.v:2579.11-2579.41" wire width 4 \builder_comb_rhs_array_muxed26 - attribute \src "ls180.v:2581.5-2581.35" + attribute \src "ls180.v:2580.5-2580.35" wire \builder_comb_rhs_array_muxed27 - attribute \src "ls180.v:2582.5-2582.35" + attribute \src "ls180.v:2581.5-2581.35" wire \builder_comb_rhs_array_muxed28 - attribute \src "ls180.v:2583.5-2583.35" + attribute \src "ls180.v:2582.5-2582.35" wire \builder_comb_rhs_array_muxed29 - attribute \src "ls180.v:2551.5-2551.34" + attribute \src "ls180.v:2550.5-2550.34" wire \builder_comb_rhs_array_muxed3 - attribute \src "ls180.v:2584.11-2584.41" + attribute \src "ls180.v:2583.11-2583.41" wire width 3 \builder_comb_rhs_array_muxed30 - attribute \src "ls180.v:2585.11-2585.41" + attribute \src "ls180.v:2584.11-2584.41" wire width 2 \builder_comb_rhs_array_muxed31 - attribute \src "ls180.v:2552.5-2552.34" + attribute \src "ls180.v:2551.5-2551.34" wire \builder_comb_rhs_array_muxed4 - attribute \src "ls180.v:2553.5-2553.34" + attribute \src "ls180.v:2552.5-2552.34" wire \builder_comb_rhs_array_muxed5 - attribute \src "ls180.v:2557.5-2557.34" + attribute \src "ls180.v:2556.5-2556.34" wire \builder_comb_rhs_array_muxed6 - attribute \src "ls180.v:2558.12-2558.41" + attribute \src "ls180.v:2557.12-2557.41" wire width 13 \builder_comb_rhs_array_muxed7 - attribute \src "ls180.v:2559.11-2559.40" + attribute \src "ls180.v:2558.11-2558.40" wire width 2 \builder_comb_rhs_array_muxed8 - attribute \src "ls180.v:2560.5-2560.34" + attribute \src "ls180.v:2559.5-2559.34" wire \builder_comb_rhs_array_muxed9 - attribute \src "ls180.v:2554.5-2554.32" + attribute \src "ls180.v:2553.5-2553.32" wire \builder_comb_t_array_muxed0 - attribute \src "ls180.v:2555.5-2555.32" + attribute \src "ls180.v:2554.5-2554.32" wire \builder_comb_t_array_muxed1 - attribute \src "ls180.v:2556.5-2556.32" + attribute \src "ls180.v:2555.5-2555.32" wire \builder_comb_t_array_muxed2 - attribute \src "ls180.v:2563.5-2563.32" + attribute \src "ls180.v:2562.5-2562.32" wire \builder_comb_t_array_muxed3 - attribute \src "ls180.v:2564.5-2564.32" + attribute \src "ls180.v:2563.5-2563.32" wire \builder_comb_t_array_muxed4 - attribute \src "ls180.v:2565.5-2565.32" + attribute \src "ls180.v:2564.5-2564.32" wire \builder_comb_t_array_muxed5 - attribute \src "ls180.v:1696.5-1696.34" + attribute \src "ls180.v:1695.5-1695.34" wire \builder_converter0_next_state - attribute \src "ls180.v:1695.5-1695.29" + attribute \src "ls180.v:1694.5-1694.29" wire \builder_converter0_state - attribute \src "ls180.v:1700.5-1700.34" + attribute \src "ls180.v:1699.5-1699.34" wire \builder_converter1_next_state - attribute \src "ls180.v:1699.5-1699.29" + attribute \src "ls180.v:1698.5-1698.29" wire \builder_converter1_state - attribute \src "ls180.v:1704.5-1704.34" + attribute \src "ls180.v:1703.5-1703.34" wire \builder_converter2_next_state - attribute \src "ls180.v:1703.5-1703.29" + attribute \src "ls180.v:1702.5-1702.29" wire \builder_converter2_state - attribute \src "ls180.v:1741.5-1741.33" + attribute \src "ls180.v:1740.5-1740.33" wire \builder_converter_next_state - attribute \src "ls180.v:1740.5-1740.28" + attribute \src "ls180.v:1739.5-1739.28" wire \builder_converter_state - attribute \src "ls180.v:1861.12-1861.25" + attribute \src "ls180.v:1860.12-1860.25" wire width 20 \builder_count - attribute \src "ls180.v:2536.13-2536.41" + attribute \src "ls180.v:2535.13-2535.41" wire width 14 \builder_csr_interconnect_adr - attribute \src "ls180.v:2539.12-2539.42" - wire width 8 \builder_csr_interconnect_dat_r attribute \src "ls180.v:2538.12-2538.42" + wire width 8 \builder_csr_interconnect_dat_r + attribute \src "ls180.v:2537.12-2537.42" wire width 8 \builder_csr_interconnect_dat_w - attribute \src "ls180.v:2537.6-2537.33" + attribute \src "ls180.v:2536.6-2536.33" wire \builder_csr_interconnect_we - attribute \src "ls180.v:1899.12-1899.42" + attribute \src "ls180.v:1898.12-1898.42" wire width 8 \builder_csrbank0_bus_errors0_r - attribute \src "ls180.v:1898.6-1898.37" + attribute \src "ls180.v:1897.6-1897.37" wire \builder_csrbank0_bus_errors0_re - attribute \src "ls180.v:1901.12-1901.42" + attribute \src "ls180.v:1900.12-1900.42" wire width 8 \builder_csrbank0_bus_errors0_w - attribute \src "ls180.v:1900.6-1900.37" + attribute \src "ls180.v:1899.6-1899.37" wire \builder_csrbank0_bus_errors0_we - attribute \src "ls180.v:1895.12-1895.42" + attribute \src "ls180.v:1894.12-1894.42" wire width 8 \builder_csrbank0_bus_errors1_r - attribute \src "ls180.v:1894.6-1894.37" + attribute \src "ls180.v:1893.6-1893.37" wire \builder_csrbank0_bus_errors1_re - attribute \src "ls180.v:1897.12-1897.42" + attribute \src "ls180.v:1896.12-1896.42" wire width 8 \builder_csrbank0_bus_errors1_w - attribute \src "ls180.v:1896.6-1896.37" + attribute \src "ls180.v:1895.6-1895.37" wire \builder_csrbank0_bus_errors1_we - attribute \src "ls180.v:1891.12-1891.42" + attribute \src "ls180.v:1890.12-1890.42" wire width 8 \builder_csrbank0_bus_errors2_r - attribute \src "ls180.v:1890.6-1890.37" + attribute \src "ls180.v:1889.6-1889.37" wire \builder_csrbank0_bus_errors2_re - attribute \src "ls180.v:1893.12-1893.42" + attribute \src "ls180.v:1892.12-1892.42" wire width 8 \builder_csrbank0_bus_errors2_w - attribute \src "ls180.v:1892.6-1892.37" + attribute \src "ls180.v:1891.6-1891.37" wire \builder_csrbank0_bus_errors2_we - attribute \src "ls180.v:1887.12-1887.42" + attribute \src "ls180.v:1886.12-1886.42" wire width 8 \builder_csrbank0_bus_errors3_r - attribute \src "ls180.v:1886.6-1886.37" + attribute \src "ls180.v:1885.6-1885.37" wire \builder_csrbank0_bus_errors3_re - attribute \src "ls180.v:1889.12-1889.42" + attribute \src "ls180.v:1888.12-1888.42" wire width 8 \builder_csrbank0_bus_errors3_w - attribute \src "ls180.v:1888.6-1888.37" + attribute \src "ls180.v:1887.6-1887.37" wire \builder_csrbank0_bus_errors3_we - attribute \src "ls180.v:1867.6-1867.31" + attribute \src "ls180.v:1866.6-1866.31" wire \builder_csrbank0_reset0_r - attribute \src "ls180.v:1866.6-1866.32" + attribute \src "ls180.v:1865.6-1865.32" wire \builder_csrbank0_reset0_re - attribute \src "ls180.v:1869.6-1869.31" + attribute \src "ls180.v:1868.6-1868.31" wire \builder_csrbank0_reset0_w - attribute \src "ls180.v:1868.6-1868.32" + attribute \src "ls180.v:1867.6-1867.32" wire \builder_csrbank0_reset0_we - attribute \src "ls180.v:1883.12-1883.39" + attribute \src "ls180.v:1882.12-1882.39" wire width 8 \builder_csrbank0_scratch0_r - attribute \src "ls180.v:1882.6-1882.34" + attribute \src "ls180.v:1881.6-1881.34" wire \builder_csrbank0_scratch0_re - attribute \src "ls180.v:1885.12-1885.39" + attribute \src "ls180.v:1884.12-1884.39" wire width 8 \builder_csrbank0_scratch0_w - attribute \src "ls180.v:1884.6-1884.34" + attribute \src "ls180.v:1883.6-1883.34" wire \builder_csrbank0_scratch0_we - attribute \src "ls180.v:1879.12-1879.39" + attribute \src "ls180.v:1878.12-1878.39" wire width 8 \builder_csrbank0_scratch1_r - attribute \src "ls180.v:1878.6-1878.34" + attribute \src "ls180.v:1877.6-1877.34" wire \builder_csrbank0_scratch1_re - attribute \src "ls180.v:1881.12-1881.39" + attribute \src "ls180.v:1880.12-1880.39" wire width 8 \builder_csrbank0_scratch1_w - attribute \src "ls180.v:1880.6-1880.34" + attribute \src "ls180.v:1879.6-1879.34" wire \builder_csrbank0_scratch1_we - attribute \src "ls180.v:1875.12-1875.39" + attribute \src "ls180.v:1874.12-1874.39" wire width 8 \builder_csrbank0_scratch2_r - attribute \src "ls180.v:1874.6-1874.34" + attribute \src "ls180.v:1873.6-1873.34" wire \builder_csrbank0_scratch2_re - attribute \src "ls180.v:1877.12-1877.39" + attribute \src "ls180.v:1876.12-1876.39" wire width 8 \builder_csrbank0_scratch2_w - attribute \src "ls180.v:1876.6-1876.34" + attribute \src "ls180.v:1875.6-1875.34" wire \builder_csrbank0_scratch2_we - attribute \src "ls180.v:1871.12-1871.39" + attribute \src "ls180.v:1870.12-1870.39" wire width 8 \builder_csrbank0_scratch3_r - attribute \src "ls180.v:1870.6-1870.34" + attribute \src "ls180.v:1869.6-1869.34" wire \builder_csrbank0_scratch3_re - attribute \src "ls180.v:1873.12-1873.39" + attribute \src "ls180.v:1872.12-1872.39" wire width 8 \builder_csrbank0_scratch3_w - attribute \src "ls180.v:1872.6-1872.34" + attribute \src "ls180.v:1871.6-1871.34" wire \builder_csrbank0_scratch3_we - attribute \src "ls180.v:1902.6-1902.26" + attribute \src "ls180.v:1901.6-1901.26" wire \builder_csrbank0_sel - attribute \src "ls180.v:2421.12-2421.44" + attribute \src "ls180.v:2420.12-2420.44" wire width 8 \builder_csrbank10_clk_divider0_r - attribute \src "ls180.v:2420.6-2420.39" + attribute \src "ls180.v:2419.6-2419.39" wire \builder_csrbank10_clk_divider0_re - attribute \src "ls180.v:2423.12-2423.44" + attribute \src "ls180.v:2422.12-2422.44" wire width 8 \builder_csrbank10_clk_divider0_w - attribute \src "ls180.v:2422.6-2422.39" + attribute \src "ls180.v:2421.6-2421.39" wire \builder_csrbank10_clk_divider0_we - attribute \src "ls180.v:2417.12-2417.44" + attribute \src "ls180.v:2416.12-2416.44" wire width 8 \builder_csrbank10_clk_divider1_r - attribute \src "ls180.v:2416.6-2416.39" + attribute \src "ls180.v:2415.6-2415.39" wire \builder_csrbank10_clk_divider1_re - attribute \src "ls180.v:2419.12-2419.44" + attribute \src "ls180.v:2418.12-2418.44" wire width 8 \builder_csrbank10_clk_divider1_w - attribute \src "ls180.v:2418.6-2418.39" + attribute \src "ls180.v:2417.6-2417.39" wire \builder_csrbank10_clk_divider1_we - attribute \src "ls180.v:2393.12-2393.40" + attribute \src "ls180.v:2392.12-2392.40" wire width 8 \builder_csrbank10_control0_r - attribute \src "ls180.v:2392.6-2392.35" + attribute \src "ls180.v:2391.6-2391.35" wire \builder_csrbank10_control0_re - attribute \src "ls180.v:2395.12-2395.40" + attribute \src "ls180.v:2394.12-2394.40" wire width 8 \builder_csrbank10_control0_w - attribute \src "ls180.v:2394.6-2394.35" + attribute \src "ls180.v:2393.6-2393.35" wire \builder_csrbank10_control0_we - attribute \src "ls180.v:2389.12-2389.40" + attribute \src "ls180.v:2388.12-2388.40" wire width 8 \builder_csrbank10_control1_r - attribute \src "ls180.v:2388.6-2388.35" + attribute \src "ls180.v:2387.6-2387.35" wire \builder_csrbank10_control1_re - attribute \src "ls180.v:2391.12-2391.40" + attribute \src "ls180.v:2390.12-2390.40" wire width 8 \builder_csrbank10_control1_w - attribute \src "ls180.v:2390.6-2390.35" + attribute \src "ls180.v:2389.6-2389.35" wire \builder_csrbank10_control1_we - attribute \src "ls180.v:2409.6-2409.29" + attribute \src "ls180.v:2408.6-2408.29" wire \builder_csrbank10_cs0_r - attribute \src "ls180.v:2408.6-2408.30" + attribute \src "ls180.v:2407.6-2407.30" wire \builder_csrbank10_cs0_re - attribute \src "ls180.v:2411.6-2411.29" + attribute \src "ls180.v:2410.6-2410.29" wire \builder_csrbank10_cs0_w - attribute \src "ls180.v:2410.6-2410.30" + attribute \src "ls180.v:2409.6-2409.30" wire \builder_csrbank10_cs0_we - attribute \src "ls180.v:2413.6-2413.35" + attribute \src "ls180.v:2412.6-2412.35" wire \builder_csrbank10_loopback0_r - attribute \src "ls180.v:2412.6-2412.36" + attribute \src "ls180.v:2411.6-2411.36" wire \builder_csrbank10_loopback0_re - attribute \src "ls180.v:2415.6-2415.35" + attribute \src "ls180.v:2414.6-2414.35" wire \builder_csrbank10_loopback0_w - attribute \src "ls180.v:2414.6-2414.36" + attribute \src "ls180.v:2413.6-2413.36" wire \builder_csrbank10_loopback0_we - attribute \src "ls180.v:2405.12-2405.36" + attribute \src "ls180.v:2404.12-2404.36" wire width 8 \builder_csrbank10_miso_r - attribute \src "ls180.v:2404.6-2404.31" + attribute \src "ls180.v:2403.6-2403.31" wire \builder_csrbank10_miso_re - attribute \src "ls180.v:2407.12-2407.36" + attribute \src "ls180.v:2406.12-2406.36" wire width 8 \builder_csrbank10_miso_w - attribute \src "ls180.v:2406.6-2406.31" + attribute \src "ls180.v:2405.6-2405.31" wire \builder_csrbank10_miso_we - attribute \src "ls180.v:2401.12-2401.37" + attribute \src "ls180.v:2400.12-2400.37" wire width 8 \builder_csrbank10_mosi0_r - attribute \src "ls180.v:2400.6-2400.32" + attribute \src "ls180.v:2399.6-2399.32" wire \builder_csrbank10_mosi0_re - attribute \src "ls180.v:2403.12-2403.37" + attribute \src "ls180.v:2402.12-2402.37" wire width 8 \builder_csrbank10_mosi0_w - attribute \src "ls180.v:2402.6-2402.32" + attribute \src "ls180.v:2401.6-2401.32" wire \builder_csrbank10_mosi0_we - attribute \src "ls180.v:2424.6-2424.27" + attribute \src "ls180.v:2423.6-2423.27" wire \builder_csrbank10_sel - attribute \src "ls180.v:2397.6-2397.32" + attribute \src "ls180.v:2396.6-2396.32" wire \builder_csrbank10_status_r - attribute \src "ls180.v:2396.6-2396.33" + attribute \src "ls180.v:2395.6-2395.33" wire \builder_csrbank10_status_re - attribute \src "ls180.v:2399.6-2399.32" + attribute \src "ls180.v:2398.6-2398.32" wire \builder_csrbank10_status_w - attribute \src "ls180.v:2398.6-2398.33" + attribute \src "ls180.v:2397.6-2397.33" wire \builder_csrbank10_status_we - attribute \src "ls180.v:2462.6-2462.29" + attribute \src "ls180.v:2461.6-2461.29" wire \builder_csrbank11_en0_r - attribute \src "ls180.v:2461.6-2461.30" + attribute \src "ls180.v:2460.6-2460.30" wire \builder_csrbank11_en0_re - attribute \src "ls180.v:2464.6-2464.29" + attribute \src "ls180.v:2463.6-2463.29" wire \builder_csrbank11_en0_w - attribute \src "ls180.v:2463.6-2463.30" + attribute \src "ls180.v:2462.6-2462.30" wire \builder_csrbank11_en0_we - attribute \src "ls180.v:2486.6-2486.36" + attribute \src "ls180.v:2485.6-2485.36" wire \builder_csrbank11_ev_enable0_r - attribute \src "ls180.v:2485.6-2485.37" + attribute \src "ls180.v:2484.6-2484.37" wire \builder_csrbank11_ev_enable0_re - attribute \src "ls180.v:2488.6-2488.36" + attribute \src "ls180.v:2487.6-2487.36" wire \builder_csrbank11_ev_enable0_w - attribute \src "ls180.v:2487.6-2487.37" + attribute \src "ls180.v:2486.6-2486.37" wire \builder_csrbank11_ev_enable0_we - attribute \src "ls180.v:2442.12-2442.37" + attribute \src "ls180.v:2441.12-2441.37" wire width 8 \builder_csrbank11_load0_r - attribute \src "ls180.v:2441.6-2441.32" + attribute \src "ls180.v:2440.6-2440.32" wire \builder_csrbank11_load0_re - attribute \src "ls180.v:2444.12-2444.37" + attribute \src "ls180.v:2443.12-2443.37" wire width 8 \builder_csrbank11_load0_w - attribute \src "ls180.v:2443.6-2443.32" + attribute \src "ls180.v:2442.6-2442.32" wire \builder_csrbank11_load0_we - attribute \src "ls180.v:2438.12-2438.37" + attribute \src "ls180.v:2437.12-2437.37" wire width 8 \builder_csrbank11_load1_r - attribute \src "ls180.v:2437.6-2437.32" + attribute \src "ls180.v:2436.6-2436.32" wire \builder_csrbank11_load1_re - attribute \src "ls180.v:2440.12-2440.37" + attribute \src "ls180.v:2439.12-2439.37" wire width 8 \builder_csrbank11_load1_w - attribute \src "ls180.v:2439.6-2439.32" + attribute \src "ls180.v:2438.6-2438.32" wire \builder_csrbank11_load1_we - attribute \src "ls180.v:2434.12-2434.37" + attribute \src "ls180.v:2433.12-2433.37" wire width 8 \builder_csrbank11_load2_r - attribute \src "ls180.v:2433.6-2433.32" + attribute \src "ls180.v:2432.6-2432.32" wire \builder_csrbank11_load2_re - attribute \src "ls180.v:2436.12-2436.37" + attribute \src "ls180.v:2435.12-2435.37" wire width 8 \builder_csrbank11_load2_w - attribute \src "ls180.v:2435.6-2435.32" + attribute \src "ls180.v:2434.6-2434.32" wire \builder_csrbank11_load2_we - attribute \src "ls180.v:2430.12-2430.37" + attribute \src "ls180.v:2429.12-2429.37" wire width 8 \builder_csrbank11_load3_r - attribute \src "ls180.v:2429.6-2429.32" + attribute \src "ls180.v:2428.6-2428.32" wire \builder_csrbank11_load3_re - attribute \src "ls180.v:2432.12-2432.37" + attribute \src "ls180.v:2431.12-2431.37" wire width 8 \builder_csrbank11_load3_w - attribute \src "ls180.v:2431.6-2431.32" + attribute \src "ls180.v:2430.6-2430.32" wire \builder_csrbank11_load3_we - attribute \src "ls180.v:2458.12-2458.39" + attribute \src "ls180.v:2457.12-2457.39" wire width 8 \builder_csrbank11_reload0_r - attribute \src "ls180.v:2457.6-2457.34" + attribute \src "ls180.v:2456.6-2456.34" wire \builder_csrbank11_reload0_re - attribute \src "ls180.v:2460.12-2460.39" + attribute \src "ls180.v:2459.12-2459.39" wire width 8 \builder_csrbank11_reload0_w - attribute \src "ls180.v:2459.6-2459.34" + attribute \src "ls180.v:2458.6-2458.34" wire \builder_csrbank11_reload0_we - attribute \src "ls180.v:2454.12-2454.39" + attribute \src "ls180.v:2453.12-2453.39" wire width 8 \builder_csrbank11_reload1_r - attribute \src "ls180.v:2453.6-2453.34" + attribute \src "ls180.v:2452.6-2452.34" wire \builder_csrbank11_reload1_re - attribute \src "ls180.v:2456.12-2456.39" + attribute \src "ls180.v:2455.12-2455.39" wire width 8 \builder_csrbank11_reload1_w - attribute \src "ls180.v:2455.6-2455.34" + attribute \src "ls180.v:2454.6-2454.34" wire \builder_csrbank11_reload1_we - attribute \src "ls180.v:2450.12-2450.39" + attribute \src "ls180.v:2449.12-2449.39" wire width 8 \builder_csrbank11_reload2_r - attribute \src "ls180.v:2449.6-2449.34" + attribute \src "ls180.v:2448.6-2448.34" wire \builder_csrbank11_reload2_re - attribute \src "ls180.v:2452.12-2452.39" + attribute \src "ls180.v:2451.12-2451.39" wire width 8 \builder_csrbank11_reload2_w - attribute \src "ls180.v:2451.6-2451.34" + attribute \src "ls180.v:2450.6-2450.34" wire \builder_csrbank11_reload2_we - attribute \src "ls180.v:2446.12-2446.39" + attribute \src "ls180.v:2445.12-2445.39" wire width 8 \builder_csrbank11_reload3_r - attribute \src "ls180.v:2445.6-2445.34" + attribute \src "ls180.v:2444.6-2444.34" wire \builder_csrbank11_reload3_re - attribute \src "ls180.v:2448.12-2448.39" + attribute \src "ls180.v:2447.12-2447.39" wire width 8 \builder_csrbank11_reload3_w - attribute \src "ls180.v:2447.6-2447.34" + attribute \src "ls180.v:2446.6-2446.34" wire \builder_csrbank11_reload3_we - attribute \src "ls180.v:2489.6-2489.27" + attribute \src "ls180.v:2488.6-2488.27" wire \builder_csrbank11_sel - attribute \src "ls180.v:2466.6-2466.39" + attribute \src "ls180.v:2465.6-2465.39" wire \builder_csrbank11_update_value0_r - attribute \src "ls180.v:2465.6-2465.40" + attribute \src "ls180.v:2464.6-2464.40" wire \builder_csrbank11_update_value0_re - attribute \src "ls180.v:2468.6-2468.39" + attribute \src "ls180.v:2467.6-2467.39" wire \builder_csrbank11_update_value0_w - attribute \src "ls180.v:2467.6-2467.40" + attribute \src "ls180.v:2466.6-2466.40" wire \builder_csrbank11_update_value0_we - attribute \src "ls180.v:2482.12-2482.38" + attribute \src "ls180.v:2481.12-2481.38" wire width 8 \builder_csrbank11_value0_r - attribute \src "ls180.v:2481.6-2481.33" + attribute \src "ls180.v:2480.6-2480.33" wire \builder_csrbank11_value0_re - attribute \src "ls180.v:2484.12-2484.38" + attribute \src "ls180.v:2483.12-2483.38" wire width 8 \builder_csrbank11_value0_w - attribute \src "ls180.v:2483.6-2483.33" + attribute \src "ls180.v:2482.6-2482.33" wire \builder_csrbank11_value0_we - attribute \src "ls180.v:2478.12-2478.38" + attribute \src "ls180.v:2477.12-2477.38" wire width 8 \builder_csrbank11_value1_r - attribute \src "ls180.v:2477.6-2477.33" + attribute \src "ls180.v:2476.6-2476.33" wire \builder_csrbank11_value1_re - attribute \src "ls180.v:2480.12-2480.38" + attribute \src "ls180.v:2479.12-2479.38" wire width 8 \builder_csrbank11_value1_w - attribute \src "ls180.v:2479.6-2479.33" + attribute \src "ls180.v:2478.6-2478.33" wire \builder_csrbank11_value1_we - attribute \src "ls180.v:2474.12-2474.38" + attribute \src "ls180.v:2473.12-2473.38" wire width 8 \builder_csrbank11_value2_r - attribute \src "ls180.v:2473.6-2473.33" + attribute \src "ls180.v:2472.6-2472.33" wire \builder_csrbank11_value2_re - attribute \src "ls180.v:2476.12-2476.38" + attribute \src "ls180.v:2475.12-2475.38" wire width 8 \builder_csrbank11_value2_w - attribute \src "ls180.v:2475.6-2475.33" + attribute \src "ls180.v:2474.6-2474.33" wire \builder_csrbank11_value2_we - attribute \src "ls180.v:2470.12-2470.38" + attribute \src "ls180.v:2469.12-2469.38" wire width 8 \builder_csrbank11_value3_r - attribute \src "ls180.v:2469.6-2469.33" + attribute \src "ls180.v:2468.6-2468.33" wire \builder_csrbank11_value3_re - attribute \src "ls180.v:2472.12-2472.38" + attribute \src "ls180.v:2471.12-2471.38" wire width 8 \builder_csrbank11_value3_w - attribute \src "ls180.v:2471.6-2471.33" + attribute \src "ls180.v:2470.6-2470.33" wire \builder_csrbank11_value3_we - attribute \src "ls180.v:2503.12-2503.42" + attribute \src "ls180.v:2502.12-2502.42" wire width 2 \builder_csrbank12_ev_enable0_r - attribute \src "ls180.v:2502.6-2502.37" + attribute \src "ls180.v:2501.6-2501.37" wire \builder_csrbank12_ev_enable0_re - attribute \src "ls180.v:2505.12-2505.42" + attribute \src "ls180.v:2504.12-2504.42" wire width 2 \builder_csrbank12_ev_enable0_w - attribute \src "ls180.v:2504.6-2504.37" + attribute \src "ls180.v:2503.6-2503.37" wire \builder_csrbank12_ev_enable0_we - attribute \src "ls180.v:2499.6-2499.33" + attribute \src "ls180.v:2498.6-2498.33" wire \builder_csrbank12_rxempty_r - attribute \src "ls180.v:2498.6-2498.34" + attribute \src "ls180.v:2497.6-2497.34" wire \builder_csrbank12_rxempty_re - attribute \src "ls180.v:2501.6-2501.33" + attribute \src "ls180.v:2500.6-2500.33" wire \builder_csrbank12_rxempty_w - attribute \src "ls180.v:2500.6-2500.34" + attribute \src "ls180.v:2499.6-2499.34" wire \builder_csrbank12_rxempty_we - attribute \src "ls180.v:2511.6-2511.32" + attribute \src "ls180.v:2510.6-2510.32" wire \builder_csrbank12_rxfull_r - attribute \src "ls180.v:2510.6-2510.33" + attribute \src "ls180.v:2509.6-2509.33" wire \builder_csrbank12_rxfull_re - attribute \src "ls180.v:2513.6-2513.32" + attribute \src "ls180.v:2512.6-2512.32" wire \builder_csrbank12_rxfull_w - attribute \src "ls180.v:2512.6-2512.33" + attribute \src "ls180.v:2511.6-2511.33" wire \builder_csrbank12_rxfull_we - attribute \src "ls180.v:2514.6-2514.27" + attribute \src "ls180.v:2513.6-2513.27" wire \builder_csrbank12_sel - attribute \src "ls180.v:2507.6-2507.33" + attribute \src "ls180.v:2506.6-2506.33" wire \builder_csrbank12_txempty_r - attribute \src "ls180.v:2506.6-2506.34" + attribute \src "ls180.v:2505.6-2505.34" wire \builder_csrbank12_txempty_re - attribute \src "ls180.v:2509.6-2509.33" + attribute \src "ls180.v:2508.6-2508.33" wire \builder_csrbank12_txempty_w - attribute \src "ls180.v:2508.6-2508.34" + attribute \src "ls180.v:2507.6-2507.34" wire \builder_csrbank12_txempty_we - attribute \src "ls180.v:2495.6-2495.32" + attribute \src "ls180.v:2494.6-2494.32" wire \builder_csrbank12_txfull_r - attribute \src "ls180.v:2494.6-2494.33" + attribute \src "ls180.v:2493.6-2493.33" wire \builder_csrbank12_txfull_re - attribute \src "ls180.v:2497.6-2497.32" + attribute \src "ls180.v:2496.6-2496.32" wire \builder_csrbank12_txfull_w - attribute \src "ls180.v:2496.6-2496.33" + attribute \src "ls180.v:2495.6-2495.33" wire \builder_csrbank12_txfull_we - attribute \src "ls180.v:2535.6-2535.27" + attribute \src "ls180.v:2534.6-2534.27" wire \builder_csrbank13_sel - attribute \src "ls180.v:2532.12-2532.44" + attribute \src "ls180.v:2531.12-2531.44" wire width 8 \builder_csrbank13_tuning_word0_r - attribute \src "ls180.v:2531.6-2531.39" + attribute \src "ls180.v:2530.6-2530.39" wire \builder_csrbank13_tuning_word0_re - attribute \src "ls180.v:2534.12-2534.44" + attribute \src "ls180.v:2533.12-2533.44" wire width 8 \builder_csrbank13_tuning_word0_w - attribute \src "ls180.v:2533.6-2533.39" + attribute \src "ls180.v:2532.6-2532.39" wire \builder_csrbank13_tuning_word0_we - attribute \src "ls180.v:2528.12-2528.44" + attribute \src "ls180.v:2527.12-2527.44" wire width 8 \builder_csrbank13_tuning_word1_r - attribute \src "ls180.v:2527.6-2527.39" + attribute \src "ls180.v:2526.6-2526.39" wire \builder_csrbank13_tuning_word1_re - attribute \src "ls180.v:2530.12-2530.44" + attribute \src "ls180.v:2529.12-2529.44" wire width 8 \builder_csrbank13_tuning_word1_w - attribute \src "ls180.v:2529.6-2529.39" + attribute \src "ls180.v:2528.6-2528.39" wire \builder_csrbank13_tuning_word1_we - attribute \src "ls180.v:2524.12-2524.44" + attribute \src "ls180.v:2523.12-2523.44" wire width 8 \builder_csrbank13_tuning_word2_r - attribute \src "ls180.v:2523.6-2523.39" + attribute \src "ls180.v:2522.6-2522.39" wire \builder_csrbank13_tuning_word2_re - attribute \src "ls180.v:2526.12-2526.44" + attribute \src "ls180.v:2525.12-2525.44" wire width 8 \builder_csrbank13_tuning_word2_w - attribute \src "ls180.v:2525.6-2525.39" + attribute \src "ls180.v:2524.6-2524.39" wire \builder_csrbank13_tuning_word2_we - attribute \src "ls180.v:2520.12-2520.44" + attribute \src "ls180.v:2519.12-2519.44" wire width 8 \builder_csrbank13_tuning_word3_r - attribute \src "ls180.v:2519.6-2519.39" + attribute \src "ls180.v:2518.6-2518.39" wire \builder_csrbank13_tuning_word3_re - attribute \src "ls180.v:2522.12-2522.44" + attribute \src "ls180.v:2521.12-2521.44" wire width 8 \builder_csrbank13_tuning_word3_w - attribute \src "ls180.v:2521.6-2521.39" + attribute \src "ls180.v:2520.6-2520.39" wire \builder_csrbank13_tuning_word3_we - attribute \src "ls180.v:1920.12-1920.34" + attribute \src "ls180.v:1919.12-1919.34" wire width 8 \builder_csrbank1_in0_r - attribute \src "ls180.v:1919.6-1919.29" + attribute \src "ls180.v:1918.6-1918.29" wire \builder_csrbank1_in0_re - attribute \src "ls180.v:1922.12-1922.34" + attribute \src "ls180.v:1921.12-1921.34" wire width 8 \builder_csrbank1_in0_w - attribute \src "ls180.v:1921.6-1921.29" + attribute \src "ls180.v:1920.6-1920.29" wire \builder_csrbank1_in0_we - attribute \src "ls180.v:1916.12-1916.34" + attribute \src "ls180.v:1915.12-1915.34" wire width 8 \builder_csrbank1_in1_r - attribute \src "ls180.v:1915.6-1915.29" + attribute \src "ls180.v:1914.6-1914.29" wire \builder_csrbank1_in1_re - attribute \src "ls180.v:1918.12-1918.34" + attribute \src "ls180.v:1917.12-1917.34" wire width 8 \builder_csrbank1_in1_w - attribute \src "ls180.v:1917.6-1917.29" + attribute \src "ls180.v:1916.6-1916.29" wire \builder_csrbank1_in1_we - attribute \src "ls180.v:1912.12-1912.34" + attribute \src "ls180.v:1911.12-1911.34" wire width 8 \builder_csrbank1_oe0_r - attribute \src "ls180.v:1911.6-1911.29" + attribute \src "ls180.v:1910.6-1910.29" wire \builder_csrbank1_oe0_re - attribute \src "ls180.v:1914.12-1914.34" + attribute \src "ls180.v:1913.12-1913.34" wire width 8 \builder_csrbank1_oe0_w - attribute \src "ls180.v:1913.6-1913.29" + attribute \src "ls180.v:1912.6-1912.29" wire \builder_csrbank1_oe0_we - attribute \src "ls180.v:1908.12-1908.34" + attribute \src "ls180.v:1907.12-1907.34" wire width 8 \builder_csrbank1_oe1_r - attribute \src "ls180.v:1907.6-1907.29" + attribute \src "ls180.v:1906.6-1906.29" wire \builder_csrbank1_oe1_re - attribute \src "ls180.v:1910.12-1910.34" + attribute \src "ls180.v:1909.12-1909.34" wire width 8 \builder_csrbank1_oe1_w - attribute \src "ls180.v:1909.6-1909.29" + attribute \src "ls180.v:1908.6-1908.29" wire \builder_csrbank1_oe1_we - attribute \src "ls180.v:1928.12-1928.35" + attribute \src "ls180.v:1927.12-1927.35" wire width 8 \builder_csrbank1_out0_r - attribute \src "ls180.v:1927.6-1927.30" + attribute \src "ls180.v:1926.6-1926.30" wire \builder_csrbank1_out0_re - attribute \src "ls180.v:1930.12-1930.35" + attribute \src "ls180.v:1929.12-1929.35" wire width 8 \builder_csrbank1_out0_w - attribute \src "ls180.v:1929.6-1929.30" + attribute \src "ls180.v:1928.6-1928.30" wire \builder_csrbank1_out0_we - attribute \src "ls180.v:1924.12-1924.35" + attribute \src "ls180.v:1923.12-1923.35" wire width 8 \builder_csrbank1_out1_r - attribute \src "ls180.v:1923.6-1923.30" + attribute \src "ls180.v:1922.6-1922.30" wire \builder_csrbank1_out1_re - attribute \src "ls180.v:1926.12-1926.35" + attribute \src "ls180.v:1925.12-1925.35" wire width 8 \builder_csrbank1_out1_w - attribute \src "ls180.v:1925.6-1925.30" + attribute \src "ls180.v:1924.6-1924.30" wire \builder_csrbank1_out1_we - attribute \src "ls180.v:1931.6-1931.26" + attribute \src "ls180.v:1930.6-1930.26" wire \builder_csrbank1_sel - attribute \src "ls180.v:1937.6-1937.32" + attribute \src "ls180.v:1936.6-1936.32" wire \builder_csrbank2_enable0_r - attribute \src "ls180.v:1936.6-1936.33" + attribute \src "ls180.v:1935.6-1935.33" wire \builder_csrbank2_enable0_re - attribute \src "ls180.v:1939.6-1939.32" + attribute \src "ls180.v:1938.6-1938.32" wire \builder_csrbank2_enable0_w - attribute \src "ls180.v:1938.6-1938.33" + attribute \src "ls180.v:1937.6-1937.33" wire \builder_csrbank2_enable0_we - attribute \src "ls180.v:1969.12-1969.38" + attribute \src "ls180.v:1968.12-1968.38" wire width 8 \builder_csrbank2_period0_r - attribute \src "ls180.v:1968.6-1968.33" + attribute \src "ls180.v:1967.6-1967.33" wire \builder_csrbank2_period0_re - attribute \src "ls180.v:1971.12-1971.38" + attribute \src "ls180.v:1970.12-1970.38" wire width 8 \builder_csrbank2_period0_w - attribute \src "ls180.v:1970.6-1970.33" + attribute \src "ls180.v:1969.6-1969.33" wire \builder_csrbank2_period0_we - attribute \src "ls180.v:1965.12-1965.38" + attribute \src "ls180.v:1964.12-1964.38" wire width 8 \builder_csrbank2_period1_r - attribute \src "ls180.v:1964.6-1964.33" + attribute \src "ls180.v:1963.6-1963.33" wire \builder_csrbank2_period1_re - attribute \src "ls180.v:1967.12-1967.38" + attribute \src "ls180.v:1966.12-1966.38" wire width 8 \builder_csrbank2_period1_w - attribute \src "ls180.v:1966.6-1966.33" + attribute \src "ls180.v:1965.6-1965.33" wire \builder_csrbank2_period1_we - attribute \src "ls180.v:1961.12-1961.38" + attribute \src "ls180.v:1960.12-1960.38" wire width 8 \builder_csrbank2_period2_r - attribute \src "ls180.v:1960.6-1960.33" + attribute \src "ls180.v:1959.6-1959.33" wire \builder_csrbank2_period2_re - attribute \src "ls180.v:1963.12-1963.38" + attribute \src "ls180.v:1962.12-1962.38" wire width 8 \builder_csrbank2_period2_w - attribute \src "ls180.v:1962.6-1962.33" + attribute \src "ls180.v:1961.6-1961.33" wire \builder_csrbank2_period2_we - attribute \src "ls180.v:1957.12-1957.38" + attribute \src "ls180.v:1956.12-1956.38" wire width 8 \builder_csrbank2_period3_r - attribute \src "ls180.v:1956.6-1956.33" + attribute \src "ls180.v:1955.6-1955.33" wire \builder_csrbank2_period3_re - attribute \src "ls180.v:1959.12-1959.38" + attribute \src "ls180.v:1958.12-1958.38" wire width 8 \builder_csrbank2_period3_w - attribute \src "ls180.v:1958.6-1958.33" + attribute \src "ls180.v:1957.6-1957.33" wire \builder_csrbank2_period3_we - attribute \src "ls180.v:1972.6-1972.26" + attribute \src "ls180.v:1971.6-1971.26" wire \builder_csrbank2_sel - attribute \src "ls180.v:1953.12-1953.37" + attribute \src "ls180.v:1952.12-1952.37" wire width 8 \builder_csrbank2_width0_r - attribute \src "ls180.v:1952.6-1952.32" + attribute \src "ls180.v:1951.6-1951.32" wire \builder_csrbank2_width0_re - attribute \src "ls180.v:1955.12-1955.37" + attribute \src "ls180.v:1954.12-1954.37" wire width 8 \builder_csrbank2_width0_w - attribute \src "ls180.v:1954.6-1954.32" + attribute \src "ls180.v:1953.6-1953.32" wire \builder_csrbank2_width0_we - attribute \src "ls180.v:1949.12-1949.37" + attribute \src "ls180.v:1948.12-1948.37" wire width 8 \builder_csrbank2_width1_r - attribute \src "ls180.v:1948.6-1948.32" + attribute \src "ls180.v:1947.6-1947.32" wire \builder_csrbank2_width1_re - attribute \src "ls180.v:1951.12-1951.37" + attribute \src "ls180.v:1950.12-1950.37" wire width 8 \builder_csrbank2_width1_w - attribute \src "ls180.v:1950.6-1950.32" + attribute \src "ls180.v:1949.6-1949.32" wire \builder_csrbank2_width1_we - attribute \src "ls180.v:1945.12-1945.37" + attribute \src "ls180.v:1944.12-1944.37" wire width 8 \builder_csrbank2_width2_r - attribute \src "ls180.v:1944.6-1944.32" + attribute \src "ls180.v:1943.6-1943.32" wire \builder_csrbank2_width2_re - attribute \src "ls180.v:1947.12-1947.37" + attribute \src "ls180.v:1946.12-1946.37" wire width 8 \builder_csrbank2_width2_w - attribute \src "ls180.v:1946.6-1946.32" + attribute \src "ls180.v:1945.6-1945.32" wire \builder_csrbank2_width2_we - attribute \src "ls180.v:1941.12-1941.37" + attribute \src "ls180.v:1940.12-1940.37" wire width 8 \builder_csrbank2_width3_r - attribute \src "ls180.v:1940.6-1940.32" + attribute \src "ls180.v:1939.6-1939.32" wire \builder_csrbank2_width3_re - attribute \src "ls180.v:1943.12-1943.37" + attribute \src "ls180.v:1942.12-1942.37" wire width 8 \builder_csrbank2_width3_w - attribute \src "ls180.v:1942.6-1942.32" + attribute \src "ls180.v:1941.6-1941.32" wire \builder_csrbank2_width3_we - attribute \src "ls180.v:1978.6-1978.32" + attribute \src "ls180.v:1977.6-1977.32" wire \builder_csrbank3_enable0_r - attribute \src "ls180.v:1977.6-1977.33" + attribute \src "ls180.v:1976.6-1976.33" wire \builder_csrbank3_enable0_re - attribute \src "ls180.v:1980.6-1980.32" + attribute \src "ls180.v:1979.6-1979.32" wire \builder_csrbank3_enable0_w - attribute \src "ls180.v:1979.6-1979.33" + attribute \src "ls180.v:1978.6-1978.33" wire \builder_csrbank3_enable0_we - attribute \src "ls180.v:2010.12-2010.38" + attribute \src "ls180.v:2009.12-2009.38" wire width 8 \builder_csrbank3_period0_r - attribute \src "ls180.v:2009.6-2009.33" + attribute \src "ls180.v:2008.6-2008.33" wire \builder_csrbank3_period0_re - attribute \src "ls180.v:2012.12-2012.38" + attribute \src "ls180.v:2011.12-2011.38" wire width 8 \builder_csrbank3_period0_w - attribute \src "ls180.v:2011.6-2011.33" + attribute \src "ls180.v:2010.6-2010.33" wire \builder_csrbank3_period0_we - attribute \src "ls180.v:2006.12-2006.38" + attribute \src "ls180.v:2005.12-2005.38" wire width 8 \builder_csrbank3_period1_r - attribute \src "ls180.v:2005.6-2005.33" + attribute \src "ls180.v:2004.6-2004.33" wire \builder_csrbank3_period1_re - attribute \src "ls180.v:2008.12-2008.38" + attribute \src "ls180.v:2007.12-2007.38" wire width 8 \builder_csrbank3_period1_w - attribute \src "ls180.v:2007.6-2007.33" + attribute \src "ls180.v:2006.6-2006.33" wire \builder_csrbank3_period1_we - attribute \src "ls180.v:2002.12-2002.38" + attribute \src "ls180.v:2001.12-2001.38" wire width 8 \builder_csrbank3_period2_r - attribute \src "ls180.v:2001.6-2001.33" + attribute \src "ls180.v:2000.6-2000.33" wire \builder_csrbank3_period2_re - attribute \src "ls180.v:2004.12-2004.38" + attribute \src "ls180.v:2003.12-2003.38" wire width 8 \builder_csrbank3_period2_w - attribute \src "ls180.v:2003.6-2003.33" + attribute \src "ls180.v:2002.6-2002.33" wire \builder_csrbank3_period2_we - attribute \src "ls180.v:1998.12-1998.38" + attribute \src "ls180.v:1997.12-1997.38" wire width 8 \builder_csrbank3_period3_r - attribute \src "ls180.v:1997.6-1997.33" + attribute \src "ls180.v:1996.6-1996.33" wire \builder_csrbank3_period3_re - attribute \src "ls180.v:2000.12-2000.38" + attribute \src "ls180.v:1999.12-1999.38" wire width 8 \builder_csrbank3_period3_w - attribute \src "ls180.v:1999.6-1999.33" + attribute \src "ls180.v:1998.6-1998.33" wire \builder_csrbank3_period3_we - attribute \src "ls180.v:2013.6-2013.26" + attribute \src "ls180.v:2012.6-2012.26" wire \builder_csrbank3_sel - attribute \src "ls180.v:1994.12-1994.37" + attribute \src "ls180.v:1993.12-1993.37" wire width 8 \builder_csrbank3_width0_r - attribute \src "ls180.v:1993.6-1993.32" + attribute \src "ls180.v:1992.6-1992.32" wire \builder_csrbank3_width0_re - attribute \src "ls180.v:1996.12-1996.37" + attribute \src "ls180.v:1995.12-1995.37" wire width 8 \builder_csrbank3_width0_w - attribute \src "ls180.v:1995.6-1995.32" + attribute \src "ls180.v:1994.6-1994.32" wire \builder_csrbank3_width0_we - attribute \src "ls180.v:1990.12-1990.37" + attribute \src "ls180.v:1989.12-1989.37" wire width 8 \builder_csrbank3_width1_r - attribute \src "ls180.v:1989.6-1989.32" + attribute \src "ls180.v:1988.6-1988.32" wire \builder_csrbank3_width1_re - attribute \src "ls180.v:1992.12-1992.37" + attribute \src "ls180.v:1991.12-1991.37" wire width 8 \builder_csrbank3_width1_w - attribute \src "ls180.v:1991.6-1991.32" + attribute \src "ls180.v:1990.6-1990.32" wire \builder_csrbank3_width1_we - attribute \src "ls180.v:1986.12-1986.37" + attribute \src "ls180.v:1985.12-1985.37" wire width 8 \builder_csrbank3_width2_r - attribute \src "ls180.v:1985.6-1985.32" + attribute \src "ls180.v:1984.6-1984.32" wire \builder_csrbank3_width2_re - attribute \src "ls180.v:1988.12-1988.37" + attribute \src "ls180.v:1987.12-1987.37" wire width 8 \builder_csrbank3_width2_w - attribute \src "ls180.v:1987.6-1987.32" + attribute \src "ls180.v:1986.6-1986.32" wire \builder_csrbank3_width2_we - attribute \src "ls180.v:1982.12-1982.37" + attribute \src "ls180.v:1981.12-1981.37" wire width 8 \builder_csrbank3_width3_r - attribute \src "ls180.v:1981.6-1981.32" + attribute \src "ls180.v:1980.6-1980.32" wire \builder_csrbank3_width3_re - attribute \src "ls180.v:1984.12-1984.37" + attribute \src "ls180.v:1983.12-1983.37" wire width 8 \builder_csrbank3_width3_w - attribute \src "ls180.v:1983.6-1983.32" + attribute \src "ls180.v:1982.6-1982.32" wire \builder_csrbank3_width3_we - attribute \src "ls180.v:2047.12-2047.40" + attribute \src "ls180.v:2046.12-2046.40" wire width 8 \builder_csrbank4_dma_base0_r - attribute \src "ls180.v:2046.6-2046.35" + attribute \src "ls180.v:2045.6-2045.35" wire \builder_csrbank4_dma_base0_re - attribute \src "ls180.v:2049.12-2049.40" + attribute \src "ls180.v:2048.12-2048.40" wire width 8 \builder_csrbank4_dma_base0_w - attribute \src "ls180.v:2048.6-2048.35" + attribute \src "ls180.v:2047.6-2047.35" wire \builder_csrbank4_dma_base0_we - attribute \src "ls180.v:2043.12-2043.40" + attribute \src "ls180.v:2042.12-2042.40" wire width 8 \builder_csrbank4_dma_base1_r - attribute \src "ls180.v:2042.6-2042.35" + attribute \src "ls180.v:2041.6-2041.35" wire \builder_csrbank4_dma_base1_re - attribute \src "ls180.v:2045.12-2045.40" + attribute \src "ls180.v:2044.12-2044.40" wire width 8 \builder_csrbank4_dma_base1_w - attribute \src "ls180.v:2044.6-2044.35" + attribute \src "ls180.v:2043.6-2043.35" wire \builder_csrbank4_dma_base1_we - attribute \src "ls180.v:2039.12-2039.40" + attribute \src "ls180.v:2038.12-2038.40" wire width 8 \builder_csrbank4_dma_base2_r - attribute \src "ls180.v:2038.6-2038.35" + attribute \src "ls180.v:2037.6-2037.35" wire \builder_csrbank4_dma_base2_re - attribute \src "ls180.v:2041.12-2041.40" + attribute \src "ls180.v:2040.12-2040.40" wire width 8 \builder_csrbank4_dma_base2_w - attribute \src "ls180.v:2040.6-2040.35" + attribute \src "ls180.v:2039.6-2039.35" wire \builder_csrbank4_dma_base2_we - attribute \src "ls180.v:2035.12-2035.40" + attribute \src "ls180.v:2034.12-2034.40" wire width 8 \builder_csrbank4_dma_base3_r - attribute \src "ls180.v:2034.6-2034.35" + attribute \src "ls180.v:2033.6-2033.35" wire \builder_csrbank4_dma_base3_re - attribute \src "ls180.v:2037.12-2037.40" + attribute \src "ls180.v:2036.12-2036.40" wire width 8 \builder_csrbank4_dma_base3_w - attribute \src "ls180.v:2036.6-2036.35" + attribute \src "ls180.v:2035.6-2035.35" wire \builder_csrbank4_dma_base3_we - attribute \src "ls180.v:2031.12-2031.40" + attribute \src "ls180.v:2030.12-2030.40" wire width 8 \builder_csrbank4_dma_base4_r - attribute \src "ls180.v:2030.6-2030.35" + attribute \src "ls180.v:2029.6-2029.35" wire \builder_csrbank4_dma_base4_re - attribute \src "ls180.v:2033.12-2033.40" + attribute \src "ls180.v:2032.12-2032.40" wire width 8 \builder_csrbank4_dma_base4_w - attribute \src "ls180.v:2032.6-2032.35" + attribute \src "ls180.v:2031.6-2031.35" wire \builder_csrbank4_dma_base4_we - attribute \src "ls180.v:2027.12-2027.40" + attribute \src "ls180.v:2026.12-2026.40" wire width 8 \builder_csrbank4_dma_base5_r - attribute \src "ls180.v:2026.6-2026.35" + attribute \src "ls180.v:2025.6-2025.35" wire \builder_csrbank4_dma_base5_re - attribute \src "ls180.v:2029.12-2029.40" + attribute \src "ls180.v:2028.12-2028.40" wire width 8 \builder_csrbank4_dma_base5_w - attribute \src "ls180.v:2028.6-2028.35" + attribute \src "ls180.v:2027.6-2027.35" wire \builder_csrbank4_dma_base5_we - attribute \src "ls180.v:2023.12-2023.40" + attribute \src "ls180.v:2022.12-2022.40" wire width 8 \builder_csrbank4_dma_base6_r - attribute \src "ls180.v:2022.6-2022.35" + attribute \src "ls180.v:2021.6-2021.35" wire \builder_csrbank4_dma_base6_re - attribute \src "ls180.v:2025.12-2025.40" + attribute \src "ls180.v:2024.12-2024.40" wire width 8 \builder_csrbank4_dma_base6_w - attribute \src "ls180.v:2024.6-2024.35" + attribute \src "ls180.v:2023.6-2023.35" wire \builder_csrbank4_dma_base6_we - attribute \src "ls180.v:2019.12-2019.40" + attribute \src "ls180.v:2018.12-2018.40" wire width 8 \builder_csrbank4_dma_base7_r - attribute \src "ls180.v:2018.6-2018.35" + attribute \src "ls180.v:2017.6-2017.35" wire \builder_csrbank4_dma_base7_re - attribute \src "ls180.v:2021.12-2021.40" + attribute \src "ls180.v:2020.12-2020.40" wire width 8 \builder_csrbank4_dma_base7_w - attribute \src "ls180.v:2020.6-2020.35" + attribute \src "ls180.v:2019.6-2019.35" wire \builder_csrbank4_dma_base7_we - attribute \src "ls180.v:2071.6-2071.33" + attribute \src "ls180.v:2070.6-2070.33" wire \builder_csrbank4_dma_done_r - attribute \src "ls180.v:2070.6-2070.34" + attribute \src "ls180.v:2069.6-2069.34" wire \builder_csrbank4_dma_done_re - attribute \src "ls180.v:2073.6-2073.33" + attribute \src "ls180.v:2072.6-2072.33" wire \builder_csrbank4_dma_done_w - attribute \src "ls180.v:2072.6-2072.34" + attribute \src "ls180.v:2071.6-2071.34" wire \builder_csrbank4_dma_done_we - attribute \src "ls180.v:2067.6-2067.36" + attribute \src "ls180.v:2066.6-2066.36" wire \builder_csrbank4_dma_enable0_r - attribute \src "ls180.v:2066.6-2066.37" + attribute \src "ls180.v:2065.6-2065.37" wire \builder_csrbank4_dma_enable0_re - attribute \src "ls180.v:2069.6-2069.36" + attribute \src "ls180.v:2068.6-2068.36" wire \builder_csrbank4_dma_enable0_w - attribute \src "ls180.v:2068.6-2068.37" + attribute \src "ls180.v:2067.6-2067.37" wire \builder_csrbank4_dma_enable0_we - attribute \src "ls180.v:2063.12-2063.42" + attribute \src "ls180.v:2062.12-2062.42" wire width 8 \builder_csrbank4_dma_length0_r - attribute \src "ls180.v:2062.6-2062.37" + attribute \src "ls180.v:2061.6-2061.37" wire \builder_csrbank4_dma_length0_re - attribute \src "ls180.v:2065.12-2065.42" + attribute \src "ls180.v:2064.12-2064.42" wire width 8 \builder_csrbank4_dma_length0_w - attribute \src "ls180.v:2064.6-2064.37" + attribute \src "ls180.v:2063.6-2063.37" wire \builder_csrbank4_dma_length0_we - attribute \src "ls180.v:2059.12-2059.42" + attribute \src "ls180.v:2058.12-2058.42" wire width 8 \builder_csrbank4_dma_length1_r - attribute \src "ls180.v:2058.6-2058.37" + attribute \src "ls180.v:2057.6-2057.37" wire \builder_csrbank4_dma_length1_re - attribute \src "ls180.v:2061.12-2061.42" + attribute \src "ls180.v:2060.12-2060.42" wire width 8 \builder_csrbank4_dma_length1_w - attribute \src "ls180.v:2060.6-2060.37" + attribute \src "ls180.v:2059.6-2059.37" wire \builder_csrbank4_dma_length1_we - attribute \src "ls180.v:2055.12-2055.42" + attribute \src "ls180.v:2054.12-2054.42" wire width 8 \builder_csrbank4_dma_length2_r - attribute \src "ls180.v:2054.6-2054.37" + attribute \src "ls180.v:2053.6-2053.37" wire \builder_csrbank4_dma_length2_re - attribute \src "ls180.v:2057.12-2057.42" + attribute \src "ls180.v:2056.12-2056.42" wire width 8 \builder_csrbank4_dma_length2_w - attribute \src "ls180.v:2056.6-2056.37" + attribute \src "ls180.v:2055.6-2055.37" wire \builder_csrbank4_dma_length2_we - attribute \src "ls180.v:2051.12-2051.42" + attribute \src "ls180.v:2050.12-2050.42" wire width 8 \builder_csrbank4_dma_length3_r - attribute \src "ls180.v:2050.6-2050.37" + attribute \src "ls180.v:2049.6-2049.37" wire \builder_csrbank4_dma_length3_re - attribute \src "ls180.v:2053.12-2053.42" + attribute \src "ls180.v:2052.12-2052.42" wire width 8 \builder_csrbank4_dma_length3_w - attribute \src "ls180.v:2052.6-2052.37" + attribute \src "ls180.v:2051.6-2051.37" wire \builder_csrbank4_dma_length3_we - attribute \src "ls180.v:2075.6-2075.34" + attribute \src "ls180.v:2074.6-2074.34" wire \builder_csrbank4_dma_loop0_r - attribute \src "ls180.v:2074.6-2074.35" + attribute \src "ls180.v:2073.6-2073.35" wire \builder_csrbank4_dma_loop0_re - attribute \src "ls180.v:2077.6-2077.34" + attribute \src "ls180.v:2076.6-2076.34" wire \builder_csrbank4_dma_loop0_w - attribute \src "ls180.v:2076.6-2076.35" + attribute \src "ls180.v:2075.6-2075.35" wire \builder_csrbank4_dma_loop0_we - attribute \src "ls180.v:2078.6-2078.26" + attribute \src "ls180.v:2077.6-2077.26" wire \builder_csrbank4_sel - attribute \src "ls180.v:2208.12-2208.43" + attribute \src "ls180.v:2207.12-2207.43" wire width 8 \builder_csrbank5_block_count0_r - attribute \src "ls180.v:2207.6-2207.38" + attribute \src "ls180.v:2206.6-2206.38" wire \builder_csrbank5_block_count0_re - attribute \src "ls180.v:2210.12-2210.43" + attribute \src "ls180.v:2209.12-2209.43" wire width 8 \builder_csrbank5_block_count0_w - attribute \src "ls180.v:2209.6-2209.38" + attribute \src "ls180.v:2208.6-2208.38" wire \builder_csrbank5_block_count0_we - attribute \src "ls180.v:2204.12-2204.43" + attribute \src "ls180.v:2203.12-2203.43" wire width 8 \builder_csrbank5_block_count1_r - attribute \src "ls180.v:2203.6-2203.38" + attribute \src "ls180.v:2202.6-2202.38" wire \builder_csrbank5_block_count1_re - attribute \src "ls180.v:2206.12-2206.43" + attribute \src "ls180.v:2205.12-2205.43" wire width 8 \builder_csrbank5_block_count1_w - attribute \src "ls180.v:2205.6-2205.38" + attribute \src "ls180.v:2204.6-2204.38" wire \builder_csrbank5_block_count1_we - attribute \src "ls180.v:2200.12-2200.43" + attribute \src "ls180.v:2199.12-2199.43" wire width 8 \builder_csrbank5_block_count2_r - attribute \src "ls180.v:2199.6-2199.38" + attribute \src "ls180.v:2198.6-2198.38" wire \builder_csrbank5_block_count2_re - attribute \src "ls180.v:2202.12-2202.43" + attribute \src "ls180.v:2201.12-2201.43" wire width 8 \builder_csrbank5_block_count2_w - attribute \src "ls180.v:2201.6-2201.38" + attribute \src "ls180.v:2200.6-2200.38" wire \builder_csrbank5_block_count2_we - attribute \src "ls180.v:2196.12-2196.43" + attribute \src "ls180.v:2195.12-2195.43" wire width 8 \builder_csrbank5_block_count3_r - attribute \src "ls180.v:2195.6-2195.38" + attribute \src "ls180.v:2194.6-2194.38" wire \builder_csrbank5_block_count3_re - attribute \src "ls180.v:2198.12-2198.43" + attribute \src "ls180.v:2197.12-2197.43" wire width 8 \builder_csrbank5_block_count3_w - attribute \src "ls180.v:2197.6-2197.38" + attribute \src "ls180.v:2196.6-2196.38" wire \builder_csrbank5_block_count3_we - attribute \src "ls180.v:2192.12-2192.44" + attribute \src "ls180.v:2191.12-2191.44" wire width 8 \builder_csrbank5_block_length0_r - attribute \src "ls180.v:2191.6-2191.39" + attribute \src "ls180.v:2190.6-2190.39" wire \builder_csrbank5_block_length0_re - attribute \src "ls180.v:2194.12-2194.44" + attribute \src "ls180.v:2193.12-2193.44" wire width 8 \builder_csrbank5_block_length0_w - attribute \src "ls180.v:2193.6-2193.39" + attribute \src "ls180.v:2192.6-2192.39" wire \builder_csrbank5_block_length0_we - attribute \src "ls180.v:2188.12-2188.44" + attribute \src "ls180.v:2187.12-2187.44" wire width 2 \builder_csrbank5_block_length1_r - attribute \src "ls180.v:2187.6-2187.39" + attribute \src "ls180.v:2186.6-2186.39" wire \builder_csrbank5_block_length1_re - attribute \src "ls180.v:2190.12-2190.44" + attribute \src "ls180.v:2189.12-2189.44" wire width 2 \builder_csrbank5_block_length1_w - attribute \src "ls180.v:2189.6-2189.39" + attribute \src "ls180.v:2188.6-2188.39" wire \builder_csrbank5_block_length1_we - attribute \src "ls180.v:2096.12-2096.44" + attribute \src "ls180.v:2095.12-2095.44" wire width 8 \builder_csrbank5_cmd_argument0_r - attribute \src "ls180.v:2095.6-2095.39" + attribute \src "ls180.v:2094.6-2094.39" wire \builder_csrbank5_cmd_argument0_re - attribute \src "ls180.v:2098.12-2098.44" + attribute \src "ls180.v:2097.12-2097.44" wire width 8 \builder_csrbank5_cmd_argument0_w - attribute \src "ls180.v:2097.6-2097.39" + attribute \src "ls180.v:2096.6-2096.39" wire \builder_csrbank5_cmd_argument0_we - attribute \src "ls180.v:2092.12-2092.44" + attribute \src "ls180.v:2091.12-2091.44" wire width 8 \builder_csrbank5_cmd_argument1_r - attribute \src "ls180.v:2091.6-2091.39" + attribute \src "ls180.v:2090.6-2090.39" wire \builder_csrbank5_cmd_argument1_re - attribute \src "ls180.v:2094.12-2094.44" + attribute \src "ls180.v:2093.12-2093.44" wire width 8 \builder_csrbank5_cmd_argument1_w - attribute \src "ls180.v:2093.6-2093.39" + attribute \src "ls180.v:2092.6-2092.39" wire \builder_csrbank5_cmd_argument1_we - attribute \src "ls180.v:2088.12-2088.44" + attribute \src "ls180.v:2087.12-2087.44" wire width 8 \builder_csrbank5_cmd_argument2_r - attribute \src "ls180.v:2087.6-2087.39" + attribute \src "ls180.v:2086.6-2086.39" wire \builder_csrbank5_cmd_argument2_re - attribute \src "ls180.v:2090.12-2090.44" + attribute \src "ls180.v:2089.12-2089.44" wire width 8 \builder_csrbank5_cmd_argument2_w - attribute \src "ls180.v:2089.6-2089.39" + attribute \src "ls180.v:2088.6-2088.39" wire \builder_csrbank5_cmd_argument2_we - attribute \src "ls180.v:2084.12-2084.44" + attribute \src "ls180.v:2083.12-2083.44" wire width 8 \builder_csrbank5_cmd_argument3_r - attribute \src "ls180.v:2083.6-2083.39" + attribute \src "ls180.v:2082.6-2082.39" wire \builder_csrbank5_cmd_argument3_re - attribute \src "ls180.v:2086.12-2086.44" + attribute \src "ls180.v:2085.12-2085.44" wire width 8 \builder_csrbank5_cmd_argument3_w - attribute \src "ls180.v:2085.6-2085.39" + attribute \src "ls180.v:2084.6-2084.39" wire \builder_csrbank5_cmd_argument3_we - attribute \src "ls180.v:2112.12-2112.43" + attribute \src "ls180.v:2111.12-2111.43" wire width 8 \builder_csrbank5_cmd_command0_r - attribute \src "ls180.v:2111.6-2111.38" + attribute \src "ls180.v:2110.6-2110.38" wire \builder_csrbank5_cmd_command0_re - attribute \src "ls180.v:2114.12-2114.43" + attribute \src "ls180.v:2113.12-2113.43" wire width 8 \builder_csrbank5_cmd_command0_w - attribute \src "ls180.v:2113.6-2113.38" + attribute \src "ls180.v:2112.6-2112.38" wire \builder_csrbank5_cmd_command0_we - attribute \src "ls180.v:2108.12-2108.43" + attribute \src "ls180.v:2107.12-2107.43" wire width 8 \builder_csrbank5_cmd_command1_r - attribute \src "ls180.v:2107.6-2107.38" + attribute \src "ls180.v:2106.6-2106.38" wire \builder_csrbank5_cmd_command1_re - attribute \src "ls180.v:2110.12-2110.43" + attribute \src "ls180.v:2109.12-2109.43" wire width 8 \builder_csrbank5_cmd_command1_w - attribute \src "ls180.v:2109.6-2109.38" + attribute \src "ls180.v:2108.6-2108.38" wire \builder_csrbank5_cmd_command1_we - attribute \src "ls180.v:2104.12-2104.43" + attribute \src "ls180.v:2103.12-2103.43" wire width 8 \builder_csrbank5_cmd_command2_r - attribute \src "ls180.v:2103.6-2103.38" + attribute \src "ls180.v:2102.6-2102.38" wire \builder_csrbank5_cmd_command2_re - attribute \src "ls180.v:2106.12-2106.43" + attribute \src "ls180.v:2105.12-2105.43" wire width 8 \builder_csrbank5_cmd_command2_w - attribute \src "ls180.v:2105.6-2105.38" + attribute \src "ls180.v:2104.6-2104.38" wire \builder_csrbank5_cmd_command2_we - attribute \src "ls180.v:2100.12-2100.43" + attribute \src "ls180.v:2099.12-2099.43" wire width 8 \builder_csrbank5_cmd_command3_r - attribute \src "ls180.v:2099.6-2099.38" + attribute \src "ls180.v:2098.6-2098.38" wire \builder_csrbank5_cmd_command3_re - attribute \src "ls180.v:2102.12-2102.43" + attribute \src "ls180.v:2101.12-2101.43" wire width 8 \builder_csrbank5_cmd_command3_w - attribute \src "ls180.v:2101.6-2101.38" + attribute \src "ls180.v:2100.6-2100.38" wire \builder_csrbank5_cmd_command3_we - attribute \src "ls180.v:2180.12-2180.40" + attribute \src "ls180.v:2179.12-2179.40" wire width 4 \builder_csrbank5_cmd_event_r - attribute \src "ls180.v:2179.6-2179.35" + attribute \src "ls180.v:2178.6-2178.35" wire \builder_csrbank5_cmd_event_re - attribute \src "ls180.v:2182.12-2182.40" + attribute \src "ls180.v:2181.12-2181.40" wire width 4 \builder_csrbank5_cmd_event_w - attribute \src "ls180.v:2181.6-2181.35" + attribute \src "ls180.v:2180.6-2180.35" wire \builder_csrbank5_cmd_event_we - attribute \src "ls180.v:2176.12-2176.44" + attribute \src "ls180.v:2175.12-2175.44" wire width 8 \builder_csrbank5_cmd_response0_r - attribute \src "ls180.v:2175.6-2175.39" + attribute \src "ls180.v:2174.6-2174.39" wire \builder_csrbank5_cmd_response0_re - attribute \src "ls180.v:2178.12-2178.44" + attribute \src "ls180.v:2177.12-2177.44" wire width 8 \builder_csrbank5_cmd_response0_w - attribute \src "ls180.v:2177.6-2177.39" + attribute \src "ls180.v:2176.6-2176.39" wire \builder_csrbank5_cmd_response0_we - attribute \src "ls180.v:2136.12-2136.45" + attribute \src "ls180.v:2135.12-2135.45" wire width 8 \builder_csrbank5_cmd_response10_r - attribute \src "ls180.v:2135.6-2135.40" + attribute \src "ls180.v:2134.6-2134.40" wire \builder_csrbank5_cmd_response10_re - attribute \src "ls180.v:2138.12-2138.45" + attribute \src "ls180.v:2137.12-2137.45" wire width 8 \builder_csrbank5_cmd_response10_w - attribute \src "ls180.v:2137.6-2137.40" + attribute \src "ls180.v:2136.6-2136.40" wire \builder_csrbank5_cmd_response10_we - attribute \src "ls180.v:2132.12-2132.45" + attribute \src "ls180.v:2131.12-2131.45" wire width 8 \builder_csrbank5_cmd_response11_r - attribute \src "ls180.v:2131.6-2131.40" + attribute \src "ls180.v:2130.6-2130.40" wire \builder_csrbank5_cmd_response11_re - attribute \src "ls180.v:2134.12-2134.45" + attribute \src "ls180.v:2133.12-2133.45" wire width 8 \builder_csrbank5_cmd_response11_w - attribute \src "ls180.v:2133.6-2133.40" + attribute \src "ls180.v:2132.6-2132.40" wire \builder_csrbank5_cmd_response11_we - attribute \src "ls180.v:2128.12-2128.45" + attribute \src "ls180.v:2127.12-2127.45" wire width 8 \builder_csrbank5_cmd_response12_r - attribute \src "ls180.v:2127.6-2127.40" + attribute \src "ls180.v:2126.6-2126.40" wire \builder_csrbank5_cmd_response12_re - attribute \src "ls180.v:2130.12-2130.45" + attribute \src "ls180.v:2129.12-2129.45" wire width 8 \builder_csrbank5_cmd_response12_w - attribute \src "ls180.v:2129.6-2129.40" + attribute \src "ls180.v:2128.6-2128.40" wire \builder_csrbank5_cmd_response12_we - attribute \src "ls180.v:2124.12-2124.45" + attribute \src "ls180.v:2123.12-2123.45" wire width 8 \builder_csrbank5_cmd_response13_r - attribute \src "ls180.v:2123.6-2123.40" + attribute \src "ls180.v:2122.6-2122.40" wire \builder_csrbank5_cmd_response13_re - attribute \src "ls180.v:2126.12-2126.45" + attribute \src "ls180.v:2125.12-2125.45" wire width 8 \builder_csrbank5_cmd_response13_w - attribute \src "ls180.v:2125.6-2125.40" + attribute \src "ls180.v:2124.6-2124.40" wire \builder_csrbank5_cmd_response13_we - attribute \src "ls180.v:2120.12-2120.45" + attribute \src "ls180.v:2119.12-2119.45" wire width 8 \builder_csrbank5_cmd_response14_r - attribute \src "ls180.v:2119.6-2119.40" + attribute \src "ls180.v:2118.6-2118.40" wire \builder_csrbank5_cmd_response14_re - attribute \src "ls180.v:2122.12-2122.45" + attribute \src "ls180.v:2121.12-2121.45" wire width 8 \builder_csrbank5_cmd_response14_w - attribute \src "ls180.v:2121.6-2121.40" + attribute \src "ls180.v:2120.6-2120.40" wire \builder_csrbank5_cmd_response14_we - attribute \src "ls180.v:2116.12-2116.45" + attribute \src "ls180.v:2115.12-2115.45" wire width 8 \builder_csrbank5_cmd_response15_r - attribute \src "ls180.v:2115.6-2115.40" + attribute \src "ls180.v:2114.6-2114.40" wire \builder_csrbank5_cmd_response15_re - attribute \src "ls180.v:2118.12-2118.45" + attribute \src "ls180.v:2117.12-2117.45" wire width 8 \builder_csrbank5_cmd_response15_w - attribute \src "ls180.v:2117.6-2117.40" + attribute \src "ls180.v:2116.6-2116.40" wire \builder_csrbank5_cmd_response15_we - attribute \src "ls180.v:2172.12-2172.44" + attribute \src "ls180.v:2171.12-2171.44" wire width 8 \builder_csrbank5_cmd_response1_r - attribute \src "ls180.v:2171.6-2171.39" + attribute \src "ls180.v:2170.6-2170.39" wire \builder_csrbank5_cmd_response1_re - attribute \src "ls180.v:2174.12-2174.44" + attribute \src "ls180.v:2173.12-2173.44" wire width 8 \builder_csrbank5_cmd_response1_w - attribute \src "ls180.v:2173.6-2173.39" + attribute \src "ls180.v:2172.6-2172.39" wire \builder_csrbank5_cmd_response1_we - attribute \src "ls180.v:2168.12-2168.44" + attribute \src "ls180.v:2167.12-2167.44" wire width 8 \builder_csrbank5_cmd_response2_r - attribute \src "ls180.v:2167.6-2167.39" + attribute \src "ls180.v:2166.6-2166.39" wire \builder_csrbank5_cmd_response2_re - attribute \src "ls180.v:2170.12-2170.44" + attribute \src "ls180.v:2169.12-2169.44" wire width 8 \builder_csrbank5_cmd_response2_w - attribute \src "ls180.v:2169.6-2169.39" + attribute \src "ls180.v:2168.6-2168.39" wire \builder_csrbank5_cmd_response2_we - attribute \src "ls180.v:2164.12-2164.44" + attribute \src "ls180.v:2163.12-2163.44" wire width 8 \builder_csrbank5_cmd_response3_r - attribute \src "ls180.v:2163.6-2163.39" + attribute \src "ls180.v:2162.6-2162.39" wire \builder_csrbank5_cmd_response3_re - attribute \src "ls180.v:2166.12-2166.44" + attribute \src "ls180.v:2165.12-2165.44" wire width 8 \builder_csrbank5_cmd_response3_w - attribute \src "ls180.v:2165.6-2165.39" + attribute \src "ls180.v:2164.6-2164.39" wire \builder_csrbank5_cmd_response3_we - attribute \src "ls180.v:2160.12-2160.44" + attribute \src "ls180.v:2159.12-2159.44" wire width 8 \builder_csrbank5_cmd_response4_r - attribute \src "ls180.v:2159.6-2159.39" + attribute \src "ls180.v:2158.6-2158.39" wire \builder_csrbank5_cmd_response4_re - attribute \src "ls180.v:2162.12-2162.44" + attribute \src "ls180.v:2161.12-2161.44" wire width 8 \builder_csrbank5_cmd_response4_w - attribute \src "ls180.v:2161.6-2161.39" + attribute \src "ls180.v:2160.6-2160.39" wire \builder_csrbank5_cmd_response4_we - attribute \src "ls180.v:2156.12-2156.44" + attribute \src "ls180.v:2155.12-2155.44" wire width 8 \builder_csrbank5_cmd_response5_r - attribute \src "ls180.v:2155.6-2155.39" + attribute \src "ls180.v:2154.6-2154.39" wire \builder_csrbank5_cmd_response5_re - attribute \src "ls180.v:2158.12-2158.44" + attribute \src "ls180.v:2157.12-2157.44" wire width 8 \builder_csrbank5_cmd_response5_w - attribute \src "ls180.v:2157.6-2157.39" + attribute \src "ls180.v:2156.6-2156.39" wire \builder_csrbank5_cmd_response5_we - attribute \src "ls180.v:2152.12-2152.44" + attribute \src "ls180.v:2151.12-2151.44" wire width 8 \builder_csrbank5_cmd_response6_r - attribute \src "ls180.v:2151.6-2151.39" + attribute \src "ls180.v:2150.6-2150.39" wire \builder_csrbank5_cmd_response6_re - attribute \src "ls180.v:2154.12-2154.44" + attribute \src "ls180.v:2153.12-2153.44" wire width 8 \builder_csrbank5_cmd_response6_w - attribute \src "ls180.v:2153.6-2153.39" + attribute \src "ls180.v:2152.6-2152.39" wire \builder_csrbank5_cmd_response6_we - attribute \src "ls180.v:2148.12-2148.44" + attribute \src "ls180.v:2147.12-2147.44" wire width 8 \builder_csrbank5_cmd_response7_r - attribute \src "ls180.v:2147.6-2147.39" + attribute \src "ls180.v:2146.6-2146.39" wire \builder_csrbank5_cmd_response7_re - attribute \src "ls180.v:2150.12-2150.44" + attribute \src "ls180.v:2149.12-2149.44" wire width 8 \builder_csrbank5_cmd_response7_w - attribute \src "ls180.v:2149.6-2149.39" + attribute \src "ls180.v:2148.6-2148.39" wire \builder_csrbank5_cmd_response7_we - attribute \src "ls180.v:2144.12-2144.44" + attribute \src "ls180.v:2143.12-2143.44" wire width 8 \builder_csrbank5_cmd_response8_r - attribute \src "ls180.v:2143.6-2143.39" + attribute \src "ls180.v:2142.6-2142.39" wire \builder_csrbank5_cmd_response8_re - attribute \src "ls180.v:2146.12-2146.44" + attribute \src "ls180.v:2145.12-2145.44" wire width 8 \builder_csrbank5_cmd_response8_w - attribute \src "ls180.v:2145.6-2145.39" + attribute \src "ls180.v:2144.6-2144.39" wire \builder_csrbank5_cmd_response8_we - attribute \src "ls180.v:2140.12-2140.44" + attribute \src "ls180.v:2139.12-2139.44" wire width 8 \builder_csrbank5_cmd_response9_r - attribute \src "ls180.v:2139.6-2139.39" + attribute \src "ls180.v:2138.6-2138.39" wire \builder_csrbank5_cmd_response9_re - attribute \src "ls180.v:2142.12-2142.44" + attribute \src "ls180.v:2141.12-2141.44" wire width 8 \builder_csrbank5_cmd_response9_w - attribute \src "ls180.v:2141.6-2141.39" + attribute \src "ls180.v:2140.6-2140.39" wire \builder_csrbank5_cmd_response9_we - attribute \src "ls180.v:2184.12-2184.41" + attribute \src "ls180.v:2183.12-2183.41" wire width 4 \builder_csrbank5_data_event_r - attribute \src "ls180.v:2183.6-2183.36" + attribute \src "ls180.v:2182.6-2182.36" wire \builder_csrbank5_data_event_re - attribute \src "ls180.v:2186.12-2186.41" + attribute \src "ls180.v:2185.12-2185.41" wire width 4 \builder_csrbank5_data_event_w - attribute \src "ls180.v:2185.6-2185.36" + attribute \src "ls180.v:2184.6-2184.36" wire \builder_csrbank5_data_event_we - attribute \src "ls180.v:2211.6-2211.26" + attribute \src "ls180.v:2210.6-2210.26" wire \builder_csrbank5_sel - attribute \src "ls180.v:2245.12-2245.40" + attribute \src "ls180.v:2244.12-2244.40" wire width 8 \builder_csrbank6_dma_base0_r - attribute \src "ls180.v:2244.6-2244.35" + attribute \src "ls180.v:2243.6-2243.35" wire \builder_csrbank6_dma_base0_re - attribute \src "ls180.v:2247.12-2247.40" + attribute \src "ls180.v:2246.12-2246.40" wire width 8 \builder_csrbank6_dma_base0_w - attribute \src "ls180.v:2246.6-2246.35" + attribute \src "ls180.v:2245.6-2245.35" wire \builder_csrbank6_dma_base0_we - attribute \src "ls180.v:2241.12-2241.40" + attribute \src "ls180.v:2240.12-2240.40" wire width 8 \builder_csrbank6_dma_base1_r - attribute \src "ls180.v:2240.6-2240.35" + attribute \src "ls180.v:2239.6-2239.35" wire \builder_csrbank6_dma_base1_re - attribute \src "ls180.v:2243.12-2243.40" + attribute \src "ls180.v:2242.12-2242.40" wire width 8 \builder_csrbank6_dma_base1_w - attribute \src "ls180.v:2242.6-2242.35" + attribute \src "ls180.v:2241.6-2241.35" wire \builder_csrbank6_dma_base1_we - attribute \src "ls180.v:2237.12-2237.40" + attribute \src "ls180.v:2236.12-2236.40" wire width 8 \builder_csrbank6_dma_base2_r - attribute \src "ls180.v:2236.6-2236.35" + attribute \src "ls180.v:2235.6-2235.35" wire \builder_csrbank6_dma_base2_re - attribute \src "ls180.v:2239.12-2239.40" + attribute \src "ls180.v:2238.12-2238.40" wire width 8 \builder_csrbank6_dma_base2_w - attribute \src "ls180.v:2238.6-2238.35" + attribute \src "ls180.v:2237.6-2237.35" wire \builder_csrbank6_dma_base2_we - attribute \src "ls180.v:2233.12-2233.40" + attribute \src "ls180.v:2232.12-2232.40" wire width 8 \builder_csrbank6_dma_base3_r - attribute \src "ls180.v:2232.6-2232.35" + attribute \src "ls180.v:2231.6-2231.35" wire \builder_csrbank6_dma_base3_re - attribute \src "ls180.v:2235.12-2235.40" + attribute \src "ls180.v:2234.12-2234.40" wire width 8 \builder_csrbank6_dma_base3_w - attribute \src "ls180.v:2234.6-2234.35" + attribute \src "ls180.v:2233.6-2233.35" wire \builder_csrbank6_dma_base3_we - attribute \src "ls180.v:2229.12-2229.40" + attribute \src "ls180.v:2228.12-2228.40" wire width 8 \builder_csrbank6_dma_base4_r - attribute \src "ls180.v:2228.6-2228.35" + attribute \src "ls180.v:2227.6-2227.35" wire \builder_csrbank6_dma_base4_re - attribute \src "ls180.v:2231.12-2231.40" + attribute \src "ls180.v:2230.12-2230.40" wire width 8 \builder_csrbank6_dma_base4_w - attribute \src "ls180.v:2230.6-2230.35" + attribute \src "ls180.v:2229.6-2229.35" wire \builder_csrbank6_dma_base4_we - attribute \src "ls180.v:2225.12-2225.40" + attribute \src "ls180.v:2224.12-2224.40" wire width 8 \builder_csrbank6_dma_base5_r - attribute \src "ls180.v:2224.6-2224.35" + attribute \src "ls180.v:2223.6-2223.35" wire \builder_csrbank6_dma_base5_re - attribute \src "ls180.v:2227.12-2227.40" + attribute \src "ls180.v:2226.12-2226.40" wire width 8 \builder_csrbank6_dma_base5_w - attribute \src "ls180.v:2226.6-2226.35" + attribute \src "ls180.v:2225.6-2225.35" wire \builder_csrbank6_dma_base5_we - attribute \src "ls180.v:2221.12-2221.40" + attribute \src "ls180.v:2220.12-2220.40" wire width 8 \builder_csrbank6_dma_base6_r - attribute \src "ls180.v:2220.6-2220.35" + attribute \src "ls180.v:2219.6-2219.35" wire \builder_csrbank6_dma_base6_re - attribute \src "ls180.v:2223.12-2223.40" + attribute \src "ls180.v:2222.12-2222.40" wire width 8 \builder_csrbank6_dma_base6_w - attribute \src "ls180.v:2222.6-2222.35" + attribute \src "ls180.v:2221.6-2221.35" wire \builder_csrbank6_dma_base6_we - attribute \src "ls180.v:2217.12-2217.40" + attribute \src "ls180.v:2216.12-2216.40" wire width 8 \builder_csrbank6_dma_base7_r - attribute \src "ls180.v:2216.6-2216.35" + attribute \src "ls180.v:2215.6-2215.35" wire \builder_csrbank6_dma_base7_re - attribute \src "ls180.v:2219.12-2219.40" + attribute \src "ls180.v:2218.12-2218.40" wire width 8 \builder_csrbank6_dma_base7_w - attribute \src "ls180.v:2218.6-2218.35" + attribute \src "ls180.v:2217.6-2217.35" wire \builder_csrbank6_dma_base7_we - attribute \src "ls180.v:2269.6-2269.33" + attribute \src "ls180.v:2268.6-2268.33" wire \builder_csrbank6_dma_done_r - attribute \src "ls180.v:2268.6-2268.34" + attribute \src "ls180.v:2267.6-2267.34" wire \builder_csrbank6_dma_done_re - attribute \src "ls180.v:2271.6-2271.33" + attribute \src "ls180.v:2270.6-2270.33" wire \builder_csrbank6_dma_done_w - attribute \src "ls180.v:2270.6-2270.34" + attribute \src "ls180.v:2269.6-2269.34" wire \builder_csrbank6_dma_done_we - attribute \src "ls180.v:2265.6-2265.36" + attribute \src "ls180.v:2264.6-2264.36" wire \builder_csrbank6_dma_enable0_r - attribute \src "ls180.v:2264.6-2264.37" + attribute \src "ls180.v:2263.6-2263.37" wire \builder_csrbank6_dma_enable0_re - attribute \src "ls180.v:2267.6-2267.36" + attribute \src "ls180.v:2266.6-2266.36" wire \builder_csrbank6_dma_enable0_w - attribute \src "ls180.v:2266.6-2266.37" + attribute \src "ls180.v:2265.6-2265.37" wire \builder_csrbank6_dma_enable0_we - attribute \src "ls180.v:2261.12-2261.42" + attribute \src "ls180.v:2260.12-2260.42" wire width 8 \builder_csrbank6_dma_length0_r - attribute \src "ls180.v:2260.6-2260.37" + attribute \src "ls180.v:2259.6-2259.37" wire \builder_csrbank6_dma_length0_re - attribute \src "ls180.v:2263.12-2263.42" + attribute \src "ls180.v:2262.12-2262.42" wire width 8 \builder_csrbank6_dma_length0_w - attribute \src "ls180.v:2262.6-2262.37" + attribute \src "ls180.v:2261.6-2261.37" wire \builder_csrbank6_dma_length0_we - attribute \src "ls180.v:2257.12-2257.42" + attribute \src "ls180.v:2256.12-2256.42" wire width 8 \builder_csrbank6_dma_length1_r - attribute \src "ls180.v:2256.6-2256.37" + attribute \src "ls180.v:2255.6-2255.37" wire \builder_csrbank6_dma_length1_re - attribute \src "ls180.v:2259.12-2259.42" + attribute \src "ls180.v:2258.12-2258.42" wire width 8 \builder_csrbank6_dma_length1_w - attribute \src "ls180.v:2258.6-2258.37" + attribute \src "ls180.v:2257.6-2257.37" wire \builder_csrbank6_dma_length1_we - attribute \src "ls180.v:2253.12-2253.42" + attribute \src "ls180.v:2252.12-2252.42" wire width 8 \builder_csrbank6_dma_length2_r - attribute \src "ls180.v:2252.6-2252.37" + attribute \src "ls180.v:2251.6-2251.37" wire \builder_csrbank6_dma_length2_re - attribute \src "ls180.v:2255.12-2255.42" + attribute \src "ls180.v:2254.12-2254.42" wire width 8 \builder_csrbank6_dma_length2_w - attribute \src "ls180.v:2254.6-2254.37" + attribute \src "ls180.v:2253.6-2253.37" wire \builder_csrbank6_dma_length2_we - attribute \src "ls180.v:2249.12-2249.42" + attribute \src "ls180.v:2248.12-2248.42" wire width 8 \builder_csrbank6_dma_length3_r - attribute \src "ls180.v:2248.6-2248.37" + attribute \src "ls180.v:2247.6-2247.37" wire \builder_csrbank6_dma_length3_re - attribute \src "ls180.v:2251.12-2251.42" + attribute \src "ls180.v:2250.12-2250.42" wire width 8 \builder_csrbank6_dma_length3_w - attribute \src "ls180.v:2250.6-2250.37" + attribute \src "ls180.v:2249.6-2249.37" wire \builder_csrbank6_dma_length3_we - attribute \src "ls180.v:2273.6-2273.34" + attribute \src "ls180.v:2272.6-2272.34" wire \builder_csrbank6_dma_loop0_r - attribute \src "ls180.v:2272.6-2272.35" + attribute \src "ls180.v:2271.6-2271.35" wire \builder_csrbank6_dma_loop0_re - attribute \src "ls180.v:2275.6-2275.34" + attribute \src "ls180.v:2274.6-2274.34" wire \builder_csrbank6_dma_loop0_w - attribute \src "ls180.v:2274.6-2274.35" + attribute \src "ls180.v:2273.6-2273.35" wire \builder_csrbank6_dma_loop0_we - attribute \src "ls180.v:2289.12-2289.42" + attribute \src "ls180.v:2288.12-2288.42" wire width 8 \builder_csrbank6_dma_offset0_r - attribute \src "ls180.v:2288.6-2288.37" + attribute \src "ls180.v:2287.6-2287.37" wire \builder_csrbank6_dma_offset0_re - attribute \src "ls180.v:2291.12-2291.42" + attribute \src "ls180.v:2290.12-2290.42" wire width 8 \builder_csrbank6_dma_offset0_w - attribute \src "ls180.v:2290.6-2290.37" + attribute \src "ls180.v:2289.6-2289.37" wire \builder_csrbank6_dma_offset0_we - attribute \src "ls180.v:2285.12-2285.42" + attribute \src "ls180.v:2284.12-2284.42" wire width 8 \builder_csrbank6_dma_offset1_r - attribute \src "ls180.v:2284.6-2284.37" + attribute \src "ls180.v:2283.6-2283.37" wire \builder_csrbank6_dma_offset1_re - attribute \src "ls180.v:2287.12-2287.42" + attribute \src "ls180.v:2286.12-2286.42" wire width 8 \builder_csrbank6_dma_offset1_w - attribute \src "ls180.v:2286.6-2286.37" + attribute \src "ls180.v:2285.6-2285.37" wire \builder_csrbank6_dma_offset1_we - attribute \src "ls180.v:2281.12-2281.42" + attribute \src "ls180.v:2280.12-2280.42" wire width 8 \builder_csrbank6_dma_offset2_r - attribute \src "ls180.v:2280.6-2280.37" + attribute \src "ls180.v:2279.6-2279.37" wire \builder_csrbank6_dma_offset2_re - attribute \src "ls180.v:2283.12-2283.42" + attribute \src "ls180.v:2282.12-2282.42" wire width 8 \builder_csrbank6_dma_offset2_w - attribute \src "ls180.v:2282.6-2282.37" + attribute \src "ls180.v:2281.6-2281.37" wire \builder_csrbank6_dma_offset2_we - attribute \src "ls180.v:2277.12-2277.42" + attribute \src "ls180.v:2276.12-2276.42" wire width 8 \builder_csrbank6_dma_offset3_r - attribute \src "ls180.v:2276.6-2276.37" + attribute \src "ls180.v:2275.6-2275.37" wire \builder_csrbank6_dma_offset3_re - attribute \src "ls180.v:2279.12-2279.42" + attribute \src "ls180.v:2278.12-2278.42" wire width 8 \builder_csrbank6_dma_offset3_w - attribute \src "ls180.v:2278.6-2278.37" + attribute \src "ls180.v:2277.6-2277.37" wire \builder_csrbank6_dma_offset3_we - attribute \src "ls180.v:2292.6-2292.26" + attribute \src "ls180.v:2291.6-2291.26" wire \builder_csrbank6_sel - attribute \src "ls180.v:2298.6-2298.36" + attribute \src "ls180.v:2297.6-2297.36" wire \builder_csrbank7_card_detect_r - attribute \src "ls180.v:2297.6-2297.37" + attribute \src "ls180.v:2296.6-2296.37" wire \builder_csrbank7_card_detect_re - attribute \src "ls180.v:2300.6-2300.36" + attribute \src "ls180.v:2299.6-2299.36" wire \builder_csrbank7_card_detect_w - attribute \src "ls180.v:2299.6-2299.37" + attribute \src "ls180.v:2298.6-2298.37" wire \builder_csrbank7_card_detect_we - attribute \src "ls180.v:2306.12-2306.47" + attribute \src "ls180.v:2305.12-2305.47" wire width 8 \builder_csrbank7_clocker_divider0_r - attribute \src "ls180.v:2305.6-2305.42" + attribute \src "ls180.v:2304.6-2304.42" wire \builder_csrbank7_clocker_divider0_re - attribute \src "ls180.v:2308.12-2308.47" + attribute \src "ls180.v:2307.12-2307.47" wire width 8 \builder_csrbank7_clocker_divider0_w - attribute \src "ls180.v:2307.6-2307.42" + attribute \src "ls180.v:2306.6-2306.42" wire \builder_csrbank7_clocker_divider0_we - attribute \src "ls180.v:2302.6-2302.41" + attribute \src "ls180.v:2301.6-2301.41" wire \builder_csrbank7_clocker_divider1_r - attribute \src "ls180.v:2301.6-2301.42" + attribute \src "ls180.v:2300.6-2300.42" wire \builder_csrbank7_clocker_divider1_re - attribute \src "ls180.v:2304.6-2304.41" + attribute \src "ls180.v:2303.6-2303.41" wire \builder_csrbank7_clocker_divider1_w - attribute \src "ls180.v:2303.6-2303.42" + attribute \src "ls180.v:2302.6-2302.42" wire \builder_csrbank7_clocker_divider1_we - attribute \src "ls180.v:2309.6-2309.26" + attribute \src "ls180.v:2308.6-2308.26" wire \builder_csrbank7_sel - attribute \src "ls180.v:2315.12-2315.44" + attribute \src "ls180.v:2314.12-2314.44" wire width 4 \builder_csrbank8_dfii_control0_r - attribute \src "ls180.v:2314.6-2314.39" + attribute \src "ls180.v:2313.6-2313.39" wire \builder_csrbank8_dfii_control0_re - attribute \src "ls180.v:2317.12-2317.44" + attribute \src "ls180.v:2316.12-2316.44" wire width 4 \builder_csrbank8_dfii_control0_w - attribute \src "ls180.v:2316.6-2316.39" + attribute \src "ls180.v:2315.6-2315.39" wire \builder_csrbank8_dfii_control0_we - attribute \src "ls180.v:2327.12-2327.48" + attribute \src "ls180.v:2326.12-2326.48" wire width 8 \builder_csrbank8_dfii_pi0_address0_r - attribute \src "ls180.v:2326.6-2326.43" + attribute \src "ls180.v:2325.6-2325.43" wire \builder_csrbank8_dfii_pi0_address0_re - attribute \src "ls180.v:2329.12-2329.48" + attribute \src "ls180.v:2328.12-2328.48" wire width 8 \builder_csrbank8_dfii_pi0_address0_w - attribute \src "ls180.v:2328.6-2328.43" + attribute \src "ls180.v:2327.6-2327.43" wire \builder_csrbank8_dfii_pi0_address0_we - attribute \src "ls180.v:2323.12-2323.48" + attribute \src "ls180.v:2322.12-2322.48" wire width 5 \builder_csrbank8_dfii_pi0_address1_r - attribute \src "ls180.v:2322.6-2322.43" + attribute \src "ls180.v:2321.6-2321.43" wire \builder_csrbank8_dfii_pi0_address1_re - attribute \src "ls180.v:2325.12-2325.48" + attribute \src "ls180.v:2324.12-2324.48" wire width 5 \builder_csrbank8_dfii_pi0_address1_w - attribute \src "ls180.v:2324.6-2324.43" + attribute \src "ls180.v:2323.6-2323.43" wire \builder_csrbank8_dfii_pi0_address1_we - attribute \src "ls180.v:2331.12-2331.49" + attribute \src "ls180.v:2330.12-2330.49" wire width 2 \builder_csrbank8_dfii_pi0_baddress0_r - attribute \src "ls180.v:2330.6-2330.44" + attribute \src "ls180.v:2329.6-2329.44" wire \builder_csrbank8_dfii_pi0_baddress0_re - attribute \src "ls180.v:2333.12-2333.49" + attribute \src "ls180.v:2332.12-2332.49" wire width 2 \builder_csrbank8_dfii_pi0_baddress0_w - attribute \src "ls180.v:2332.6-2332.44" + attribute \src "ls180.v:2331.6-2331.44" wire \builder_csrbank8_dfii_pi0_baddress0_we - attribute \src "ls180.v:2319.12-2319.48" + attribute \src "ls180.v:2318.12-2318.48" wire width 6 \builder_csrbank8_dfii_pi0_command0_r - attribute \src "ls180.v:2318.6-2318.43" + attribute \src "ls180.v:2317.6-2317.43" wire \builder_csrbank8_dfii_pi0_command0_re - attribute \src "ls180.v:2321.12-2321.48" + attribute \src "ls180.v:2320.12-2320.48" wire width 6 \builder_csrbank8_dfii_pi0_command0_w - attribute \src "ls180.v:2320.6-2320.43" + attribute \src "ls180.v:2319.6-2319.43" wire \builder_csrbank8_dfii_pi0_command0_we - attribute \src "ls180.v:2347.12-2347.47" + attribute \src "ls180.v:2346.12-2346.47" wire width 8 \builder_csrbank8_dfii_pi0_rddata0_r - attribute \src "ls180.v:2346.6-2346.42" + attribute \src "ls180.v:2345.6-2345.42" wire \builder_csrbank8_dfii_pi0_rddata0_re - attribute \src "ls180.v:2349.12-2349.47" + attribute \src "ls180.v:2348.12-2348.47" wire width 8 \builder_csrbank8_dfii_pi0_rddata0_w - attribute \src "ls180.v:2348.6-2348.42" + attribute \src "ls180.v:2347.6-2347.42" wire \builder_csrbank8_dfii_pi0_rddata0_we - attribute \src "ls180.v:2343.12-2343.47" + attribute \src "ls180.v:2342.12-2342.47" wire width 8 \builder_csrbank8_dfii_pi0_rddata1_r - attribute \src "ls180.v:2342.6-2342.42" + attribute \src "ls180.v:2341.6-2341.42" wire \builder_csrbank8_dfii_pi0_rddata1_re - attribute \src "ls180.v:2345.12-2345.47" + attribute \src "ls180.v:2344.12-2344.47" wire width 8 \builder_csrbank8_dfii_pi0_rddata1_w - attribute \src "ls180.v:2344.6-2344.42" + attribute \src "ls180.v:2343.6-2343.42" wire \builder_csrbank8_dfii_pi0_rddata1_we - attribute \src "ls180.v:2339.12-2339.47" + attribute \src "ls180.v:2338.12-2338.47" wire width 8 \builder_csrbank8_dfii_pi0_wrdata0_r - attribute \src "ls180.v:2338.6-2338.42" + attribute \src "ls180.v:2337.6-2337.42" wire \builder_csrbank8_dfii_pi0_wrdata0_re - attribute \src "ls180.v:2341.12-2341.47" + attribute \src "ls180.v:2340.12-2340.47" wire width 8 \builder_csrbank8_dfii_pi0_wrdata0_w - attribute \src "ls180.v:2340.6-2340.42" + attribute \src "ls180.v:2339.6-2339.42" wire \builder_csrbank8_dfii_pi0_wrdata0_we - attribute \src "ls180.v:2335.12-2335.47" + attribute \src "ls180.v:2334.12-2334.47" wire width 8 \builder_csrbank8_dfii_pi0_wrdata1_r - attribute \src "ls180.v:2334.6-2334.42" + attribute \src "ls180.v:2333.6-2333.42" wire \builder_csrbank8_dfii_pi0_wrdata1_re - attribute \src "ls180.v:2337.12-2337.47" + attribute \src "ls180.v:2336.12-2336.47" wire width 8 \builder_csrbank8_dfii_pi0_wrdata1_w - attribute \src "ls180.v:2336.6-2336.42" + attribute \src "ls180.v:2335.6-2335.42" wire \builder_csrbank8_dfii_pi0_wrdata1_we - attribute \src "ls180.v:2350.6-2350.26" + attribute \src "ls180.v:2349.6-2349.26" wire \builder_csrbank8_sel - attribute \src "ls180.v:2360.12-2360.39" + attribute \src "ls180.v:2359.12-2359.39" wire width 8 \builder_csrbank9_control0_r - attribute \src "ls180.v:2359.6-2359.34" + attribute \src "ls180.v:2358.6-2358.34" wire \builder_csrbank9_control0_re - attribute \src "ls180.v:2362.12-2362.39" + attribute \src "ls180.v:2361.12-2361.39" wire width 8 \builder_csrbank9_control0_w - attribute \src "ls180.v:2361.6-2361.34" + attribute \src "ls180.v:2360.6-2360.34" wire \builder_csrbank9_control0_we - attribute \src "ls180.v:2356.12-2356.39" + attribute \src "ls180.v:2355.12-2355.39" wire width 8 \builder_csrbank9_control1_r - attribute \src "ls180.v:2355.6-2355.34" + attribute \src "ls180.v:2354.6-2354.34" wire \builder_csrbank9_control1_re - attribute \src "ls180.v:2358.12-2358.39" + attribute \src "ls180.v:2357.12-2357.39" wire width 8 \builder_csrbank9_control1_w - attribute \src "ls180.v:2357.6-2357.34" + attribute \src "ls180.v:2356.6-2356.34" wire \builder_csrbank9_control1_we - attribute \src "ls180.v:2376.6-2376.28" + attribute \src "ls180.v:2375.6-2375.28" wire \builder_csrbank9_cs0_r - attribute \src "ls180.v:2375.6-2375.29" + attribute \src "ls180.v:2374.6-2374.29" wire \builder_csrbank9_cs0_re - attribute \src "ls180.v:2378.6-2378.28" + attribute \src "ls180.v:2377.6-2377.28" wire \builder_csrbank9_cs0_w - attribute \src "ls180.v:2377.6-2377.29" + attribute \src "ls180.v:2376.6-2376.29" wire \builder_csrbank9_cs0_we - attribute \src "ls180.v:2380.6-2380.34" + attribute \src "ls180.v:2379.6-2379.34" wire \builder_csrbank9_loopback0_r - attribute \src "ls180.v:2379.6-2379.35" + attribute \src "ls180.v:2378.6-2378.35" wire \builder_csrbank9_loopback0_re - attribute \src "ls180.v:2382.6-2382.34" + attribute \src "ls180.v:2381.6-2381.34" wire \builder_csrbank9_loopback0_w - attribute \src "ls180.v:2381.6-2381.35" + attribute \src "ls180.v:2380.6-2380.35" wire \builder_csrbank9_loopback0_we - attribute \src "ls180.v:2372.12-2372.35" + attribute \src "ls180.v:2371.12-2371.35" wire width 8 \builder_csrbank9_miso_r - attribute \src "ls180.v:2371.6-2371.30" + attribute \src "ls180.v:2370.6-2370.30" wire \builder_csrbank9_miso_re - attribute \src "ls180.v:2374.12-2374.35" + attribute \src "ls180.v:2373.12-2373.35" wire width 8 \builder_csrbank9_miso_w - attribute \src "ls180.v:2373.6-2373.30" + attribute \src "ls180.v:2372.6-2372.30" wire \builder_csrbank9_miso_we - attribute \src "ls180.v:2368.12-2368.36" + attribute \src "ls180.v:2367.12-2367.36" wire width 8 \builder_csrbank9_mosi0_r - attribute \src "ls180.v:2367.6-2367.31" + attribute \src "ls180.v:2366.6-2366.31" wire \builder_csrbank9_mosi0_re - attribute \src "ls180.v:2370.12-2370.36" + attribute \src "ls180.v:2369.12-2369.36" wire width 8 \builder_csrbank9_mosi0_w - attribute \src "ls180.v:2369.6-2369.31" + attribute \src "ls180.v:2368.6-2368.31" wire \builder_csrbank9_mosi0_we - attribute \src "ls180.v:2383.6-2383.26" + attribute \src "ls180.v:2382.6-2382.26" wire \builder_csrbank9_sel - attribute \src "ls180.v:2364.6-2364.31" + attribute \src "ls180.v:2363.6-2363.31" wire \builder_csrbank9_status_r - attribute \src "ls180.v:2363.6-2363.32" + attribute \src "ls180.v:2362.6-2362.32" wire \builder_csrbank9_status_re - attribute \src "ls180.v:2366.6-2366.31" + attribute \src "ls180.v:2365.6-2365.31" wire \builder_csrbank9_status_w - attribute \src "ls180.v:2365.6-2365.32" + attribute \src "ls180.v:2364.6-2364.32" wire \builder_csrbank9_status_we - attribute \src "ls180.v:1860.6-1860.18" + attribute \src "ls180.v:1859.6-1859.18" wire \builder_done - attribute \src "ls180.v:1858.5-1858.18" + attribute \src "ls180.v:1857.5-1857.18" wire \builder_error - attribute \src "ls180.v:1855.11-1855.24" + attribute \src "ls180.v:1854.11-1854.24" wire width 3 \builder_grant - attribute \src "ls180.v:1862.13-1862.44" + attribute \src "ls180.v:1861.13-1861.44" wire width 14 \builder_interface0_bank_bus_adr - attribute \src "ls180.v:1865.11-1865.44" + attribute \src "ls180.v:1864.11-1864.44" wire width 8 \builder_interface0_bank_bus_dat_r - attribute \src "ls180.v:1864.12-1864.45" + attribute \src "ls180.v:1863.12-1863.45" wire width 8 \builder_interface0_bank_bus_dat_w - attribute \src "ls180.v:1863.6-1863.36" + attribute \src "ls180.v:1862.6-1862.36" wire \builder_interface0_bank_bus_we - attribute \src "ls180.v:2384.13-2384.45" + attribute \src "ls180.v:2383.13-2383.45" wire width 14 \builder_interface10_bank_bus_adr - attribute \src "ls180.v:2387.11-2387.45" + attribute \src "ls180.v:2386.11-2386.45" wire width 8 \builder_interface10_bank_bus_dat_r - attribute \src "ls180.v:2386.12-2386.46" + attribute \src "ls180.v:2385.12-2385.46" wire width 8 \builder_interface10_bank_bus_dat_w - attribute \src "ls180.v:2385.6-2385.37" + attribute \src "ls180.v:2384.6-2384.37" wire \builder_interface10_bank_bus_we - attribute \src "ls180.v:2425.13-2425.45" + attribute \src "ls180.v:2424.13-2424.45" wire width 14 \builder_interface11_bank_bus_adr - attribute \src "ls180.v:2428.11-2428.45" + attribute \src "ls180.v:2427.11-2427.45" wire width 8 \builder_interface11_bank_bus_dat_r - attribute \src "ls180.v:2427.12-2427.46" + attribute \src "ls180.v:2426.12-2426.46" wire width 8 \builder_interface11_bank_bus_dat_w - attribute \src "ls180.v:2426.6-2426.37" + attribute \src "ls180.v:2425.6-2425.37" wire \builder_interface11_bank_bus_we - attribute \src "ls180.v:2490.13-2490.45" + attribute \src "ls180.v:2489.13-2489.45" wire width 14 \builder_interface12_bank_bus_adr - attribute \src "ls180.v:2493.11-2493.45" + attribute \src "ls180.v:2492.11-2492.45" wire width 8 \builder_interface12_bank_bus_dat_r - attribute \src "ls180.v:2492.12-2492.46" + attribute \src "ls180.v:2491.12-2491.46" wire width 8 \builder_interface12_bank_bus_dat_w - attribute \src "ls180.v:2491.6-2491.37" + attribute \src "ls180.v:2490.6-2490.37" wire \builder_interface12_bank_bus_we - attribute \src "ls180.v:2515.13-2515.45" + attribute \src "ls180.v:2514.13-2514.45" wire width 14 \builder_interface13_bank_bus_adr - attribute \src "ls180.v:2518.11-2518.45" + attribute \src "ls180.v:2517.11-2517.45" wire width 8 \builder_interface13_bank_bus_dat_r - attribute \src "ls180.v:2517.12-2517.46" + attribute \src "ls180.v:2516.12-2516.46" wire width 8 \builder_interface13_bank_bus_dat_w - attribute \src "ls180.v:2516.6-2516.37" + attribute \src "ls180.v:2515.6-2515.37" wire \builder_interface13_bank_bus_we - attribute \src "ls180.v:1903.13-1903.44" + attribute \src "ls180.v:1902.13-1902.44" wire width 14 \builder_interface1_bank_bus_adr - attribute \src "ls180.v:1906.11-1906.44" + attribute \src "ls180.v:1905.11-1905.44" wire width 8 \builder_interface1_bank_bus_dat_r - attribute \src "ls180.v:1905.12-1905.45" + attribute \src "ls180.v:1904.12-1904.45" wire width 8 \builder_interface1_bank_bus_dat_w - attribute \src "ls180.v:1904.6-1904.36" + attribute \src "ls180.v:1903.6-1903.36" wire \builder_interface1_bank_bus_we - attribute \src "ls180.v:1932.13-1932.44" + attribute \src "ls180.v:1931.13-1931.44" wire width 14 \builder_interface2_bank_bus_adr - attribute \src "ls180.v:1935.11-1935.44" + attribute \src "ls180.v:1934.11-1934.44" wire width 8 \builder_interface2_bank_bus_dat_r - attribute \src "ls180.v:1934.12-1934.45" + attribute \src "ls180.v:1933.12-1933.45" wire width 8 \builder_interface2_bank_bus_dat_w - attribute \src "ls180.v:1933.6-1933.36" + attribute \src "ls180.v:1932.6-1932.36" wire \builder_interface2_bank_bus_we - attribute \src "ls180.v:1973.13-1973.44" + attribute \src "ls180.v:1972.13-1972.44" wire width 14 \builder_interface3_bank_bus_adr - attribute \src "ls180.v:1976.11-1976.44" + attribute \src "ls180.v:1975.11-1975.44" wire width 8 \builder_interface3_bank_bus_dat_r - attribute \src "ls180.v:1975.12-1975.45" + attribute \src "ls180.v:1974.12-1974.45" wire width 8 \builder_interface3_bank_bus_dat_w - attribute \src "ls180.v:1974.6-1974.36" + attribute \src "ls180.v:1973.6-1973.36" wire \builder_interface3_bank_bus_we - attribute \src "ls180.v:2014.13-2014.44" + attribute \src "ls180.v:2013.13-2013.44" wire width 14 \builder_interface4_bank_bus_adr - attribute \src "ls180.v:2017.11-2017.44" + attribute \src "ls180.v:2016.11-2016.44" wire width 8 \builder_interface4_bank_bus_dat_r - attribute \src "ls180.v:2016.12-2016.45" + attribute \src "ls180.v:2015.12-2015.45" wire width 8 \builder_interface4_bank_bus_dat_w - attribute \src "ls180.v:2015.6-2015.36" + attribute \src "ls180.v:2014.6-2014.36" wire \builder_interface4_bank_bus_we - attribute \src "ls180.v:2079.13-2079.44" + attribute \src "ls180.v:2078.13-2078.44" wire width 14 \builder_interface5_bank_bus_adr - attribute \src "ls180.v:2082.11-2082.44" + attribute \src "ls180.v:2081.11-2081.44" wire width 8 \builder_interface5_bank_bus_dat_r - attribute \src "ls180.v:2081.12-2081.45" + attribute \src "ls180.v:2080.12-2080.45" wire width 8 \builder_interface5_bank_bus_dat_w - attribute \src "ls180.v:2080.6-2080.36" + attribute \src "ls180.v:2079.6-2079.36" wire \builder_interface5_bank_bus_we - attribute \src "ls180.v:2212.13-2212.44" + attribute \src "ls180.v:2211.13-2211.44" wire width 14 \builder_interface6_bank_bus_adr - attribute \src "ls180.v:2215.11-2215.44" + attribute \src "ls180.v:2214.11-2214.44" wire width 8 \builder_interface6_bank_bus_dat_r - attribute \src "ls180.v:2214.12-2214.45" + attribute \src "ls180.v:2213.12-2213.45" wire width 8 \builder_interface6_bank_bus_dat_w - attribute \src "ls180.v:2213.6-2213.36" + attribute \src "ls180.v:2212.6-2212.36" wire \builder_interface6_bank_bus_we - attribute \src "ls180.v:2293.13-2293.44" + attribute \src "ls180.v:2292.13-2292.44" wire width 14 \builder_interface7_bank_bus_adr - attribute \src "ls180.v:2296.11-2296.44" + attribute \src "ls180.v:2295.11-2295.44" wire width 8 \builder_interface7_bank_bus_dat_r - attribute \src "ls180.v:2295.12-2295.45" + attribute \src "ls180.v:2294.12-2294.45" wire width 8 \builder_interface7_bank_bus_dat_w - attribute \src "ls180.v:2294.6-2294.36" + attribute \src "ls180.v:2293.6-2293.36" wire \builder_interface7_bank_bus_we - attribute \src "ls180.v:2310.13-2310.44" + attribute \src "ls180.v:2309.13-2309.44" wire width 14 \builder_interface8_bank_bus_adr - attribute \src "ls180.v:2313.11-2313.44" + attribute \src "ls180.v:2312.11-2312.44" wire width 8 \builder_interface8_bank_bus_dat_r - attribute \src "ls180.v:2312.12-2312.45" + attribute \src "ls180.v:2311.12-2311.45" wire width 8 \builder_interface8_bank_bus_dat_w - attribute \src "ls180.v:2311.6-2311.36" + attribute \src "ls180.v:2310.6-2310.36" wire \builder_interface8_bank_bus_we - attribute \src "ls180.v:2351.13-2351.44" + attribute \src "ls180.v:2350.13-2350.44" wire width 14 \builder_interface9_bank_bus_adr - attribute \src "ls180.v:2354.11-2354.44" + attribute \src "ls180.v:2353.11-2353.44" wire width 8 \builder_interface9_bank_bus_dat_r - attribute \src "ls180.v:2353.12-2353.45" + attribute \src "ls180.v:2352.12-2352.45" wire width 8 \builder_interface9_bank_bus_dat_w - attribute \src "ls180.v:2352.6-2352.36" + attribute \src "ls180.v:2351.6-2351.36" wire \builder_interface9_bank_bus_we - attribute \src "ls180.v:1828.12-1828.35" + attribute \src "ls180.v:1827.12-1827.35" wire width 14 \builder_libresocsim_adr - attribute \src "ls180.v:2544.12-2544.47" + attribute \src "ls180.v:2543.12-2543.47" wire width 14 \builder_libresocsim_adr_next_value1 - attribute \src "ls180.v:2545.5-2545.43" + attribute \src "ls180.v:2544.5-2544.43" wire \builder_libresocsim_adr_next_value_ce1 - attribute \src "ls180.v:1831.12-1831.37" + attribute \src "ls180.v:1830.12-1830.37" wire width 8 \builder_libresocsim_dat_r - attribute \src "ls180.v:1830.11-1830.36" + attribute \src "ls180.v:1829.11-1829.36" wire width 8 \builder_libresocsim_dat_w - attribute \src "ls180.v:2542.11-2542.48" + attribute \src "ls180.v:2541.11-2541.48" wire width 8 \builder_libresocsim_dat_w_next_value0 - attribute \src "ls180.v:2543.5-2543.45" + attribute \src "ls180.v:2542.5-2542.45" wire \builder_libresocsim_dat_w_next_value_ce0 - attribute \src "ls180.v:1829.5-1829.27" + attribute \src "ls180.v:1828.5-1828.27" wire \builder_libresocsim_we - attribute \src "ls180.v:2546.5-2546.39" + attribute \src "ls180.v:2545.5-2545.39" wire \builder_libresocsim_we_next_value2 - attribute \src "ls180.v:2547.5-2547.42" + attribute \src "ls180.v:2546.5-2546.42" wire \builder_libresocsim_we_next_value_ce2 - attribute \src "ls180.v:1838.5-1838.37" + attribute \src "ls180.v:1837.5-1837.37" wire \builder_libresocsim_wishbone_ack - attribute \src "ls180.v:1832.13-1832.45" + attribute \src "ls180.v:1831.13-1831.45" wire width 30 \builder_libresocsim_wishbone_adr - attribute \src "ls180.v:1841.12-1841.44" - wire width 2 \builder_libresocsim_wishbone_bte attribute \src "ls180.v:1840.12-1840.44" + wire width 2 \builder_libresocsim_wishbone_bte + attribute \src "ls180.v:1839.12-1839.44" wire width 3 \builder_libresocsim_wishbone_cti - attribute \src "ls180.v:1836.6-1836.38" + attribute \src "ls180.v:1835.6-1835.38" wire \builder_libresocsim_wishbone_cyc - attribute \src "ls180.v:1834.12-1834.46" + attribute \src "ls180.v:1833.12-1833.46" wire width 32 \builder_libresocsim_wishbone_dat_r - attribute \src "ls180.v:1833.13-1833.47" + attribute \src "ls180.v:1832.13-1832.47" wire width 32 \builder_libresocsim_wishbone_dat_w - attribute \src "ls180.v:1842.5-1842.37" + attribute \src "ls180.v:1841.5-1841.37" wire \builder_libresocsim_wishbone_err - attribute \src "ls180.v:1835.12-1835.44" + attribute \src "ls180.v:1834.12-1834.44" wire width 4 \builder_libresocsim_wishbone_sel - attribute \src "ls180.v:1837.6-1837.38" + attribute \src "ls180.v:1836.6-1836.38" wire \builder_libresocsim_wishbone_stb - attribute \src "ls180.v:1839.6-1839.37" + attribute \src "ls180.v:1838.6-1838.37" wire \builder_libresocsim_wishbone_we - attribute \src "ls180.v:1731.5-1731.20" + attribute \src "ls180.v:1730.5-1730.20" wire \builder_locked0 - attribute \src "ls180.v:1732.5-1732.20" + attribute \src "ls180.v:1731.5-1731.20" wire \builder_locked1 - attribute \src "ls180.v:1733.5-1733.20" + attribute \src "ls180.v:1732.5-1732.20" wire \builder_locked2 - attribute \src "ls180.v:1734.5-1734.20" + attribute \src "ls180.v:1733.5-1733.20" wire \builder_locked3 - attribute \src "ls180.v:1718.11-1718.41" + attribute \src "ls180.v:1717.11-1717.41" wire width 3 \builder_multiplexer_next_state - attribute \src "ls180.v:1717.11-1717.36" + attribute \src "ls180.v:1716.11-1716.36" wire width 3 \builder_multiplexer_state attribute \no_retiming "true" - attribute \src "ls180.v:2649.32-2649.59" + attribute \src "ls180.v:2650.32-2650.59" wire \builder_multiregimpl0_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2650.32-2650.59" + attribute \src "ls180.v:2651.32-2651.59" wire \builder_multiregimpl0_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2669.32-2669.60" + attribute \src "ls180.v:2670.32-2670.60" wire \builder_multiregimpl10_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2670.32-2670.60" + attribute \src "ls180.v:2671.32-2671.60" wire \builder_multiregimpl10_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2671.32-2671.60" + attribute \src "ls180.v:2672.32-2672.60" wire \builder_multiregimpl11_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2672.32-2672.60" + attribute \src "ls180.v:2673.32-2673.60" wire \builder_multiregimpl11_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2673.32-2673.60" + attribute \src "ls180.v:2674.32-2674.60" wire \builder_multiregimpl12_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2674.32-2674.60" + attribute \src "ls180.v:2675.32-2675.60" wire \builder_multiregimpl12_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2675.32-2675.60" + attribute \src "ls180.v:2676.32-2676.60" wire \builder_multiregimpl13_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2676.32-2676.60" + attribute \src "ls180.v:2677.32-2677.60" wire \builder_multiregimpl13_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2677.32-2677.60" + attribute \src "ls180.v:2678.32-2678.60" wire \builder_multiregimpl14_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2678.32-2678.60" + attribute \src "ls180.v:2679.32-2679.60" wire \builder_multiregimpl14_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2679.32-2679.60" + attribute \src "ls180.v:2680.32-2680.60" wire \builder_multiregimpl15_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2680.32-2680.60" + attribute \src "ls180.v:2681.32-2681.60" wire \builder_multiregimpl15_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2681.32-2681.60" + attribute \src "ls180.v:2682.32-2682.60" wire \builder_multiregimpl16_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2682.32-2682.60" + attribute \src "ls180.v:2683.32-2683.60" wire \builder_multiregimpl16_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2651.32-2651.59" + attribute \src "ls180.v:2652.32-2652.59" wire \builder_multiregimpl1_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2652.32-2652.59" + attribute \src "ls180.v:2653.32-2653.59" wire \builder_multiregimpl1_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2653.32-2653.59" + attribute \src "ls180.v:2654.32-2654.59" wire \builder_multiregimpl2_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2654.32-2654.59" + attribute \src "ls180.v:2655.32-2655.59" wire \builder_multiregimpl2_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2655.32-2655.59" + attribute \src "ls180.v:2656.32-2656.59" wire \builder_multiregimpl3_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2656.32-2656.59" + attribute \src "ls180.v:2657.32-2657.59" wire \builder_multiregimpl3_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2657.32-2657.59" + attribute \src "ls180.v:2658.32-2658.59" wire \builder_multiregimpl4_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2658.32-2658.59" + attribute \src "ls180.v:2659.32-2659.59" wire \builder_multiregimpl4_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2659.32-2659.59" + attribute \src "ls180.v:2660.32-2660.59" wire \builder_multiregimpl5_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2660.32-2660.59" + attribute \src "ls180.v:2661.32-2661.59" wire \builder_multiregimpl5_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2661.32-2661.59" + attribute \src "ls180.v:2662.32-2662.59" wire \builder_multiregimpl6_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2662.32-2662.59" + attribute \src "ls180.v:2663.32-2663.59" wire \builder_multiregimpl6_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2663.32-2663.59" + attribute \src "ls180.v:2664.32-2664.59" wire \builder_multiregimpl7_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2664.32-2664.59" + attribute \src "ls180.v:2665.32-2665.59" wire \builder_multiregimpl7_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2665.32-2665.59" + attribute \src "ls180.v:2666.32-2666.59" wire \builder_multiregimpl8_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2666.32-2666.59" + attribute \src "ls180.v:2667.32-2667.59" wire \builder_multiregimpl8_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2667.32-2667.59" + attribute \src "ls180.v:2668.32-2668.59" wire \builder_multiregimpl9_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2668.32-2668.59" + attribute \src "ls180.v:2669.32-2669.59" wire \builder_multiregimpl9_regs1 - attribute \src "ls180.v:1736.5-1736.36" + attribute \src "ls180.v:1735.5-1735.36" wire \builder_new_master_rdata_valid0 - attribute \src "ls180.v:1737.5-1737.36" + attribute \src "ls180.v:1736.5-1736.36" wire \builder_new_master_rdata_valid1 - attribute \src "ls180.v:1738.5-1738.36" + attribute \src "ls180.v:1737.5-1737.36" wire \builder_new_master_rdata_valid2 - attribute \src "ls180.v:1739.5-1739.36" + attribute \src "ls180.v:1738.5-1738.36" wire \builder_new_master_rdata_valid3 - attribute \src "ls180.v:1735.5-1735.35" + attribute \src "ls180.v:1734.5-1734.35" wire \builder_new_master_wdata_ready - attribute \src "ls180.v:2541.11-2541.29" + attribute \src "ls180.v:2540.11-2540.29" wire width 2 \builder_next_state - attribute \src "ls180.v:1708.11-1708.39" + attribute \src "ls180.v:1707.11-1707.39" wire width 2 \builder_refresher_next_state - attribute \src "ls180.v:1707.11-1707.34" + attribute \src "ls180.v:1706.11-1706.34" wire width 2 \builder_refresher_state - attribute \src "ls180.v:1854.12-1854.27" + attribute \src "ls180.v:1853.12-1853.27" wire width 5 \builder_request - attribute \src "ls180.v:1721.6-1721.28" + attribute \src "ls180.v:1720.6-1720.28" wire \builder_roundrobin0_ce - attribute \src "ls180.v:1720.6-1720.31" + attribute \src "ls180.v:1719.6-1719.31" wire \builder_roundrobin0_grant - attribute \src "ls180.v:1719.6-1719.33" + attribute \src "ls180.v:1718.6-1718.33" wire \builder_roundrobin0_request - attribute \src "ls180.v:1724.6-1724.28" + attribute \src "ls180.v:1723.6-1723.28" wire \builder_roundrobin1_ce - attribute \src "ls180.v:1723.6-1723.31" + attribute \src "ls180.v:1722.6-1722.31" wire \builder_roundrobin1_grant - attribute \src "ls180.v:1722.6-1722.33" + attribute \src "ls180.v:1721.6-1721.33" wire \builder_roundrobin1_request - attribute \src "ls180.v:1727.6-1727.28" + attribute \src "ls180.v:1726.6-1726.28" wire \builder_roundrobin2_ce - attribute \src "ls180.v:1726.6-1726.31" + attribute \src "ls180.v:1725.6-1725.31" wire \builder_roundrobin2_grant - attribute \src "ls180.v:1725.6-1725.33" + attribute \src "ls180.v:1724.6-1724.33" wire \builder_roundrobin2_request - attribute \src "ls180.v:1730.6-1730.28" + attribute \src "ls180.v:1729.6-1729.28" wire \builder_roundrobin3_ce - attribute \src "ls180.v:1729.6-1729.31" + attribute \src "ls180.v:1728.6-1728.31" wire \builder_roundrobin3_grant - attribute \src "ls180.v:1728.6-1728.33" + attribute \src "ls180.v:1727.6-1727.33" wire \builder_roundrobin3_request - attribute \src "ls180.v:1813.11-1813.44" + attribute \src "ls180.v:1812.11-1812.44" wire width 2 \builder_sdblock2memdma_next_state - attribute \src "ls180.v:1812.11-1812.39" + attribute \src "ls180.v:1811.11-1811.39" wire width 2 \builder_sdblock2memdma_state - attribute \src "ls180.v:1781.5-1781.50" + attribute \src "ls180.v:1780.5-1780.50" wire \builder_sdcore_crcupstreaminserter_next_state - attribute \src "ls180.v:1780.5-1780.45" + attribute \src "ls180.v:1779.5-1779.45" wire \builder_sdcore_crcupstreaminserter_state - attribute \src "ls180.v:1793.11-1793.40" + attribute \src "ls180.v:1792.11-1792.40" wire width 3 \builder_sdcore_fsm_next_state - attribute \src "ls180.v:1792.11-1792.35" + attribute \src "ls180.v:1791.11-1791.35" wire width 3 \builder_sdcore_fsm_state - attribute \src "ls180.v:1817.5-1817.42" + attribute \src "ls180.v:1816.5-1816.42" wire \builder_sdmem2blockdma_fsm_next_state - attribute \src "ls180.v:1816.5-1816.37" + attribute \src "ls180.v:1815.5-1815.37" wire \builder_sdmem2blockdma_fsm_state - attribute \src "ls180.v:1821.11-1821.58" + attribute \src "ls180.v:1820.11-1820.58" wire width 2 \builder_sdmem2blockdma_resetinserter_next_state - attribute \src "ls180.v:1820.11-1820.53" + attribute \src "ls180.v:1819.11-1819.53" wire width 2 \builder_sdmem2blockdma_resetinserter_state - attribute \src "ls180.v:1769.11-1769.39" + attribute \src "ls180.v:1768.11-1768.39" wire width 3 \builder_sdphy_fsm_next_state - attribute \src "ls180.v:1768.11-1768.34" + attribute \src "ls180.v:1767.11-1767.34" wire width 3 \builder_sdphy_fsm_state - attribute \src "ls180.v:1757.11-1757.45" + attribute \src "ls180.v:1756.11-1756.45" wire width 3 \builder_sdphy_sdphycmdr_next_state - attribute \src "ls180.v:1756.11-1756.40" + attribute \src "ls180.v:1755.11-1755.40" wire width 3 \builder_sdphy_sdphycmdr_state - attribute \src "ls180.v:1753.11-1753.45" + attribute \src "ls180.v:1752.11-1752.45" wire width 2 \builder_sdphy_sdphycmdw_next_state - attribute \src "ls180.v:1752.11-1752.40" + attribute \src "ls180.v:1751.11-1751.40" wire width 2 \builder_sdphy_sdphycmdw_state - attribute \src "ls180.v:1765.5-1765.39" + attribute \src "ls180.v:1764.5-1764.39" wire \builder_sdphy_sdphycrcr_next_state - attribute \src "ls180.v:1764.5-1764.34" + attribute \src "ls180.v:1763.5-1763.34" wire \builder_sdphy_sdphycrcr_state - attribute \src "ls180.v:1773.11-1773.46" + attribute \src "ls180.v:1772.11-1772.46" wire width 3 \builder_sdphy_sdphydatar_next_state - attribute \src "ls180.v:1772.11-1772.41" + attribute \src "ls180.v:1771.11-1771.41" wire width 3 \builder_sdphy_sdphydatar_state - attribute \src "ls180.v:1749.5-1749.39" + attribute \src "ls180.v:1748.5-1748.39" wire \builder_sdphy_sdphyinit_next_state - attribute \src "ls180.v:1748.5-1748.34" + attribute \src "ls180.v:1747.5-1747.34" wire \builder_sdphy_sdphyinit_state - attribute \src "ls180.v:1849.5-1849.23" + attribute \src "ls180.v:1848.5-1848.23" wire \builder_shared_ack - attribute \src "ls180.v:1843.13-1843.31" + attribute \src "ls180.v:1842.13-1842.31" wire width 30 \builder_shared_adr - attribute \src "ls180.v:1852.12-1852.30" - wire width 2 \builder_shared_bte attribute \src "ls180.v:1851.12-1851.30" + wire width 2 \builder_shared_bte + attribute \src "ls180.v:1850.12-1850.30" wire width 3 \builder_shared_cti - attribute \src "ls180.v:1847.6-1847.24" + attribute \src "ls180.v:1846.6-1846.24" wire \builder_shared_cyc - attribute \src "ls180.v:1845.12-1845.32" + attribute \src "ls180.v:1844.12-1844.32" wire width 32 \builder_shared_dat_r - attribute \src "ls180.v:1844.13-1844.33" + attribute \src "ls180.v:1843.13-1843.33" wire width 32 \builder_shared_dat_w - attribute \src "ls180.v:1853.6-1853.24" + attribute \src "ls180.v:1852.6-1852.24" wire \builder_shared_err - attribute \src "ls180.v:1846.12-1846.30" + attribute \src "ls180.v:1845.12-1845.30" wire width 4 \builder_shared_sel - attribute \src "ls180.v:1848.6-1848.24" + attribute \src "ls180.v:1847.6-1847.24" wire \builder_shared_stb - attribute \src "ls180.v:1850.6-1850.23" + attribute \src "ls180.v:1849.6-1849.23" wire \builder_shared_we - attribute \src "ls180.v:1856.11-1856.28" + attribute \src "ls180.v:1855.11-1855.28" wire width 5 \builder_slave_sel - attribute \src "ls180.v:1857.11-1857.30" + attribute \src "ls180.v:1856.11-1856.30" wire width 5 \builder_slave_sel_r - attribute \src "ls180.v:1745.11-1745.40" + attribute \src "ls180.v:1744.11-1744.40" wire width 2 \builder_spimaster0_next_state - attribute \src "ls180.v:1744.11-1744.35" + attribute \src "ls180.v:1743.11-1743.35" wire width 2 \builder_spimaster0_state - attribute \src "ls180.v:1825.11-1825.40" + attribute \src "ls180.v:1824.11-1824.40" wire width 2 \builder_spimaster1_next_state - attribute \src "ls180.v:1824.11-1824.35" + attribute \src "ls180.v:1823.11-1823.35" wire width 2 \builder_spimaster1_state - attribute \src "ls180.v:2540.11-2540.24" + attribute \src "ls180.v:2539.11-2539.24" wire width 2 \builder_state - attribute \src "ls180.v:2593.5-2593.32" + attribute \src "ls180.v:2592.5-2592.32" wire \builder_sync_f_array_muxed0 - attribute \src "ls180.v:2594.5-2594.32" + attribute \src "ls180.v:2593.5-2593.32" wire \builder_sync_f_array_muxed1 - attribute \src "ls180.v:2586.11-2586.40" + attribute \src "ls180.v:2585.11-2585.40" wire width 2 \builder_sync_rhs_array_muxed0 - attribute \src "ls180.v:2587.12-2587.41" + attribute \src "ls180.v:2586.12-2586.41" wire width 13 \builder_sync_rhs_array_muxed1 - attribute \src "ls180.v:2588.5-2588.34" + attribute \src "ls180.v:2587.5-2587.34" wire \builder_sync_rhs_array_muxed2 - attribute \src "ls180.v:2589.5-2589.34" + attribute \src "ls180.v:2588.5-2588.34" wire \builder_sync_rhs_array_muxed3 - attribute \src "ls180.v:2590.5-2590.34" + attribute \src "ls180.v:2589.5-2589.34" wire \builder_sync_rhs_array_muxed4 - attribute \src "ls180.v:2591.5-2591.34" + attribute \src "ls180.v:2590.5-2590.34" wire \builder_sync_rhs_array_muxed5 - attribute \src "ls180.v:2592.5-2592.34" + attribute \src "ls180.v:2591.5-2591.34" wire \builder_sync_rhs_array_muxed6 - attribute \src "ls180.v:1859.6-1859.18" + attribute \src "ls180.v:1858.6-1858.18" wire \builder_wait attribute \src "ls180.v:28.19-28.23" wire width 3 input 24 \eint @@ -79072,105 +79066,105 @@ module \ls180 wire output 28 \jtag_tdo attribute \src "ls180.v:29.13-29.21" wire input 25 \jtag_tms - attribute \src "ls180.v:1665.13-1665.37" + attribute \src "ls180.v:1664.13-1664.37" wire width 16 \libresocsim_clk_divider0 - attribute \src "ls180.v:1687.12-1687.36" + attribute \src "ls180.v:1686.12-1686.36" wire width 16 \libresocsim_clk_divider1 - attribute \src "ls180.v:1682.5-1682.27" + attribute \src "ls180.v:1681.5-1681.27" wire \libresocsim_clk_enable - attribute \src "ls180.v:1689.6-1689.26" - wire \libresocsim_clk_fall attribute \src "ls180.v:1688.6-1688.26" + wire \libresocsim_clk_fall + attribute \src "ls180.v:1687.6-1687.26" wire \libresocsim_clk_rise - attribute \src "ls180.v:1669.5-1669.27" + attribute \src "ls180.v:1668.5-1668.27" wire \libresocsim_control_re - attribute \src "ls180.v:1668.12-1668.39" + attribute \src "ls180.v:1667.12-1667.39" wire width 16 \libresocsim_control_storage - attribute \src "ls180.v:1684.11-1684.28" + attribute \src "ls180.v:1683.11-1683.28" wire width 3 \libresocsim_count - attribute \src "ls180.v:1826.11-1826.50" + attribute \src "ls180.v:1825.11-1825.50" wire width 3 \libresocsim_count_spimaster1_next_value - attribute \src "ls180.v:1827.5-1827.47" + attribute \src "ls180.v:1826.5-1826.47" wire \libresocsim_count_spimaster1_next_value_ce - attribute \src "ls180.v:1663.6-1663.20" + attribute \src "ls180.v:1662.6-1662.20" wire \libresocsim_cs - attribute \src "ls180.v:1683.5-1683.26" + attribute \src "ls180.v:1682.5-1682.26" wire \libresocsim_cs_enable - attribute \src "ls180.v:1679.5-1679.22" + attribute \src "ls180.v:1678.5-1678.22" wire \libresocsim_cs_re - attribute \src "ls180.v:1678.5-1678.27" + attribute \src "ls180.v:1677.5-1677.27" wire \libresocsim_cs_storage - attribute \src "ls180.v:1659.5-1659.22" + attribute \src "ls180.v:1658.5-1658.22" wire \libresocsim_done0 - attribute \src "ls180.v:1670.6-1670.23" + attribute \src "ls180.v:1669.6-1669.23" wire \libresocsim_done1 - attribute \src "ls180.v:1660.5-1660.20" + attribute \src "ls180.v:1659.5-1659.20" wire \libresocsim_irq - attribute \src "ls180.v:1658.12-1658.31" + attribute \src "ls180.v:1657.12-1657.31" wire width 8 \libresocsim_length0 - attribute \src "ls180.v:1667.12-1667.31" + attribute \src "ls180.v:1666.12-1666.31" wire width 8 \libresocsim_length1 - attribute \src "ls180.v:1664.6-1664.26" + attribute \src "ls180.v:1663.6-1663.26" wire \libresocsim_loopback - attribute \src "ls180.v:1681.5-1681.28" + attribute \src "ls180.v:1680.5-1680.28" wire \libresocsim_loopback_re - attribute \src "ls180.v:1680.5-1680.33" + attribute \src "ls180.v:1679.5-1679.33" wire \libresocsim_loopback_storage - attribute \src "ls180.v:1662.11-1662.27" + attribute \src "ls180.v:1661.11-1661.27" wire width 8 \libresocsim_miso - attribute \src "ls180.v:1692.11-1692.32" + attribute \src "ls180.v:1691.11-1691.32" wire width 8 \libresocsim_miso_data - attribute \src "ls180.v:1686.5-1686.27" + attribute \src "ls180.v:1685.5-1685.27" wire \libresocsim_miso_latch - attribute \src "ls180.v:1675.12-1675.35" + attribute \src "ls180.v:1674.12-1674.35" wire width 8 \libresocsim_miso_status - attribute \src "ls180.v:1676.6-1676.25" + attribute \src "ls180.v:1675.6-1675.25" wire \libresocsim_miso_we - attribute \src "ls180.v:1661.12-1661.28" + attribute \src "ls180.v:1660.12-1660.28" wire width 8 \libresocsim_mosi - attribute \src "ls180.v:1690.11-1690.32" + attribute \src "ls180.v:1689.11-1689.32" wire width 8 \libresocsim_mosi_data - attribute \src "ls180.v:1685.5-1685.27" + attribute \src "ls180.v:1684.5-1684.27" wire \libresocsim_mosi_latch - attribute \src "ls180.v:1674.5-1674.24" + attribute \src "ls180.v:1673.5-1673.24" wire \libresocsim_mosi_re - attribute \src "ls180.v:1691.11-1691.31" + attribute \src "ls180.v:1690.11-1690.31" wire width 3 \libresocsim_mosi_sel - attribute \src "ls180.v:1673.11-1673.35" + attribute \src "ls180.v:1672.11-1672.35" wire width 8 \libresocsim_mosi_storage - attribute \src "ls180.v:1694.5-1694.19" + attribute \src "ls180.v:1693.5-1693.19" wire \libresocsim_re - attribute \src "ls180.v:1677.6-1677.21" + attribute \src "ls180.v:1676.6-1676.21" wire \libresocsim_sel - attribute \src "ls180.v:1657.6-1657.24" + attribute \src "ls180.v:1656.6-1656.24" wire \libresocsim_start0 - attribute \src "ls180.v:1666.5-1666.23" + attribute \src "ls180.v:1665.5-1665.23" wire \libresocsim_start1 - attribute \src "ls180.v:1671.6-1671.31" + attribute \src "ls180.v:1670.6-1670.31" wire \libresocsim_status_status - attribute \src "ls180.v:1672.6-1672.27" + attribute \src "ls180.v:1671.6-1671.27" wire \libresocsim_status_we - attribute \src "ls180.v:1693.12-1693.31" + attribute \src "ls180.v:1692.12-1692.31" wire width 16 \libresocsim_storage - attribute \src "ls180.v:807.6-807.18" + attribute \src "ls180.v:806.6-806.18" wire \main_ack_cmd - attribute \src "ls180.v:809.6-809.20" - wire \main_ack_rdata attribute \src "ls180.v:808.6-808.20" + wire \main_ack_rdata + attribute \src "ls180.v:807.6-807.20" wire \main_ack_wdata - attribute \src "ls180.v:805.5-805.22" + attribute \src "ls180.v:804.5-804.22" wire \main_cmd_consumed - attribute \src "ls180.v:802.5-802.27" + attribute \src "ls180.v:801.5-801.27" wire \main_converter_counter - attribute \src "ls180.v:1742.5-1742.48" + attribute \src "ls180.v:1741.5-1741.48" wire \main_converter_counter_converter_next_value - attribute \src "ls180.v:1743.5-1743.51" + attribute \src "ls180.v:1742.5-1742.51" wire \main_converter_counter_converter_next_value_ce - attribute \src "ls180.v:804.12-804.32" + attribute \src "ls180.v:803.12-803.32" wire width 32 \main_converter_dat_r - attribute \src "ls180.v:803.6-803.26" + attribute \src "ls180.v:802.6-802.26" wire \main_converter_reset - attribute \src "ls180.v:801.5-801.24" + attribute \src "ls180.v:800.5-800.24" wire \main_converter_skip attribute \src "ls180.v:230.6-230.23" wire \main_dfi_p0_act_n @@ -79204,73 +79198,71 @@ module \ls180 wire \main_dfi_p0_wrdata_en attribute \src "ls180.v:233.12-233.35" wire width 2 \main_dfi_p0_wrdata_mask - attribute \src "ls180.v:237.11-237.18" - wire width 2 \main_dm - attribute \src "ls180.v:998.12-998.22" - wire width 43 \main_dummy - attribute \src "ls180.v:953.5-953.20" + attribute \src "ls180.v:997.12-997.22" + wire width 42 \main_dummy + attribute \src "ls180.v:952.5-952.20" wire \main_gpio_oe_re - attribute \src "ls180.v:952.12-952.32" + attribute \src "ls180.v:951.12-951.32" wire width 16 \main_gpio_oe_storage - attribute \src "ls180.v:957.5-957.21" + attribute \src "ls180.v:956.5-956.21" wire \main_gpio_out_re - attribute \src "ls180.v:956.12-956.33" + attribute \src "ls180.v:955.12-955.33" wire width 16 \main_gpio_out_storage - attribute \src "ls180.v:958.13-958.29" + attribute \src "ls180.v:957.13-957.29" wire width 16 \main_gpio_pads_i - attribute \src "ls180.v:959.13-959.29" + attribute \src "ls180.v:958.13-958.29" wire width 16 \main_gpio_pads_o - attribute \src "ls180.v:960.13-960.30" + attribute \src "ls180.v:959.13-959.30" wire width 16 \main_gpio_pads_oe - attribute \src "ls180.v:954.12-954.28" + attribute \src "ls180.v:953.12-953.28" wire width 16 \main_gpio_status - attribute \src "ls180.v:955.6-955.18" + attribute \src "ls180.v:954.6-954.18" wire \main_gpio_we attribute \src "ls180.v:220.5-220.17" wire \main_int_rst - attribute \src "ls180.v:1478.6-1478.29" + attribute \src "ls180.v:1477.6-1477.29" wire \main_interface0_bus_ack - attribute \src "ls180.v:1472.13-1472.36" + attribute \src "ls180.v:1471.13-1471.36" wire width 32 \main_interface0_bus_adr - attribute \src "ls180.v:1481.11-1481.34" - wire width 2 \main_interface0_bus_bte attribute \src "ls180.v:1480.11-1480.34" + wire width 2 \main_interface0_bus_bte + attribute \src "ls180.v:1479.11-1479.34" wire width 3 \main_interface0_bus_cti - attribute \src "ls180.v:1476.6-1476.29" + attribute \src "ls180.v:1475.6-1475.29" wire \main_interface0_bus_cyc - attribute \src "ls180.v:1474.13-1474.38" - wire width 32 \main_interface0_bus_dat_r attribute \src "ls180.v:1473.13-1473.38" + wire width 32 \main_interface0_bus_dat_r + attribute \src "ls180.v:1472.13-1472.38" wire width 32 \main_interface0_bus_dat_w - attribute \src "ls180.v:1482.6-1482.29" + attribute \src "ls180.v:1481.6-1481.29" wire \main_interface0_bus_err - attribute \src "ls180.v:1475.12-1475.35" + attribute \src "ls180.v:1474.12-1474.35" wire width 4 \main_interface0_bus_sel - attribute \src "ls180.v:1477.6-1477.29" + attribute \src "ls180.v:1476.6-1476.29" wire \main_interface0_bus_stb - attribute \src "ls180.v:1479.6-1479.28" + attribute \src "ls180.v:1478.6-1478.28" wire \main_interface0_bus_we - attribute \src "ls180.v:1569.6-1569.29" + attribute \src "ls180.v:1568.6-1568.29" wire \main_interface1_bus_ack - attribute \src "ls180.v:1563.12-1563.35" + attribute \src "ls180.v:1562.12-1562.35" wire width 32 \main_interface1_bus_adr - attribute \src "ls180.v:1572.11-1572.34" - wire width 2 \main_interface1_bus_bte attribute \src "ls180.v:1571.11-1571.34" + wire width 2 \main_interface1_bus_bte + attribute \src "ls180.v:1570.11-1570.34" wire width 3 \main_interface1_bus_cti - attribute \src "ls180.v:1567.5-1567.28" + attribute \src "ls180.v:1566.5-1566.28" wire \main_interface1_bus_cyc - attribute \src "ls180.v:1565.13-1565.38" + attribute \src "ls180.v:1564.13-1564.38" wire width 32 \main_interface1_bus_dat_r - attribute \src "ls180.v:1564.12-1564.37" + attribute \src "ls180.v:1563.12-1563.37" wire width 32 \main_interface1_bus_dat_w - attribute \src "ls180.v:1573.6-1573.29" + attribute \src "ls180.v:1572.6-1572.29" wire \main_interface1_bus_err - attribute \src "ls180.v:1566.11-1566.34" + attribute \src "ls180.v:1565.11-1565.34" wire width 4 \main_interface1_bus_sel - attribute \src "ls180.v:1568.5-1568.28" + attribute \src "ls180.v:1567.5-1567.28" wire \main_interface1_bus_stb - attribute \src "ls180.v:1570.5-1570.27" + attribute \src "ls180.v:1569.5-1569.27" wire \main_interface1_bus_we attribute \src "ls180.v:186.12-186.32" wire width 7 \main_libresocsim_adr @@ -79284,9 +79276,9 @@ module \ls180 wire \main_libresocsim_bus_errors_we attribute \src "ls180.v:142.5-142.40" wire \main_libresocsim_converter0_counter - attribute \src "ls180.v:1697.5-1697.62" + attribute \src "ls180.v:1696.5-1696.62" wire \main_libresocsim_converter0_counter_converter0_next_value - attribute \src "ls180.v:1698.5-1698.65" + attribute \src "ls180.v:1697.5-1697.65" wire \main_libresocsim_converter0_counter_converter0_next_value_ce attribute \src "ls180.v:144.12-144.45" wire width 64 \main_libresocsim_converter0_dat_r @@ -79296,9 +79288,9 @@ module \ls180 wire \main_libresocsim_converter0_skip attribute \src "ls180.v:157.5-157.40" wire \main_libresocsim_converter1_counter - attribute \src "ls180.v:1701.5-1701.62" + attribute \src "ls180.v:1700.5-1700.62" wire \main_libresocsim_converter1_counter_converter1_next_value - attribute \src "ls180.v:1702.5-1702.65" + attribute \src "ls180.v:1701.5-1701.65" wire \main_libresocsim_converter1_counter_converter1_next_value_ce attribute \src "ls180.v:159.12-159.45" wire width 64 \main_libresocsim_converter1_dat_r @@ -79308,9 +79300,9 @@ module \ls180 wire \main_libresocsim_converter1_skip attribute \src "ls180.v:172.5-172.40" wire \main_libresocsim_converter2_counter - attribute \src "ls180.v:1705.5-1705.62" + attribute \src "ls180.v:1704.5-1704.62" wire \main_libresocsim_converter2_counter_converter2_next_value - attribute \src "ls180.v:1706.5-1706.65" + attribute \src "ls180.v:1705.5-1705.65" wire \main_libresocsim_converter2_counter_converter2_next_value_ce attribute \src "ls180.v:174.12-174.45" wire width 64 \main_libresocsim_converter2_dat_r @@ -79620,2916 +79612,2916 @@ module \ls180 wire \main_libresocsim_zero_status attribute \src "ls180.v:203.6-203.35" wire \main_libresocsim_zero_trigger - attribute \src "ls180.v:799.6-799.26" + attribute \src "ls180.v:798.6-798.26" wire \main_litedram_wb_ack - attribute \src "ls180.v:793.12-793.32" + attribute \src "ls180.v:792.12-792.32" wire width 30 \main_litedram_wb_adr - attribute \src "ls180.v:797.5-797.25" + attribute \src "ls180.v:796.5-796.25" wire \main_litedram_wb_cyc - attribute \src "ls180.v:795.13-795.35" + attribute \src "ls180.v:794.13-794.35" wire width 16 \main_litedram_wb_dat_r - attribute \src "ls180.v:794.12-794.34" + attribute \src "ls180.v:793.12-793.34" wire width 16 \main_litedram_wb_dat_w - attribute \src "ls180.v:796.11-796.31" + attribute \src "ls180.v:795.11-795.31" wire width 2 \main_litedram_wb_sel - attribute \src "ls180.v:798.5-798.25" + attribute \src "ls180.v:797.5-797.25" wire \main_litedram_wb_stb - attribute \src "ls180.v:800.5-800.24" + attribute \src "ls180.v:799.5-799.24" wire \main_litedram_wb_we - attribute \src "ls180.v:997.13-997.20" - wire width 43 \main_nc - attribute \src "ls180.v:828.12-828.37" + attribute \src "ls180.v:996.13-996.20" + wire width 42 \main_nc + attribute \src "ls180.v:827.12-827.37" wire width 32 \main_phase_accumulator_rx - attribute \src "ls180.v:818.12-818.37" + attribute \src "ls180.v:817.12-817.37" wire width 32 \main_phase_accumulator_tx - attribute \src "ls180.v:772.6-772.24" + attribute \src "ls180.v:771.6-771.24" wire \main_port_cmd_last - attribute \src "ls180.v:774.13-774.39" + attribute \src "ls180.v:773.13-773.39" wire width 24 \main_port_cmd_payload_addr - attribute \src "ls180.v:773.6-773.30" + attribute \src "ls180.v:772.6-772.30" wire \main_port_cmd_payload_we - attribute \src "ls180.v:771.6-771.25" - wire \main_port_cmd_ready attribute \src "ls180.v:770.6-770.25" + wire \main_port_cmd_ready + attribute \src "ls180.v:769.6-769.25" wire \main_port_cmd_valid - attribute \src "ls180.v:769.6-769.21" + attribute \src "ls180.v:768.6-768.21" wire \main_port_flush - attribute \src "ls180.v:781.13-781.41" + attribute \src "ls180.v:780.13-780.41" wire width 16 \main_port_rdata_payload_data - attribute \src "ls180.v:780.6-780.27" - wire \main_port_rdata_ready attribute \src "ls180.v:779.6-779.27" + wire \main_port_rdata_ready + attribute \src "ls180.v:778.6-778.27" wire \main_port_rdata_valid - attribute \src "ls180.v:777.13-777.41" + attribute \src "ls180.v:776.13-776.41" wire width 16 \main_port_wdata_payload_data - attribute \src "ls180.v:778.12-778.38" + attribute \src "ls180.v:777.12-777.38" wire width 2 \main_port_wdata_payload_we - attribute \src "ls180.v:776.6-776.27" - wire \main_port_wdata_ready attribute \src "ls180.v:775.6-775.27" + wire \main_port_wdata_ready + attribute \src "ls180.v:774.6-774.27" wire \main_port_wdata_valid - attribute \src "ls180.v:1002.12-1002.29" + attribute \src "ls180.v:1001.12-1001.29" wire width 32 \main_pwm0_counter - attribute \src "ls180.v:999.6-999.22" + attribute \src "ls180.v:998.6-998.22" wire \main_pwm0_enable - attribute \src "ls180.v:1004.5-1004.24" + attribute \src "ls180.v:1003.5-1003.24" wire \main_pwm0_enable_re - attribute \src "ls180.v:1003.5-1003.29" + attribute \src "ls180.v:1002.5-1002.29" wire \main_pwm0_enable_storage - attribute \src "ls180.v:1001.13-1001.29" + attribute \src "ls180.v:1000.13-1000.29" wire width 32 \main_pwm0_period - attribute \src "ls180.v:1008.5-1008.24" + attribute \src "ls180.v:1007.5-1007.24" wire \main_pwm0_period_re - attribute \src "ls180.v:1007.12-1007.36" + attribute \src "ls180.v:1006.12-1006.36" wire width 32 \main_pwm0_period_storage - attribute \src "ls180.v:1000.13-1000.28" + attribute \src "ls180.v:999.13-999.28" wire width 32 \main_pwm0_width - attribute \src "ls180.v:1006.5-1006.23" + attribute \src "ls180.v:1005.5-1005.23" wire \main_pwm0_width_re - attribute \src "ls180.v:1005.12-1005.35" + attribute \src "ls180.v:1004.12-1004.35" wire width 32 \main_pwm0_width_storage - attribute \src "ls180.v:1012.12-1012.29" + attribute \src "ls180.v:1011.12-1011.29" wire width 32 \main_pwm1_counter - attribute \src "ls180.v:1009.6-1009.22" + attribute \src "ls180.v:1008.6-1008.22" wire \main_pwm1_enable - attribute \src "ls180.v:1014.5-1014.24" + attribute \src "ls180.v:1013.5-1013.24" wire \main_pwm1_enable_re - attribute \src "ls180.v:1013.5-1013.29" + attribute \src "ls180.v:1012.5-1012.29" wire \main_pwm1_enable_storage - attribute \src "ls180.v:1011.13-1011.29" + attribute \src "ls180.v:1010.13-1010.29" wire width 32 \main_pwm1_period - attribute \src "ls180.v:1018.5-1018.24" + attribute \src "ls180.v:1017.5-1017.24" wire \main_pwm1_period_re - attribute \src "ls180.v:1017.12-1017.36" + attribute \src "ls180.v:1016.12-1016.36" wire width 32 \main_pwm1_period_storage - attribute \src "ls180.v:1010.13-1010.28" + attribute \src "ls180.v:1009.13-1009.28" wire width 32 \main_pwm1_width - attribute \src "ls180.v:1016.5-1016.23" + attribute \src "ls180.v:1015.5-1015.23" wire \main_pwm1_width_re - attribute \src "ls180.v:1015.12-1015.35" + attribute \src "ls180.v:1014.12-1014.35" wire width 32 \main_pwm1_width_storage - attribute \src "ls180.v:238.11-238.25" + attribute \src "ls180.v:237.11-237.25" wire width 3 \main_rddata_en - attribute \src "ls180.v:811.5-811.12" + attribute \src "ls180.v:810.5-810.12" wire \main_re - attribute \src "ls180.v:829.6-829.13" + attribute \src "ls180.v:828.6-828.13" wire \main_rx - attribute \src "ls180.v:832.11-832.27" + attribute \src "ls180.v:831.11-831.27" wire width 4 \main_rx_bitcount - attribute \src "ls180.v:833.5-833.17" + attribute \src "ls180.v:832.5-832.17" wire \main_rx_busy - attribute \src "ls180.v:830.5-830.14" + attribute \src "ls180.v:829.5-829.14" wire \main_rx_r - attribute \src "ls180.v:831.11-831.22" + attribute \src "ls180.v:830.11-830.22" wire width 8 \main_rx_reg - attribute \src "ls180.v:1532.11-1532.43" + attribute \src "ls180.v:1531.11-1531.43" wire width 2 \main_sdblock2mem_converter_demux - attribute \src "ls180.v:1533.6-1533.42" + attribute \src "ls180.v:1532.6-1532.42" wire \main_sdblock2mem_converter_load_part - attribute \src "ls180.v:1523.6-1523.43" + attribute \src "ls180.v:1522.6-1522.43" wire \main_sdblock2mem_converter_sink_first - attribute \src "ls180.v:1524.6-1524.42" + attribute \src "ls180.v:1523.6-1523.42" wire \main_sdblock2mem_converter_sink_last - attribute \src "ls180.v:1525.12-1525.56" + attribute \src "ls180.v:1524.12-1524.56" wire width 8 \main_sdblock2mem_converter_sink_payload_data - attribute \src "ls180.v:1522.6-1522.43" - wire \main_sdblock2mem_converter_sink_ready attribute \src "ls180.v:1521.6-1521.43" + wire \main_sdblock2mem_converter_sink_ready + attribute \src "ls180.v:1520.6-1520.43" wire \main_sdblock2mem_converter_sink_valid - attribute \src "ls180.v:1528.5-1528.44" + attribute \src "ls180.v:1527.5-1527.44" wire \main_sdblock2mem_converter_source_first - attribute \src "ls180.v:1529.5-1529.43" + attribute \src "ls180.v:1528.5-1528.43" wire \main_sdblock2mem_converter_source_last - attribute \src "ls180.v:1530.12-1530.58" + attribute \src "ls180.v:1529.12-1529.58" wire width 32 \main_sdblock2mem_converter_source_payload_data - attribute \src "ls180.v:1531.11-1531.70" + attribute \src "ls180.v:1530.11-1530.70" wire width 3 \main_sdblock2mem_converter_source_payload_valid_token_count - attribute \src "ls180.v:1527.6-1527.45" - wire \main_sdblock2mem_converter_source_ready attribute \src "ls180.v:1526.6-1526.45" + wire \main_sdblock2mem_converter_source_ready + attribute \src "ls180.v:1525.6-1525.45" wire \main_sdblock2mem_converter_source_valid - attribute \src "ls180.v:1534.5-1534.42" + attribute \src "ls180.v:1533.5-1533.42" wire \main_sdblock2mem_converter_strobe_all - attribute \src "ls180.v:1507.11-1507.40" + attribute \src "ls180.v:1506.11-1506.40" wire width 5 \main_sdblock2mem_fifo_consume - attribute \src "ls180.v:1512.6-1512.35" + attribute \src "ls180.v:1511.6-1511.35" wire \main_sdblock2mem_fifo_do_read - attribute \src "ls180.v:1516.6-1516.41" + attribute \src "ls180.v:1515.6-1515.41" wire \main_sdblock2mem_fifo_fifo_in_first - attribute \src "ls180.v:1517.6-1517.40" + attribute \src "ls180.v:1516.6-1516.40" wire \main_sdblock2mem_fifo_fifo_in_last - attribute \src "ls180.v:1515.12-1515.54" + attribute \src "ls180.v:1514.12-1514.54" wire width 8 \main_sdblock2mem_fifo_fifo_in_payload_data - attribute \src "ls180.v:1519.6-1519.42" + attribute \src "ls180.v:1518.6-1518.42" wire \main_sdblock2mem_fifo_fifo_out_first - attribute \src "ls180.v:1520.6-1520.41" + attribute \src "ls180.v:1519.6-1519.41" wire \main_sdblock2mem_fifo_fifo_out_last - attribute \src "ls180.v:1518.12-1518.55" + attribute \src "ls180.v:1517.12-1517.55" wire width 8 \main_sdblock2mem_fifo_fifo_out_payload_data - attribute \src "ls180.v:1504.11-1504.38" + attribute \src "ls180.v:1503.11-1503.38" wire width 6 \main_sdblock2mem_fifo_level - attribute \src "ls180.v:1506.11-1506.40" + attribute \src "ls180.v:1505.11-1505.40" wire width 5 \main_sdblock2mem_fifo_produce - attribute \src "ls180.v:1513.12-1513.44" + attribute \src "ls180.v:1512.12-1512.44" wire width 5 \main_sdblock2mem_fifo_rdport_adr - attribute \src "ls180.v:1514.12-1514.46" + attribute \src "ls180.v:1513.12-1513.46" wire width 10 \main_sdblock2mem_fifo_rdport_dat_r - attribute \src "ls180.v:1505.5-1505.34" + attribute \src "ls180.v:1504.5-1504.34" wire \main_sdblock2mem_fifo_replace - attribute \src "ls180.v:1490.6-1490.38" + attribute \src "ls180.v:1489.6-1489.38" wire \main_sdblock2mem_fifo_sink_first - attribute \src "ls180.v:1491.6-1491.37" + attribute \src "ls180.v:1490.6-1490.37" wire \main_sdblock2mem_fifo_sink_last - attribute \src "ls180.v:1492.12-1492.51" + attribute \src "ls180.v:1491.12-1491.51" wire width 8 \main_sdblock2mem_fifo_sink_payload_data - attribute \src "ls180.v:1489.6-1489.38" - wire \main_sdblock2mem_fifo_sink_ready attribute \src "ls180.v:1488.6-1488.38" + wire \main_sdblock2mem_fifo_sink_ready + attribute \src "ls180.v:1487.6-1487.38" wire \main_sdblock2mem_fifo_sink_valid - attribute \src "ls180.v:1495.6-1495.40" + attribute \src "ls180.v:1494.6-1494.40" wire \main_sdblock2mem_fifo_source_first - attribute \src "ls180.v:1496.6-1496.39" + attribute \src "ls180.v:1495.6-1495.39" wire \main_sdblock2mem_fifo_source_last - attribute \src "ls180.v:1497.12-1497.53" + attribute \src "ls180.v:1496.12-1496.53" wire width 8 \main_sdblock2mem_fifo_source_payload_data - attribute \src "ls180.v:1494.6-1494.40" - wire \main_sdblock2mem_fifo_source_ready attribute \src "ls180.v:1493.6-1493.40" + wire \main_sdblock2mem_fifo_source_ready + attribute \src "ls180.v:1492.6-1492.40" wire \main_sdblock2mem_fifo_source_valid - attribute \src "ls180.v:1502.12-1502.46" + attribute \src "ls180.v:1501.12-1501.46" wire width 10 \main_sdblock2mem_fifo_syncfifo_din - attribute \src "ls180.v:1503.12-1503.47" + attribute \src "ls180.v:1502.12-1502.47" wire width 10 \main_sdblock2mem_fifo_syncfifo_dout - attribute \src "ls180.v:1500.6-1500.39" + attribute \src "ls180.v:1499.6-1499.39" wire \main_sdblock2mem_fifo_syncfifo_re - attribute \src "ls180.v:1501.6-1501.45" + attribute \src "ls180.v:1500.6-1500.45" wire \main_sdblock2mem_fifo_syncfifo_readable - attribute \src "ls180.v:1498.6-1498.39" + attribute \src "ls180.v:1497.6-1497.39" wire \main_sdblock2mem_fifo_syncfifo_we - attribute \src "ls180.v:1499.6-1499.45" + attribute \src "ls180.v:1498.6-1498.45" wire \main_sdblock2mem_fifo_syncfifo_writable - attribute \src "ls180.v:1508.11-1508.43" + attribute \src "ls180.v:1507.11-1507.43" wire width 5 \main_sdblock2mem_fifo_wrport_adr - attribute \src "ls180.v:1509.12-1509.46" + attribute \src "ls180.v:1508.12-1508.46" wire width 10 \main_sdblock2mem_fifo_wrport_dat_r - attribute \src "ls180.v:1511.12-1511.46" + attribute \src "ls180.v:1510.12-1510.46" wire width 10 \main_sdblock2mem_fifo_wrport_dat_w - attribute \src "ls180.v:1510.6-1510.37" + attribute \src "ls180.v:1509.6-1509.37" wire \main_sdblock2mem_fifo_wrport_we - attribute \src "ls180.v:1485.6-1485.38" + attribute \src "ls180.v:1484.6-1484.38" wire \main_sdblock2mem_sink_sink_first - attribute \src "ls180.v:1486.6-1486.37" + attribute \src "ls180.v:1485.6-1485.37" wire \main_sdblock2mem_sink_sink_last - attribute \src "ls180.v:1542.12-1542.54" + attribute \src "ls180.v:1541.12-1541.54" wire width 32 \main_sdblock2mem_sink_sink_payload_address - attribute \src "ls180.v:1487.12-1487.52" + attribute \src "ls180.v:1486.12-1486.52" wire width 8 \main_sdblock2mem_sink_sink_payload_data0 - attribute \src "ls180.v:1543.12-1543.52" + attribute \src "ls180.v:1542.12-1542.52" wire width 32 \main_sdblock2mem_sink_sink_payload_data1 - attribute \src "ls180.v:1484.6-1484.39" + attribute \src "ls180.v:1483.6-1483.39" wire \main_sdblock2mem_sink_sink_ready0 - attribute \src "ls180.v:1541.6-1541.39" + attribute \src "ls180.v:1540.6-1540.39" wire \main_sdblock2mem_sink_sink_ready1 - attribute \src "ls180.v:1483.6-1483.39" + attribute \src "ls180.v:1482.6-1482.39" wire \main_sdblock2mem_sink_sink_valid0 - attribute \src "ls180.v:1540.5-1540.38" + attribute \src "ls180.v:1539.5-1539.38" wire \main_sdblock2mem_sink_sink_valid1 - attribute \src "ls180.v:1537.6-1537.42" + attribute \src "ls180.v:1536.6-1536.42" wire \main_sdblock2mem_source_source_first - attribute \src "ls180.v:1538.6-1538.41" + attribute \src "ls180.v:1537.6-1537.41" wire \main_sdblock2mem_source_source_last - attribute \src "ls180.v:1539.13-1539.56" + attribute \src "ls180.v:1538.13-1538.56" wire width 32 \main_sdblock2mem_source_source_payload_data - attribute \src "ls180.v:1536.6-1536.42" - wire \main_sdblock2mem_source_source_ready attribute \src "ls180.v:1535.6-1535.42" + wire \main_sdblock2mem_source_source_ready + attribute \src "ls180.v:1534.6-1534.42" wire \main_sdblock2mem_source_source_valid - attribute \src "ls180.v:1559.13-1559.52" + attribute \src "ls180.v:1558.13-1558.52" wire width 32 \main_sdblock2mem_wishbonedmawriter_base - attribute \src "ls180.v:1550.5-1550.47" + attribute \src "ls180.v:1549.5-1549.47" wire \main_sdblock2mem_wishbonedmawriter_base_re - attribute \src "ls180.v:1549.12-1549.59" + attribute \src "ls180.v:1548.12-1548.59" wire width 64 \main_sdblock2mem_wishbonedmawriter_base_storage - attribute \src "ls180.v:1554.5-1554.49" + attribute \src "ls180.v:1553.5-1553.49" wire \main_sdblock2mem_wishbonedmawriter_enable_re - attribute \src "ls180.v:1553.5-1553.54" + attribute \src "ls180.v:1552.5-1552.54" wire \main_sdblock2mem_wishbonedmawriter_enable_storage - attribute \src "ls180.v:1561.13-1561.54" + attribute \src "ls180.v:1560.13-1560.54" wire width 32 \main_sdblock2mem_wishbonedmawriter_length - attribute \src "ls180.v:1552.5-1552.49" + attribute \src "ls180.v:1551.5-1551.49" wire \main_sdblock2mem_wishbonedmawriter_length_re - attribute \src "ls180.v:1551.12-1551.61" + attribute \src "ls180.v:1550.12-1550.61" wire width 32 \main_sdblock2mem_wishbonedmawriter_length_storage - attribute \src "ls180.v:1558.5-1558.47" + attribute \src "ls180.v:1557.5-1557.47" wire \main_sdblock2mem_wishbonedmawriter_loop_re - attribute \src "ls180.v:1557.5-1557.52" + attribute \src "ls180.v:1556.5-1556.52" wire \main_sdblock2mem_wishbonedmawriter_loop_storage - attribute \src "ls180.v:1560.12-1560.53" + attribute \src "ls180.v:1559.12-1559.53" wire width 32 \main_sdblock2mem_wishbonedmawriter_offset - attribute \src "ls180.v:1814.12-1814.79" + attribute \src "ls180.v:1813.12-1813.79" wire width 32 \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value - attribute \src "ls180.v:1815.5-1815.75" + attribute \src "ls180.v:1814.5-1814.75" wire \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce - attribute \src "ls180.v:1562.6-1562.46" + attribute \src "ls180.v:1561.6-1561.46" wire \main_sdblock2mem_wishbonedmawriter_reset - attribute \src "ls180.v:1546.6-1546.51" + attribute \src "ls180.v:1545.6-1545.51" wire \main_sdblock2mem_wishbonedmawriter_sink_first - attribute \src "ls180.v:1547.6-1547.50" + attribute \src "ls180.v:1546.6-1546.50" wire \main_sdblock2mem_wishbonedmawriter_sink_last - attribute \src "ls180.v:1548.13-1548.65" + attribute \src "ls180.v:1547.13-1547.65" wire width 32 \main_sdblock2mem_wishbonedmawriter_sink_payload_data - attribute \src "ls180.v:1545.5-1545.50" + attribute \src "ls180.v:1544.5-1544.50" wire \main_sdblock2mem_wishbonedmawriter_sink_ready - attribute \src "ls180.v:1544.6-1544.51" + attribute \src "ls180.v:1543.6-1543.51" wire \main_sdblock2mem_wishbonedmawriter_sink_valid - attribute \src "ls180.v:1555.5-1555.46" + attribute \src "ls180.v:1554.5-1554.46" wire \main_sdblock2mem_wishbonedmawriter_status - attribute \src "ls180.v:1556.6-1556.43" + attribute \src "ls180.v:1555.6-1555.43" wire \main_sdblock2mem_wishbonedmawriter_we - attribute \src "ls180.v:1324.5-1324.31" + attribute \src "ls180.v:1323.5-1323.31" wire \main_sdcore_block_count_re - attribute \src "ls180.v:1323.12-1323.43" + attribute \src "ls180.v:1322.12-1322.43" wire width 32 \main_sdcore_block_count_storage - attribute \src "ls180.v:1322.5-1322.32" + attribute \src "ls180.v:1321.5-1321.32" wire \main_sdcore_block_length_re - attribute \src "ls180.v:1321.11-1321.43" + attribute \src "ls180.v:1320.11-1320.43" wire width 10 \main_sdcore_block_length_storage - attribute \src "ls180.v:1308.5-1308.32" + attribute \src "ls180.v:1307.5-1307.32" wire \main_sdcore_cmd_argument_re - attribute \src "ls180.v:1307.12-1307.44" + attribute \src "ls180.v:1306.12-1306.44" wire width 32 \main_sdcore_cmd_argument_storage - attribute \src "ls180.v:1310.5-1310.31" + attribute \src "ls180.v:1309.5-1309.31" wire \main_sdcore_cmd_command_re - attribute \src "ls180.v:1309.12-1309.43" + attribute \src "ls180.v:1308.12-1308.43" wire width 32 \main_sdcore_cmd_command_storage - attribute \src "ls180.v:1463.11-1463.32" + attribute \src "ls180.v:1462.11-1462.32" wire width 3 \main_sdcore_cmd_count - attribute \src "ls180.v:1798.11-1798.55" + attribute \src "ls180.v:1797.11-1797.55" wire width 3 \main_sdcore_cmd_count_sdcore_fsm_next_value2 - attribute \src "ls180.v:1799.5-1799.52" + attribute \src "ls180.v:1798.5-1798.52" wire \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 - attribute \src "ls180.v:1464.5-1464.25" + attribute \src "ls180.v:1463.5-1463.25" wire \main_sdcore_cmd_done - attribute \src "ls180.v:1794.5-1794.48" + attribute \src "ls180.v:1793.5-1793.48" wire \main_sdcore_cmd_done_sdcore_fsm_next_value0 - attribute \src "ls180.v:1795.5-1795.51" + attribute \src "ls180.v:1794.5-1794.51" wire \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 - attribute \src "ls180.v:1465.5-1465.26" + attribute \src "ls180.v:1464.5-1464.26" wire \main_sdcore_cmd_error - attribute \src "ls180.v:1802.5-1802.49" + attribute \src "ls180.v:1801.5-1801.49" wire \main_sdcore_cmd_error_sdcore_fsm_next_value4 - attribute \src "ls180.v:1803.5-1803.52" + attribute \src "ls180.v:1802.5-1802.52" wire \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 - attribute \src "ls180.v:1317.12-1317.40" + attribute \src "ls180.v:1316.12-1316.40" wire width 4 \main_sdcore_cmd_event_status - attribute \src "ls180.v:1318.6-1318.30" + attribute \src "ls180.v:1317.6-1317.30" wire \main_sdcore_cmd_event_we - attribute \src "ls180.v:1315.13-1315.44" + attribute \src "ls180.v:1314.13-1314.44" wire width 128 \main_sdcore_cmd_response_status - attribute \src "ls180.v:1810.13-1810.67" + attribute \src "ls180.v:1809.13-1809.67" wire width 128 \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 - attribute \src "ls180.v:1811.5-1811.62" + attribute \src "ls180.v:1810.5-1810.62" wire \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 - attribute \src "ls180.v:1316.6-1316.33" + attribute \src "ls180.v:1315.6-1315.33" wire \main_sdcore_cmd_response_we - attribute \src "ls180.v:1312.6-1312.28" + attribute \src "ls180.v:1311.6-1311.28" wire \main_sdcore_cmd_send_r - attribute \src "ls180.v:1311.6-1311.29" + attribute \src "ls180.v:1310.6-1310.29" wire \main_sdcore_cmd_send_re - attribute \src "ls180.v:1314.5-1314.27" + attribute \src "ls180.v:1313.5-1313.27" wire \main_sdcore_cmd_send_w - attribute \src "ls180.v:1313.6-1313.29" + attribute \src "ls180.v:1312.6-1312.29" wire \main_sdcore_cmd_send_we - attribute \src "ls180.v:1466.5-1466.28" + attribute \src "ls180.v:1465.5-1465.28" wire \main_sdcore_cmd_timeout - attribute \src "ls180.v:1804.5-1804.51" + attribute \src "ls180.v:1803.5-1803.51" wire \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 - attribute \src "ls180.v:1805.5-1805.54" + attribute \src "ls180.v:1804.5-1804.54" wire \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 - attribute \src "ls180.v:1462.12-1462.32" + attribute \src "ls180.v:1461.12-1461.32" wire width 2 \main_sdcore_cmd_type - attribute \src "ls180.v:1424.11-1424.40" + attribute \src "ls180.v:1423.11-1423.40" wire width 4 \main_sdcore_crc16_checker_cnt - attribute \src "ls180.v:1430.5-1430.39" + attribute \src "ls180.v:1429.5-1429.39" wire \main_sdcore_crc16_checker_crc0_clr - attribute \src "ls180.v:1429.12-1429.46" + attribute \src "ls180.v:1428.12-1428.46" wire width 16 \main_sdcore_crc16_checker_crc0_crc - attribute \src "ls180.v:1425.12-1425.50" + attribute \src "ls180.v:1424.12-1424.50" wire width 16 \main_sdcore_crc16_checker_crc0_crcreg0 - attribute \src "ls180.v:1426.13-1426.51" + attribute \src "ls180.v:1425.13-1425.51" wire width 16 \main_sdcore_crc16_checker_crc0_crcreg1 - attribute \src "ls180.v:1427.13-1427.51" + attribute \src "ls180.v:1426.13-1426.51" wire width 16 \main_sdcore_crc16_checker_crc0_crcreg2 - attribute \src "ls180.v:1431.6-1431.43" + attribute \src "ls180.v:1430.6-1430.43" wire \main_sdcore_crc16_checker_crc0_enable - attribute \src "ls180.v:1428.12-1428.46" + attribute \src "ls180.v:1427.12-1427.46" wire width 2 \main_sdcore_crc16_checker_crc0_val - attribute \src "ls180.v:1437.5-1437.39" + attribute \src "ls180.v:1436.5-1436.39" wire \main_sdcore_crc16_checker_crc1_clr - attribute \src "ls180.v:1436.12-1436.46" + attribute \src "ls180.v:1435.12-1435.46" wire width 16 \main_sdcore_crc16_checker_crc1_crc - attribute \src "ls180.v:1432.12-1432.50" + attribute \src "ls180.v:1431.12-1431.50" wire width 16 \main_sdcore_crc16_checker_crc1_crcreg0 - attribute \src "ls180.v:1433.13-1433.51" + attribute \src "ls180.v:1432.13-1432.51" wire width 16 \main_sdcore_crc16_checker_crc1_crcreg1 - attribute \src "ls180.v:1434.13-1434.51" + attribute \src "ls180.v:1433.13-1433.51" wire width 16 \main_sdcore_crc16_checker_crc1_crcreg2 - attribute \src "ls180.v:1438.6-1438.43" + attribute \src "ls180.v:1437.6-1437.43" wire \main_sdcore_crc16_checker_crc1_enable - attribute \src "ls180.v:1435.12-1435.46" + attribute \src "ls180.v:1434.12-1434.46" wire width 2 \main_sdcore_crc16_checker_crc1_val - attribute \src "ls180.v:1444.5-1444.39" + attribute \src "ls180.v:1443.5-1443.39" wire \main_sdcore_crc16_checker_crc2_clr - attribute \src "ls180.v:1443.12-1443.46" + attribute \src "ls180.v:1442.12-1442.46" wire width 16 \main_sdcore_crc16_checker_crc2_crc - attribute \src "ls180.v:1439.12-1439.50" + attribute \src "ls180.v:1438.12-1438.50" wire width 16 \main_sdcore_crc16_checker_crc2_crcreg0 - attribute \src "ls180.v:1440.13-1440.51" + attribute \src "ls180.v:1439.13-1439.51" wire width 16 \main_sdcore_crc16_checker_crc2_crcreg1 - attribute \src "ls180.v:1441.13-1441.51" + attribute \src "ls180.v:1440.13-1440.51" wire width 16 \main_sdcore_crc16_checker_crc2_crcreg2 - attribute \src "ls180.v:1445.6-1445.43" + attribute \src "ls180.v:1444.6-1444.43" wire \main_sdcore_crc16_checker_crc2_enable - attribute \src "ls180.v:1442.12-1442.46" + attribute \src "ls180.v:1441.12-1441.46" wire width 2 \main_sdcore_crc16_checker_crc2_val - attribute \src "ls180.v:1451.5-1451.39" + attribute \src "ls180.v:1450.5-1450.39" wire \main_sdcore_crc16_checker_crc3_clr - attribute \src "ls180.v:1450.12-1450.46" + attribute \src "ls180.v:1449.12-1449.46" wire width 16 \main_sdcore_crc16_checker_crc3_crc - attribute \src "ls180.v:1446.12-1446.50" + attribute \src "ls180.v:1445.12-1445.50" wire width 16 \main_sdcore_crc16_checker_crc3_crcreg0 - attribute \src "ls180.v:1447.13-1447.51" + attribute \src "ls180.v:1446.13-1446.51" wire width 16 \main_sdcore_crc16_checker_crc3_crcreg1 - attribute \src "ls180.v:1448.13-1448.51" + attribute \src "ls180.v:1447.13-1447.51" wire width 16 \main_sdcore_crc16_checker_crc3_crcreg2 - attribute \src "ls180.v:1452.6-1452.43" + attribute \src "ls180.v:1451.6-1451.43" wire \main_sdcore_crc16_checker_crc3_enable - attribute \src "ls180.v:1449.12-1449.46" + attribute \src "ls180.v:1448.12-1448.46" wire width 2 \main_sdcore_crc16_checker_crc3_val - attribute \src "ls180.v:1453.12-1453.45" + attribute \src "ls180.v:1452.12-1452.45" wire width 16 \main_sdcore_crc16_checker_crctmp0 - attribute \src "ls180.v:1454.12-1454.45" + attribute \src "ls180.v:1453.12-1453.45" wire width 16 \main_sdcore_crc16_checker_crctmp1 - attribute \src "ls180.v:1455.12-1455.45" + attribute \src "ls180.v:1454.12-1454.45" wire width 16 \main_sdcore_crc16_checker_crctmp2 - attribute \src "ls180.v:1456.12-1456.45" + attribute \src "ls180.v:1455.12-1455.45" wire width 16 \main_sdcore_crc16_checker_crctmp3 - attribute \src "ls180.v:1458.12-1458.43" + attribute \src "ls180.v:1457.12-1457.43" wire width 16 \main_sdcore_crc16_checker_fifo0 - attribute \src "ls180.v:1459.12-1459.43" + attribute \src "ls180.v:1458.12-1458.43" wire width 16 \main_sdcore_crc16_checker_fifo1 - attribute \src "ls180.v:1460.12-1460.43" + attribute \src "ls180.v:1459.12-1459.43" wire width 16 \main_sdcore_crc16_checker_fifo2 - attribute \src "ls180.v:1461.12-1461.43" + attribute \src "ls180.v:1460.12-1460.43" wire width 16 \main_sdcore_crc16_checker_fifo3 - attribute \src "ls180.v:1415.5-1415.41" + attribute \src "ls180.v:1414.5-1414.41" wire \main_sdcore_crc16_checker_sink_first - attribute \src "ls180.v:1416.5-1416.40" + attribute \src "ls180.v:1415.5-1415.40" wire \main_sdcore_crc16_checker_sink_last - attribute \src "ls180.v:1417.11-1417.54" + attribute \src "ls180.v:1416.11-1416.54" wire width 8 \main_sdcore_crc16_checker_sink_payload_data - attribute \src "ls180.v:1414.5-1414.41" - wire \main_sdcore_crc16_checker_sink_ready attribute \src "ls180.v:1413.5-1413.41" + wire \main_sdcore_crc16_checker_sink_ready + attribute \src "ls180.v:1412.5-1412.41" wire \main_sdcore_crc16_checker_sink_valid - attribute \src "ls180.v:1420.5-1420.43" + attribute \src "ls180.v:1419.5-1419.43" wire \main_sdcore_crc16_checker_source_first - attribute \src "ls180.v:1421.6-1421.43" + attribute \src "ls180.v:1420.6-1420.43" wire \main_sdcore_crc16_checker_source_last - attribute \src "ls180.v:1422.12-1422.57" + attribute \src "ls180.v:1421.12-1421.57" wire width 8 \main_sdcore_crc16_checker_source_payload_data - attribute \src "ls180.v:1419.6-1419.44" + attribute \src "ls180.v:1418.6-1418.44" wire \main_sdcore_crc16_checker_source_ready - attribute \src "ls180.v:1418.5-1418.43" + attribute \src "ls180.v:1417.5-1417.43" wire \main_sdcore_crc16_checker_source_valid - attribute \src "ls180.v:1423.11-1423.40" + attribute \src "ls180.v:1422.11-1422.40" wire width 8 \main_sdcore_crc16_checker_val - attribute \src "ls180.v:1457.5-1457.36" + attribute \src "ls180.v:1456.5-1456.36" wire \main_sdcore_crc16_checker_valid - attribute \src "ls180.v:1380.11-1380.41" + attribute \src "ls180.v:1379.11-1379.41" wire width 3 \main_sdcore_crc16_inserter_cnt - attribute \src "ls180.v:1790.11-1790.80" + attribute \src "ls180.v:1789.11-1789.80" wire width 3 \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 - attribute \src "ls180.v:1791.5-1791.77" + attribute \src "ls180.v:1790.5-1790.77" wire \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 - attribute \src "ls180.v:1386.6-1386.41" + attribute \src "ls180.v:1385.6-1385.41" wire \main_sdcore_crc16_inserter_crc0_clr - attribute \src "ls180.v:1385.12-1385.47" + attribute \src "ls180.v:1384.12-1384.47" wire width 16 \main_sdcore_crc16_inserter_crc0_crc - attribute \src "ls180.v:1381.12-1381.51" + attribute \src "ls180.v:1380.12-1380.51" wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg0 - attribute \src "ls180.v:1382.13-1382.52" + attribute \src "ls180.v:1381.13-1381.52" wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg1 - attribute \src "ls180.v:1383.13-1383.52" + attribute \src "ls180.v:1382.13-1382.52" wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg2 - attribute \src "ls180.v:1387.6-1387.44" + attribute \src "ls180.v:1386.6-1386.44" wire \main_sdcore_crc16_inserter_crc0_enable - attribute \src "ls180.v:1384.12-1384.47" + attribute \src "ls180.v:1383.12-1383.47" wire width 2 \main_sdcore_crc16_inserter_crc0_val - attribute \src "ls180.v:1393.6-1393.41" + attribute \src "ls180.v:1392.6-1392.41" wire \main_sdcore_crc16_inserter_crc1_clr - attribute \src "ls180.v:1392.12-1392.47" + attribute \src "ls180.v:1391.12-1391.47" wire width 16 \main_sdcore_crc16_inserter_crc1_crc - attribute \src "ls180.v:1388.12-1388.51" + attribute \src "ls180.v:1387.12-1387.51" wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg0 - attribute \src "ls180.v:1389.13-1389.52" + attribute \src "ls180.v:1388.13-1388.52" wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg1 - attribute \src "ls180.v:1390.13-1390.52" + attribute \src "ls180.v:1389.13-1389.52" wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg2 - attribute \src "ls180.v:1394.6-1394.44" + attribute \src "ls180.v:1393.6-1393.44" wire \main_sdcore_crc16_inserter_crc1_enable - attribute \src "ls180.v:1391.12-1391.47" + attribute \src "ls180.v:1390.12-1390.47" wire width 2 \main_sdcore_crc16_inserter_crc1_val - attribute \src "ls180.v:1400.6-1400.41" + attribute \src "ls180.v:1399.6-1399.41" wire \main_sdcore_crc16_inserter_crc2_clr - attribute \src "ls180.v:1399.12-1399.47" + attribute \src "ls180.v:1398.12-1398.47" wire width 16 \main_sdcore_crc16_inserter_crc2_crc - attribute \src "ls180.v:1395.12-1395.51" + attribute \src "ls180.v:1394.12-1394.51" wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg0 - attribute \src "ls180.v:1396.13-1396.52" + attribute \src "ls180.v:1395.13-1395.52" wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg1 - attribute \src "ls180.v:1397.13-1397.52" + attribute \src "ls180.v:1396.13-1396.52" wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg2 - attribute \src "ls180.v:1401.6-1401.44" + attribute \src "ls180.v:1400.6-1400.44" wire \main_sdcore_crc16_inserter_crc2_enable - attribute \src "ls180.v:1398.12-1398.47" + attribute \src "ls180.v:1397.12-1397.47" wire width 2 \main_sdcore_crc16_inserter_crc2_val - attribute \src "ls180.v:1407.6-1407.41" + attribute \src "ls180.v:1406.6-1406.41" wire \main_sdcore_crc16_inserter_crc3_clr - attribute \src "ls180.v:1406.12-1406.47" + attribute \src "ls180.v:1405.12-1405.47" wire width 16 \main_sdcore_crc16_inserter_crc3_crc - attribute \src "ls180.v:1402.12-1402.51" + attribute \src "ls180.v:1401.12-1401.51" wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg0 - attribute \src "ls180.v:1403.13-1403.52" + attribute \src "ls180.v:1402.13-1402.52" wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg1 - attribute \src "ls180.v:1404.13-1404.52" + attribute \src "ls180.v:1403.13-1403.52" wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg2 - attribute \src "ls180.v:1408.6-1408.44" + attribute \src "ls180.v:1407.6-1407.44" wire \main_sdcore_crc16_inserter_crc3_enable - attribute \src "ls180.v:1405.12-1405.47" + attribute \src "ls180.v:1404.12-1404.47" wire width 2 \main_sdcore_crc16_inserter_crc3_val - attribute \src "ls180.v:1409.12-1409.46" + attribute \src "ls180.v:1408.12-1408.46" wire width 16 \main_sdcore_crc16_inserter_crctmp0 - attribute \src "ls180.v:1782.12-1782.85" + attribute \src "ls180.v:1781.12-1781.85" wire width 16 \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 - attribute \src "ls180.v:1783.5-1783.81" + attribute \src "ls180.v:1782.5-1782.81" wire \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 - attribute \src "ls180.v:1410.12-1410.46" + attribute \src "ls180.v:1409.12-1409.46" wire width 16 \main_sdcore_crc16_inserter_crctmp1 - attribute \src "ls180.v:1784.12-1784.85" + attribute \src "ls180.v:1783.12-1783.85" wire width 16 \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 - attribute \src "ls180.v:1785.5-1785.81" + attribute \src "ls180.v:1784.5-1784.81" wire \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 - attribute \src "ls180.v:1411.12-1411.46" + attribute \src "ls180.v:1410.12-1410.46" wire width 16 \main_sdcore_crc16_inserter_crctmp2 - attribute \src "ls180.v:1786.12-1786.85" + attribute \src "ls180.v:1785.12-1785.85" wire width 16 \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 - attribute \src "ls180.v:1787.5-1787.81" + attribute \src "ls180.v:1786.5-1786.81" wire \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 - attribute \src "ls180.v:1412.12-1412.46" + attribute \src "ls180.v:1411.12-1411.46" wire width 16 \main_sdcore_crc16_inserter_crctmp3 - attribute \src "ls180.v:1788.12-1788.85" + attribute \src "ls180.v:1787.12-1787.85" wire width 16 \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 - attribute \src "ls180.v:1789.5-1789.81" + attribute \src "ls180.v:1788.5-1788.81" wire \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 - attribute \src "ls180.v:1372.6-1372.43" + attribute \src "ls180.v:1371.6-1371.43" wire \main_sdcore_crc16_inserter_sink_first - attribute \src "ls180.v:1373.6-1373.42" + attribute \src "ls180.v:1372.6-1372.42" wire \main_sdcore_crc16_inserter_sink_last - attribute \src "ls180.v:1374.12-1374.56" + attribute \src "ls180.v:1373.12-1373.56" wire width 8 \main_sdcore_crc16_inserter_sink_payload_data - attribute \src "ls180.v:1371.5-1371.42" + attribute \src "ls180.v:1370.5-1370.42" wire \main_sdcore_crc16_inserter_sink_ready - attribute \src "ls180.v:1370.6-1370.43" + attribute \src "ls180.v:1369.6-1369.43" wire \main_sdcore_crc16_inserter_sink_valid - attribute \src "ls180.v:1377.5-1377.44" + attribute \src "ls180.v:1376.5-1376.44" wire \main_sdcore_crc16_inserter_source_first - attribute \src "ls180.v:1378.5-1378.43" + attribute \src "ls180.v:1377.5-1377.43" wire \main_sdcore_crc16_inserter_source_last - attribute \src "ls180.v:1379.11-1379.57" + attribute \src "ls180.v:1378.11-1378.57" wire width 8 \main_sdcore_crc16_inserter_source_payload_data - attribute \src "ls180.v:1376.5-1376.44" - wire \main_sdcore_crc16_inserter_source_ready attribute \src "ls180.v:1375.5-1375.44" + wire \main_sdcore_crc16_inserter_source_ready + attribute \src "ls180.v:1374.5-1374.44" wire \main_sdcore_crc16_inserter_source_valid - attribute \src "ls180.v:1368.6-1368.35" + attribute \src "ls180.v:1367.6-1367.35" wire \main_sdcore_crc7_inserter_clr - attribute \src "ls180.v:1367.11-1367.40" + attribute \src "ls180.v:1366.11-1366.40" wire width 7 \main_sdcore_crc7_inserter_crc - attribute \src "ls180.v:1325.11-1325.44" + attribute \src "ls180.v:1324.11-1324.44" wire width 7 \main_sdcore_crc7_inserter_crcreg0 - attribute \src "ls180.v:1326.12-1326.45" + attribute \src "ls180.v:1325.12-1325.45" wire width 7 \main_sdcore_crc7_inserter_crcreg1 - attribute \src "ls180.v:1335.12-1335.46" + attribute \src "ls180.v:1334.12-1334.46" wire width 7 \main_sdcore_crc7_inserter_crcreg10 - attribute \src "ls180.v:1336.12-1336.46" + attribute \src "ls180.v:1335.12-1335.46" wire width 7 \main_sdcore_crc7_inserter_crcreg11 - attribute \src "ls180.v:1337.12-1337.46" + attribute \src "ls180.v:1336.12-1336.46" wire width 7 \main_sdcore_crc7_inserter_crcreg12 - attribute \src "ls180.v:1338.12-1338.46" + attribute \src "ls180.v:1337.12-1337.46" wire width 7 \main_sdcore_crc7_inserter_crcreg13 - attribute \src "ls180.v:1339.12-1339.46" + attribute \src "ls180.v:1338.12-1338.46" wire width 7 \main_sdcore_crc7_inserter_crcreg14 - attribute \src "ls180.v:1340.12-1340.46" + attribute \src "ls180.v:1339.12-1339.46" wire width 7 \main_sdcore_crc7_inserter_crcreg15 - attribute \src "ls180.v:1341.12-1341.46" + attribute \src "ls180.v:1340.12-1340.46" wire width 7 \main_sdcore_crc7_inserter_crcreg16 - attribute \src "ls180.v:1342.12-1342.46" + attribute \src "ls180.v:1341.12-1341.46" wire width 7 \main_sdcore_crc7_inserter_crcreg17 - attribute \src "ls180.v:1343.12-1343.46" + attribute \src "ls180.v:1342.12-1342.46" wire width 7 \main_sdcore_crc7_inserter_crcreg18 - attribute \src "ls180.v:1344.12-1344.46" + attribute \src "ls180.v:1343.12-1343.46" wire width 7 \main_sdcore_crc7_inserter_crcreg19 - attribute \src "ls180.v:1327.12-1327.45" + attribute \src "ls180.v:1326.12-1326.45" wire width 7 \main_sdcore_crc7_inserter_crcreg2 - attribute \src "ls180.v:1345.12-1345.46" + attribute \src "ls180.v:1344.12-1344.46" wire width 7 \main_sdcore_crc7_inserter_crcreg20 - attribute \src "ls180.v:1346.12-1346.46" + attribute \src "ls180.v:1345.12-1345.46" wire width 7 \main_sdcore_crc7_inserter_crcreg21 - attribute \src "ls180.v:1347.12-1347.46" + attribute \src "ls180.v:1346.12-1346.46" wire width 7 \main_sdcore_crc7_inserter_crcreg22 - attribute \src "ls180.v:1348.12-1348.46" + attribute \src "ls180.v:1347.12-1347.46" wire width 7 \main_sdcore_crc7_inserter_crcreg23 - attribute \src "ls180.v:1349.12-1349.46" + attribute \src "ls180.v:1348.12-1348.46" wire width 7 \main_sdcore_crc7_inserter_crcreg24 - attribute \src "ls180.v:1350.12-1350.46" + attribute \src "ls180.v:1349.12-1349.46" wire width 7 \main_sdcore_crc7_inserter_crcreg25 - attribute \src "ls180.v:1351.12-1351.46" + attribute \src "ls180.v:1350.12-1350.46" wire width 7 \main_sdcore_crc7_inserter_crcreg26 - attribute \src "ls180.v:1352.12-1352.46" + attribute \src "ls180.v:1351.12-1351.46" wire width 7 \main_sdcore_crc7_inserter_crcreg27 - attribute \src "ls180.v:1353.12-1353.46" + attribute \src "ls180.v:1352.12-1352.46" wire width 7 \main_sdcore_crc7_inserter_crcreg28 - attribute \src "ls180.v:1354.12-1354.46" + attribute \src "ls180.v:1353.12-1353.46" wire width 7 \main_sdcore_crc7_inserter_crcreg29 - attribute \src "ls180.v:1328.12-1328.45" + attribute \src "ls180.v:1327.12-1327.45" wire width 7 \main_sdcore_crc7_inserter_crcreg3 - attribute \src "ls180.v:1355.12-1355.46" + attribute \src "ls180.v:1354.12-1354.46" wire width 7 \main_sdcore_crc7_inserter_crcreg30 - attribute \src "ls180.v:1356.12-1356.46" + attribute \src "ls180.v:1355.12-1355.46" wire width 7 \main_sdcore_crc7_inserter_crcreg31 - attribute \src "ls180.v:1357.12-1357.46" + attribute \src "ls180.v:1356.12-1356.46" wire width 7 \main_sdcore_crc7_inserter_crcreg32 - attribute \src "ls180.v:1358.12-1358.46" + attribute \src "ls180.v:1357.12-1357.46" wire width 7 \main_sdcore_crc7_inserter_crcreg33 - attribute \src "ls180.v:1359.12-1359.46" + attribute \src "ls180.v:1358.12-1358.46" wire width 7 \main_sdcore_crc7_inserter_crcreg34 - attribute \src "ls180.v:1360.12-1360.46" + attribute \src "ls180.v:1359.12-1359.46" wire width 7 \main_sdcore_crc7_inserter_crcreg35 - attribute \src "ls180.v:1361.12-1361.46" + attribute \src "ls180.v:1360.12-1360.46" wire width 7 \main_sdcore_crc7_inserter_crcreg36 - attribute \src "ls180.v:1362.12-1362.46" + attribute \src "ls180.v:1361.12-1361.46" wire width 7 \main_sdcore_crc7_inserter_crcreg37 - attribute \src "ls180.v:1363.12-1363.46" + attribute \src "ls180.v:1362.12-1362.46" wire width 7 \main_sdcore_crc7_inserter_crcreg38 - attribute \src "ls180.v:1364.12-1364.46" + attribute \src "ls180.v:1363.12-1363.46" wire width 7 \main_sdcore_crc7_inserter_crcreg39 - attribute \src "ls180.v:1329.12-1329.45" + attribute \src "ls180.v:1328.12-1328.45" wire width 7 \main_sdcore_crc7_inserter_crcreg4 - attribute \src "ls180.v:1365.12-1365.46" + attribute \src "ls180.v:1364.12-1364.46" wire width 7 \main_sdcore_crc7_inserter_crcreg40 - attribute \src "ls180.v:1330.12-1330.45" + attribute \src "ls180.v:1329.12-1329.45" wire width 7 \main_sdcore_crc7_inserter_crcreg5 - attribute \src "ls180.v:1331.12-1331.45" + attribute \src "ls180.v:1330.12-1330.45" wire width 7 \main_sdcore_crc7_inserter_crcreg6 - attribute \src "ls180.v:1332.12-1332.45" + attribute \src "ls180.v:1331.12-1331.45" wire width 7 \main_sdcore_crc7_inserter_crcreg7 - attribute \src "ls180.v:1333.12-1333.45" + attribute \src "ls180.v:1332.12-1332.45" wire width 7 \main_sdcore_crc7_inserter_crcreg8 - attribute \src "ls180.v:1334.12-1334.45" + attribute \src "ls180.v:1333.12-1333.45" wire width 7 \main_sdcore_crc7_inserter_crcreg9 - attribute \src "ls180.v:1369.6-1369.38" + attribute \src "ls180.v:1368.6-1368.38" wire \main_sdcore_crc7_inserter_enable - attribute \src "ls180.v:1366.13-1366.42" + attribute \src "ls180.v:1365.13-1365.42" wire width 40 \main_sdcore_crc7_inserter_val - attribute \src "ls180.v:1468.12-1468.34" + attribute \src "ls180.v:1467.12-1467.34" wire width 32 \main_sdcore_data_count - attribute \src "ls180.v:1800.12-1800.57" + attribute \src "ls180.v:1799.12-1799.57" wire width 32 \main_sdcore_data_count_sdcore_fsm_next_value3 - attribute \src "ls180.v:1801.5-1801.53" + attribute \src "ls180.v:1800.5-1800.53" wire \main_sdcore_data_count_sdcore_fsm_next_value_ce3 - attribute \src "ls180.v:1469.5-1469.26" + attribute \src "ls180.v:1468.5-1468.26" wire \main_sdcore_data_done - attribute \src "ls180.v:1796.5-1796.49" + attribute \src "ls180.v:1795.5-1795.49" wire \main_sdcore_data_done_sdcore_fsm_next_value1 - attribute \src "ls180.v:1797.5-1797.52" + attribute \src "ls180.v:1796.5-1796.52" wire \main_sdcore_data_done_sdcore_fsm_next_value_ce1 - attribute \src "ls180.v:1470.5-1470.27" + attribute \src "ls180.v:1469.5-1469.27" wire \main_sdcore_data_error - attribute \src "ls180.v:1806.5-1806.50" + attribute \src "ls180.v:1805.5-1805.50" wire \main_sdcore_data_error_sdcore_fsm_next_value6 - attribute \src "ls180.v:1807.5-1807.53" + attribute \src "ls180.v:1806.5-1806.53" wire \main_sdcore_data_error_sdcore_fsm_next_value_ce6 - attribute \src "ls180.v:1319.12-1319.41" + attribute \src "ls180.v:1318.12-1318.41" wire width 4 \main_sdcore_data_event_status - attribute \src "ls180.v:1320.6-1320.31" + attribute \src "ls180.v:1319.6-1319.31" wire \main_sdcore_data_event_we - attribute \src "ls180.v:1471.5-1471.29" + attribute \src "ls180.v:1470.5-1470.29" wire \main_sdcore_data_timeout - attribute \src "ls180.v:1808.5-1808.52" + attribute \src "ls180.v:1807.5-1807.52" wire \main_sdcore_data_timeout_sdcore_fsm_next_value7 - attribute \src "ls180.v:1809.5-1809.55" + attribute \src "ls180.v:1808.5-1808.55" wire \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 - attribute \src "ls180.v:1467.12-1467.33" + attribute \src "ls180.v:1466.12-1466.33" wire width 2 \main_sdcore_data_type - attribute \src "ls180.v:1299.6-1299.33" + attribute \src "ls180.v:1298.6-1298.33" wire \main_sdcore_sink_sink_first - attribute \src "ls180.v:1300.6-1300.32" + attribute \src "ls180.v:1299.6-1299.32" wire \main_sdcore_sink_sink_last - attribute \src "ls180.v:1301.12-1301.46" + attribute \src "ls180.v:1300.12-1300.46" wire width 8 \main_sdcore_sink_sink_payload_data - attribute \src "ls180.v:1298.6-1298.33" - wire \main_sdcore_sink_sink_ready attribute \src "ls180.v:1297.6-1297.33" + wire \main_sdcore_sink_sink_ready + attribute \src "ls180.v:1296.6-1296.33" wire \main_sdcore_sink_sink_valid - attribute \src "ls180.v:1304.6-1304.37" + attribute \src "ls180.v:1303.6-1303.37" wire \main_sdcore_source_source_first - attribute \src "ls180.v:1305.6-1305.36" + attribute \src "ls180.v:1304.6-1304.36" wire \main_sdcore_source_source_last - attribute \src "ls180.v:1306.12-1306.50" + attribute \src "ls180.v:1305.12-1305.50" wire width 8 \main_sdcore_source_source_payload_data - attribute \src "ls180.v:1303.6-1303.37" - wire \main_sdcore_source_source_ready attribute \src "ls180.v:1302.6-1302.37" + wire \main_sdcore_source_source_ready + attribute \src "ls180.v:1301.6-1301.37" wire \main_sdcore_source_source_valid - attribute \src "ls180.v:1617.6-1617.38" + attribute \src "ls180.v:1616.6-1616.38" wire \main_sdmem2block_converter_first - attribute \src "ls180.v:1618.6-1618.37" + attribute \src "ls180.v:1617.6-1617.37" wire \main_sdmem2block_converter_last - attribute \src "ls180.v:1616.11-1616.41" + attribute \src "ls180.v:1615.11-1615.41" wire width 2 \main_sdmem2block_converter_mux - attribute \src "ls180.v:1607.6-1607.43" + attribute \src "ls180.v:1606.6-1606.43" wire \main_sdmem2block_converter_sink_first - attribute \src "ls180.v:1608.6-1608.42" + attribute \src "ls180.v:1607.6-1607.42" wire \main_sdmem2block_converter_sink_last - attribute \src "ls180.v:1609.13-1609.57" + attribute \src "ls180.v:1608.13-1608.57" wire width 32 \main_sdmem2block_converter_sink_payload_data - attribute \src "ls180.v:1606.6-1606.43" - wire \main_sdmem2block_converter_sink_ready attribute \src "ls180.v:1605.6-1605.43" + wire \main_sdmem2block_converter_sink_ready + attribute \src "ls180.v:1604.6-1604.43" wire \main_sdmem2block_converter_sink_valid - attribute \src "ls180.v:1612.6-1612.45" + attribute \src "ls180.v:1611.6-1611.45" wire \main_sdmem2block_converter_source_first - attribute \src "ls180.v:1613.6-1613.44" + attribute \src "ls180.v:1612.6-1612.44" wire \main_sdmem2block_converter_source_last - attribute \src "ls180.v:1614.11-1614.57" + attribute \src "ls180.v:1613.11-1613.57" wire width 8 \main_sdmem2block_converter_source_payload_data - attribute \src "ls180.v:1615.6-1615.65" + attribute \src "ls180.v:1614.6-1614.65" wire \main_sdmem2block_converter_source_payload_valid_token_count - attribute \src "ls180.v:1611.6-1611.45" - wire \main_sdmem2block_converter_source_ready attribute \src "ls180.v:1610.6-1610.45" + wire \main_sdmem2block_converter_source_ready + attribute \src "ls180.v:1609.6-1609.45" wire \main_sdmem2block_converter_source_valid - attribute \src "ls180.v:1601.13-1601.38" + attribute \src "ls180.v:1600.13-1600.38" wire width 32 \main_sdmem2block_dma_base - attribute \src "ls180.v:1590.5-1590.33" + attribute \src "ls180.v:1589.5-1589.33" wire \main_sdmem2block_dma_base_re - attribute \src "ls180.v:1589.12-1589.45" + attribute \src "ls180.v:1588.12-1588.45" wire width 64 \main_sdmem2block_dma_base_storage - attribute \src "ls180.v:1588.12-1588.37" + attribute \src "ls180.v:1587.12-1587.37" wire width 32 \main_sdmem2block_dma_data - attribute \src "ls180.v:1818.12-1818.67" + attribute \src "ls180.v:1817.12-1817.67" wire width 32 \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value - attribute \src "ls180.v:1819.5-1819.63" + attribute \src "ls180.v:1818.5-1818.63" wire \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce - attribute \src "ls180.v:1595.5-1595.37" + attribute \src "ls180.v:1594.5-1594.37" wire \main_sdmem2block_dma_done_status - attribute \src "ls180.v:1596.6-1596.34" + attribute \src "ls180.v:1595.6-1595.34" wire \main_sdmem2block_dma_done_we - attribute \src "ls180.v:1594.5-1594.35" + attribute \src "ls180.v:1593.5-1593.35" wire \main_sdmem2block_dma_enable_re - attribute \src "ls180.v:1593.5-1593.40" + attribute \src "ls180.v:1592.5-1592.40" wire \main_sdmem2block_dma_enable_storage - attribute \src "ls180.v:1603.13-1603.40" + attribute \src "ls180.v:1602.13-1602.40" wire width 32 \main_sdmem2block_dma_length - attribute \src "ls180.v:1592.5-1592.35" + attribute \src "ls180.v:1591.5-1591.35" wire \main_sdmem2block_dma_length_re - attribute \src "ls180.v:1591.12-1591.47" + attribute \src "ls180.v:1590.12-1590.47" wire width 32 \main_sdmem2block_dma_length_storage - attribute \src "ls180.v:1598.5-1598.33" + attribute \src "ls180.v:1597.5-1597.33" wire \main_sdmem2block_dma_loop_re - attribute \src "ls180.v:1597.5-1597.38" + attribute \src "ls180.v:1596.5-1596.38" wire \main_sdmem2block_dma_loop_storage - attribute \src "ls180.v:1602.12-1602.39" + attribute \src "ls180.v:1601.12-1601.39" wire width 32 \main_sdmem2block_dma_offset - attribute \src "ls180.v:1822.12-1822.79" + attribute \src "ls180.v:1821.12-1821.79" wire width 32 \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value - attribute \src "ls180.v:1823.5-1823.75" + attribute \src "ls180.v:1822.5-1822.75" wire \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce - attribute \src "ls180.v:1599.13-1599.47" + attribute \src "ls180.v:1598.13-1598.47" wire width 32 \main_sdmem2block_dma_offset_status - attribute \src "ls180.v:1600.6-1600.36" + attribute \src "ls180.v:1599.6-1599.36" wire \main_sdmem2block_dma_offset_we - attribute \src "ls180.v:1604.6-1604.32" + attribute \src "ls180.v:1603.6-1603.32" wire \main_sdmem2block_dma_reset - attribute \src "ls180.v:1581.5-1581.35" + attribute \src "ls180.v:1580.5-1580.35" wire \main_sdmem2block_dma_sink_last - attribute \src "ls180.v:1582.12-1582.53" + attribute \src "ls180.v:1581.12-1581.53" wire width 32 \main_sdmem2block_dma_sink_payload_address - attribute \src "ls180.v:1580.5-1580.36" - wire \main_sdmem2block_dma_sink_ready attribute \src "ls180.v:1579.5-1579.36" + wire \main_sdmem2block_dma_sink_ready + attribute \src "ls180.v:1578.5-1578.36" wire \main_sdmem2block_dma_sink_valid - attribute \src "ls180.v:1585.5-1585.38" + attribute \src "ls180.v:1584.5-1584.38" wire \main_sdmem2block_dma_source_first - attribute \src "ls180.v:1586.5-1586.37" + attribute \src "ls180.v:1585.5-1585.37" wire \main_sdmem2block_dma_source_last - attribute \src "ls180.v:1587.12-1587.52" + attribute \src "ls180.v:1586.12-1586.52" wire width 32 \main_sdmem2block_dma_source_payload_data - attribute \src "ls180.v:1584.6-1584.39" + attribute \src "ls180.v:1583.6-1583.39" wire \main_sdmem2block_dma_source_ready - attribute \src "ls180.v:1583.5-1583.38" + attribute \src "ls180.v:1582.5-1582.38" wire \main_sdmem2block_dma_source_valid - attribute \src "ls180.v:1643.11-1643.40" + attribute \src "ls180.v:1642.11-1642.40" wire width 5 \main_sdmem2block_fifo_consume - attribute \src "ls180.v:1648.6-1648.35" + attribute \src "ls180.v:1647.6-1647.35" wire \main_sdmem2block_fifo_do_read - attribute \src "ls180.v:1652.6-1652.41" + attribute \src "ls180.v:1651.6-1651.41" wire \main_sdmem2block_fifo_fifo_in_first - attribute \src "ls180.v:1653.6-1653.40" + attribute \src "ls180.v:1652.6-1652.40" wire \main_sdmem2block_fifo_fifo_in_last - attribute \src "ls180.v:1651.12-1651.54" + attribute \src "ls180.v:1650.12-1650.54" wire width 8 \main_sdmem2block_fifo_fifo_in_payload_data - attribute \src "ls180.v:1655.6-1655.42" + attribute \src "ls180.v:1654.6-1654.42" wire \main_sdmem2block_fifo_fifo_out_first - attribute \src "ls180.v:1656.6-1656.41" + attribute \src "ls180.v:1655.6-1655.41" wire \main_sdmem2block_fifo_fifo_out_last - attribute \src "ls180.v:1654.12-1654.55" + attribute \src "ls180.v:1653.12-1653.55" wire width 8 \main_sdmem2block_fifo_fifo_out_payload_data - attribute \src "ls180.v:1640.11-1640.38" + attribute \src "ls180.v:1639.11-1639.38" wire width 6 \main_sdmem2block_fifo_level - attribute \src "ls180.v:1642.11-1642.40" + attribute \src "ls180.v:1641.11-1641.40" wire width 5 \main_sdmem2block_fifo_produce - attribute \src "ls180.v:1649.12-1649.44" + attribute \src "ls180.v:1648.12-1648.44" wire width 5 \main_sdmem2block_fifo_rdport_adr - attribute \src "ls180.v:1650.12-1650.46" + attribute \src "ls180.v:1649.12-1649.46" wire width 10 \main_sdmem2block_fifo_rdport_dat_r - attribute \src "ls180.v:1641.5-1641.34" + attribute \src "ls180.v:1640.5-1640.34" wire \main_sdmem2block_fifo_replace - attribute \src "ls180.v:1626.6-1626.38" + attribute \src "ls180.v:1625.6-1625.38" wire \main_sdmem2block_fifo_sink_first - attribute \src "ls180.v:1627.6-1627.37" + attribute \src "ls180.v:1626.6-1626.37" wire \main_sdmem2block_fifo_sink_last - attribute \src "ls180.v:1628.12-1628.51" + attribute \src "ls180.v:1627.12-1627.51" wire width 8 \main_sdmem2block_fifo_sink_payload_data - attribute \src "ls180.v:1625.6-1625.38" - wire \main_sdmem2block_fifo_sink_ready attribute \src "ls180.v:1624.6-1624.38" + wire \main_sdmem2block_fifo_sink_ready + attribute \src "ls180.v:1623.6-1623.38" wire \main_sdmem2block_fifo_sink_valid - attribute \src "ls180.v:1631.6-1631.40" + attribute \src "ls180.v:1630.6-1630.40" wire \main_sdmem2block_fifo_source_first - attribute \src "ls180.v:1632.6-1632.39" + attribute \src "ls180.v:1631.6-1631.39" wire \main_sdmem2block_fifo_source_last - attribute \src "ls180.v:1633.12-1633.53" + attribute \src "ls180.v:1632.12-1632.53" wire width 8 \main_sdmem2block_fifo_source_payload_data - attribute \src "ls180.v:1630.6-1630.40" - wire \main_sdmem2block_fifo_source_ready attribute \src "ls180.v:1629.6-1629.40" + wire \main_sdmem2block_fifo_source_ready + attribute \src "ls180.v:1628.6-1628.40" wire \main_sdmem2block_fifo_source_valid - attribute \src "ls180.v:1638.12-1638.46" + attribute \src "ls180.v:1637.12-1637.46" wire width 10 \main_sdmem2block_fifo_syncfifo_din - attribute \src "ls180.v:1639.12-1639.47" + attribute \src "ls180.v:1638.12-1638.47" wire width 10 \main_sdmem2block_fifo_syncfifo_dout - attribute \src "ls180.v:1636.6-1636.39" + attribute \src "ls180.v:1635.6-1635.39" wire \main_sdmem2block_fifo_syncfifo_re - attribute \src "ls180.v:1637.6-1637.45" + attribute \src "ls180.v:1636.6-1636.45" wire \main_sdmem2block_fifo_syncfifo_readable - attribute \src "ls180.v:1634.6-1634.39" + attribute \src "ls180.v:1633.6-1633.39" wire \main_sdmem2block_fifo_syncfifo_we - attribute \src "ls180.v:1635.6-1635.45" + attribute \src "ls180.v:1634.6-1634.45" wire \main_sdmem2block_fifo_syncfifo_writable - attribute \src "ls180.v:1644.11-1644.43" + attribute \src "ls180.v:1643.11-1643.43" wire width 5 \main_sdmem2block_fifo_wrport_adr - attribute \src "ls180.v:1645.12-1645.46" + attribute \src "ls180.v:1644.12-1644.46" wire width 10 \main_sdmem2block_fifo_wrport_dat_r - attribute \src "ls180.v:1647.12-1647.46" + attribute \src "ls180.v:1646.12-1646.46" wire width 10 \main_sdmem2block_fifo_wrport_dat_w - attribute \src "ls180.v:1646.6-1646.37" + attribute \src "ls180.v:1645.6-1645.37" wire \main_sdmem2block_fifo_wrport_we - attribute \src "ls180.v:1576.6-1576.43" + attribute \src "ls180.v:1575.6-1575.43" wire \main_sdmem2block_source_source_first0 - attribute \src "ls180.v:1621.6-1621.43" + attribute \src "ls180.v:1620.6-1620.43" wire \main_sdmem2block_source_source_first1 - attribute \src "ls180.v:1577.6-1577.42" + attribute \src "ls180.v:1576.6-1576.42" wire \main_sdmem2block_source_source_last0 - attribute \src "ls180.v:1622.6-1622.42" + attribute \src "ls180.v:1621.6-1621.42" wire \main_sdmem2block_source_source_last1 - attribute \src "ls180.v:1578.12-1578.56" + attribute \src "ls180.v:1577.12-1577.56" wire width 8 \main_sdmem2block_source_source_payload_data0 - attribute \src "ls180.v:1623.12-1623.56" + attribute \src "ls180.v:1622.12-1622.56" wire width 8 \main_sdmem2block_source_source_payload_data1 - attribute \src "ls180.v:1575.6-1575.43" + attribute \src "ls180.v:1574.6-1574.43" wire \main_sdmem2block_source_source_ready0 - attribute \src "ls180.v:1620.6-1620.43" + attribute \src "ls180.v:1619.6-1619.43" wire \main_sdmem2block_source_source_ready1 - attribute \src "ls180.v:1574.6-1574.43" + attribute \src "ls180.v:1573.6-1573.43" wire \main_sdmem2block_source_source_valid0 - attribute \src "ls180.v:1619.6-1619.43" + attribute \src "ls180.v:1618.6-1618.43" wire \main_sdmem2block_source_source_valid1 - attribute \src "ls180.v:1025.6-1025.27" + attribute \src "ls180.v:1024.6-1024.27" wire \main_sdphy_clocker_ce - attribute \src "ls180.v:1024.5-1024.28" + attribute \src "ls180.v:1023.5-1023.28" wire \main_sdphy_clocker_clk0 - attribute \src "ls180.v:1027.5-1027.28" + attribute \src "ls180.v:1026.5-1026.28" wire \main_sdphy_clocker_clk1 - attribute \src "ls180.v:1028.5-1028.29" + attribute \src "ls180.v:1027.5-1027.29" wire \main_sdphy_clocker_clk_d - attribute \src "ls180.v:1026.11-1026.34" + attribute \src "ls180.v:1025.11-1025.34" wire width 9 \main_sdphy_clocker_clks - attribute \src "ls180.v:1022.5-1022.26" + attribute \src "ls180.v:1021.5-1021.26" wire \main_sdphy_clocker_re - attribute \src "ls180.v:1023.6-1023.29" + attribute \src "ls180.v:1022.6-1022.29" wire \main_sdphy_clocker_stop - attribute \src "ls180.v:1021.11-1021.37" + attribute \src "ls180.v:1020.11-1020.37" wire width 9 \main_sdphy_clocker_storage - attribute \src "ls180.v:1125.6-1125.41" + attribute \src "ls180.v:1124.6-1124.41" wire \main_sdphy_cmdr_cmdr_buf_sink_first - attribute \src "ls180.v:1126.6-1126.40" + attribute \src "ls180.v:1125.6-1125.40" wire \main_sdphy_cmdr_cmdr_buf_sink_last - attribute \src "ls180.v:1127.12-1127.54" + attribute \src "ls180.v:1126.12-1126.54" wire width 8 \main_sdphy_cmdr_cmdr_buf_sink_payload_data - attribute \src "ls180.v:1124.6-1124.41" - wire \main_sdphy_cmdr_cmdr_buf_sink_ready attribute \src "ls180.v:1123.6-1123.41" + wire \main_sdphy_cmdr_cmdr_buf_sink_ready + attribute \src "ls180.v:1122.6-1122.41" wire \main_sdphy_cmdr_cmdr_buf_sink_valid - attribute \src "ls180.v:1130.5-1130.42" + attribute \src "ls180.v:1129.5-1129.42" wire \main_sdphy_cmdr_cmdr_buf_source_first - attribute \src "ls180.v:1131.5-1131.41" + attribute \src "ls180.v:1130.5-1130.41" wire \main_sdphy_cmdr_cmdr_buf_source_last - attribute \src "ls180.v:1132.11-1132.55" + attribute \src "ls180.v:1131.11-1131.55" wire width 8 \main_sdphy_cmdr_cmdr_buf_source_payload_data - attribute \src "ls180.v:1129.6-1129.43" + attribute \src "ls180.v:1128.6-1128.43" wire \main_sdphy_cmdr_cmdr_buf_source_ready - attribute \src "ls180.v:1128.5-1128.42" + attribute \src "ls180.v:1127.5-1127.42" wire \main_sdphy_cmdr_cmdr_buf_source_valid - attribute \src "ls180.v:1115.11-1115.47" + attribute \src "ls180.v:1114.11-1114.47" wire width 3 \main_sdphy_cmdr_cmdr_converter_demux - attribute \src "ls180.v:1116.6-1116.46" + attribute \src "ls180.v:1115.6-1115.46" wire \main_sdphy_cmdr_cmdr_converter_load_part - attribute \src "ls180.v:1106.5-1106.46" + attribute \src "ls180.v:1105.5-1105.46" wire \main_sdphy_cmdr_cmdr_converter_sink_first - attribute \src "ls180.v:1107.5-1107.45" + attribute \src "ls180.v:1106.5-1106.45" wire \main_sdphy_cmdr_cmdr_converter_sink_last - attribute \src "ls180.v:1108.6-1108.54" + attribute \src "ls180.v:1107.6-1107.54" wire \main_sdphy_cmdr_cmdr_converter_sink_payload_data - attribute \src "ls180.v:1105.6-1105.47" - wire \main_sdphy_cmdr_cmdr_converter_sink_ready attribute \src "ls180.v:1104.6-1104.47" + wire \main_sdphy_cmdr_cmdr_converter_sink_ready + attribute \src "ls180.v:1103.6-1103.47" wire \main_sdphy_cmdr_cmdr_converter_sink_valid - attribute \src "ls180.v:1111.5-1111.48" + attribute \src "ls180.v:1110.5-1110.48" wire \main_sdphy_cmdr_cmdr_converter_source_first - attribute \src "ls180.v:1112.5-1112.47" + attribute \src "ls180.v:1111.5-1111.47" wire \main_sdphy_cmdr_cmdr_converter_source_last - attribute \src "ls180.v:1113.11-1113.61" + attribute \src "ls180.v:1112.11-1112.61" wire width 8 \main_sdphy_cmdr_cmdr_converter_source_payload_data - attribute \src "ls180.v:1114.11-1114.74" + attribute \src "ls180.v:1113.11-1113.74" wire width 4 \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count - attribute \src "ls180.v:1110.6-1110.49" - wire \main_sdphy_cmdr_cmdr_converter_source_ready attribute \src "ls180.v:1109.6-1109.49" + wire \main_sdphy_cmdr_cmdr_converter_source_ready + attribute \src "ls180.v:1108.6-1108.49" wire \main_sdphy_cmdr_cmdr_converter_source_valid - attribute \src "ls180.v:1117.5-1117.46" + attribute \src "ls180.v:1116.5-1116.46" wire \main_sdphy_cmdr_cmdr_converter_strobe_all - attribute \src "ls180.v:1088.6-1088.40" + attribute \src "ls180.v:1087.6-1087.40" wire \main_sdphy_cmdr_cmdr_pads_in_first - attribute \src "ls180.v:1089.6-1089.39" + attribute \src "ls180.v:1088.6-1088.39" wire \main_sdphy_cmdr_cmdr_pads_in_last - attribute \src "ls180.v:1090.6-1090.46" + attribute \src "ls180.v:1089.6-1089.46" wire \main_sdphy_cmdr_cmdr_pads_in_payload_clk - attribute \src "ls180.v:1091.6-1091.48" + attribute \src "ls180.v:1090.6-1090.48" wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i - attribute \src "ls180.v:1092.6-1092.48" + attribute \src "ls180.v:1091.6-1091.48" wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_o - attribute \src "ls180.v:1093.6-1093.49" + attribute \src "ls180.v:1092.6-1092.49" wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_oe - attribute \src "ls180.v:1094.12-1094.55" + attribute \src "ls180.v:1093.12-1093.55" wire width 4 \main_sdphy_cmdr_cmdr_pads_in_payload_data_i - attribute \src "ls180.v:1095.12-1095.55" + attribute \src "ls180.v:1094.12-1094.55" wire width 4 \main_sdphy_cmdr_cmdr_pads_in_payload_data_o - attribute \src "ls180.v:1096.6-1096.50" + attribute \src "ls180.v:1095.6-1095.50" wire \main_sdphy_cmdr_cmdr_pads_in_payload_data_oe - attribute \src "ls180.v:1087.5-1087.39" + attribute \src "ls180.v:1086.5-1086.39" wire \main_sdphy_cmdr_cmdr_pads_in_ready - attribute \src "ls180.v:1086.6-1086.40" + attribute \src "ls180.v:1085.6-1085.40" wire \main_sdphy_cmdr_cmdr_pads_in_valid - attribute \src "ls180.v:1133.5-1133.31" + attribute \src "ls180.v:1132.5-1132.31" wire \main_sdphy_cmdr_cmdr_reset - attribute \src "ls180.v:1762.5-1762.59" + attribute \src "ls180.v:1761.5-1761.59" wire \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 - attribute \src "ls180.v:1763.5-1763.62" + attribute \src "ls180.v:1762.5-1762.62" wire \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 - attribute \src "ls180.v:1103.5-1103.29" + attribute \src "ls180.v:1102.5-1102.29" wire \main_sdphy_cmdr_cmdr_run - attribute \src "ls180.v:1099.6-1099.47" + attribute \src "ls180.v:1098.6-1098.47" wire \main_sdphy_cmdr_cmdr_source_source_first0 - attribute \src "ls180.v:1120.6-1120.47" + attribute \src "ls180.v:1119.6-1119.47" wire \main_sdphy_cmdr_cmdr_source_source_first1 - attribute \src "ls180.v:1100.6-1100.46" + attribute \src "ls180.v:1099.6-1099.46" wire \main_sdphy_cmdr_cmdr_source_source_last0 - attribute \src "ls180.v:1121.6-1121.46" + attribute \src "ls180.v:1120.6-1120.46" wire \main_sdphy_cmdr_cmdr_source_source_last1 - attribute \src "ls180.v:1101.12-1101.60" + attribute \src "ls180.v:1100.12-1100.60" wire width 8 \main_sdphy_cmdr_cmdr_source_source_payload_data0 - attribute \src "ls180.v:1122.12-1122.60" + attribute \src "ls180.v:1121.12-1121.60" wire width 8 \main_sdphy_cmdr_cmdr_source_source_payload_data1 - attribute \src "ls180.v:1098.5-1098.46" + attribute \src "ls180.v:1097.5-1097.46" wire \main_sdphy_cmdr_cmdr_source_source_ready0 - attribute \src "ls180.v:1119.6-1119.47" + attribute \src "ls180.v:1118.6-1118.47" wire \main_sdphy_cmdr_cmdr_source_source_ready1 - attribute \src "ls180.v:1097.6-1097.47" + attribute \src "ls180.v:1096.6-1096.47" wire \main_sdphy_cmdr_cmdr_source_source_valid0 - attribute \src "ls180.v:1118.6-1118.47" + attribute \src "ls180.v:1117.6-1117.47" wire \main_sdphy_cmdr_cmdr_source_source_valid1 - attribute \src "ls180.v:1102.6-1102.32" + attribute \src "ls180.v:1101.6-1101.32" wire \main_sdphy_cmdr_cmdr_start - attribute \src "ls180.v:1085.11-1085.32" + attribute \src "ls180.v:1084.11-1084.32" wire width 8 \main_sdphy_cmdr_count - attribute \src "ls180.v:1758.11-1758.60" + attribute \src "ls180.v:1757.11-1757.60" wire width 8 \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 - attribute \src "ls180.v:1759.5-1759.57" + attribute \src "ls180.v:1758.5-1758.57" wire \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 - attribute \src "ls180.v:1060.5-1060.42" + attribute \src "ls180.v:1059.5-1059.42" wire \main_sdphy_cmdr_pads_in_pads_in_first - attribute \src "ls180.v:1061.5-1061.41" + attribute \src "ls180.v:1060.5-1060.41" wire \main_sdphy_cmdr_pads_in_pads_in_last - attribute \src "ls180.v:1062.5-1062.48" + attribute \src "ls180.v:1061.5-1061.48" wire \main_sdphy_cmdr_pads_in_pads_in_payload_clk - attribute \src "ls180.v:1063.6-1063.51" + attribute \src "ls180.v:1062.6-1062.51" wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_i - attribute \src "ls180.v:1064.5-1064.50" + attribute \src "ls180.v:1063.5-1063.50" wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o - attribute \src "ls180.v:1065.5-1065.51" + attribute \src "ls180.v:1064.5-1064.51" wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe - attribute \src "ls180.v:1066.12-1066.58" + attribute \src "ls180.v:1065.12-1065.58" wire width 4 \main_sdphy_cmdr_pads_in_pads_in_payload_data_i - attribute \src "ls180.v:1067.11-1067.57" + attribute \src "ls180.v:1066.11-1066.57" wire width 4 \main_sdphy_cmdr_pads_in_pads_in_payload_data_o - attribute \src "ls180.v:1068.5-1068.52" + attribute \src "ls180.v:1067.5-1067.52" wire \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe - attribute \src "ls180.v:1059.6-1059.43" - wire \main_sdphy_cmdr_pads_in_pads_in_ready attribute \src "ls180.v:1058.6-1058.43" + wire \main_sdphy_cmdr_pads_in_pads_in_ready + attribute \src "ls180.v:1057.6-1057.43" wire \main_sdphy_cmdr_pads_in_pads_in_valid - attribute \src "ls180.v:1070.5-1070.41" + attribute \src "ls180.v:1069.5-1069.41" wire \main_sdphy_cmdr_pads_out_payload_clk - attribute \src "ls180.v:1071.5-1071.43" + attribute \src "ls180.v:1070.5-1070.43" wire \main_sdphy_cmdr_pads_out_payload_cmd_o - attribute \src "ls180.v:1072.5-1072.44" + attribute \src "ls180.v:1071.5-1071.44" wire \main_sdphy_cmdr_pads_out_payload_cmd_oe - attribute \src "ls180.v:1073.11-1073.50" + attribute \src "ls180.v:1072.11-1072.50" wire width 4 \main_sdphy_cmdr_pads_out_payload_data_o - attribute \src "ls180.v:1074.5-1074.45" + attribute \src "ls180.v:1073.5-1073.45" wire \main_sdphy_cmdr_pads_out_payload_data_oe - attribute \src "ls180.v:1069.6-1069.36" + attribute \src "ls180.v:1068.6-1068.36" wire \main_sdphy_cmdr_pads_out_ready - attribute \src "ls180.v:1077.5-1077.30" + attribute \src "ls180.v:1076.5-1076.30" wire \main_sdphy_cmdr_sink_last - attribute \src "ls180.v:1078.11-1078.46" + attribute \src "ls180.v:1077.11-1077.46" wire width 8 \main_sdphy_cmdr_sink_payload_length - attribute \src "ls180.v:1076.5-1076.31" - wire \main_sdphy_cmdr_sink_ready attribute \src "ls180.v:1075.5-1075.31" + wire \main_sdphy_cmdr_sink_ready + attribute \src "ls180.v:1074.5-1074.31" wire \main_sdphy_cmdr_sink_valid - attribute \src "ls180.v:1081.5-1081.32" + attribute \src "ls180.v:1080.5-1080.32" wire \main_sdphy_cmdr_source_last - attribute \src "ls180.v:1082.11-1082.46" + attribute \src "ls180.v:1081.11-1081.46" wire width 8 \main_sdphy_cmdr_source_payload_data - attribute \src "ls180.v:1083.11-1083.48" + attribute \src "ls180.v:1082.11-1082.48" wire width 3 \main_sdphy_cmdr_source_payload_status - attribute \src "ls180.v:1080.5-1080.33" - wire \main_sdphy_cmdr_source_ready attribute \src "ls180.v:1079.5-1079.33" + wire \main_sdphy_cmdr_source_ready + attribute \src "ls180.v:1078.5-1078.33" wire \main_sdphy_cmdr_source_valid - attribute \src "ls180.v:1084.12-1084.35" + attribute \src "ls180.v:1083.12-1083.35" wire width 32 \main_sdphy_cmdr_timeout - attribute \src "ls180.v:1760.12-1760.63" + attribute \src "ls180.v:1759.12-1759.63" wire width 32 \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 - attribute \src "ls180.v:1761.5-1761.59" + attribute \src "ls180.v:1760.5-1760.59" wire \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 - attribute \src "ls180.v:1057.11-1057.32" + attribute \src "ls180.v:1056.11-1056.32" wire width 8 \main_sdphy_cmdw_count - attribute \src "ls180.v:1754.11-1754.59" + attribute \src "ls180.v:1753.11-1753.59" wire width 8 \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value - attribute \src "ls180.v:1755.5-1755.56" + attribute \src "ls180.v:1754.5-1754.56" wire \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce - attribute \src "ls180.v:1056.5-1056.25" + attribute \src "ls180.v:1055.5-1055.25" wire \main_sdphy_cmdw_done - attribute \src "ls180.v:1044.6-1044.43" + attribute \src "ls180.v:1043.6-1043.43" wire \main_sdphy_cmdw_pads_in_payload_cmd_i - attribute \src "ls180.v:1045.12-1045.50" + attribute \src "ls180.v:1044.12-1044.50" wire width 4 \main_sdphy_cmdw_pads_in_payload_data_i - attribute \src "ls180.v:1043.6-1043.35" + attribute \src "ls180.v:1042.6-1042.35" wire \main_sdphy_cmdw_pads_in_valid - attribute \src "ls180.v:1047.5-1047.41" + attribute \src "ls180.v:1046.5-1046.41" wire \main_sdphy_cmdw_pads_out_payload_clk - attribute \src "ls180.v:1048.5-1048.43" + attribute \src "ls180.v:1047.5-1047.43" wire \main_sdphy_cmdw_pads_out_payload_cmd_o - attribute \src "ls180.v:1049.5-1049.44" + attribute \src "ls180.v:1048.5-1048.44" wire \main_sdphy_cmdw_pads_out_payload_cmd_oe - attribute \src "ls180.v:1050.11-1050.50" + attribute \src "ls180.v:1049.11-1049.50" wire width 4 \main_sdphy_cmdw_pads_out_payload_data_o - attribute \src "ls180.v:1051.5-1051.45" + attribute \src "ls180.v:1050.5-1050.45" wire \main_sdphy_cmdw_pads_out_payload_data_oe - attribute \src "ls180.v:1046.6-1046.36" + attribute \src "ls180.v:1045.6-1045.36" wire \main_sdphy_cmdw_pads_out_ready - attribute \src "ls180.v:1054.5-1054.30" + attribute \src "ls180.v:1053.5-1053.30" wire \main_sdphy_cmdw_sink_last - attribute \src "ls180.v:1055.11-1055.44" + attribute \src "ls180.v:1054.11-1054.44" wire width 8 \main_sdphy_cmdw_sink_payload_data - attribute \src "ls180.v:1053.5-1053.31" - wire \main_sdphy_cmdw_sink_ready attribute \src "ls180.v:1052.5-1052.31" + wire \main_sdphy_cmdw_sink_ready + attribute \src "ls180.v:1051.5-1051.31" wire \main_sdphy_cmdw_sink_valid - attribute \src "ls180.v:1241.11-1241.33" + attribute \src "ls180.v:1240.11-1240.33" wire width 10 \main_sdphy_datar_count - attribute \src "ls180.v:1774.11-1774.62" + attribute \src "ls180.v:1773.11-1773.62" wire width 10 \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 - attribute \src "ls180.v:1775.5-1775.59" + attribute \src "ls180.v:1774.5-1774.59" wire \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 - attribute \src "ls180.v:1281.6-1281.43" + attribute \src "ls180.v:1280.6-1280.43" wire \main_sdphy_datar_datar_buf_sink_first - attribute \src "ls180.v:1282.6-1282.42" + attribute \src "ls180.v:1281.6-1281.42" wire \main_sdphy_datar_datar_buf_sink_last - attribute \src "ls180.v:1283.12-1283.56" + attribute \src "ls180.v:1282.12-1282.56" wire width 8 \main_sdphy_datar_datar_buf_sink_payload_data - attribute \src "ls180.v:1280.6-1280.43" - wire \main_sdphy_datar_datar_buf_sink_ready attribute \src "ls180.v:1279.6-1279.43" + wire \main_sdphy_datar_datar_buf_sink_ready + attribute \src "ls180.v:1278.6-1278.43" wire \main_sdphy_datar_datar_buf_sink_valid - attribute \src "ls180.v:1286.5-1286.44" + attribute \src "ls180.v:1285.5-1285.44" wire \main_sdphy_datar_datar_buf_source_first - attribute \src "ls180.v:1287.5-1287.43" + attribute \src "ls180.v:1286.5-1286.43" wire \main_sdphy_datar_datar_buf_source_last - attribute \src "ls180.v:1288.11-1288.57" + attribute \src "ls180.v:1287.11-1287.57" wire width 8 \main_sdphy_datar_datar_buf_source_payload_data - attribute \src "ls180.v:1285.6-1285.45" + attribute \src "ls180.v:1284.6-1284.45" wire \main_sdphy_datar_datar_buf_source_ready - attribute \src "ls180.v:1284.5-1284.44" + attribute \src "ls180.v:1283.5-1283.44" wire \main_sdphy_datar_datar_buf_source_valid - attribute \src "ls180.v:1271.5-1271.43" + attribute \src "ls180.v:1270.5-1270.43" wire \main_sdphy_datar_datar_converter_demux - attribute \src "ls180.v:1272.6-1272.48" + attribute \src "ls180.v:1271.6-1271.48" wire \main_sdphy_datar_datar_converter_load_part - attribute \src "ls180.v:1262.5-1262.48" + attribute \src "ls180.v:1261.5-1261.48" wire \main_sdphy_datar_datar_converter_sink_first - attribute \src "ls180.v:1263.5-1263.47" + attribute \src "ls180.v:1262.5-1262.47" wire \main_sdphy_datar_datar_converter_sink_last - attribute \src "ls180.v:1264.12-1264.62" + attribute \src "ls180.v:1263.12-1263.62" wire width 4 \main_sdphy_datar_datar_converter_sink_payload_data - attribute \src "ls180.v:1261.6-1261.49" - wire \main_sdphy_datar_datar_converter_sink_ready attribute \src "ls180.v:1260.6-1260.49" + wire \main_sdphy_datar_datar_converter_sink_ready + attribute \src "ls180.v:1259.6-1259.49" wire \main_sdphy_datar_datar_converter_sink_valid - attribute \src "ls180.v:1267.5-1267.50" + attribute \src "ls180.v:1266.5-1266.50" wire \main_sdphy_datar_datar_converter_source_first - attribute \src "ls180.v:1268.5-1268.49" + attribute \src "ls180.v:1267.5-1267.49" wire \main_sdphy_datar_datar_converter_source_last - attribute \src "ls180.v:1269.11-1269.63" + attribute \src "ls180.v:1268.11-1268.63" wire width 8 \main_sdphy_datar_datar_converter_source_payload_data - attribute \src "ls180.v:1270.11-1270.76" + attribute \src "ls180.v:1269.11-1269.76" wire width 2 \main_sdphy_datar_datar_converter_source_payload_valid_token_count - attribute \src "ls180.v:1266.6-1266.51" - wire \main_sdphy_datar_datar_converter_source_ready attribute \src "ls180.v:1265.6-1265.51" + wire \main_sdphy_datar_datar_converter_source_ready + attribute \src "ls180.v:1264.6-1264.51" wire \main_sdphy_datar_datar_converter_source_valid - attribute \src "ls180.v:1273.5-1273.48" + attribute \src "ls180.v:1272.5-1272.48" wire \main_sdphy_datar_datar_converter_strobe_all - attribute \src "ls180.v:1244.6-1244.42" + attribute \src "ls180.v:1243.6-1243.42" wire \main_sdphy_datar_datar_pads_in_first - attribute \src "ls180.v:1245.6-1245.41" + attribute \src "ls180.v:1244.6-1244.41" wire \main_sdphy_datar_datar_pads_in_last - attribute \src "ls180.v:1246.6-1246.48" + attribute \src "ls180.v:1245.6-1245.48" wire \main_sdphy_datar_datar_pads_in_payload_clk - attribute \src "ls180.v:1247.6-1247.50" + attribute \src "ls180.v:1246.6-1246.50" wire \main_sdphy_datar_datar_pads_in_payload_cmd_i - attribute \src "ls180.v:1248.6-1248.50" + attribute \src "ls180.v:1247.6-1247.50" wire \main_sdphy_datar_datar_pads_in_payload_cmd_o - attribute \src "ls180.v:1249.6-1249.51" + attribute \src "ls180.v:1248.6-1248.51" wire \main_sdphy_datar_datar_pads_in_payload_cmd_oe - attribute \src "ls180.v:1250.12-1250.57" + attribute \src "ls180.v:1249.12-1249.57" wire width 4 \main_sdphy_datar_datar_pads_in_payload_data_i - attribute \src "ls180.v:1251.12-1251.57" + attribute \src "ls180.v:1250.12-1250.57" wire width 4 \main_sdphy_datar_datar_pads_in_payload_data_o - attribute \src "ls180.v:1252.6-1252.52" + attribute \src "ls180.v:1251.6-1251.52" wire \main_sdphy_datar_datar_pads_in_payload_data_oe - attribute \src "ls180.v:1243.5-1243.41" + attribute \src "ls180.v:1242.5-1242.41" wire \main_sdphy_datar_datar_pads_in_ready - attribute \src "ls180.v:1242.6-1242.42" + attribute \src "ls180.v:1241.6-1241.42" wire \main_sdphy_datar_datar_pads_in_valid - attribute \src "ls180.v:1289.5-1289.33" + attribute \src "ls180.v:1288.5-1288.33" wire \main_sdphy_datar_datar_reset - attribute \src "ls180.v:1778.5-1778.62" + attribute \src "ls180.v:1777.5-1777.62" wire \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 - attribute \src "ls180.v:1779.5-1779.65" + attribute \src "ls180.v:1778.5-1778.65" wire \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 - attribute \src "ls180.v:1259.5-1259.31" + attribute \src "ls180.v:1258.5-1258.31" wire \main_sdphy_datar_datar_run - attribute \src "ls180.v:1255.6-1255.49" + attribute \src "ls180.v:1254.6-1254.49" wire \main_sdphy_datar_datar_source_source_first0 - attribute \src "ls180.v:1276.6-1276.49" + attribute \src "ls180.v:1275.6-1275.49" wire \main_sdphy_datar_datar_source_source_first1 - attribute \src "ls180.v:1256.6-1256.48" + attribute \src "ls180.v:1255.6-1255.48" wire \main_sdphy_datar_datar_source_source_last0 - attribute \src "ls180.v:1277.6-1277.48" + attribute \src "ls180.v:1276.6-1276.48" wire \main_sdphy_datar_datar_source_source_last1 - attribute \src "ls180.v:1257.12-1257.62" + attribute \src "ls180.v:1256.12-1256.62" wire width 8 \main_sdphy_datar_datar_source_source_payload_data0 - attribute \src "ls180.v:1278.12-1278.62" + attribute \src "ls180.v:1277.12-1277.62" wire width 8 \main_sdphy_datar_datar_source_source_payload_data1 - attribute \src "ls180.v:1254.5-1254.48" + attribute \src "ls180.v:1253.5-1253.48" wire \main_sdphy_datar_datar_source_source_ready0 - attribute \src "ls180.v:1275.6-1275.49" + attribute \src "ls180.v:1274.6-1274.49" wire \main_sdphy_datar_datar_source_source_ready1 - attribute \src "ls180.v:1253.6-1253.49" + attribute \src "ls180.v:1252.6-1252.49" wire \main_sdphy_datar_datar_source_source_valid0 - attribute \src "ls180.v:1274.6-1274.49" + attribute \src "ls180.v:1273.6-1273.49" wire \main_sdphy_datar_datar_source_source_valid1 - attribute \src "ls180.v:1258.6-1258.34" + attribute \src "ls180.v:1257.6-1257.34" wire \main_sdphy_datar_datar_start - attribute \src "ls180.v:1214.5-1214.43" + attribute \src "ls180.v:1213.5-1213.43" wire \main_sdphy_datar_pads_in_pads_in_first - attribute \src "ls180.v:1215.5-1215.42" + attribute \src "ls180.v:1214.5-1214.42" wire \main_sdphy_datar_pads_in_pads_in_last - attribute \src "ls180.v:1216.5-1216.49" + attribute \src "ls180.v:1215.5-1215.49" wire \main_sdphy_datar_pads_in_pads_in_payload_clk - attribute \src "ls180.v:1217.6-1217.52" + attribute \src "ls180.v:1216.6-1216.52" wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_i - attribute \src "ls180.v:1218.5-1218.51" + attribute \src "ls180.v:1217.5-1217.51" wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_o - attribute \src "ls180.v:1219.5-1219.52" + attribute \src "ls180.v:1218.5-1218.52" wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_oe - attribute \src "ls180.v:1220.12-1220.59" + attribute \src "ls180.v:1219.12-1219.59" wire width 4 \main_sdphy_datar_pads_in_pads_in_payload_data_i - attribute \src "ls180.v:1221.11-1221.58" + attribute \src "ls180.v:1220.11-1220.58" wire width 4 \main_sdphy_datar_pads_in_pads_in_payload_data_o - attribute \src "ls180.v:1222.5-1222.53" + attribute \src "ls180.v:1221.5-1221.53" wire \main_sdphy_datar_pads_in_pads_in_payload_data_oe - attribute \src "ls180.v:1213.6-1213.44" - wire \main_sdphy_datar_pads_in_pads_in_ready attribute \src "ls180.v:1212.6-1212.44" + wire \main_sdphy_datar_pads_in_pads_in_ready + attribute \src "ls180.v:1211.6-1211.44" wire \main_sdphy_datar_pads_in_pads_in_valid - attribute \src "ls180.v:1224.5-1224.42" + attribute \src "ls180.v:1223.5-1223.42" wire \main_sdphy_datar_pads_out_payload_clk - attribute \src "ls180.v:1225.5-1225.44" + attribute \src "ls180.v:1224.5-1224.44" wire \main_sdphy_datar_pads_out_payload_cmd_o - attribute \src "ls180.v:1226.5-1226.45" + attribute \src "ls180.v:1225.5-1225.45" wire \main_sdphy_datar_pads_out_payload_cmd_oe - attribute \src "ls180.v:1227.11-1227.51" + attribute \src "ls180.v:1226.11-1226.51" wire width 4 \main_sdphy_datar_pads_out_payload_data_o - attribute \src "ls180.v:1228.5-1228.46" + attribute \src "ls180.v:1227.5-1227.46" wire \main_sdphy_datar_pads_out_payload_data_oe - attribute \src "ls180.v:1223.6-1223.37" + attribute \src "ls180.v:1222.6-1222.37" wire \main_sdphy_datar_pads_out_ready - attribute \src "ls180.v:1231.5-1231.31" + attribute \src "ls180.v:1230.5-1230.31" wire \main_sdphy_datar_sink_last - attribute \src "ls180.v:1232.11-1232.53" + attribute \src "ls180.v:1231.11-1231.53" wire width 10 \main_sdphy_datar_sink_payload_block_length - attribute \src "ls180.v:1230.5-1230.32" - wire \main_sdphy_datar_sink_ready attribute \src "ls180.v:1229.5-1229.32" + wire \main_sdphy_datar_sink_ready + attribute \src "ls180.v:1228.5-1228.32" wire \main_sdphy_datar_sink_valid - attribute \src "ls180.v:1235.5-1235.34" + attribute \src "ls180.v:1234.5-1234.34" wire \main_sdphy_datar_source_first - attribute \src "ls180.v:1236.5-1236.33" + attribute \src "ls180.v:1235.5-1235.33" wire \main_sdphy_datar_source_last - attribute \src "ls180.v:1237.11-1237.47" + attribute \src "ls180.v:1236.11-1236.47" wire width 8 \main_sdphy_datar_source_payload_data - attribute \src "ls180.v:1238.11-1238.49" + attribute \src "ls180.v:1237.11-1237.49" wire width 3 \main_sdphy_datar_source_payload_status - attribute \src "ls180.v:1234.5-1234.34" - wire \main_sdphy_datar_source_ready attribute \src "ls180.v:1233.5-1233.34" + wire \main_sdphy_datar_source_ready + attribute \src "ls180.v:1232.5-1232.34" wire \main_sdphy_datar_source_valid - attribute \src "ls180.v:1239.5-1239.26" + attribute \src "ls180.v:1238.5-1238.26" wire \main_sdphy_datar_stop - attribute \src "ls180.v:1240.12-1240.36" + attribute \src "ls180.v:1239.12-1239.36" wire width 32 \main_sdphy_datar_timeout - attribute \src "ls180.v:1776.12-1776.65" + attribute \src "ls180.v:1775.12-1775.65" wire width 32 \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 - attribute \src "ls180.v:1777.5-1777.61" + attribute \src "ls180.v:1776.5-1776.61" wire \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 - attribute \src "ls180.v:1149.11-1149.33" + attribute \src "ls180.v:1148.11-1148.33" wire width 8 \main_sdphy_dataw_count - attribute \src "ls180.v:1770.11-1770.54" + attribute \src "ls180.v:1769.11-1769.54" wire width 8 \main_sdphy_dataw_count_sdphy_fsm_next_value - attribute \src "ls180.v:1771.5-1771.51" + attribute \src "ls180.v:1770.5-1770.51" wire \main_sdphy_dataw_count_sdphy_fsm_next_value_ce - attribute \src "ls180.v:1203.6-1203.42" + attribute \src "ls180.v:1202.6-1202.42" wire \main_sdphy_dataw_crcr_buf_sink_first - attribute \src "ls180.v:1204.6-1204.41" + attribute \src "ls180.v:1203.6-1203.41" wire \main_sdphy_dataw_crcr_buf_sink_last - attribute \src "ls180.v:1205.12-1205.55" + attribute \src "ls180.v:1204.12-1204.55" wire width 8 \main_sdphy_dataw_crcr_buf_sink_payload_data - attribute \src "ls180.v:1202.6-1202.42" - wire \main_sdphy_dataw_crcr_buf_sink_ready attribute \src "ls180.v:1201.6-1201.42" + wire \main_sdphy_dataw_crcr_buf_sink_ready + attribute \src "ls180.v:1200.6-1200.42" wire \main_sdphy_dataw_crcr_buf_sink_valid - attribute \src "ls180.v:1208.5-1208.43" + attribute \src "ls180.v:1207.5-1207.43" wire \main_sdphy_dataw_crcr_buf_source_first - attribute \src "ls180.v:1209.5-1209.42" + attribute \src "ls180.v:1208.5-1208.42" wire \main_sdphy_dataw_crcr_buf_source_last - attribute \src "ls180.v:1210.11-1210.56" + attribute \src "ls180.v:1209.11-1209.56" wire width 8 \main_sdphy_dataw_crcr_buf_source_payload_data - attribute \src "ls180.v:1207.6-1207.44" + attribute \src "ls180.v:1206.6-1206.44" wire \main_sdphy_dataw_crcr_buf_source_ready - attribute \src "ls180.v:1206.5-1206.43" + attribute \src "ls180.v:1205.5-1205.43" wire \main_sdphy_dataw_crcr_buf_source_valid - attribute \src "ls180.v:1193.11-1193.48" + attribute \src "ls180.v:1192.11-1192.48" wire width 3 \main_sdphy_dataw_crcr_converter_demux - attribute \src "ls180.v:1194.6-1194.47" + attribute \src "ls180.v:1193.6-1193.47" wire \main_sdphy_dataw_crcr_converter_load_part - attribute \src "ls180.v:1184.5-1184.47" + attribute \src "ls180.v:1183.5-1183.47" wire \main_sdphy_dataw_crcr_converter_sink_first - attribute \src "ls180.v:1185.5-1185.46" + attribute \src "ls180.v:1184.5-1184.46" wire \main_sdphy_dataw_crcr_converter_sink_last - attribute \src "ls180.v:1186.6-1186.55" + attribute \src "ls180.v:1185.6-1185.55" wire \main_sdphy_dataw_crcr_converter_sink_payload_data - attribute \src "ls180.v:1183.6-1183.48" - wire \main_sdphy_dataw_crcr_converter_sink_ready attribute \src "ls180.v:1182.6-1182.48" + wire \main_sdphy_dataw_crcr_converter_sink_ready + attribute \src "ls180.v:1181.6-1181.48" wire \main_sdphy_dataw_crcr_converter_sink_valid - attribute \src "ls180.v:1189.5-1189.49" + attribute \src "ls180.v:1188.5-1188.49" wire \main_sdphy_dataw_crcr_converter_source_first - attribute \src "ls180.v:1190.5-1190.48" + attribute \src "ls180.v:1189.5-1189.48" wire \main_sdphy_dataw_crcr_converter_source_last - attribute \src "ls180.v:1191.11-1191.62" + attribute \src "ls180.v:1190.11-1190.62" wire width 8 \main_sdphy_dataw_crcr_converter_source_payload_data - attribute \src "ls180.v:1192.11-1192.75" + attribute \src "ls180.v:1191.11-1191.75" wire width 4 \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count - attribute \src "ls180.v:1188.6-1188.50" - wire \main_sdphy_dataw_crcr_converter_source_ready attribute \src "ls180.v:1187.6-1187.50" + wire \main_sdphy_dataw_crcr_converter_source_ready + attribute \src "ls180.v:1186.6-1186.50" wire \main_sdphy_dataw_crcr_converter_source_valid - attribute \src "ls180.v:1195.5-1195.47" + attribute \src "ls180.v:1194.5-1194.47" wire \main_sdphy_dataw_crcr_converter_strobe_all - attribute \src "ls180.v:1166.6-1166.41" + attribute \src "ls180.v:1165.6-1165.41" wire \main_sdphy_dataw_crcr_pads_in_first - attribute \src "ls180.v:1167.6-1167.40" + attribute \src "ls180.v:1166.6-1166.40" wire \main_sdphy_dataw_crcr_pads_in_last - attribute \src "ls180.v:1168.6-1168.47" + attribute \src "ls180.v:1167.6-1167.47" wire \main_sdphy_dataw_crcr_pads_in_payload_clk - attribute \src "ls180.v:1169.6-1169.49" + attribute \src "ls180.v:1168.6-1168.49" wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_i - attribute \src "ls180.v:1170.6-1170.49" + attribute \src "ls180.v:1169.6-1169.49" wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_o - attribute \src "ls180.v:1171.6-1171.50" + attribute \src "ls180.v:1170.6-1170.50" wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_oe - attribute \src "ls180.v:1172.12-1172.56" + attribute \src "ls180.v:1171.12-1171.56" wire width 4 \main_sdphy_dataw_crcr_pads_in_payload_data_i - attribute \src "ls180.v:1173.12-1173.56" + attribute \src "ls180.v:1172.12-1172.56" wire width 4 \main_sdphy_dataw_crcr_pads_in_payload_data_o - attribute \src "ls180.v:1174.6-1174.51" + attribute \src "ls180.v:1173.6-1173.51" wire \main_sdphy_dataw_crcr_pads_in_payload_data_oe - attribute \src "ls180.v:1165.5-1165.40" + attribute \src "ls180.v:1164.5-1164.40" wire \main_sdphy_dataw_crcr_pads_in_ready - attribute \src "ls180.v:1164.6-1164.41" + attribute \src "ls180.v:1163.6-1163.41" wire \main_sdphy_dataw_crcr_pads_in_valid - attribute \src "ls180.v:1211.5-1211.32" + attribute \src "ls180.v:1210.5-1210.32" wire \main_sdphy_dataw_crcr_reset - attribute \src "ls180.v:1766.5-1766.59" + attribute \src "ls180.v:1765.5-1765.59" wire \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value - attribute \src "ls180.v:1767.5-1767.62" + attribute \src "ls180.v:1766.5-1766.62" wire \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce - attribute \src "ls180.v:1181.5-1181.30" + attribute \src "ls180.v:1180.5-1180.30" wire \main_sdphy_dataw_crcr_run - attribute \src "ls180.v:1177.6-1177.48" + attribute \src "ls180.v:1176.6-1176.48" wire \main_sdphy_dataw_crcr_source_source_first0 - attribute \src "ls180.v:1198.6-1198.48" + attribute \src "ls180.v:1197.6-1197.48" wire \main_sdphy_dataw_crcr_source_source_first1 - attribute \src "ls180.v:1178.6-1178.47" + attribute \src "ls180.v:1177.6-1177.47" wire \main_sdphy_dataw_crcr_source_source_last0 - attribute \src "ls180.v:1199.6-1199.47" + attribute \src "ls180.v:1198.6-1198.47" wire \main_sdphy_dataw_crcr_source_source_last1 - attribute \src "ls180.v:1179.12-1179.61" + attribute \src "ls180.v:1178.12-1178.61" wire width 8 \main_sdphy_dataw_crcr_source_source_payload_data0 - attribute \src "ls180.v:1200.12-1200.61" + attribute \src "ls180.v:1199.12-1199.61" wire width 8 \main_sdphy_dataw_crcr_source_source_payload_data1 - attribute \src "ls180.v:1176.5-1176.47" + attribute \src "ls180.v:1175.5-1175.47" wire \main_sdphy_dataw_crcr_source_source_ready0 - attribute \src "ls180.v:1197.6-1197.48" + attribute \src "ls180.v:1196.6-1196.48" wire \main_sdphy_dataw_crcr_source_source_ready1 - attribute \src "ls180.v:1175.6-1175.48" + attribute \src "ls180.v:1174.6-1174.48" wire \main_sdphy_dataw_crcr_source_source_valid0 - attribute \src "ls180.v:1196.6-1196.48" + attribute \src "ls180.v:1195.6-1195.48" wire \main_sdphy_dataw_crcr_source_source_valid1 - attribute \src "ls180.v:1180.6-1180.33" + attribute \src "ls180.v:1179.6-1179.33" wire \main_sdphy_dataw_crcr_start - attribute \src "ls180.v:1163.5-1163.27" + attribute \src "ls180.v:1162.5-1162.27" wire \main_sdphy_dataw_error - attribute \src "ls180.v:1152.5-1152.43" + attribute \src "ls180.v:1151.5-1151.43" wire \main_sdphy_dataw_pads_in_pads_in_first - attribute \src "ls180.v:1153.5-1153.42" + attribute \src "ls180.v:1152.5-1152.42" wire \main_sdphy_dataw_pads_in_pads_in_last - attribute \src "ls180.v:1154.5-1154.49" + attribute \src "ls180.v:1153.5-1153.49" wire \main_sdphy_dataw_pads_in_pads_in_payload_clk - attribute \src "ls180.v:1155.5-1155.51" + attribute \src "ls180.v:1154.5-1154.51" wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_i - attribute \src "ls180.v:1156.5-1156.51" + attribute \src "ls180.v:1155.5-1155.51" wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_o - attribute \src "ls180.v:1157.5-1157.52" + attribute \src "ls180.v:1156.5-1156.52" wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe - attribute \src "ls180.v:1158.11-1158.58" + attribute \src "ls180.v:1157.11-1157.58" wire width 4 \main_sdphy_dataw_pads_in_pads_in_payload_data_i - attribute \src "ls180.v:1159.11-1159.58" + attribute \src "ls180.v:1158.11-1158.58" wire width 4 \main_sdphy_dataw_pads_in_pads_in_payload_data_o - attribute \src "ls180.v:1160.5-1160.53" + attribute \src "ls180.v:1159.5-1159.53" wire \main_sdphy_dataw_pads_in_pads_in_payload_data_oe - attribute \src "ls180.v:1151.6-1151.44" + attribute \src "ls180.v:1150.6-1150.44" wire \main_sdphy_dataw_pads_in_pads_in_ready - attribute \src "ls180.v:1150.5-1150.43" + attribute \src "ls180.v:1149.5-1149.43" wire \main_sdphy_dataw_pads_in_pads_in_valid - attribute \src "ls180.v:1135.6-1135.44" + attribute \src "ls180.v:1134.6-1134.44" wire \main_sdphy_dataw_pads_in_payload_cmd_i - attribute \src "ls180.v:1136.12-1136.51" + attribute \src "ls180.v:1135.12-1135.51" wire width 4 \main_sdphy_dataw_pads_in_payload_data_i - attribute \src "ls180.v:1134.6-1134.36" + attribute \src "ls180.v:1133.6-1133.36" wire \main_sdphy_dataw_pads_in_valid - attribute \src "ls180.v:1138.5-1138.42" + attribute \src "ls180.v:1137.5-1137.42" wire \main_sdphy_dataw_pads_out_payload_clk - attribute \src "ls180.v:1139.5-1139.44" + attribute \src "ls180.v:1138.5-1138.44" wire \main_sdphy_dataw_pads_out_payload_cmd_o - attribute \src "ls180.v:1140.5-1140.45" + attribute \src "ls180.v:1139.5-1139.45" wire \main_sdphy_dataw_pads_out_payload_cmd_oe - attribute \src "ls180.v:1141.11-1141.51" + attribute \src "ls180.v:1140.11-1140.51" wire width 4 \main_sdphy_dataw_pads_out_payload_data_o - attribute \src "ls180.v:1142.5-1142.46" + attribute \src "ls180.v:1141.5-1141.46" wire \main_sdphy_dataw_pads_out_payload_data_oe - attribute \src "ls180.v:1137.6-1137.37" + attribute \src "ls180.v:1136.6-1136.37" wire \main_sdphy_dataw_pads_out_ready - attribute \src "ls180.v:1145.5-1145.32" + attribute \src "ls180.v:1144.5-1144.32" wire \main_sdphy_dataw_sink_first - attribute \src "ls180.v:1146.5-1146.31" + attribute \src "ls180.v:1145.5-1145.31" wire \main_sdphy_dataw_sink_last - attribute \src "ls180.v:1147.11-1147.45" + attribute \src "ls180.v:1146.11-1146.45" wire width 8 \main_sdphy_dataw_sink_payload_data - attribute \src "ls180.v:1144.5-1144.32" - wire \main_sdphy_dataw_sink_ready attribute \src "ls180.v:1143.5-1143.32" + wire \main_sdphy_dataw_sink_ready + attribute \src "ls180.v:1142.5-1142.32" wire \main_sdphy_dataw_sink_valid - attribute \src "ls180.v:1161.5-1161.27" + attribute \src "ls180.v:1160.5-1160.27" wire \main_sdphy_dataw_start - attribute \src "ls180.v:1148.5-1148.26" + attribute \src "ls180.v:1147.5-1147.26" wire \main_sdphy_dataw_stop - attribute \src "ls180.v:1162.5-1162.27" + attribute \src "ls180.v:1161.5-1161.27" wire \main_sdphy_dataw_valid - attribute \src "ls180.v:1042.11-1042.32" + attribute \src "ls180.v:1041.11-1041.32" wire width 8 \main_sdphy_init_count - attribute \src "ls180.v:1750.11-1750.59" + attribute \src "ls180.v:1749.11-1749.59" wire width 8 \main_sdphy_init_count_sdphy_sdphyinit_next_value - attribute \src "ls180.v:1751.5-1751.56" + attribute \src "ls180.v:1750.5-1750.56" wire \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce - attribute \src "ls180.v:1030.6-1030.34" + attribute \src "ls180.v:1029.6-1029.34" wire \main_sdphy_init_initialize_r - attribute \src "ls180.v:1029.6-1029.35" + attribute \src "ls180.v:1028.6-1028.35" wire \main_sdphy_init_initialize_re - attribute \src "ls180.v:1032.5-1032.33" + attribute \src "ls180.v:1031.5-1031.33" wire \main_sdphy_init_initialize_w - attribute \src "ls180.v:1031.6-1031.35" + attribute \src "ls180.v:1030.6-1030.35" wire \main_sdphy_init_initialize_we - attribute \src "ls180.v:1034.6-1034.43" + attribute \src "ls180.v:1033.6-1033.43" wire \main_sdphy_init_pads_in_payload_cmd_i - attribute \src "ls180.v:1035.12-1035.50" + attribute \src "ls180.v:1034.12-1034.50" wire width 4 \main_sdphy_init_pads_in_payload_data_i - attribute \src "ls180.v:1033.6-1033.35" + attribute \src "ls180.v:1032.6-1032.35" wire \main_sdphy_init_pads_in_valid - attribute \src "ls180.v:1037.5-1037.41" + attribute \src "ls180.v:1036.5-1036.41" wire \main_sdphy_init_pads_out_payload_clk - attribute \src "ls180.v:1038.5-1038.43" + attribute \src "ls180.v:1037.5-1037.43" wire \main_sdphy_init_pads_out_payload_cmd_o - attribute \src "ls180.v:1039.5-1039.44" + attribute \src "ls180.v:1038.5-1038.44" wire \main_sdphy_init_pads_out_payload_cmd_oe - attribute \src "ls180.v:1040.11-1040.50" + attribute \src "ls180.v:1039.11-1039.50" wire width 4 \main_sdphy_init_pads_out_payload_data_o - attribute \src "ls180.v:1041.5-1041.45" + attribute \src "ls180.v:1040.5-1040.45" wire \main_sdphy_init_pads_out_payload_data_oe - attribute \src "ls180.v:1036.6-1036.36" + attribute \src "ls180.v:1035.6-1035.36" wire \main_sdphy_init_pads_out_ready - attribute \src "ls180.v:1290.6-1290.27" + attribute \src "ls180.v:1289.6-1289.27" wire \main_sdphy_sdpads_clk - attribute \src "ls180.v:1291.5-1291.28" + attribute \src "ls180.v:1290.5-1290.28" wire \main_sdphy_sdpads_cmd_i - attribute \src "ls180.v:1292.6-1292.29" + attribute \src "ls180.v:1291.6-1291.29" wire \main_sdphy_sdpads_cmd_o - attribute \src "ls180.v:1293.6-1293.30" + attribute \src "ls180.v:1292.6-1292.30" wire \main_sdphy_sdpads_cmd_oe - attribute \src "ls180.v:1294.11-1294.35" + attribute \src "ls180.v:1293.11-1293.35" wire width 4 \main_sdphy_sdpads_data_i - attribute \src "ls180.v:1295.12-1295.36" + attribute \src "ls180.v:1294.12-1294.36" wire width 4 \main_sdphy_sdpads_data_o - attribute \src "ls180.v:1296.6-1296.31" + attribute \src "ls180.v:1295.6-1295.31" wire \main_sdphy_sdpads_data_oe - attribute \src "ls180.v:1019.6-1019.23" + attribute \src "ls180.v:1018.6-1018.23" wire \main_sdphy_status - attribute \src "ls180.v:1020.6-1020.19" + attribute \src "ls180.v:1019.6-1019.19" wire \main_sdphy_we - attribute \src "ls180.v:300.5-300.26" + attribute \src "ls180.v:299.5-299.26" wire \main_sdram_address_re - attribute \src "ls180.v:299.12-299.38" + attribute \src "ls180.v:298.12-298.38" wire width 13 \main_sdram_address_storage - attribute \src "ls180.v:302.5-302.27" + attribute \src "ls180.v:301.5-301.27" wire \main_sdram_baddress_re - attribute \src "ls180.v:301.11-301.38" + attribute \src "ls180.v:300.11-300.38" wire width 2 \main_sdram_baddress_storage - attribute \src "ls180.v:398.5-398.43" + attribute \src "ls180.v:397.5-397.43" wire \main_sdram_bankmachine0_auto_precharge - attribute \src "ls180.v:420.11-420.63" + attribute \src "ls180.v:419.11-419.63" wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_consume - attribute \src "ls180.v:425.6-425.58" + attribute \src "ls180.v:424.6-424.58" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:430.6-430.64" + attribute \src "ls180.v:429.6-429.64" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first - attribute \src "ls180.v:431.6-431.63" + attribute \src "ls180.v:430.6-430.63" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last - attribute \src "ls180.v:429.13-429.78" + attribute \src "ls180.v:428.13-428.78" wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr - attribute \src "ls180.v:428.6-428.69" + attribute \src "ls180.v:427.6-427.69" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we - attribute \src "ls180.v:434.6-434.65" + attribute \src "ls180.v:433.6-433.65" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first - attribute \src "ls180.v:435.6-435.64" + attribute \src "ls180.v:434.6-434.64" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last - attribute \src "ls180.v:433.13-433.79" + attribute \src "ls180.v:432.13-432.79" wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr - attribute \src "ls180.v:432.6-432.70" + attribute \src "ls180.v:431.6-431.70" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we - attribute \src "ls180.v:417.11-417.61" + attribute \src "ls180.v:416.11-416.61" wire width 4 \main_sdram_bankmachine0_cmd_buffer_lookahead_level - attribute \src "ls180.v:419.11-419.63" + attribute \src "ls180.v:418.11-418.63" wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_produce - attribute \src "ls180.v:426.12-426.67" + attribute \src "ls180.v:425.12-425.67" wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr - attribute \src "ls180.v:427.13-427.70" + attribute \src "ls180.v:426.13-426.70" wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r - attribute \src "ls180.v:418.5-418.57" + attribute \src "ls180.v:417.5-417.57" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - attribute \src "ls180.v:401.5-401.60" + attribute \src "ls180.v:400.5-400.60" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first - attribute \src "ls180.v:402.5-402.59" + attribute \src "ls180.v:401.5-401.59" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last - attribute \src "ls180.v:404.13-404.75" + attribute \src "ls180.v:403.13-403.75" wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr - attribute \src "ls180.v:403.6-403.66" + attribute \src "ls180.v:402.6-402.66" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we - attribute \src "ls180.v:400.6-400.61" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready attribute \src "ls180.v:399.6-399.61" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready + attribute \src "ls180.v:398.6-398.61" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid - attribute \src "ls180.v:407.6-407.63" + attribute \src "ls180.v:406.6-406.63" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_first - attribute \src "ls180.v:408.6-408.62" + attribute \src "ls180.v:407.6-407.62" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last - attribute \src "ls180.v:410.13-410.77" + attribute \src "ls180.v:409.13-409.77" wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr - attribute \src "ls180.v:409.6-409.68" + attribute \src "ls180.v:408.6-408.68" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we - attribute \src "ls180.v:406.6-406.63" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready attribute \src "ls180.v:405.6-405.63" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready + attribute \src "ls180.v:404.6-404.63" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid - attribute \src "ls180.v:415.13-415.71" + attribute \src "ls180.v:414.13-414.71" wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din - attribute \src "ls180.v:416.13-416.72" + attribute \src "ls180.v:415.13-415.72" wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout - attribute \src "ls180.v:413.6-413.63" + attribute \src "ls180.v:412.6-412.63" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re - attribute \src "ls180.v:414.6-414.69" + attribute \src "ls180.v:413.6-413.69" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable - attribute \src "ls180.v:411.6-411.63" + attribute \src "ls180.v:410.6-410.63" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we - attribute \src "ls180.v:412.6-412.69" + attribute \src "ls180.v:411.6-411.69" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable - attribute \src "ls180.v:421.11-421.66" + attribute \src "ls180.v:420.11-420.66" wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr - attribute \src "ls180.v:422.13-422.70" + attribute \src "ls180.v:421.13-421.70" wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r - attribute \src "ls180.v:424.13-424.70" + attribute \src "ls180.v:423.13-423.70" wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w - attribute \src "ls180.v:423.6-423.60" + attribute \src "ls180.v:422.6-422.60" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:438.6-438.51" + attribute \src "ls180.v:437.6-437.51" wire \main_sdram_bankmachine0_cmd_buffer_sink_first - attribute \src "ls180.v:439.6-439.50" + attribute \src "ls180.v:438.6-438.50" wire \main_sdram_bankmachine0_cmd_buffer_sink_last - attribute \src "ls180.v:441.13-441.65" + attribute \src "ls180.v:440.13-440.65" wire width 22 \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr - attribute \src "ls180.v:440.6-440.56" + attribute \src "ls180.v:439.6-439.56" wire \main_sdram_bankmachine0_cmd_buffer_sink_payload_we - attribute \src "ls180.v:437.6-437.51" - wire \main_sdram_bankmachine0_cmd_buffer_sink_ready attribute \src "ls180.v:436.6-436.51" + wire \main_sdram_bankmachine0_cmd_buffer_sink_ready + attribute \src "ls180.v:435.6-435.51" wire \main_sdram_bankmachine0_cmd_buffer_sink_valid - attribute \src "ls180.v:444.5-444.52" + attribute \src "ls180.v:443.5-443.52" wire \main_sdram_bankmachine0_cmd_buffer_source_first - attribute \src "ls180.v:445.5-445.51" + attribute \src "ls180.v:444.5-444.51" wire \main_sdram_bankmachine0_cmd_buffer_source_last - attribute \src "ls180.v:447.12-447.66" + attribute \src "ls180.v:446.12-446.66" wire width 22 \main_sdram_bankmachine0_cmd_buffer_source_payload_addr - attribute \src "ls180.v:446.5-446.57" + attribute \src "ls180.v:445.5-445.57" wire \main_sdram_bankmachine0_cmd_buffer_source_payload_we - attribute \src "ls180.v:443.6-443.53" + attribute \src "ls180.v:442.6-442.53" wire \main_sdram_bankmachine0_cmd_buffer_source_ready - attribute \src "ls180.v:442.5-442.52" + attribute \src "ls180.v:441.5-441.52" wire \main_sdram_bankmachine0_cmd_buffer_source_valid - attribute \src "ls180.v:390.12-390.49" + attribute \src "ls180.v:389.12-389.49" wire width 13 \main_sdram_bankmachine0_cmd_payload_a - attribute \src "ls180.v:391.12-391.50" + attribute \src "ls180.v:390.12-390.50" wire width 2 \main_sdram_bankmachine0_cmd_payload_ba - attribute \src "ls180.v:392.5-392.44" + attribute \src "ls180.v:391.5-391.44" wire \main_sdram_bankmachine0_cmd_payload_cas - attribute \src "ls180.v:395.5-395.47" + attribute \src "ls180.v:394.5-394.47" wire \main_sdram_bankmachine0_cmd_payload_is_cmd - attribute \src "ls180.v:396.5-396.48" + attribute \src "ls180.v:395.5-395.48" wire \main_sdram_bankmachine0_cmd_payload_is_read - attribute \src "ls180.v:397.5-397.49" + attribute \src "ls180.v:396.5-396.49" wire \main_sdram_bankmachine0_cmd_payload_is_write - attribute \src "ls180.v:393.5-393.44" + attribute \src "ls180.v:392.5-392.44" wire \main_sdram_bankmachine0_cmd_payload_ras - attribute \src "ls180.v:394.5-394.43" + attribute \src "ls180.v:393.5-393.43" wire \main_sdram_bankmachine0_cmd_payload_we - attribute \src "ls180.v:389.5-389.38" - wire \main_sdram_bankmachine0_cmd_ready attribute \src "ls180.v:388.5-388.38" + wire \main_sdram_bankmachine0_cmd_ready + attribute \src "ls180.v:387.5-387.38" wire \main_sdram_bankmachine0_cmd_valid - attribute \src "ls180.v:387.5-387.40" + attribute \src "ls180.v:386.5-386.40" wire \main_sdram_bankmachine0_refresh_gnt - attribute \src "ls180.v:386.6-386.41" + attribute \src "ls180.v:385.6-385.41" wire \main_sdram_bankmachine0_refresh_req - attribute \src "ls180.v:382.13-382.45" + attribute \src "ls180.v:381.13-381.45" wire width 22 \main_sdram_bankmachine0_req_addr - attribute \src "ls180.v:383.6-383.38" + attribute \src "ls180.v:382.6-382.38" wire \main_sdram_bankmachine0_req_lock - attribute \src "ls180.v:385.5-385.44" + attribute \src "ls180.v:384.5-384.44" wire \main_sdram_bankmachine0_req_rdata_valid - attribute \src "ls180.v:380.6-380.39" - wire \main_sdram_bankmachine0_req_ready attribute \src "ls180.v:379.6-379.39" + wire \main_sdram_bankmachine0_req_ready + attribute \src "ls180.v:378.6-378.39" wire \main_sdram_bankmachine0_req_valid - attribute \src "ls180.v:384.5-384.44" + attribute \src "ls180.v:383.5-383.44" wire \main_sdram_bankmachine0_req_wdata_ready - attribute \src "ls180.v:381.6-381.36" + attribute \src "ls180.v:380.6-380.36" wire \main_sdram_bankmachine0_req_we - attribute \src "ls180.v:448.12-448.39" + attribute \src "ls180.v:447.12-447.39" wire width 13 \main_sdram_bankmachine0_row - attribute \src "ls180.v:452.5-452.38" + attribute \src "ls180.v:451.5-451.38" wire \main_sdram_bankmachine0_row_close - attribute \src "ls180.v:453.5-453.47" + attribute \src "ls180.v:452.5-452.47" wire \main_sdram_bankmachine0_row_col_n_addr_sel - attribute \src "ls180.v:450.6-450.37" + attribute \src "ls180.v:449.6-449.37" wire \main_sdram_bankmachine0_row_hit - attribute \src "ls180.v:451.5-451.37" + attribute \src "ls180.v:450.5-450.37" wire \main_sdram_bankmachine0_row_open - attribute \src "ls180.v:449.5-449.39" + attribute \src "ls180.v:448.5-448.39" wire \main_sdram_bankmachine0_row_opened attribute \no_retiming "true" - attribute \src "ls180.v:460.32-460.69" + attribute \src "ls180.v:459.32-459.69" wire \main_sdram_bankmachine0_trascon_ready - attribute \src "ls180.v:459.6-459.43" + attribute \src "ls180.v:458.6-458.43" wire \main_sdram_bankmachine0_trascon_valid attribute \no_retiming "true" - attribute \src "ls180.v:458.32-458.68" + attribute \src "ls180.v:457.32-457.68" wire \main_sdram_bankmachine0_trccon_ready - attribute \src "ls180.v:457.6-457.42" + attribute \src "ls180.v:456.6-456.42" wire \main_sdram_bankmachine0_trccon_valid - attribute \src "ls180.v:456.11-456.48" + attribute \src "ls180.v:455.11-455.48" wire width 3 \main_sdram_bankmachine0_twtpcon_count attribute \no_retiming "true" - attribute \src "ls180.v:455.32-455.69" + attribute \src "ls180.v:454.32-454.69" wire \main_sdram_bankmachine0_twtpcon_ready - attribute \src "ls180.v:454.6-454.43" + attribute \src "ls180.v:453.6-453.43" wire \main_sdram_bankmachine0_twtpcon_valid - attribute \src "ls180.v:480.5-480.43" + attribute \src "ls180.v:479.5-479.43" wire \main_sdram_bankmachine1_auto_precharge - attribute \src "ls180.v:502.11-502.63" + attribute \src "ls180.v:501.11-501.63" wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_consume - attribute \src "ls180.v:507.6-507.58" + attribute \src "ls180.v:506.6-506.58" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:512.6-512.64" + attribute \src "ls180.v:511.6-511.64" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first - attribute \src "ls180.v:513.6-513.63" + attribute \src "ls180.v:512.6-512.63" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last - attribute \src "ls180.v:511.13-511.78" + attribute \src "ls180.v:510.13-510.78" wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr - attribute \src "ls180.v:510.6-510.69" + attribute \src "ls180.v:509.6-509.69" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we - attribute \src "ls180.v:516.6-516.65" + attribute \src "ls180.v:515.6-515.65" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first - attribute \src "ls180.v:517.6-517.64" + attribute \src "ls180.v:516.6-516.64" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last - attribute \src "ls180.v:515.13-515.79" + attribute \src "ls180.v:514.13-514.79" wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr - attribute \src "ls180.v:514.6-514.70" + attribute \src "ls180.v:513.6-513.70" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we - attribute \src "ls180.v:499.11-499.61" + attribute \src "ls180.v:498.11-498.61" wire width 4 \main_sdram_bankmachine1_cmd_buffer_lookahead_level - attribute \src "ls180.v:501.11-501.63" + attribute \src "ls180.v:500.11-500.63" wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_produce - attribute \src "ls180.v:508.12-508.67" + attribute \src "ls180.v:507.12-507.67" wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr - attribute \src "ls180.v:509.13-509.70" + attribute \src "ls180.v:508.13-508.70" wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r - attribute \src "ls180.v:500.5-500.57" + attribute \src "ls180.v:499.5-499.57" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - attribute \src "ls180.v:483.5-483.60" + attribute \src "ls180.v:482.5-482.60" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first - attribute \src "ls180.v:484.5-484.59" + attribute \src "ls180.v:483.5-483.59" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last - attribute \src "ls180.v:486.13-486.75" + attribute \src "ls180.v:485.13-485.75" wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr - attribute \src "ls180.v:485.6-485.66" + attribute \src "ls180.v:484.6-484.66" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we - attribute \src "ls180.v:482.6-482.61" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready attribute \src "ls180.v:481.6-481.61" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready + attribute \src "ls180.v:480.6-480.61" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid - attribute \src "ls180.v:489.6-489.63" + attribute \src "ls180.v:488.6-488.63" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_first - attribute \src "ls180.v:490.6-490.62" + attribute \src "ls180.v:489.6-489.62" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last - attribute \src "ls180.v:492.13-492.77" + attribute \src "ls180.v:491.13-491.77" wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr - attribute \src "ls180.v:491.6-491.68" + attribute \src "ls180.v:490.6-490.68" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we - attribute \src "ls180.v:488.6-488.63" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready attribute \src "ls180.v:487.6-487.63" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready + attribute \src "ls180.v:486.6-486.63" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid - attribute \src "ls180.v:497.13-497.71" + attribute \src "ls180.v:496.13-496.71" wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din - attribute \src "ls180.v:498.13-498.72" + attribute \src "ls180.v:497.13-497.72" wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout - attribute \src "ls180.v:495.6-495.63" + attribute \src "ls180.v:494.6-494.63" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re - attribute \src "ls180.v:496.6-496.69" + attribute \src "ls180.v:495.6-495.69" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable - attribute \src "ls180.v:493.6-493.63" + attribute \src "ls180.v:492.6-492.63" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we - attribute \src "ls180.v:494.6-494.69" + attribute \src "ls180.v:493.6-493.69" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable - attribute \src "ls180.v:503.11-503.66" + attribute \src "ls180.v:502.11-502.66" wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr - attribute \src "ls180.v:504.13-504.70" + attribute \src "ls180.v:503.13-503.70" wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r - attribute \src "ls180.v:506.13-506.70" + attribute \src "ls180.v:505.13-505.70" wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w - attribute \src "ls180.v:505.6-505.60" + attribute \src "ls180.v:504.6-504.60" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:520.6-520.51" + attribute \src "ls180.v:519.6-519.51" wire \main_sdram_bankmachine1_cmd_buffer_sink_first - attribute \src "ls180.v:521.6-521.50" + attribute \src "ls180.v:520.6-520.50" wire \main_sdram_bankmachine1_cmd_buffer_sink_last - attribute \src "ls180.v:523.13-523.65" + attribute \src "ls180.v:522.13-522.65" wire width 22 \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr - attribute \src "ls180.v:522.6-522.56" + attribute \src "ls180.v:521.6-521.56" wire \main_sdram_bankmachine1_cmd_buffer_sink_payload_we - attribute \src "ls180.v:519.6-519.51" - wire \main_sdram_bankmachine1_cmd_buffer_sink_ready attribute \src "ls180.v:518.6-518.51" + wire \main_sdram_bankmachine1_cmd_buffer_sink_ready + attribute \src "ls180.v:517.6-517.51" wire \main_sdram_bankmachine1_cmd_buffer_sink_valid - attribute \src "ls180.v:526.5-526.52" + attribute \src "ls180.v:525.5-525.52" wire \main_sdram_bankmachine1_cmd_buffer_source_first - attribute \src "ls180.v:527.5-527.51" + attribute \src "ls180.v:526.5-526.51" wire \main_sdram_bankmachine1_cmd_buffer_source_last - attribute \src "ls180.v:529.12-529.66" + attribute \src "ls180.v:528.12-528.66" wire width 22 \main_sdram_bankmachine1_cmd_buffer_source_payload_addr - attribute \src "ls180.v:528.5-528.57" + attribute \src "ls180.v:527.5-527.57" wire \main_sdram_bankmachine1_cmd_buffer_source_payload_we - attribute \src "ls180.v:525.6-525.53" + attribute \src "ls180.v:524.6-524.53" wire \main_sdram_bankmachine1_cmd_buffer_source_ready - attribute \src "ls180.v:524.5-524.52" + attribute \src "ls180.v:523.5-523.52" wire \main_sdram_bankmachine1_cmd_buffer_source_valid - attribute \src "ls180.v:472.12-472.49" + attribute \src "ls180.v:471.12-471.49" wire width 13 \main_sdram_bankmachine1_cmd_payload_a - attribute \src "ls180.v:473.12-473.50" + attribute \src "ls180.v:472.12-472.50" wire width 2 \main_sdram_bankmachine1_cmd_payload_ba - attribute \src "ls180.v:474.5-474.44" + attribute \src "ls180.v:473.5-473.44" wire \main_sdram_bankmachine1_cmd_payload_cas - attribute \src "ls180.v:477.5-477.47" + attribute \src "ls180.v:476.5-476.47" wire \main_sdram_bankmachine1_cmd_payload_is_cmd - attribute \src "ls180.v:478.5-478.48" + attribute \src "ls180.v:477.5-477.48" wire \main_sdram_bankmachine1_cmd_payload_is_read - attribute \src "ls180.v:479.5-479.49" + attribute \src "ls180.v:478.5-478.49" wire \main_sdram_bankmachine1_cmd_payload_is_write - attribute \src "ls180.v:475.5-475.44" + attribute \src "ls180.v:474.5-474.44" wire \main_sdram_bankmachine1_cmd_payload_ras - attribute \src "ls180.v:476.5-476.43" + attribute \src "ls180.v:475.5-475.43" wire \main_sdram_bankmachine1_cmd_payload_we - attribute \src "ls180.v:471.5-471.38" - wire \main_sdram_bankmachine1_cmd_ready attribute \src "ls180.v:470.5-470.38" + wire \main_sdram_bankmachine1_cmd_ready + attribute \src "ls180.v:469.5-469.38" wire \main_sdram_bankmachine1_cmd_valid - attribute \src "ls180.v:469.5-469.40" + attribute \src "ls180.v:468.5-468.40" wire \main_sdram_bankmachine1_refresh_gnt - attribute \src "ls180.v:468.6-468.41" + attribute \src "ls180.v:467.6-467.41" wire \main_sdram_bankmachine1_refresh_req - attribute \src "ls180.v:464.13-464.45" + attribute \src "ls180.v:463.13-463.45" wire width 22 \main_sdram_bankmachine1_req_addr - attribute \src "ls180.v:465.6-465.38" + attribute \src "ls180.v:464.6-464.38" wire \main_sdram_bankmachine1_req_lock - attribute \src "ls180.v:467.5-467.44" + attribute \src "ls180.v:466.5-466.44" wire \main_sdram_bankmachine1_req_rdata_valid - attribute \src "ls180.v:462.6-462.39" - wire \main_sdram_bankmachine1_req_ready attribute \src "ls180.v:461.6-461.39" + wire \main_sdram_bankmachine1_req_ready + attribute \src "ls180.v:460.6-460.39" wire \main_sdram_bankmachine1_req_valid - attribute \src "ls180.v:466.5-466.44" + attribute \src "ls180.v:465.5-465.44" wire \main_sdram_bankmachine1_req_wdata_ready - attribute \src "ls180.v:463.6-463.36" + attribute \src "ls180.v:462.6-462.36" wire \main_sdram_bankmachine1_req_we - attribute \src "ls180.v:530.12-530.39" + attribute \src "ls180.v:529.12-529.39" wire width 13 \main_sdram_bankmachine1_row - attribute \src "ls180.v:534.5-534.38" + attribute \src "ls180.v:533.5-533.38" wire \main_sdram_bankmachine1_row_close - attribute \src "ls180.v:535.5-535.47" + attribute \src "ls180.v:534.5-534.47" wire \main_sdram_bankmachine1_row_col_n_addr_sel - attribute \src "ls180.v:532.6-532.37" + attribute \src "ls180.v:531.6-531.37" wire \main_sdram_bankmachine1_row_hit - attribute \src "ls180.v:533.5-533.37" + attribute \src "ls180.v:532.5-532.37" wire \main_sdram_bankmachine1_row_open - attribute \src "ls180.v:531.5-531.39" + attribute \src "ls180.v:530.5-530.39" wire \main_sdram_bankmachine1_row_opened attribute \no_retiming "true" - attribute \src "ls180.v:542.32-542.69" + attribute \src "ls180.v:541.32-541.69" wire \main_sdram_bankmachine1_trascon_ready - attribute \src "ls180.v:541.6-541.43" + attribute \src "ls180.v:540.6-540.43" wire \main_sdram_bankmachine1_trascon_valid attribute \no_retiming "true" - attribute \src "ls180.v:540.32-540.68" + attribute \src "ls180.v:539.32-539.68" wire \main_sdram_bankmachine1_trccon_ready - attribute \src "ls180.v:539.6-539.42" + attribute \src "ls180.v:538.6-538.42" wire \main_sdram_bankmachine1_trccon_valid - attribute \src "ls180.v:538.11-538.48" + attribute \src "ls180.v:537.11-537.48" wire width 3 \main_sdram_bankmachine1_twtpcon_count attribute \no_retiming "true" - attribute \src "ls180.v:537.32-537.69" + attribute \src "ls180.v:536.32-536.69" wire \main_sdram_bankmachine1_twtpcon_ready - attribute \src "ls180.v:536.6-536.43" + attribute \src "ls180.v:535.6-535.43" wire \main_sdram_bankmachine1_twtpcon_valid - attribute \src "ls180.v:562.5-562.43" + attribute \src "ls180.v:561.5-561.43" wire \main_sdram_bankmachine2_auto_precharge - attribute \src "ls180.v:584.11-584.63" + attribute \src "ls180.v:583.11-583.63" wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_consume - attribute \src "ls180.v:589.6-589.58" + attribute \src "ls180.v:588.6-588.58" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:594.6-594.64" + attribute \src "ls180.v:593.6-593.64" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first - attribute \src "ls180.v:595.6-595.63" + attribute \src "ls180.v:594.6-594.63" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last - attribute \src "ls180.v:593.13-593.78" + attribute \src "ls180.v:592.13-592.78" wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr - attribute \src "ls180.v:592.6-592.69" + attribute \src "ls180.v:591.6-591.69" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we - attribute \src "ls180.v:598.6-598.65" + attribute \src "ls180.v:597.6-597.65" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first - attribute \src "ls180.v:599.6-599.64" + attribute \src "ls180.v:598.6-598.64" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last - attribute \src "ls180.v:597.13-597.79" + attribute \src "ls180.v:596.13-596.79" wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr - attribute \src "ls180.v:596.6-596.70" + attribute \src "ls180.v:595.6-595.70" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we - attribute \src "ls180.v:581.11-581.61" + attribute \src "ls180.v:580.11-580.61" wire width 4 \main_sdram_bankmachine2_cmd_buffer_lookahead_level - attribute \src "ls180.v:583.11-583.63" + attribute \src "ls180.v:582.11-582.63" wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_produce - attribute \src "ls180.v:590.12-590.67" + attribute \src "ls180.v:589.12-589.67" wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr - attribute \src "ls180.v:591.13-591.70" + attribute \src "ls180.v:590.13-590.70" wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r - attribute \src "ls180.v:582.5-582.57" + attribute \src "ls180.v:581.5-581.57" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - attribute \src "ls180.v:565.5-565.60" + attribute \src "ls180.v:564.5-564.60" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first - attribute \src "ls180.v:566.5-566.59" + attribute \src "ls180.v:565.5-565.59" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last - attribute \src "ls180.v:568.13-568.75" + attribute \src "ls180.v:567.13-567.75" wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr - attribute \src "ls180.v:567.6-567.66" + attribute \src "ls180.v:566.6-566.66" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we - attribute \src "ls180.v:564.6-564.61" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready attribute \src "ls180.v:563.6-563.61" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready + attribute \src "ls180.v:562.6-562.61" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid - attribute \src "ls180.v:571.6-571.63" + attribute \src "ls180.v:570.6-570.63" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_first - attribute \src "ls180.v:572.6-572.62" + attribute \src "ls180.v:571.6-571.62" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last - attribute \src "ls180.v:574.13-574.77" + attribute \src "ls180.v:573.13-573.77" wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr - attribute \src "ls180.v:573.6-573.68" + attribute \src "ls180.v:572.6-572.68" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we - attribute \src "ls180.v:570.6-570.63" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready attribute \src "ls180.v:569.6-569.63" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready + attribute \src "ls180.v:568.6-568.63" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid - attribute \src "ls180.v:579.13-579.71" + attribute \src "ls180.v:578.13-578.71" wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din - attribute \src "ls180.v:580.13-580.72" + attribute \src "ls180.v:579.13-579.72" wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout - attribute \src "ls180.v:577.6-577.63" + attribute \src "ls180.v:576.6-576.63" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re - attribute \src "ls180.v:578.6-578.69" + attribute \src "ls180.v:577.6-577.69" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable - attribute \src "ls180.v:575.6-575.63" + attribute \src "ls180.v:574.6-574.63" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we - attribute \src "ls180.v:576.6-576.69" + attribute \src "ls180.v:575.6-575.69" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable - attribute \src "ls180.v:585.11-585.66" + attribute \src "ls180.v:584.11-584.66" wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr - attribute \src "ls180.v:586.13-586.70" + attribute \src "ls180.v:585.13-585.70" wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r - attribute \src "ls180.v:588.13-588.70" + attribute \src "ls180.v:587.13-587.70" wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w - attribute \src "ls180.v:587.6-587.60" + attribute \src "ls180.v:586.6-586.60" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:602.6-602.51" + attribute \src "ls180.v:601.6-601.51" wire \main_sdram_bankmachine2_cmd_buffer_sink_first - attribute \src "ls180.v:603.6-603.50" + attribute \src "ls180.v:602.6-602.50" wire \main_sdram_bankmachine2_cmd_buffer_sink_last - attribute \src "ls180.v:605.13-605.65" + attribute \src "ls180.v:604.13-604.65" wire width 22 \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr - attribute \src "ls180.v:604.6-604.56" + attribute \src "ls180.v:603.6-603.56" wire \main_sdram_bankmachine2_cmd_buffer_sink_payload_we - attribute \src "ls180.v:601.6-601.51" - wire \main_sdram_bankmachine2_cmd_buffer_sink_ready attribute \src "ls180.v:600.6-600.51" + wire \main_sdram_bankmachine2_cmd_buffer_sink_ready + attribute \src "ls180.v:599.6-599.51" wire \main_sdram_bankmachine2_cmd_buffer_sink_valid - attribute \src "ls180.v:608.5-608.52" + attribute \src "ls180.v:607.5-607.52" wire \main_sdram_bankmachine2_cmd_buffer_source_first - attribute \src "ls180.v:609.5-609.51" + attribute \src "ls180.v:608.5-608.51" wire \main_sdram_bankmachine2_cmd_buffer_source_last - attribute \src "ls180.v:611.12-611.66" + attribute \src "ls180.v:610.12-610.66" wire width 22 \main_sdram_bankmachine2_cmd_buffer_source_payload_addr - attribute \src "ls180.v:610.5-610.57" + attribute \src "ls180.v:609.5-609.57" wire \main_sdram_bankmachine2_cmd_buffer_source_payload_we - attribute \src "ls180.v:607.6-607.53" + attribute \src "ls180.v:606.6-606.53" wire \main_sdram_bankmachine2_cmd_buffer_source_ready - attribute \src "ls180.v:606.5-606.52" + attribute \src "ls180.v:605.5-605.52" wire \main_sdram_bankmachine2_cmd_buffer_source_valid - attribute \src "ls180.v:554.12-554.49" + attribute \src "ls180.v:553.12-553.49" wire width 13 \main_sdram_bankmachine2_cmd_payload_a - attribute \src "ls180.v:555.12-555.50" + attribute \src "ls180.v:554.12-554.50" wire width 2 \main_sdram_bankmachine2_cmd_payload_ba - attribute \src "ls180.v:556.5-556.44" + attribute \src "ls180.v:555.5-555.44" wire \main_sdram_bankmachine2_cmd_payload_cas - attribute \src "ls180.v:559.5-559.47" + attribute \src "ls180.v:558.5-558.47" wire \main_sdram_bankmachine2_cmd_payload_is_cmd - attribute \src "ls180.v:560.5-560.48" + attribute \src "ls180.v:559.5-559.48" wire \main_sdram_bankmachine2_cmd_payload_is_read - attribute \src "ls180.v:561.5-561.49" + attribute \src "ls180.v:560.5-560.49" wire \main_sdram_bankmachine2_cmd_payload_is_write - attribute \src "ls180.v:557.5-557.44" + attribute \src "ls180.v:556.5-556.44" wire \main_sdram_bankmachine2_cmd_payload_ras - attribute \src "ls180.v:558.5-558.43" + attribute \src "ls180.v:557.5-557.43" wire \main_sdram_bankmachine2_cmd_payload_we - attribute \src "ls180.v:553.5-553.38" - wire \main_sdram_bankmachine2_cmd_ready attribute \src "ls180.v:552.5-552.38" + wire \main_sdram_bankmachine2_cmd_ready + attribute \src "ls180.v:551.5-551.38" wire \main_sdram_bankmachine2_cmd_valid - attribute \src "ls180.v:551.5-551.40" + attribute \src "ls180.v:550.5-550.40" wire \main_sdram_bankmachine2_refresh_gnt - attribute \src "ls180.v:550.6-550.41" + attribute \src "ls180.v:549.6-549.41" wire \main_sdram_bankmachine2_refresh_req - attribute \src "ls180.v:546.13-546.45" + attribute \src "ls180.v:545.13-545.45" wire width 22 \main_sdram_bankmachine2_req_addr - attribute \src "ls180.v:547.6-547.38" + attribute \src "ls180.v:546.6-546.38" wire \main_sdram_bankmachine2_req_lock - attribute \src "ls180.v:549.5-549.44" + attribute \src "ls180.v:548.5-548.44" wire \main_sdram_bankmachine2_req_rdata_valid - attribute \src "ls180.v:544.6-544.39" - wire \main_sdram_bankmachine2_req_ready attribute \src "ls180.v:543.6-543.39" + wire \main_sdram_bankmachine2_req_ready + attribute \src "ls180.v:542.6-542.39" wire \main_sdram_bankmachine2_req_valid - attribute \src "ls180.v:548.5-548.44" + attribute \src "ls180.v:547.5-547.44" wire \main_sdram_bankmachine2_req_wdata_ready - attribute \src "ls180.v:545.6-545.36" + attribute \src "ls180.v:544.6-544.36" wire \main_sdram_bankmachine2_req_we - attribute \src "ls180.v:612.12-612.39" + attribute \src "ls180.v:611.12-611.39" wire width 13 \main_sdram_bankmachine2_row - attribute \src "ls180.v:616.5-616.38" + attribute \src "ls180.v:615.5-615.38" wire \main_sdram_bankmachine2_row_close - attribute \src "ls180.v:617.5-617.47" + attribute \src "ls180.v:616.5-616.47" wire \main_sdram_bankmachine2_row_col_n_addr_sel - attribute \src "ls180.v:614.6-614.37" + attribute \src "ls180.v:613.6-613.37" wire \main_sdram_bankmachine2_row_hit - attribute \src "ls180.v:615.5-615.37" + attribute \src "ls180.v:614.5-614.37" wire \main_sdram_bankmachine2_row_open - attribute \src "ls180.v:613.5-613.39" + attribute \src "ls180.v:612.5-612.39" wire \main_sdram_bankmachine2_row_opened attribute \no_retiming "true" - attribute \src "ls180.v:624.32-624.69" + attribute \src "ls180.v:623.32-623.69" wire \main_sdram_bankmachine2_trascon_ready - attribute \src "ls180.v:623.6-623.43" + attribute \src "ls180.v:622.6-622.43" wire \main_sdram_bankmachine2_trascon_valid attribute \no_retiming "true" - attribute \src "ls180.v:622.32-622.68" + attribute \src "ls180.v:621.32-621.68" wire \main_sdram_bankmachine2_trccon_ready - attribute \src "ls180.v:621.6-621.42" + attribute \src "ls180.v:620.6-620.42" wire \main_sdram_bankmachine2_trccon_valid - attribute \src "ls180.v:620.11-620.48" + attribute \src "ls180.v:619.11-619.48" wire width 3 \main_sdram_bankmachine2_twtpcon_count attribute \no_retiming "true" - attribute \src "ls180.v:619.32-619.69" + attribute \src "ls180.v:618.32-618.69" wire \main_sdram_bankmachine2_twtpcon_ready - attribute \src "ls180.v:618.6-618.43" + attribute \src "ls180.v:617.6-617.43" wire \main_sdram_bankmachine2_twtpcon_valid - attribute \src "ls180.v:644.5-644.43" + attribute \src "ls180.v:643.5-643.43" wire \main_sdram_bankmachine3_auto_precharge - attribute \src "ls180.v:666.11-666.63" + attribute \src "ls180.v:665.11-665.63" wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_consume - attribute \src "ls180.v:671.6-671.58" + attribute \src "ls180.v:670.6-670.58" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:676.6-676.64" + attribute \src "ls180.v:675.6-675.64" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first - attribute \src "ls180.v:677.6-677.63" + attribute \src "ls180.v:676.6-676.63" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last - attribute \src "ls180.v:675.13-675.78" + attribute \src "ls180.v:674.13-674.78" wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr - attribute \src "ls180.v:674.6-674.69" + attribute \src "ls180.v:673.6-673.69" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we - attribute \src "ls180.v:680.6-680.65" + attribute \src "ls180.v:679.6-679.65" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first - attribute \src "ls180.v:681.6-681.64" + attribute \src "ls180.v:680.6-680.64" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last - attribute \src "ls180.v:679.13-679.79" + attribute \src "ls180.v:678.13-678.79" wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr - attribute \src "ls180.v:678.6-678.70" + attribute \src "ls180.v:677.6-677.70" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we - attribute \src "ls180.v:663.11-663.61" + attribute \src "ls180.v:662.11-662.61" wire width 4 \main_sdram_bankmachine3_cmd_buffer_lookahead_level - attribute \src "ls180.v:665.11-665.63" + attribute \src "ls180.v:664.11-664.63" wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_produce - attribute \src "ls180.v:672.12-672.67" + attribute \src "ls180.v:671.12-671.67" wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr - attribute \src "ls180.v:673.13-673.70" + attribute \src "ls180.v:672.13-672.70" wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r - attribute \src "ls180.v:664.5-664.57" + attribute \src "ls180.v:663.5-663.57" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - attribute \src "ls180.v:647.5-647.60" + attribute \src "ls180.v:646.5-646.60" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first - attribute \src "ls180.v:648.5-648.59" + attribute \src "ls180.v:647.5-647.59" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last - attribute \src "ls180.v:650.13-650.75" + attribute \src "ls180.v:649.13-649.75" wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr - attribute \src "ls180.v:649.6-649.66" + attribute \src "ls180.v:648.6-648.66" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we - attribute \src "ls180.v:646.6-646.61" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready attribute \src "ls180.v:645.6-645.61" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready + attribute \src "ls180.v:644.6-644.61" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid - attribute \src "ls180.v:653.6-653.63" + attribute \src "ls180.v:652.6-652.63" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_first - attribute \src "ls180.v:654.6-654.62" + attribute \src "ls180.v:653.6-653.62" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last - attribute \src "ls180.v:656.13-656.77" + attribute \src "ls180.v:655.13-655.77" wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr - attribute \src "ls180.v:655.6-655.68" + attribute \src "ls180.v:654.6-654.68" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we - attribute \src "ls180.v:652.6-652.63" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready attribute \src "ls180.v:651.6-651.63" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready + attribute \src "ls180.v:650.6-650.63" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid - attribute \src "ls180.v:661.13-661.71" + attribute \src "ls180.v:660.13-660.71" wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din - attribute \src "ls180.v:662.13-662.72" + attribute \src "ls180.v:661.13-661.72" wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout - attribute \src "ls180.v:659.6-659.63" + attribute \src "ls180.v:658.6-658.63" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re - attribute \src "ls180.v:660.6-660.69" + attribute \src "ls180.v:659.6-659.69" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable - attribute \src "ls180.v:657.6-657.63" + attribute \src "ls180.v:656.6-656.63" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we - attribute \src "ls180.v:658.6-658.69" + attribute \src "ls180.v:657.6-657.69" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable - attribute \src "ls180.v:667.11-667.66" + attribute \src "ls180.v:666.11-666.66" wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr - attribute \src "ls180.v:668.13-668.70" + attribute \src "ls180.v:667.13-667.70" wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r - attribute \src "ls180.v:670.13-670.70" + attribute \src "ls180.v:669.13-669.70" wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w - attribute \src "ls180.v:669.6-669.60" + attribute \src "ls180.v:668.6-668.60" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:684.6-684.51" + attribute \src "ls180.v:683.6-683.51" wire \main_sdram_bankmachine3_cmd_buffer_sink_first - attribute \src "ls180.v:685.6-685.50" + attribute \src "ls180.v:684.6-684.50" wire \main_sdram_bankmachine3_cmd_buffer_sink_last - attribute \src "ls180.v:687.13-687.65" + attribute \src "ls180.v:686.13-686.65" wire width 22 \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr - attribute \src "ls180.v:686.6-686.56" + attribute \src "ls180.v:685.6-685.56" wire \main_sdram_bankmachine3_cmd_buffer_sink_payload_we - attribute \src "ls180.v:683.6-683.51" - wire \main_sdram_bankmachine3_cmd_buffer_sink_ready attribute \src "ls180.v:682.6-682.51" + wire \main_sdram_bankmachine3_cmd_buffer_sink_ready + attribute \src "ls180.v:681.6-681.51" wire \main_sdram_bankmachine3_cmd_buffer_sink_valid - attribute \src "ls180.v:690.5-690.52" + attribute \src "ls180.v:689.5-689.52" wire \main_sdram_bankmachine3_cmd_buffer_source_first - attribute \src "ls180.v:691.5-691.51" + attribute \src "ls180.v:690.5-690.51" wire \main_sdram_bankmachine3_cmd_buffer_source_last - attribute \src "ls180.v:693.12-693.66" + attribute \src "ls180.v:692.12-692.66" wire width 22 \main_sdram_bankmachine3_cmd_buffer_source_payload_addr - attribute \src "ls180.v:692.5-692.57" + attribute \src "ls180.v:691.5-691.57" wire \main_sdram_bankmachine3_cmd_buffer_source_payload_we - attribute \src "ls180.v:689.6-689.53" + attribute \src "ls180.v:688.6-688.53" wire \main_sdram_bankmachine3_cmd_buffer_source_ready - attribute \src "ls180.v:688.5-688.52" + attribute \src "ls180.v:687.5-687.52" wire \main_sdram_bankmachine3_cmd_buffer_source_valid - attribute \src "ls180.v:636.12-636.49" + attribute \src "ls180.v:635.12-635.49" wire width 13 \main_sdram_bankmachine3_cmd_payload_a - attribute \src "ls180.v:637.12-637.50" + attribute \src "ls180.v:636.12-636.50" wire width 2 \main_sdram_bankmachine3_cmd_payload_ba - attribute \src "ls180.v:638.5-638.44" + attribute \src "ls180.v:637.5-637.44" wire \main_sdram_bankmachine3_cmd_payload_cas - attribute \src "ls180.v:641.5-641.47" + attribute \src "ls180.v:640.5-640.47" wire \main_sdram_bankmachine3_cmd_payload_is_cmd - attribute \src "ls180.v:642.5-642.48" + attribute \src "ls180.v:641.5-641.48" wire \main_sdram_bankmachine3_cmd_payload_is_read - attribute \src "ls180.v:643.5-643.49" + attribute \src "ls180.v:642.5-642.49" wire \main_sdram_bankmachine3_cmd_payload_is_write - attribute \src "ls180.v:639.5-639.44" + attribute \src "ls180.v:638.5-638.44" wire \main_sdram_bankmachine3_cmd_payload_ras - attribute \src "ls180.v:640.5-640.43" + attribute \src "ls180.v:639.5-639.43" wire \main_sdram_bankmachine3_cmd_payload_we - attribute \src "ls180.v:635.5-635.38" - wire \main_sdram_bankmachine3_cmd_ready attribute \src "ls180.v:634.5-634.38" + wire \main_sdram_bankmachine3_cmd_ready + attribute \src "ls180.v:633.5-633.38" wire \main_sdram_bankmachine3_cmd_valid - attribute \src "ls180.v:633.5-633.40" + attribute \src "ls180.v:632.5-632.40" wire \main_sdram_bankmachine3_refresh_gnt - attribute \src "ls180.v:632.6-632.41" + attribute \src "ls180.v:631.6-631.41" wire \main_sdram_bankmachine3_refresh_req - attribute \src "ls180.v:628.13-628.45" + attribute \src "ls180.v:627.13-627.45" wire width 22 \main_sdram_bankmachine3_req_addr - attribute \src "ls180.v:629.6-629.38" + attribute \src "ls180.v:628.6-628.38" wire \main_sdram_bankmachine3_req_lock - attribute \src "ls180.v:631.5-631.44" + attribute \src "ls180.v:630.5-630.44" wire \main_sdram_bankmachine3_req_rdata_valid - attribute \src "ls180.v:626.6-626.39" - wire \main_sdram_bankmachine3_req_ready attribute \src "ls180.v:625.6-625.39" + wire \main_sdram_bankmachine3_req_ready + attribute \src "ls180.v:624.6-624.39" wire \main_sdram_bankmachine3_req_valid - attribute \src "ls180.v:630.5-630.44" + attribute \src "ls180.v:629.5-629.44" wire \main_sdram_bankmachine3_req_wdata_ready - attribute \src "ls180.v:627.6-627.36" + attribute \src "ls180.v:626.6-626.36" wire \main_sdram_bankmachine3_req_we - attribute \src "ls180.v:694.12-694.39" + attribute \src "ls180.v:693.12-693.39" wire width 13 \main_sdram_bankmachine3_row - attribute \src "ls180.v:698.5-698.38" + attribute \src "ls180.v:697.5-697.38" wire \main_sdram_bankmachine3_row_close - attribute \src "ls180.v:699.5-699.47" + attribute \src "ls180.v:698.5-698.47" wire \main_sdram_bankmachine3_row_col_n_addr_sel - attribute \src "ls180.v:696.6-696.37" + attribute \src "ls180.v:695.6-695.37" wire \main_sdram_bankmachine3_row_hit - attribute \src "ls180.v:697.5-697.37" + attribute \src "ls180.v:696.5-696.37" wire \main_sdram_bankmachine3_row_open - attribute \src "ls180.v:695.5-695.39" + attribute \src "ls180.v:694.5-694.39" wire \main_sdram_bankmachine3_row_opened attribute \no_retiming "true" - attribute \src "ls180.v:706.32-706.69" + attribute \src "ls180.v:705.32-705.69" wire \main_sdram_bankmachine3_trascon_ready - attribute \src "ls180.v:705.6-705.43" + attribute \src "ls180.v:704.6-704.43" wire \main_sdram_bankmachine3_trascon_valid attribute \no_retiming "true" - attribute \src "ls180.v:704.32-704.68" + attribute \src "ls180.v:703.32-703.68" wire \main_sdram_bankmachine3_trccon_ready - attribute \src "ls180.v:703.6-703.42" + attribute \src "ls180.v:702.6-702.42" wire \main_sdram_bankmachine3_trccon_valid - attribute \src "ls180.v:702.11-702.48" + attribute \src "ls180.v:701.11-701.48" wire width 3 \main_sdram_bankmachine3_twtpcon_count attribute \no_retiming "true" - attribute \src "ls180.v:701.32-701.69" + attribute \src "ls180.v:700.32-700.69" wire \main_sdram_bankmachine3_twtpcon_ready - attribute \src "ls180.v:700.6-700.43" + attribute \src "ls180.v:699.6-699.43" wire \main_sdram_bankmachine3_twtpcon_valid - attribute \src "ls180.v:708.6-708.28" + attribute \src "ls180.v:707.6-707.28" wire \main_sdram_cas_allowed - attribute \src "ls180.v:726.6-726.30" + attribute \src "ls180.v:725.6-725.30" wire \main_sdram_choose_cmd_ce - attribute \src "ls180.v:715.13-715.48" + attribute \src "ls180.v:714.13-714.48" wire width 13 \main_sdram_choose_cmd_cmd_payload_a - attribute \src "ls180.v:716.12-716.48" + attribute \src "ls180.v:715.12-715.48" wire width 2 \main_sdram_choose_cmd_cmd_payload_ba - attribute \src "ls180.v:717.5-717.42" + attribute \src "ls180.v:716.5-716.42" wire \main_sdram_choose_cmd_cmd_payload_cas - attribute \src "ls180.v:720.6-720.46" + attribute \src "ls180.v:719.6-719.46" wire \main_sdram_choose_cmd_cmd_payload_is_cmd - attribute \src "ls180.v:721.6-721.47" + attribute \src "ls180.v:720.6-720.47" wire \main_sdram_choose_cmd_cmd_payload_is_read - attribute \src "ls180.v:722.6-722.48" + attribute \src "ls180.v:721.6-721.48" wire \main_sdram_choose_cmd_cmd_payload_is_write - attribute \src "ls180.v:718.5-718.42" + attribute \src "ls180.v:717.5-717.42" wire \main_sdram_choose_cmd_cmd_payload_ras - attribute \src "ls180.v:719.5-719.41" + attribute \src "ls180.v:718.5-718.41" wire \main_sdram_choose_cmd_cmd_payload_we - attribute \src "ls180.v:714.5-714.36" + attribute \src "ls180.v:713.5-713.36" wire \main_sdram_choose_cmd_cmd_ready - attribute \src "ls180.v:713.6-713.37" + attribute \src "ls180.v:712.6-712.37" wire \main_sdram_choose_cmd_cmd_valid - attribute \src "ls180.v:725.11-725.38" + attribute \src "ls180.v:724.11-724.38" wire width 2 \main_sdram_choose_cmd_grant - attribute \src "ls180.v:724.12-724.41" + attribute \src "ls180.v:723.12-723.41" wire width 4 \main_sdram_choose_cmd_request - attribute \src "ls180.v:723.11-723.39" + attribute \src "ls180.v:722.11-722.39" wire width 4 \main_sdram_choose_cmd_valids - attribute \src "ls180.v:712.5-712.41" + attribute \src "ls180.v:711.5-711.41" wire \main_sdram_choose_cmd_want_activates - attribute \src "ls180.v:711.5-711.36" + attribute \src "ls180.v:710.5-710.36" wire \main_sdram_choose_cmd_want_cmds - attribute \src "ls180.v:709.5-709.37" + attribute \src "ls180.v:708.5-708.37" wire \main_sdram_choose_cmd_want_reads - attribute \src "ls180.v:710.5-710.38" + attribute \src "ls180.v:709.5-709.38" wire \main_sdram_choose_cmd_want_writes - attribute \src "ls180.v:744.6-744.30" + attribute \src "ls180.v:743.6-743.30" wire \main_sdram_choose_req_ce - attribute \src "ls180.v:733.13-733.48" + attribute \src "ls180.v:732.13-732.48" wire width 13 \main_sdram_choose_req_cmd_payload_a - attribute \src "ls180.v:734.12-734.48" + attribute \src "ls180.v:733.12-733.48" wire width 2 \main_sdram_choose_req_cmd_payload_ba - attribute \src "ls180.v:735.5-735.42" + attribute \src "ls180.v:734.5-734.42" wire \main_sdram_choose_req_cmd_payload_cas - attribute \src "ls180.v:738.6-738.46" + attribute \src "ls180.v:737.6-737.46" wire \main_sdram_choose_req_cmd_payload_is_cmd - attribute \src "ls180.v:739.6-739.47" + attribute \src "ls180.v:738.6-738.47" wire \main_sdram_choose_req_cmd_payload_is_read - attribute \src "ls180.v:740.6-740.48" + attribute \src "ls180.v:739.6-739.48" wire \main_sdram_choose_req_cmd_payload_is_write - attribute \src "ls180.v:736.5-736.42" + attribute \src "ls180.v:735.5-735.42" wire \main_sdram_choose_req_cmd_payload_ras - attribute \src "ls180.v:737.5-737.41" + attribute \src "ls180.v:736.5-736.41" wire \main_sdram_choose_req_cmd_payload_we - attribute \src "ls180.v:732.5-732.36" + attribute \src "ls180.v:731.5-731.36" wire \main_sdram_choose_req_cmd_ready - attribute \src "ls180.v:731.6-731.37" + attribute \src "ls180.v:730.6-730.37" wire \main_sdram_choose_req_cmd_valid - attribute \src "ls180.v:743.11-743.38" + attribute \src "ls180.v:742.11-742.38" wire width 2 \main_sdram_choose_req_grant - attribute \src "ls180.v:742.12-742.41" + attribute \src "ls180.v:741.12-741.41" wire width 4 \main_sdram_choose_req_request - attribute \src "ls180.v:741.11-741.39" + attribute \src "ls180.v:740.11-740.39" wire width 4 \main_sdram_choose_req_valids - attribute \src "ls180.v:730.5-730.41" + attribute \src "ls180.v:729.5-729.41" wire \main_sdram_choose_req_want_activates - attribute \src "ls180.v:729.6-729.37" + attribute \src "ls180.v:728.6-728.37" wire \main_sdram_choose_req_want_cmds - attribute \src "ls180.v:727.5-727.37" + attribute \src "ls180.v:726.5-726.37" wire \main_sdram_choose_req_want_reads - attribute \src "ls180.v:728.5-728.38" + attribute \src "ls180.v:727.5-727.38" wire \main_sdram_choose_req_want_writes - attribute \src "ls180.v:288.6-288.20" + attribute \src "ls180.v:287.6-287.20" wire \main_sdram_cke - attribute \src "ls180.v:356.5-356.24" + attribute \src "ls180.v:355.5-355.24" wire \main_sdram_cmd_last - attribute \src "ls180.v:357.12-357.36" + attribute \src "ls180.v:356.12-356.36" wire width 13 \main_sdram_cmd_payload_a - attribute \src "ls180.v:358.11-358.36" + attribute \src "ls180.v:357.11-357.36" wire width 2 \main_sdram_cmd_payload_ba - attribute \src "ls180.v:359.5-359.31" + attribute \src "ls180.v:358.5-358.31" wire \main_sdram_cmd_payload_cas - attribute \src "ls180.v:362.5-362.35" + attribute \src "ls180.v:361.5-361.35" wire \main_sdram_cmd_payload_is_read - attribute \src "ls180.v:363.5-363.36" + attribute \src "ls180.v:362.5-362.36" wire \main_sdram_cmd_payload_is_write - attribute \src "ls180.v:360.5-360.31" + attribute \src "ls180.v:359.5-359.31" wire \main_sdram_cmd_payload_ras - attribute \src "ls180.v:361.5-361.30" + attribute \src "ls180.v:360.5-360.30" wire \main_sdram_cmd_payload_we - attribute \src "ls180.v:355.5-355.25" - wire \main_sdram_cmd_ready attribute \src "ls180.v:354.5-354.25" + wire \main_sdram_cmd_ready + attribute \src "ls180.v:353.5-353.25" wire \main_sdram_cmd_valid - attribute \src "ls180.v:296.6-296.32" + attribute \src "ls180.v:295.6-295.32" wire \main_sdram_command_issue_r - attribute \src "ls180.v:295.6-295.33" + attribute \src "ls180.v:294.6-294.33" wire \main_sdram_command_issue_re - attribute \src "ls180.v:298.5-298.31" + attribute \src "ls180.v:297.5-297.31" wire \main_sdram_command_issue_w - attribute \src "ls180.v:297.6-297.33" + attribute \src "ls180.v:296.6-296.33" wire \main_sdram_command_issue_we - attribute \src "ls180.v:294.5-294.26" + attribute \src "ls180.v:293.5-293.26" wire \main_sdram_command_re - attribute \src "ls180.v:293.11-293.37" + attribute \src "ls180.v:292.11-292.37" wire width 6 \main_sdram_command_storage - attribute \src "ls180.v:347.5-347.28" + attribute \src "ls180.v:346.5-346.28" wire \main_sdram_dfi_p0_act_n - attribute \src "ls180.v:338.12-338.37" + attribute \src "ls180.v:337.12-337.37" wire width 13 \main_sdram_dfi_p0_address - attribute \src "ls180.v:339.11-339.33" + attribute \src "ls180.v:338.11-338.33" wire width 2 \main_sdram_dfi_p0_bank - attribute \src "ls180.v:340.5-340.28" + attribute \src "ls180.v:339.5-339.28" wire \main_sdram_dfi_p0_cas_n - attribute \src "ls180.v:344.6-344.27" + attribute \src "ls180.v:343.6-343.27" wire \main_sdram_dfi_p0_cke - attribute \src "ls180.v:341.5-341.27" + attribute \src "ls180.v:340.5-340.27" wire \main_sdram_dfi_p0_cs_n - attribute \src "ls180.v:345.6-345.27" + attribute \src "ls180.v:344.6-344.27" wire \main_sdram_dfi_p0_odt - attribute \src "ls180.v:342.5-342.28" + attribute \src "ls180.v:341.5-341.28" wire \main_sdram_dfi_p0_ras_n - attribute \src "ls180.v:352.13-352.37" + attribute \src "ls180.v:351.13-351.37" wire width 16 \main_sdram_dfi_p0_rddata - attribute \src "ls180.v:351.5-351.32" + attribute \src "ls180.v:350.5-350.32" wire \main_sdram_dfi_p0_rddata_en - attribute \src "ls180.v:353.6-353.36" + attribute \src "ls180.v:352.6-352.36" wire \main_sdram_dfi_p0_rddata_valid - attribute \src "ls180.v:346.6-346.31" + attribute \src "ls180.v:345.6-345.31" wire \main_sdram_dfi_p0_reset_n - attribute \src "ls180.v:343.5-343.27" + attribute \src "ls180.v:342.5-342.27" wire \main_sdram_dfi_p0_we_n - attribute \src "ls180.v:348.13-348.37" + attribute \src "ls180.v:347.13-347.37" wire width 16 \main_sdram_dfi_p0_wrdata - attribute \src "ls180.v:349.5-349.32" + attribute \src "ls180.v:348.5-348.32" wire \main_sdram_dfi_p0_wrdata_en - attribute \src "ls180.v:350.12-350.41" + attribute \src "ls180.v:349.12-349.41" wire width 2 \main_sdram_dfi_p0_wrdata_mask - attribute \src "ls180.v:762.5-762.19" + attribute \src "ls180.v:761.5-761.19" wire \main_sdram_en0 - attribute \src "ls180.v:765.5-765.19" + attribute \src "ls180.v:764.5-764.19" wire \main_sdram_en1 - attribute \src "ls180.v:768.6-768.30" + attribute \src "ls180.v:767.6-767.30" wire \main_sdram_go_to_refresh - attribute \src "ls180.v:310.13-310.44" + attribute \src "ls180.v:309.13-309.44" wire width 22 \main_sdram_interface_bank0_addr - attribute \src "ls180.v:311.6-311.37" + attribute \src "ls180.v:310.6-310.37" wire \main_sdram_interface_bank0_lock - attribute \src "ls180.v:313.6-313.44" + attribute \src "ls180.v:312.6-312.44" wire \main_sdram_interface_bank0_rdata_valid - attribute \src "ls180.v:308.6-308.38" - wire \main_sdram_interface_bank0_ready attribute \src "ls180.v:307.6-307.38" + wire \main_sdram_interface_bank0_ready + attribute \src "ls180.v:306.6-306.38" wire \main_sdram_interface_bank0_valid - attribute \src "ls180.v:312.6-312.44" + attribute \src "ls180.v:311.6-311.44" wire \main_sdram_interface_bank0_wdata_ready - attribute \src "ls180.v:309.6-309.35" + attribute \src "ls180.v:308.6-308.35" wire \main_sdram_interface_bank0_we - attribute \src "ls180.v:317.13-317.44" + attribute \src "ls180.v:316.13-316.44" wire width 22 \main_sdram_interface_bank1_addr - attribute \src "ls180.v:318.6-318.37" + attribute \src "ls180.v:317.6-317.37" wire \main_sdram_interface_bank1_lock - attribute \src "ls180.v:320.6-320.44" + attribute \src "ls180.v:319.6-319.44" wire \main_sdram_interface_bank1_rdata_valid - attribute \src "ls180.v:315.6-315.38" - wire \main_sdram_interface_bank1_ready attribute \src "ls180.v:314.6-314.38" + wire \main_sdram_interface_bank1_ready + attribute \src "ls180.v:313.6-313.38" wire \main_sdram_interface_bank1_valid - attribute \src "ls180.v:319.6-319.44" + attribute \src "ls180.v:318.6-318.44" wire \main_sdram_interface_bank1_wdata_ready - attribute \src "ls180.v:316.6-316.35" + attribute \src "ls180.v:315.6-315.35" wire \main_sdram_interface_bank1_we - attribute \src "ls180.v:324.13-324.44" + attribute \src "ls180.v:323.13-323.44" wire width 22 \main_sdram_interface_bank2_addr - attribute \src "ls180.v:325.6-325.37" + attribute \src "ls180.v:324.6-324.37" wire \main_sdram_interface_bank2_lock - attribute \src "ls180.v:327.6-327.44" + attribute \src "ls180.v:326.6-326.44" wire \main_sdram_interface_bank2_rdata_valid - attribute \src "ls180.v:322.6-322.38" - wire \main_sdram_interface_bank2_ready attribute \src "ls180.v:321.6-321.38" + wire \main_sdram_interface_bank2_ready + attribute \src "ls180.v:320.6-320.38" wire \main_sdram_interface_bank2_valid - attribute \src "ls180.v:326.6-326.44" + attribute \src "ls180.v:325.6-325.44" wire \main_sdram_interface_bank2_wdata_ready - attribute \src "ls180.v:323.6-323.35" + attribute \src "ls180.v:322.6-322.35" wire \main_sdram_interface_bank2_we - attribute \src "ls180.v:331.13-331.44" + attribute \src "ls180.v:330.13-330.44" wire width 22 \main_sdram_interface_bank3_addr - attribute \src "ls180.v:332.6-332.37" + attribute \src "ls180.v:331.6-331.37" wire \main_sdram_interface_bank3_lock - attribute \src "ls180.v:334.6-334.44" + attribute \src "ls180.v:333.6-333.44" wire \main_sdram_interface_bank3_rdata_valid - attribute \src "ls180.v:329.6-329.38" - wire \main_sdram_interface_bank3_ready attribute \src "ls180.v:328.6-328.38" + wire \main_sdram_interface_bank3_ready + attribute \src "ls180.v:327.6-327.38" wire \main_sdram_interface_bank3_valid - attribute \src "ls180.v:333.6-333.44" + attribute \src "ls180.v:332.6-332.44" wire \main_sdram_interface_bank3_wdata_ready - attribute \src "ls180.v:330.6-330.35" + attribute \src "ls180.v:329.6-329.35" wire \main_sdram_interface_bank3_we - attribute \src "ls180.v:337.13-337.39" + attribute \src "ls180.v:336.13-336.39" wire width 16 \main_sdram_interface_rdata - attribute \src "ls180.v:335.12-335.38" + attribute \src "ls180.v:334.12-334.38" wire width 16 \main_sdram_interface_wdata - attribute \src "ls180.v:336.11-336.40" + attribute \src "ls180.v:335.11-335.40" wire width 2 \main_sdram_interface_wdata_we - attribute \src "ls180.v:248.5-248.29" + attribute \src "ls180.v:247.5-247.29" wire \main_sdram_inti_p0_act_n - attribute \src "ls180.v:239.13-239.39" + attribute \src "ls180.v:238.13-238.39" wire width 13 \main_sdram_inti_p0_address - attribute \src "ls180.v:240.12-240.35" + attribute \src "ls180.v:239.12-239.35" wire width 2 \main_sdram_inti_p0_bank - attribute \src "ls180.v:241.5-241.29" + attribute \src "ls180.v:240.5-240.29" wire \main_sdram_inti_p0_cas_n - attribute \src "ls180.v:245.6-245.28" + attribute \src "ls180.v:244.6-244.28" wire \main_sdram_inti_p0_cke - attribute \src "ls180.v:242.5-242.28" + attribute \src "ls180.v:241.5-241.28" wire \main_sdram_inti_p0_cs_n - attribute \src "ls180.v:246.6-246.28" + attribute \src "ls180.v:245.6-245.28" wire \main_sdram_inti_p0_odt - attribute \src "ls180.v:243.5-243.29" + attribute \src "ls180.v:242.5-242.29" wire \main_sdram_inti_p0_ras_n - attribute \src "ls180.v:253.12-253.37" + attribute \src "ls180.v:252.12-252.37" wire width 16 \main_sdram_inti_p0_rddata - attribute \src "ls180.v:252.6-252.34" + attribute \src "ls180.v:251.6-251.34" wire \main_sdram_inti_p0_rddata_en - attribute \src "ls180.v:254.5-254.36" + attribute \src "ls180.v:253.5-253.36" wire \main_sdram_inti_p0_rddata_valid - attribute \src "ls180.v:247.6-247.32" + attribute \src "ls180.v:246.6-246.32" wire \main_sdram_inti_p0_reset_n - attribute \src "ls180.v:244.5-244.28" + attribute \src "ls180.v:243.5-243.28" wire \main_sdram_inti_p0_we_n - attribute \src "ls180.v:249.13-249.38" + attribute \src "ls180.v:248.13-248.38" wire width 16 \main_sdram_inti_p0_wrdata - attribute \src "ls180.v:250.6-250.34" + attribute \src "ls180.v:249.6-249.34" wire \main_sdram_inti_p0_wrdata_en - attribute \src "ls180.v:251.12-251.42" + attribute \src "ls180.v:250.12-250.42" wire width 2 \main_sdram_inti_p0_wrdata_mask - attribute \src "ls180.v:280.5-280.31" + attribute \src "ls180.v:279.5-279.31" wire \main_sdram_master_p0_act_n - attribute \src "ls180.v:271.12-271.40" + attribute \src "ls180.v:270.12-270.40" wire width 13 \main_sdram_master_p0_address - attribute \src "ls180.v:272.11-272.36" + attribute \src "ls180.v:271.11-271.36" wire width 2 \main_sdram_master_p0_bank - attribute \src "ls180.v:273.5-273.31" + attribute \src "ls180.v:272.5-272.31" wire \main_sdram_master_p0_cas_n - attribute \src "ls180.v:277.5-277.29" + attribute \src "ls180.v:276.5-276.29" wire \main_sdram_master_p0_cke - attribute \src "ls180.v:274.5-274.30" + attribute \src "ls180.v:273.5-273.30" wire \main_sdram_master_p0_cs_n - attribute \src "ls180.v:278.5-278.29" + attribute \src "ls180.v:277.5-277.29" wire \main_sdram_master_p0_odt - attribute \src "ls180.v:275.5-275.31" + attribute \src "ls180.v:274.5-274.31" wire \main_sdram_master_p0_ras_n - attribute \src "ls180.v:285.13-285.40" + attribute \src "ls180.v:284.13-284.40" wire width 16 \main_sdram_master_p0_rddata - attribute \src "ls180.v:284.5-284.35" + attribute \src "ls180.v:283.5-283.35" wire \main_sdram_master_p0_rddata_en - attribute \src "ls180.v:286.6-286.39" + attribute \src "ls180.v:285.6-285.39" wire \main_sdram_master_p0_rddata_valid - attribute \src "ls180.v:279.5-279.33" + attribute \src "ls180.v:278.5-278.33" wire \main_sdram_master_p0_reset_n - attribute \src "ls180.v:276.5-276.30" + attribute \src "ls180.v:275.5-275.30" wire \main_sdram_master_p0_we_n - attribute \src "ls180.v:281.12-281.39" + attribute \src "ls180.v:280.12-280.39" wire width 16 \main_sdram_master_p0_wrdata - attribute \src "ls180.v:282.5-282.35" + attribute \src "ls180.v:281.5-281.35" wire \main_sdram_master_p0_wrdata_en - attribute \src "ls180.v:283.11-283.43" + attribute \src "ls180.v:282.11-282.43" wire width 2 \main_sdram_master_p0_wrdata_mask - attribute \src "ls180.v:763.6-763.26" + attribute \src "ls180.v:762.6-762.26" wire \main_sdram_max_time0 - attribute \src "ls180.v:766.6-766.26" + attribute \src "ls180.v:765.6-765.26" wire \main_sdram_max_time1 - attribute \src "ls180.v:745.12-745.28" + attribute \src "ls180.v:744.12-744.28" wire width 13 \main_sdram_nop_a - attribute \src "ls180.v:746.11-746.28" + attribute \src "ls180.v:745.11-745.28" wire width 2 \main_sdram_nop_ba - attribute \src "ls180.v:289.6-289.20" + attribute \src "ls180.v:288.6-288.20" wire \main_sdram_odt - attribute \src "ls180.v:372.5-372.31" + attribute \src "ls180.v:371.5-371.31" wire \main_sdram_postponer_count - attribute \src "ls180.v:370.6-370.32" + attribute \src "ls180.v:369.6-369.32" wire \main_sdram_postponer_req_i - attribute \src "ls180.v:371.5-371.31" + attribute \src "ls180.v:370.5-370.31" wire \main_sdram_postponer_req_o - attribute \src "ls180.v:707.6-707.28" + attribute \src "ls180.v:706.6-706.28" wire \main_sdram_ras_allowed - attribute \src "ls180.v:292.5-292.18" + attribute \src "ls180.v:291.5-291.18" wire \main_sdram_re - attribute \src "ls180.v:760.6-760.31" + attribute \src "ls180.v:759.6-759.31" wire \main_sdram_read_available - attribute \src "ls180.v:290.6-290.24" + attribute \src "ls180.v:289.6-289.24" wire \main_sdram_reset_n - attribute \src "ls180.v:287.6-287.20" + attribute \src "ls180.v:286.6-286.20" wire \main_sdram_sel - attribute \src "ls180.v:378.5-378.31" + attribute \src "ls180.v:377.5-377.31" wire \main_sdram_sequencer_count - attribute \src "ls180.v:377.11-377.39" + attribute \src "ls180.v:376.11-376.39" wire width 4 \main_sdram_sequencer_counter - attribute \src "ls180.v:374.6-374.32" + attribute \src "ls180.v:373.6-373.32" wire \main_sdram_sequencer_done0 - attribute \src "ls180.v:376.5-376.31" + attribute \src "ls180.v:375.5-375.31" wire \main_sdram_sequencer_done1 - attribute \src "ls180.v:373.5-373.32" + attribute \src "ls180.v:372.5-372.32" wire \main_sdram_sequencer_start0 - attribute \src "ls180.v:375.6-375.33" + attribute \src "ls180.v:374.6-374.33" wire \main_sdram_sequencer_start1 - attribute \src "ls180.v:264.6-264.31" + attribute \src "ls180.v:263.6-263.31" wire \main_sdram_slave_p0_act_n - attribute \src "ls180.v:255.13-255.40" + attribute \src "ls180.v:254.13-254.40" wire width 13 \main_sdram_slave_p0_address - attribute \src "ls180.v:256.12-256.36" + attribute \src "ls180.v:255.12-255.36" wire width 2 \main_sdram_slave_p0_bank - attribute \src "ls180.v:257.6-257.31" + attribute \src "ls180.v:256.6-256.31" wire \main_sdram_slave_p0_cas_n - attribute \src "ls180.v:261.6-261.29" + attribute \src "ls180.v:260.6-260.29" wire \main_sdram_slave_p0_cke - attribute \src "ls180.v:258.6-258.30" + attribute \src "ls180.v:257.6-257.30" wire \main_sdram_slave_p0_cs_n - attribute \src "ls180.v:262.6-262.29" + attribute \src "ls180.v:261.6-261.29" wire \main_sdram_slave_p0_odt - attribute \src "ls180.v:259.6-259.31" + attribute \src "ls180.v:258.6-258.31" wire \main_sdram_slave_p0_ras_n - attribute \src "ls180.v:269.12-269.38" + attribute \src "ls180.v:268.12-268.38" wire width 16 \main_sdram_slave_p0_rddata - attribute \src "ls180.v:268.6-268.35" + attribute \src "ls180.v:267.6-267.35" wire \main_sdram_slave_p0_rddata_en - attribute \src "ls180.v:270.5-270.37" + attribute \src "ls180.v:269.5-269.37" wire \main_sdram_slave_p0_rddata_valid - attribute \src "ls180.v:263.6-263.33" + attribute \src "ls180.v:262.6-262.33" wire \main_sdram_slave_p0_reset_n - attribute \src "ls180.v:260.6-260.30" + attribute \src "ls180.v:259.6-259.30" wire \main_sdram_slave_p0_we_n - attribute \src "ls180.v:265.13-265.39" + attribute \src "ls180.v:264.13-264.39" wire width 16 \main_sdram_slave_p0_wrdata - attribute \src "ls180.v:266.6-266.35" + attribute \src "ls180.v:265.6-265.35" wire \main_sdram_slave_p0_wrdata_en - attribute \src "ls180.v:267.12-267.43" + attribute \src "ls180.v:266.12-266.43" wire width 2 \main_sdram_slave_p0_wrdata_mask - attribute \src "ls180.v:305.12-305.29" + attribute \src "ls180.v:304.12-304.29" wire width 16 \main_sdram_status - attribute \src "ls180.v:748.5-748.24" + attribute \src "ls180.v:747.5-747.24" wire \main_sdram_steerer0 - attribute \src "ls180.v:749.5-749.24" + attribute \src "ls180.v:748.5-748.24" wire \main_sdram_steerer1 - attribute \src "ls180.v:747.11-747.33" + attribute \src "ls180.v:746.11-746.33" wire width 2 \main_sdram_steerer_sel - attribute \src "ls180.v:291.11-291.29" + attribute \src "ls180.v:290.11-290.29" wire width 4 \main_sdram_storage - attribute \src "ls180.v:756.5-756.29" + attribute \src "ls180.v:755.5-755.29" wire \main_sdram_tccdcon_count attribute \no_retiming "true" - attribute \src "ls180.v:755.32-755.56" + attribute \src "ls180.v:754.32-754.56" wire \main_sdram_tccdcon_ready - attribute \src "ls180.v:754.6-754.30" + attribute \src "ls180.v:753.6-753.30" wire \main_sdram_tccdcon_valid attribute \no_retiming "true" - attribute \src "ls180.v:753.32-753.56" + attribute \src "ls180.v:752.32-752.56" wire \main_sdram_tfawcon_ready - attribute \src "ls180.v:752.6-752.30" + attribute \src "ls180.v:751.6-751.30" wire \main_sdram_tfawcon_valid - attribute \src "ls180.v:764.11-764.27" + attribute \src "ls180.v:763.11-763.27" wire width 5 \main_sdram_time0 - attribute \src "ls180.v:767.11-767.27" + attribute \src "ls180.v:766.11-766.27" wire width 4 \main_sdram_time1 - attribute \src "ls180.v:367.12-367.35" + attribute \src "ls180.v:366.12-366.35" wire width 10 \main_sdram_timer_count0 - attribute \src "ls180.v:369.11-369.34" + attribute \src "ls180.v:368.11-368.34" wire width 10 \main_sdram_timer_count1 - attribute \src "ls180.v:366.6-366.28" + attribute \src "ls180.v:365.6-365.28" wire \main_sdram_timer_done0 - attribute \src "ls180.v:368.6-368.28" + attribute \src "ls180.v:367.6-367.28" wire \main_sdram_timer_done1 - attribute \src "ls180.v:365.6-365.27" + attribute \src "ls180.v:364.6-364.27" wire \main_sdram_timer_wait attribute \no_retiming "true" - attribute \src "ls180.v:751.32-751.56" + attribute \src "ls180.v:750.32-750.56" wire \main_sdram_trrdcon_ready - attribute \src "ls180.v:750.6-750.30" + attribute \src "ls180.v:749.6-749.30" wire \main_sdram_trrdcon_valid - attribute \src "ls180.v:759.11-759.35" + attribute \src "ls180.v:758.11-758.35" wire width 3 \main_sdram_twtrcon_count attribute \no_retiming "true" - attribute \src "ls180.v:758.32-758.56" + attribute \src "ls180.v:757.32-757.56" wire \main_sdram_twtrcon_ready - attribute \src "ls180.v:757.6-757.30" + attribute \src "ls180.v:756.6-756.30" wire \main_sdram_twtrcon_valid - attribute \src "ls180.v:364.6-364.30" + attribute \src "ls180.v:363.6-363.30" wire \main_sdram_wants_refresh - attribute \src "ls180.v:306.6-306.19" + attribute \src "ls180.v:305.6-305.19" wire \main_sdram_we - attribute \src "ls180.v:304.5-304.25" + attribute \src "ls180.v:303.5-303.25" wire \main_sdram_wrdata_re - attribute \src "ls180.v:303.12-303.37" + attribute \src "ls180.v:302.12-302.37" wire width 16 \main_sdram_wrdata_storage - attribute \src "ls180.v:761.6-761.32" + attribute \src "ls180.v:760.6-760.32" wire \main_sdram_write_available - attribute \src "ls180.v:814.6-814.21" + attribute \src "ls180.v:813.6-813.21" wire \main_sink_first - attribute \src "ls180.v:815.6-815.20" + attribute \src "ls180.v:814.6-814.20" wire \main_sink_last - attribute \src "ls180.v:816.12-816.34" + attribute \src "ls180.v:815.12-815.34" wire width 8 \main_sink_payload_data - attribute \src "ls180.v:813.5-813.20" + attribute \src "ls180.v:812.5-812.20" wire \main_sink_ready - attribute \src "ls180.v:812.6-812.21" + attribute \src "ls180.v:811.6-811.21" wire \main_sink_valid - attribute \src "ls180.v:824.5-824.22" + attribute \src "ls180.v:823.5-823.22" wire \main_source_first - attribute \src "ls180.v:825.5-825.21" + attribute \src "ls180.v:824.5-824.21" wire \main_source_last - attribute \src "ls180.v:826.11-826.35" + attribute \src "ls180.v:825.11-825.35" wire width 8 \main_source_payload_data - attribute \src "ls180.v:823.6-823.23" + attribute \src "ls180.v:822.6-822.23" wire \main_source_ready - attribute \src "ls180.v:822.5-822.22" + attribute \src "ls180.v:821.5-821.22" wire \main_source_valid - attribute \src "ls180.v:969.12-969.40" + attribute \src "ls180.v:968.12-968.40" wire width 16 \main_spi_master_clk_divider0 - attribute \src "ls180.v:991.12-991.40" + attribute \src "ls180.v:990.12-990.40" wire width 16 \main_spi_master_clk_divider1 - attribute \src "ls180.v:986.5-986.31" + attribute \src "ls180.v:985.5-985.31" wire \main_spi_master_clk_enable - attribute \src "ls180.v:993.6-993.30" - wire \main_spi_master_clk_fall attribute \src "ls180.v:992.6-992.30" + wire \main_spi_master_clk_fall + attribute \src "ls180.v:991.6-991.30" wire \main_spi_master_clk_rise - attribute \src "ls180.v:973.5-973.31" + attribute \src "ls180.v:972.5-972.31" wire \main_spi_master_control_re - attribute \src "ls180.v:972.12-972.43" + attribute \src "ls180.v:971.12-971.43" wire width 16 \main_spi_master_control_storage - attribute \src "ls180.v:988.11-988.32" + attribute \src "ls180.v:987.11-987.32" wire width 3 \main_spi_master_count - attribute \src "ls180.v:1746.11-1746.54" + attribute \src "ls180.v:1745.11-1745.54" wire width 3 \main_spi_master_count_spimaster0_next_value - attribute \src "ls180.v:1747.5-1747.51" + attribute \src "ls180.v:1746.5-1746.51" wire \main_spi_master_count_spimaster0_next_value_ce - attribute \src "ls180.v:967.6-967.24" + attribute \src "ls180.v:966.6-966.24" wire \main_spi_master_cs - attribute \src "ls180.v:987.5-987.30" + attribute \src "ls180.v:986.5-986.30" wire \main_spi_master_cs_enable - attribute \src "ls180.v:983.5-983.26" + attribute \src "ls180.v:982.5-982.26" wire \main_spi_master_cs_re - attribute \src "ls180.v:982.5-982.31" + attribute \src "ls180.v:981.5-981.31" wire \main_spi_master_cs_storage - attribute \src "ls180.v:963.5-963.26" + attribute \src "ls180.v:962.5-962.26" wire \main_spi_master_done0 - attribute \src "ls180.v:974.6-974.27" + attribute \src "ls180.v:973.6-973.27" wire \main_spi_master_done1 - attribute \src "ls180.v:964.5-964.24" + attribute \src "ls180.v:963.5-963.24" wire \main_spi_master_irq - attribute \src "ls180.v:962.12-962.35" + attribute \src "ls180.v:961.12-961.35" wire width 8 \main_spi_master_length0 - attribute \src "ls180.v:971.12-971.35" + attribute \src "ls180.v:970.12-970.35" wire width 8 \main_spi_master_length1 - attribute \src "ls180.v:968.6-968.30" + attribute \src "ls180.v:967.6-967.30" wire \main_spi_master_loopback - attribute \src "ls180.v:985.5-985.32" + attribute \src "ls180.v:984.5-984.32" wire \main_spi_master_loopback_re - attribute \src "ls180.v:984.5-984.37" + attribute \src "ls180.v:983.5-983.37" wire \main_spi_master_loopback_storage - attribute \src "ls180.v:966.11-966.31" + attribute \src "ls180.v:965.11-965.31" wire width 8 \main_spi_master_miso - attribute \src "ls180.v:996.11-996.36" + attribute \src "ls180.v:995.11-995.36" wire width 8 \main_spi_master_miso_data - attribute \src "ls180.v:990.5-990.31" + attribute \src "ls180.v:989.5-989.31" wire \main_spi_master_miso_latch - attribute \src "ls180.v:979.12-979.39" + attribute \src "ls180.v:978.12-978.39" wire width 8 \main_spi_master_miso_status - attribute \src "ls180.v:980.6-980.29" + attribute \src "ls180.v:979.6-979.29" wire \main_spi_master_miso_we - attribute \src "ls180.v:965.12-965.32" + attribute \src "ls180.v:964.12-964.32" wire width 8 \main_spi_master_mosi - attribute \src "ls180.v:994.11-994.36" + attribute \src "ls180.v:993.11-993.36" wire width 8 \main_spi_master_mosi_data - attribute \src "ls180.v:989.5-989.31" + attribute \src "ls180.v:988.5-988.31" wire \main_spi_master_mosi_latch - attribute \src "ls180.v:978.5-978.28" + attribute \src "ls180.v:977.5-977.28" wire \main_spi_master_mosi_re - attribute \src "ls180.v:995.11-995.35" + attribute \src "ls180.v:994.11-994.35" wire width 3 \main_spi_master_mosi_sel - attribute \src "ls180.v:977.11-977.39" + attribute \src "ls180.v:976.11-976.39" wire width 8 \main_spi_master_mosi_storage - attribute \src "ls180.v:981.6-981.25" + attribute \src "ls180.v:980.6-980.25" wire \main_spi_master_sel - attribute \src "ls180.v:961.6-961.28" + attribute \src "ls180.v:960.6-960.28" wire \main_spi_master_start0 - attribute \src "ls180.v:970.5-970.27" + attribute \src "ls180.v:969.5-969.27" wire \main_spi_master_start1 - attribute \src "ls180.v:975.6-975.35" + attribute \src "ls180.v:974.6-974.35" wire \main_spi_master_status_status - attribute \src "ls180.v:976.6-976.31" + attribute \src "ls180.v:975.6-975.31" wire \main_spi_master_status_we - attribute \src "ls180.v:810.12-810.24" + attribute \src "ls180.v:809.12-809.24" wire width 32 \main_storage - attribute \src "ls180.v:820.11-820.27" + attribute \src "ls180.v:819.11-819.27" wire width 4 \main_tx_bitcount - attribute \src "ls180.v:821.5-821.17" + attribute \src "ls180.v:820.5-820.17" wire \main_tx_busy - attribute \src "ls180.v:819.11-819.22" + attribute \src "ls180.v:818.11-818.22" wire width 8 \main_tx_reg - attribute \src "ls180.v:827.5-827.23" + attribute \src "ls180.v:826.5-826.23" wire \main_uart_clk_rxen - attribute \src "ls180.v:817.5-817.23" + attribute \src "ls180.v:816.5-816.23" wire \main_uart_clk_txen - attribute \src "ls180.v:858.12-858.44" + attribute \src "ls180.v:857.12-857.44" wire width 2 \main_uart_eventmanager_pending_r - attribute \src "ls180.v:857.6-857.39" + attribute \src "ls180.v:856.6-856.39" wire \main_uart_eventmanager_pending_re - attribute \src "ls180.v:860.11-860.43" + attribute \src "ls180.v:859.11-859.43" wire width 2 \main_uart_eventmanager_pending_w - attribute \src "ls180.v:859.6-859.39" + attribute \src "ls180.v:858.6-858.39" wire \main_uart_eventmanager_pending_we - attribute \src "ls180.v:862.5-862.30" + attribute \src "ls180.v:861.5-861.30" wire \main_uart_eventmanager_re - attribute \src "ls180.v:854.12-854.43" + attribute \src "ls180.v:853.12-853.43" wire width 2 \main_uart_eventmanager_status_r - attribute \src "ls180.v:853.6-853.38" + attribute \src "ls180.v:852.6-852.38" wire \main_uart_eventmanager_status_re - attribute \src "ls180.v:856.11-856.42" + attribute \src "ls180.v:855.11-855.42" wire width 2 \main_uart_eventmanager_status_w - attribute \src "ls180.v:855.6-855.38" + attribute \src "ls180.v:854.6-854.38" wire \main_uart_eventmanager_status_we - attribute \src "ls180.v:861.11-861.41" + attribute \src "ls180.v:860.11-860.41" wire width 2 \main_uart_eventmanager_storage - attribute \src "ls180.v:842.6-842.19" + attribute \src "ls180.v:841.6-841.19" wire \main_uart_irq - attribute \src "ls180.v:951.5-951.20" + attribute \src "ls180.v:950.5-950.20" wire \main_uart_reset - attribute \src "ls180.v:851.5-851.23" + attribute \src "ls180.v:850.5-850.23" wire \main_uart_rx_clear - attribute \src "ls180.v:935.11-935.36" + attribute \src "ls180.v:934.11-934.36" wire width 4 \main_uart_rx_fifo_consume - attribute \src "ls180.v:940.6-940.31" + attribute \src "ls180.v:939.6-939.31" wire \main_uart_rx_fifo_do_read - attribute \src "ls180.v:946.6-946.37" + attribute \src "ls180.v:945.6-945.37" wire \main_uart_rx_fifo_fifo_in_first - attribute \src "ls180.v:947.6-947.36" + attribute \src "ls180.v:946.6-946.36" wire \main_uart_rx_fifo_fifo_in_last - attribute \src "ls180.v:945.12-945.50" + attribute \src "ls180.v:944.12-944.50" wire width 8 \main_uart_rx_fifo_fifo_in_payload_data - attribute \src "ls180.v:949.6-949.38" + attribute \src "ls180.v:948.6-948.38" wire \main_uart_rx_fifo_fifo_out_first - attribute \src "ls180.v:950.6-950.37" + attribute \src "ls180.v:949.6-949.37" wire \main_uart_rx_fifo_fifo_out_last - attribute \src "ls180.v:948.12-948.51" + attribute \src "ls180.v:947.12-947.51" wire width 8 \main_uart_rx_fifo_fifo_out_payload_data - attribute \src "ls180.v:932.11-932.35" + attribute \src "ls180.v:931.11-931.35" wire width 5 \main_uart_rx_fifo_level0 - attribute \src "ls180.v:944.12-944.36" + attribute \src "ls180.v:943.12-943.36" wire width 5 \main_uart_rx_fifo_level1 - attribute \src "ls180.v:934.11-934.36" + attribute \src "ls180.v:933.11-933.36" wire width 4 \main_uart_rx_fifo_produce - attribute \src "ls180.v:941.12-941.40" + attribute \src "ls180.v:940.12-940.40" wire width 4 \main_uart_rx_fifo_rdport_adr - attribute \src "ls180.v:942.12-942.42" + attribute \src "ls180.v:941.12-941.42" wire width 10 \main_uart_rx_fifo_rdport_dat_r - attribute \src "ls180.v:943.6-943.33" + attribute \src "ls180.v:942.6-942.33" wire \main_uart_rx_fifo_rdport_re - attribute \src "ls180.v:924.6-924.26" + attribute \src "ls180.v:923.6-923.26" wire \main_uart_rx_fifo_re - attribute \src "ls180.v:925.5-925.31" + attribute \src "ls180.v:924.5-924.31" wire \main_uart_rx_fifo_readable - attribute \src "ls180.v:933.5-933.30" + attribute \src "ls180.v:932.5-932.30" wire \main_uart_rx_fifo_replace - attribute \src "ls180.v:916.6-916.34" + attribute \src "ls180.v:915.6-915.34" wire \main_uart_rx_fifo_sink_first - attribute \src "ls180.v:917.6-917.33" + attribute \src "ls180.v:916.6-916.33" wire \main_uart_rx_fifo_sink_last - attribute \src "ls180.v:918.12-918.47" + attribute \src "ls180.v:917.12-917.47" wire width 8 \main_uart_rx_fifo_sink_payload_data - attribute \src "ls180.v:915.6-915.34" - wire \main_uart_rx_fifo_sink_ready attribute \src "ls180.v:914.6-914.34" + wire \main_uart_rx_fifo_sink_ready + attribute \src "ls180.v:913.6-913.34" wire \main_uart_rx_fifo_sink_valid - attribute \src "ls180.v:921.6-921.36" + attribute \src "ls180.v:920.6-920.36" wire \main_uart_rx_fifo_source_first - attribute \src "ls180.v:922.6-922.35" + attribute \src "ls180.v:921.6-921.35" wire \main_uart_rx_fifo_source_last - attribute \src "ls180.v:923.12-923.49" + attribute \src "ls180.v:922.12-922.49" wire width 8 \main_uart_rx_fifo_source_payload_data - attribute \src "ls180.v:920.6-920.36" - wire \main_uart_rx_fifo_source_ready attribute \src "ls180.v:919.6-919.36" + wire \main_uart_rx_fifo_source_ready + attribute \src "ls180.v:918.6-918.36" wire \main_uart_rx_fifo_source_valid - attribute \src "ls180.v:930.12-930.42" + attribute \src "ls180.v:929.12-929.42" wire width 10 \main_uart_rx_fifo_syncfifo_din - attribute \src "ls180.v:931.12-931.43" + attribute \src "ls180.v:930.12-930.43" wire width 10 \main_uart_rx_fifo_syncfifo_dout - attribute \src "ls180.v:928.6-928.35" + attribute \src "ls180.v:927.6-927.35" wire \main_uart_rx_fifo_syncfifo_re - attribute \src "ls180.v:929.6-929.41" + attribute \src "ls180.v:928.6-928.41" wire \main_uart_rx_fifo_syncfifo_readable - attribute \src "ls180.v:926.6-926.35" + attribute \src "ls180.v:925.6-925.35" wire \main_uart_rx_fifo_syncfifo_we - attribute \src "ls180.v:927.6-927.41" + attribute \src "ls180.v:926.6-926.41" wire \main_uart_rx_fifo_syncfifo_writable - attribute \src "ls180.v:936.11-936.39" + attribute \src "ls180.v:935.11-935.39" wire width 4 \main_uart_rx_fifo_wrport_adr - attribute \src "ls180.v:937.12-937.42" + attribute \src "ls180.v:936.12-936.42" wire width 10 \main_uart_rx_fifo_wrport_dat_r - attribute \src "ls180.v:939.12-939.42" + attribute \src "ls180.v:938.12-938.42" wire width 10 \main_uart_rx_fifo_wrport_dat_w - attribute \src "ls180.v:938.6-938.33" + attribute \src "ls180.v:937.6-937.33" wire \main_uart_rx_fifo_wrport_we - attribute \src "ls180.v:852.5-852.29" + attribute \src "ls180.v:851.5-851.29" wire \main_uart_rx_old_trigger - attribute \src "ls180.v:849.5-849.25" + attribute \src "ls180.v:848.5-848.25" wire \main_uart_rx_pending - attribute \src "ls180.v:848.6-848.25" + attribute \src "ls180.v:847.6-847.25" wire \main_uart_rx_status - attribute \src "ls180.v:850.6-850.26" + attribute \src "ls180.v:849.6-849.26" wire \main_uart_rx_trigger - attribute \src "ls180.v:840.6-840.30" + attribute \src "ls180.v:839.6-839.30" wire \main_uart_rxempty_status - attribute \src "ls180.v:841.6-841.26" + attribute \src "ls180.v:840.6-840.26" wire \main_uart_rxempty_we - attribute \src "ls180.v:865.6-865.29" + attribute \src "ls180.v:864.6-864.29" wire \main_uart_rxfull_status - attribute \src "ls180.v:866.6-866.25" + attribute \src "ls180.v:865.6-865.25" wire \main_uart_rxfull_we - attribute \src "ls180.v:835.12-835.28" + attribute \src "ls180.v:834.12-834.28" wire width 8 \main_uart_rxtx_r - attribute \src "ls180.v:834.6-834.23" + attribute \src "ls180.v:833.6-833.23" wire \main_uart_rxtx_re - attribute \src "ls180.v:837.12-837.28" + attribute \src "ls180.v:836.12-836.28" wire width 8 \main_uart_rxtx_w - attribute \src "ls180.v:836.6-836.23" + attribute \src "ls180.v:835.6-835.23" wire \main_uart_rxtx_we - attribute \src "ls180.v:846.5-846.23" + attribute \src "ls180.v:845.5-845.23" wire \main_uart_tx_clear - attribute \src "ls180.v:898.11-898.36" + attribute \src "ls180.v:897.11-897.36" wire width 4 \main_uart_tx_fifo_consume - attribute \src "ls180.v:903.6-903.31" + attribute \src "ls180.v:902.6-902.31" wire \main_uart_tx_fifo_do_read - attribute \src "ls180.v:909.6-909.37" + attribute \src "ls180.v:908.6-908.37" wire \main_uart_tx_fifo_fifo_in_first - attribute \src "ls180.v:910.6-910.36" + attribute \src "ls180.v:909.6-909.36" wire \main_uart_tx_fifo_fifo_in_last - attribute \src "ls180.v:908.12-908.50" + attribute \src "ls180.v:907.12-907.50" wire width 8 \main_uart_tx_fifo_fifo_in_payload_data - attribute \src "ls180.v:912.6-912.38" + attribute \src "ls180.v:911.6-911.38" wire \main_uart_tx_fifo_fifo_out_first - attribute \src "ls180.v:913.6-913.37" + attribute \src "ls180.v:912.6-912.37" wire \main_uart_tx_fifo_fifo_out_last - attribute \src "ls180.v:911.12-911.51" + attribute \src "ls180.v:910.12-910.51" wire width 8 \main_uart_tx_fifo_fifo_out_payload_data - attribute \src "ls180.v:895.11-895.35" + attribute \src "ls180.v:894.11-894.35" wire width 5 \main_uart_tx_fifo_level0 - attribute \src "ls180.v:907.12-907.36" + attribute \src "ls180.v:906.12-906.36" wire width 5 \main_uart_tx_fifo_level1 - attribute \src "ls180.v:897.11-897.36" + attribute \src "ls180.v:896.11-896.36" wire width 4 \main_uart_tx_fifo_produce - attribute \src "ls180.v:904.12-904.40" + attribute \src "ls180.v:903.12-903.40" wire width 4 \main_uart_tx_fifo_rdport_adr - attribute \src "ls180.v:905.12-905.42" + attribute \src "ls180.v:904.12-904.42" wire width 10 \main_uart_tx_fifo_rdport_dat_r - attribute \src "ls180.v:906.6-906.33" + attribute \src "ls180.v:905.6-905.33" wire \main_uart_tx_fifo_rdport_re - attribute \src "ls180.v:887.6-887.26" + attribute \src "ls180.v:886.6-886.26" wire \main_uart_tx_fifo_re - attribute \src "ls180.v:888.5-888.31" + attribute \src "ls180.v:887.5-887.31" wire \main_uart_tx_fifo_readable - attribute \src "ls180.v:896.5-896.30" + attribute \src "ls180.v:895.5-895.30" wire \main_uart_tx_fifo_replace - attribute \src "ls180.v:879.5-879.33" + attribute \src "ls180.v:878.5-878.33" wire \main_uart_tx_fifo_sink_first - attribute \src "ls180.v:880.5-880.32" + attribute \src "ls180.v:879.5-879.32" wire \main_uart_tx_fifo_sink_last - attribute \src "ls180.v:881.12-881.47" + attribute \src "ls180.v:880.12-880.47" wire width 8 \main_uart_tx_fifo_sink_payload_data - attribute \src "ls180.v:878.6-878.34" - wire \main_uart_tx_fifo_sink_ready attribute \src "ls180.v:877.6-877.34" + wire \main_uart_tx_fifo_sink_ready + attribute \src "ls180.v:876.6-876.34" wire \main_uart_tx_fifo_sink_valid - attribute \src "ls180.v:884.6-884.36" + attribute \src "ls180.v:883.6-883.36" wire \main_uart_tx_fifo_source_first - attribute \src "ls180.v:885.6-885.35" + attribute \src "ls180.v:884.6-884.35" wire \main_uart_tx_fifo_source_last - attribute \src "ls180.v:886.12-886.49" + attribute \src "ls180.v:885.12-885.49" wire width 8 \main_uart_tx_fifo_source_payload_data - attribute \src "ls180.v:883.6-883.36" - wire \main_uart_tx_fifo_source_ready attribute \src "ls180.v:882.6-882.36" + wire \main_uart_tx_fifo_source_ready + attribute \src "ls180.v:881.6-881.36" wire \main_uart_tx_fifo_source_valid - attribute \src "ls180.v:893.12-893.42" + attribute \src "ls180.v:892.12-892.42" wire width 10 \main_uart_tx_fifo_syncfifo_din - attribute \src "ls180.v:894.12-894.43" + attribute \src "ls180.v:893.12-893.43" wire width 10 \main_uart_tx_fifo_syncfifo_dout - attribute \src "ls180.v:891.6-891.35" + attribute \src "ls180.v:890.6-890.35" wire \main_uart_tx_fifo_syncfifo_re - attribute \src "ls180.v:892.6-892.41" + attribute \src "ls180.v:891.6-891.41" wire \main_uart_tx_fifo_syncfifo_readable - attribute \src "ls180.v:889.6-889.35" + attribute \src "ls180.v:888.6-888.35" wire \main_uart_tx_fifo_syncfifo_we - attribute \src "ls180.v:890.6-890.41" + attribute \src "ls180.v:889.6-889.41" wire \main_uart_tx_fifo_syncfifo_writable - attribute \src "ls180.v:899.11-899.39" + attribute \src "ls180.v:898.11-898.39" wire width 4 \main_uart_tx_fifo_wrport_adr - attribute \src "ls180.v:900.12-900.42" + attribute \src "ls180.v:899.12-899.42" wire width 10 \main_uart_tx_fifo_wrport_dat_r - attribute \src "ls180.v:902.12-902.42" + attribute \src "ls180.v:901.12-901.42" wire width 10 \main_uart_tx_fifo_wrport_dat_w - attribute \src "ls180.v:901.6-901.33" + attribute \src "ls180.v:900.6-900.33" wire \main_uart_tx_fifo_wrport_we - attribute \src "ls180.v:847.5-847.29" + attribute \src "ls180.v:846.5-846.29" wire \main_uart_tx_old_trigger - attribute \src "ls180.v:844.5-844.25" + attribute \src "ls180.v:843.5-843.25" wire \main_uart_tx_pending - attribute \src "ls180.v:843.6-843.25" + attribute \src "ls180.v:842.6-842.25" wire \main_uart_tx_status - attribute \src "ls180.v:845.6-845.26" + attribute \src "ls180.v:844.6-844.26" wire \main_uart_tx_trigger - attribute \src "ls180.v:863.6-863.30" + attribute \src "ls180.v:862.6-862.30" wire \main_uart_txempty_status - attribute \src "ls180.v:864.6-864.26" + attribute \src "ls180.v:863.6-863.26" wire \main_uart_txempty_we - attribute \src "ls180.v:838.6-838.29" + attribute \src "ls180.v:837.6-837.29" wire \main_uart_txfull_status - attribute \src "ls180.v:839.6-839.25" + attribute \src "ls180.v:838.6-838.25" wire \main_uart_txfull_we - attribute \src "ls180.v:869.6-869.31" + attribute \src "ls180.v:868.6-868.31" wire \main_uart_uart_sink_first - attribute \src "ls180.v:870.6-870.30" + attribute \src "ls180.v:869.6-869.30" wire \main_uart_uart_sink_last - attribute \src "ls180.v:871.12-871.44" + attribute \src "ls180.v:870.12-870.44" wire width 8 \main_uart_uart_sink_payload_data - attribute \src "ls180.v:868.6-868.31" - wire \main_uart_uart_sink_ready attribute \src "ls180.v:867.6-867.31" + wire \main_uart_uart_sink_ready + attribute \src "ls180.v:866.6-866.31" wire \main_uart_uart_sink_valid - attribute \src "ls180.v:874.6-874.33" + attribute \src "ls180.v:873.6-873.33" wire \main_uart_uart_source_first - attribute \src "ls180.v:875.6-875.32" + attribute \src "ls180.v:874.6-874.32" wire \main_uart_uart_source_last - attribute \src "ls180.v:876.12-876.46" + attribute \src "ls180.v:875.12-875.46" wire width 8 \main_uart_uart_source_payload_data - attribute \src "ls180.v:873.6-873.33" - wire \main_uart_uart_source_ready attribute \src "ls180.v:872.6-872.33" + wire \main_uart_uart_source_ready + attribute \src "ls180.v:871.6-871.33" wire \main_uart_uart_source_valid - attribute \src "ls180.v:788.5-788.22" + attribute \src "ls180.v:787.5-787.22" wire \main_wb_sdram_ack - attribute \src "ls180.v:782.13-782.30" + attribute \src "ls180.v:781.13-781.30" wire width 30 \main_wb_sdram_adr - attribute \src "ls180.v:791.12-791.29" - wire width 2 \main_wb_sdram_bte attribute \src "ls180.v:790.12-790.29" + wire width 2 \main_wb_sdram_bte + attribute \src "ls180.v:789.12-789.29" wire width 3 \main_wb_sdram_cti - attribute \src "ls180.v:786.6-786.23" + attribute \src "ls180.v:785.6-785.23" wire \main_wb_sdram_cyc - attribute \src "ls180.v:784.13-784.32" - wire width 32 \main_wb_sdram_dat_r attribute \src "ls180.v:783.13-783.32" + wire width 32 \main_wb_sdram_dat_r + attribute \src "ls180.v:782.13-782.32" wire width 32 \main_wb_sdram_dat_w - attribute \src "ls180.v:792.5-792.22" + attribute \src "ls180.v:791.5-791.22" wire \main_wb_sdram_err - attribute \src "ls180.v:785.12-785.29" + attribute \src "ls180.v:784.12-784.29" wire width 4 \main_wb_sdram_sel - attribute \src "ls180.v:787.6-787.23" + attribute \src "ls180.v:786.6-786.23" wire \main_wb_sdram_stb - attribute \src "ls180.v:789.6-789.22" + attribute \src "ls180.v:788.6-788.22" wire \main_wb_sdram_we - attribute \src "ls180.v:806.5-806.24" + attribute \src "ls180.v:805.5-805.24" wire \main_wdata_consumed - attribute \src "ls180.v:9980.11-9980.17" + attribute \src "ls180.v:9976.11-9976.17" wire width 7 \memadr - attribute \src "ls180.v:10000.12-10000.18" + attribute \src "ls180.v:9996.12-9996.18" wire width 25 \memdat - attribute \src "ls180.v:10014.12-10014.20" + attribute \src "ls180.v:10010.12-10010.20" wire width 25 \memdat_1 - attribute \src "ls180.v:10028.12-10028.20" + attribute \src "ls180.v:10024.12-10024.20" wire width 25 \memdat_2 - attribute \src "ls180.v:10042.12-10042.20" + attribute \src "ls180.v:10038.12-10038.20" wire width 25 \memdat_3 - attribute \src "ls180.v:10056.11-10056.19" + attribute \src "ls180.v:10052.11-10052.19" wire width 10 \memdat_4 - attribute \src "ls180.v:10057.11-10057.19" + attribute \src "ls180.v:10053.11-10053.19" wire width 10 \memdat_5 - attribute \src "ls180.v:10073.11-10073.19" + attribute \src "ls180.v:10069.11-10069.19" wire width 10 \memdat_6 - attribute \src "ls180.v:10074.11-10074.19" + attribute \src "ls180.v:10070.11-10070.19" wire width 10 \memdat_7 - attribute \src "ls180.v:10090.11-10090.19" + attribute \src "ls180.v:10086.11-10086.19" wire width 10 \memdat_8 - attribute \src "ls180.v:10104.11-10104.19" + attribute \src "ls180.v:10100.11-10100.19" wire width 10 \memdat_9 attribute \src "ls180.v:33.20-33.22" - wire width 43 input 29 \nc + wire width 42 input 29 \nc attribute \src "ls180.v:219.6-219.13" wire \por_clk attribute \src "ls180.v:34.13-34.17" @@ -82574,139 +82566,143 @@ module \ls180 wire output 8 \sdram_ras_n attribute \src "ls180.v:11.13-11.23" wire output 7 \sdram_we_n - attribute \src "ls180.v:2595.6-2595.15" + attribute \src "ls180.v:2594.6-2594.15" wire \sdrio_clk - attribute \src "ls180.v:2596.6-2596.17" + attribute \src "ls180.v:2595.6-2595.17" wire \sdrio_clk_1 - attribute \src "ls180.v:2605.6-2605.18" + attribute \src "ls180.v:2604.6-2604.18" wire \sdrio_clk_10 - attribute \src "ls180.v:2606.6-2606.18" + attribute \src "ls180.v:2605.6-2605.18" wire \sdrio_clk_11 - attribute \src "ls180.v:2607.6-2607.18" + attribute \src "ls180.v:2606.6-2606.18" wire \sdrio_clk_12 - attribute \src "ls180.v:2608.6-2608.18" + attribute \src "ls180.v:2607.6-2607.18" wire \sdrio_clk_13 - attribute \src "ls180.v:2609.6-2609.18" + attribute \src "ls180.v:2608.6-2608.18" wire \sdrio_clk_14 - attribute \src "ls180.v:2610.6-2610.18" + attribute \src "ls180.v:2609.6-2609.18" wire \sdrio_clk_15 - attribute \src "ls180.v:2611.6-2611.18" + attribute \src "ls180.v:2610.6-2610.18" wire \sdrio_clk_16 - attribute \src "ls180.v:2612.6-2612.18" + attribute \src "ls180.v:2611.6-2611.18" wire \sdrio_clk_17 - attribute \src "ls180.v:2613.6-2613.18" + attribute \src "ls180.v:2612.6-2612.18" wire \sdrio_clk_18 - attribute \src "ls180.v:2614.6-2614.18" + attribute \src "ls180.v:2613.6-2613.18" wire \sdrio_clk_19 - attribute \src "ls180.v:2597.6-2597.17" + attribute \src "ls180.v:2596.6-2596.17" wire \sdrio_clk_2 - attribute \src "ls180.v:2615.6-2615.18" + attribute \src "ls180.v:2614.6-2614.18" wire \sdrio_clk_20 - attribute \src "ls180.v:2616.6-2616.18" + attribute \src "ls180.v:2615.6-2615.18" wire \sdrio_clk_21 - attribute \src "ls180.v:2617.6-2617.18" + attribute \src "ls180.v:2616.6-2616.18" wire \sdrio_clk_22 - attribute \src "ls180.v:2618.6-2618.18" + attribute \src "ls180.v:2617.6-2617.18" wire \sdrio_clk_23 - attribute \src "ls180.v:2619.6-2619.18" + attribute \src "ls180.v:2618.6-2618.18" wire \sdrio_clk_24 - attribute \src "ls180.v:2620.6-2620.18" + attribute \src "ls180.v:2619.6-2619.18" wire \sdrio_clk_25 - attribute \src "ls180.v:2621.6-2621.18" + attribute \src "ls180.v:2620.6-2620.18" wire \sdrio_clk_26 - attribute \src "ls180.v:2622.6-2622.18" + attribute \src "ls180.v:2621.6-2621.18" wire \sdrio_clk_27 - attribute \src "ls180.v:2623.6-2623.18" + attribute \src "ls180.v:2622.6-2622.18" wire \sdrio_clk_28 - attribute \src "ls180.v:2624.6-2624.18" + attribute \src "ls180.v:2623.6-2623.18" wire \sdrio_clk_29 - attribute \src "ls180.v:2598.6-2598.17" + attribute \src "ls180.v:2597.6-2597.17" wire \sdrio_clk_3 - attribute \src "ls180.v:2625.6-2625.18" + attribute \src "ls180.v:2624.6-2624.18" wire \sdrio_clk_30 - attribute \src "ls180.v:2626.6-2626.18" + attribute \src "ls180.v:2625.6-2625.18" wire \sdrio_clk_31 - attribute \src "ls180.v:2627.6-2627.18" + attribute \src "ls180.v:2626.6-2626.18" wire \sdrio_clk_32 - attribute \src "ls180.v:2628.6-2628.18" + attribute \src "ls180.v:2627.6-2627.18" wire \sdrio_clk_33 - attribute \src "ls180.v:2629.6-2629.18" + attribute \src "ls180.v:2628.6-2628.18" wire \sdrio_clk_34 - attribute \src "ls180.v:2630.6-2630.18" + attribute \src "ls180.v:2629.6-2629.18" wire \sdrio_clk_35 - attribute \src "ls180.v:2631.6-2631.18" + attribute \src "ls180.v:2630.6-2630.18" wire \sdrio_clk_36 - attribute \src "ls180.v:2632.6-2632.18" + attribute \src "ls180.v:2631.6-2631.18" wire \sdrio_clk_37 - attribute \src "ls180.v:2633.6-2633.18" + attribute \src "ls180.v:2632.6-2632.18" wire \sdrio_clk_38 - attribute \src "ls180.v:2634.6-2634.18" + attribute \src "ls180.v:2633.6-2633.18" wire \sdrio_clk_39 - attribute \src "ls180.v:2599.6-2599.17" + attribute \src "ls180.v:2598.6-2598.17" wire \sdrio_clk_4 - attribute \src "ls180.v:2635.6-2635.18" + attribute \src "ls180.v:2634.6-2634.18" wire \sdrio_clk_40 - attribute \src "ls180.v:2636.6-2636.18" + attribute \src "ls180.v:2635.6-2635.18" wire \sdrio_clk_41 - attribute \src "ls180.v:2637.6-2637.18" + attribute \src "ls180.v:2636.6-2636.18" wire \sdrio_clk_42 - attribute \src "ls180.v:2638.6-2638.18" + attribute \src "ls180.v:2637.6-2637.18" wire \sdrio_clk_43 - attribute \src "ls180.v:2639.6-2639.18" + attribute \src "ls180.v:2638.6-2638.18" wire \sdrio_clk_44 - attribute \src "ls180.v:2640.6-2640.18" + attribute \src "ls180.v:2639.6-2639.18" wire \sdrio_clk_45 - attribute \src "ls180.v:2641.6-2641.18" + attribute \src "ls180.v:2640.6-2640.18" wire \sdrio_clk_46 - attribute \src "ls180.v:2642.6-2642.18" + attribute \src "ls180.v:2641.6-2641.18" wire \sdrio_clk_47 - attribute \src "ls180.v:2643.6-2643.18" + attribute \src "ls180.v:2642.6-2642.18" wire \sdrio_clk_48 - attribute \src "ls180.v:2644.6-2644.18" + attribute \src "ls180.v:2643.6-2643.18" wire \sdrio_clk_49 - attribute \src "ls180.v:2600.6-2600.17" + attribute \src "ls180.v:2599.6-2599.17" wire \sdrio_clk_5 - attribute \src "ls180.v:2645.6-2645.18" + attribute \src "ls180.v:2644.6-2644.18" wire \sdrio_clk_50 - attribute \src "ls180.v:2646.6-2646.18" + attribute \src "ls180.v:2645.6-2645.18" wire \sdrio_clk_51 - attribute \src "ls180.v:2647.6-2647.18" + attribute \src "ls180.v:2646.6-2646.18" wire \sdrio_clk_52 - attribute \src "ls180.v:2648.6-2648.18" + attribute \src "ls180.v:2647.6-2647.18" wire \sdrio_clk_53 - attribute \src "ls180.v:2683.6-2683.18" + attribute \src "ls180.v:2648.6-2648.18" wire \sdrio_clk_54 - attribute \src "ls180.v:2684.6-2684.18" + attribute \src "ls180.v:2649.6-2649.18" wire \sdrio_clk_55 - attribute \src "ls180.v:2685.6-2685.18" + attribute \src "ls180.v:2684.6-2684.18" wire \sdrio_clk_56 - attribute \src "ls180.v:2686.6-2686.18" + attribute \src "ls180.v:2685.6-2685.18" wire \sdrio_clk_57 - attribute \src "ls180.v:2687.6-2687.18" + attribute \src "ls180.v:2686.6-2686.18" wire \sdrio_clk_58 - attribute \src "ls180.v:2688.6-2688.18" + attribute \src "ls180.v:2687.6-2687.18" wire \sdrio_clk_59 - attribute \src "ls180.v:2601.6-2601.17" + attribute \src "ls180.v:2600.6-2600.17" wire \sdrio_clk_6 - attribute \src "ls180.v:2689.6-2689.18" + attribute \src "ls180.v:2688.6-2688.18" wire \sdrio_clk_60 - attribute \src "ls180.v:2690.6-2690.18" + attribute \src "ls180.v:2689.6-2689.18" wire \sdrio_clk_61 - attribute \src "ls180.v:2691.6-2691.18" + attribute \src "ls180.v:2690.6-2690.18" wire \sdrio_clk_62 - attribute \src "ls180.v:2692.6-2692.18" + attribute \src "ls180.v:2691.6-2691.18" wire \sdrio_clk_63 - attribute \src "ls180.v:2693.6-2693.18" + attribute \src "ls180.v:2692.6-2692.18" wire \sdrio_clk_64 - attribute \src "ls180.v:2694.6-2694.18" + attribute \src "ls180.v:2693.6-2693.18" wire \sdrio_clk_65 - attribute \src "ls180.v:2695.6-2695.18" + attribute \src "ls180.v:2694.6-2694.18" wire \sdrio_clk_66 - attribute \src "ls180.v:2602.6-2602.17" + attribute \src "ls180.v:2695.6-2695.18" + wire \sdrio_clk_67 + attribute \src "ls180.v:2696.6-2696.18" + wire \sdrio_clk_68 + attribute \src "ls180.v:2601.6-2601.17" wire \sdrio_clk_7 - attribute \src "ls180.v:2603.6-2603.17" + attribute \src "ls180.v:2602.6-2602.17" wire \sdrio_clk_8 - attribute \src "ls180.v:2604.6-2604.17" + attribute \src "ls180.v:2603.6-2603.17" wire \sdrio_clk_9 attribute \src "ls180.v:24.13-24.27" wire output 20 \spi_master_clk @@ -82736,26 +82732,26 @@ module \ls180 wire input 16 \uart_rx attribute \src "ls180.v:19.14-19.21" wire output 15 \uart_tx - attribute \src "ls180.v:9979.12-9979.15" + attribute \src "ls180.v:9975.12-9975.15" memory width 32 size 128 \mem - attribute \src "ls180.v:9999.12-9999.19" + attribute \src "ls180.v:9995.12-9995.19" memory width 25 size 8 \storage - attribute \src "ls180.v:10013.12-10013.21" + attribute \src "ls180.v:10009.12-10009.21" memory width 25 size 8 \storage_1 - attribute \src "ls180.v:10027.12-10027.21" + attribute \src "ls180.v:10023.12-10023.21" memory width 25 size 8 \storage_2 - attribute \src "ls180.v:10041.12-10041.21" + attribute \src "ls180.v:10037.12-10037.21" memory width 25 size 8 \storage_3 - attribute \src "ls180.v:10055.11-10055.20" + attribute \src "ls180.v:10051.11-10051.20" memory width 10 size 16 \storage_4 - attribute \src "ls180.v:10072.11-10072.20" + attribute \src "ls180.v:10068.11-10068.20" memory width 10 size 16 \storage_5 - attribute \src "ls180.v:10089.11-10089.20" + attribute \src "ls180.v:10085.11-10085.20" memory width 10 size 32 \storage_6 - attribute \src "ls180.v:10103.11-10103.20" + attribute \src "ls180.v:10099.11-10099.20" memory width 10 size 32 \storage_7 - attribute \src "ls180.v:2767.68-2767.110" - cell $add $add$ls180.v:2767$22 + attribute \src "ls180.v:2768.68-2768.110" + cell $add $add$ls180.v:2768$22 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -82763,10 +82759,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_converter0_counter connect \B 1'1 - connect \Y $add$ls180.v:2767$22_Y + connect \Y $add$ls180.v:2768$22_Y end - attribute \src "ls180.v:2827.68-2827.110" - cell $add $add$ls180.v:2827$33 + attribute \src "ls180.v:2828.68-2828.110" + cell $add $add$ls180.v:2828$33 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -82774,10 +82770,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_converter1_counter connect \B 1'1 - connect \Y $add$ls180.v:2827$33_Y + connect \Y $add$ls180.v:2828$33_Y end - attribute \src "ls180.v:2887.68-2887.110" - cell $add $add$ls180.v:2887$44 + attribute \src "ls180.v:2888.68-2888.110" + cell $add $add$ls180.v:2888$44 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -82785,10 +82781,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_converter2_counter connect \B 1'1 - connect \Y $add$ls180.v:2887$44_Y + connect \Y $add$ls180.v:2888$44_Y end - attribute \src "ls180.v:4025.54-4025.83" - cell $add $add$ls180.v:4025$538 + attribute \src "ls180.v:4021.54-4021.83" + cell $add $add$ls180.v:4021$537 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -82796,10 +82792,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_converter_counter connect \B 1'1 - connect \Y $add$ls180.v:4025$538_Y + connect \Y $add$ls180.v:4021$537_Y end - attribute \src "ls180.v:4125.36-4125.89" - cell $add $add$ls180.v:4125$584 + attribute \src "ls180.v:4121.36-4121.89" + cell $add $add$ls180.v:4121$583 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -82807,10 +82803,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_uart_tx_fifo_level0 connect \B \main_uart_tx_fifo_readable - connect \Y $add$ls180.v:4125$584_Y + connect \Y $add$ls180.v:4121$583_Y end - attribute \src "ls180.v:4155.36-4155.89" - cell $add $add$ls180.v:4155$595 + attribute \src "ls180.v:4151.36-4151.89" + cell $add $add$ls180.v:4151$594 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -82818,10 +82814,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_uart_rx_fifo_level0 connect \B \main_uart_rx_fifo_readable - connect \Y $add$ls180.v:4155$595_Y + connect \Y $add$ls180.v:4151$594_Y end - attribute \src "ls180.v:4210.53-4210.81" - cell $add $add$ls180.v:4210$608 + attribute \src "ls180.v:4206.53-4206.81" + cell $add $add$ls180.v:4206$607 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -82829,10 +82825,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_spi_master_count connect \B 1'1 - connect \Y $add$ls180.v:4210$608_Y + connect \Y $add$ls180.v:4206$607_Y end - attribute \src "ls180.v:4310.58-4310.86" - cell $add $add$ls180.v:4310$636 + attribute \src "ls180.v:4306.58-4306.86" + cell $add $add$ls180.v:4306$635 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -82840,10 +82836,10 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \main_sdphy_init_count connect \B 1'1 - connect \Y $add$ls180.v:4310$636_Y + connect \Y $add$ls180.v:4306$635_Y end - attribute \src "ls180.v:4367.58-4367.86" - cell $add $add$ls180.v:4367$639 + attribute \src "ls180.v:4363.58-4363.86" + cell $add $add$ls180.v:4363$638 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -82851,10 +82847,10 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \main_sdphy_cmdw_count connect \B 1'1 - connect \Y $add$ls180.v:4367$639_Y + connect \Y $add$ls180.v:4363$638_Y end - attribute \src "ls180.v:4384.58-4384.86" - cell $add $add$ls180.v:4384$641 + attribute \src "ls180.v:4380.58-4380.86" + cell $add $add$ls180.v:4380$640 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -82862,10 +82858,10 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \main_sdphy_cmdw_count connect \B 1'1 - connect \Y $add$ls180.v:4384$641_Y + connect \Y $add$ls180.v:4380$640_Y end - attribute \src "ls180.v:4477.59-4477.87" - cell $add $add$ls180.v:4477$658 + attribute \src "ls180.v:4473.59-4473.87" + cell $add $add$ls180.v:4473$657 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -82873,10 +82869,10 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \main_sdphy_cmdr_count connect \B 1'1 - connect \Y $add$ls180.v:4477$658_Y + connect \Y $add$ls180.v:4473$657_Y end - attribute \src "ls180.v:4502.59-4502.87" - cell $add $add$ls180.v:4502$661 + attribute \src "ls180.v:4498.59-4498.87" + cell $add $add$ls180.v:4498$660 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -82884,10 +82880,10 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \main_sdphy_cmdr_count connect \B 1'1 - connect \Y $add$ls180.v:4502$661_Y + connect \Y $add$ls180.v:4498$660_Y end - attribute \src "ls180.v:4624.53-4624.82" - cell $add $add$ls180.v:4624$678 + attribute \src "ls180.v:4620.53-4620.82" + cell $add $add$ls180.v:4620$677 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -82895,10 +82891,10 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \main_sdphy_dataw_count connect \B 1'1 - connect \Y $add$ls180.v:4624$678_Y + connect \Y $add$ls180.v:4620$677_Y end - attribute \src "ls180.v:4735.65-4735.114" - cell $add $add$ls180.v:4735$692 + attribute \src "ls180.v:4731.65-4731.114" + cell $add $add$ls180.v:4731$691 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -82906,10 +82902,10 @@ module \ls180 parameter \Y_WIDTH 10 connect \A \main_sdphy_datar_sink_payload_block_length connect \B 4'1000 - connect \Y $add$ls180.v:4735$692_Y + connect \Y $add$ls180.v:4731$691_Y end - attribute \src "ls180.v:4740.62-4740.91" - cell $add $add$ls180.v:4740$695 + attribute \src "ls180.v:4736.62-4736.91" + cell $add $add$ls180.v:4736$694 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -82917,10 +82913,10 @@ module \ls180 parameter \Y_WIDTH 10 connect \A \main_sdphy_datar_count connect \B 1'1 - connect \Y $add$ls180.v:4740$695_Y + connect \Y $add$ls180.v:4736$694_Y end - attribute \src "ls180.v:4766.61-4766.90" - cell $add $add$ls180.v:4766$698 + attribute \src "ls180.v:4762.61-4762.90" + cell $add $add$ls180.v:4762$697 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -82928,10 +82924,10 @@ module \ls180 parameter \Y_WIDTH 10 connect \A \main_sdphy_datar_count connect \B 1'1 - connect \Y $add$ls180.v:4766$698_Y + connect \Y $add$ls180.v:4762$697_Y end - attribute \src "ls180.v:4970.80-4970.117" - cell $add $add$ls180.v:4970$883 + attribute \src "ls180.v:4966.80-4966.117" + cell $add $add$ls180.v:4966$882 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -82939,10 +82935,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdcore_crc16_inserter_cnt connect \B 1'1 - connect \Y $add$ls180.v:4970$883_Y + connect \Y $add$ls180.v:4966$882_Y end - attribute \src "ls180.v:5164.54-5164.82" - cell $add $add$ls180.v:5164$958 + attribute \src "ls180.v:5160.54-5160.82" + cell $add $add$ls180.v:5160$957 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -82950,10 +82946,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdcore_cmd_count connect \B 1'1 - connect \Y $add$ls180.v:5164$958_Y + connect \Y $add$ls180.v:5160$957_Y end - attribute \src "ls180.v:5216.55-5216.84" - cell $add $add$ls180.v:5216$968 + attribute \src "ls180.v:5212.55-5212.84" + cell $add $add$ls180.v:5212$967 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -82961,10 +82957,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdcore_data_count connect \B 1'1 - connect \Y $add$ls180.v:5216$968_Y + connect \Y $add$ls180.v:5212$967_Y end - attribute \src "ls180.v:5242.57-5242.86" - cell $add $add$ls180.v:5242$976 + attribute \src "ls180.v:5238.57-5238.86" + cell $add $add$ls180.v:5238$975 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -82972,10 +82968,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdcore_data_count connect \B 1'1 - connect \Y $add$ls180.v:5242$976_Y + connect \Y $add$ls180.v:5238$975_Y end - attribute \src "ls180.v:5363.51-5363.134" - cell $add $add$ls180.v:5363$992 + attribute \src "ls180.v:5359.51-5359.134" + cell $add $add$ls180.v:5359$991 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -82983,10 +82979,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdblock2mem_wishbonedmawriter_base connect \B \main_sdblock2mem_wishbonedmawriter_offset - connect \Y $add$ls180.v:5363$992_Y + connect \Y $add$ls180.v:5359$991_Y end - attribute \src "ls180.v:5366.77-5366.125" - cell $add $add$ls180.v:5366$994 + attribute \src "ls180.v:5362.77-5362.125" + cell $add $add$ls180.v:5362$993 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -82994,10 +82990,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdblock2mem_wishbonedmawriter_offset connect \B 1'1 - connect \Y $add$ls180.v:5366$994_Y + connect \Y $add$ls180.v:5362$993_Y end - attribute \src "ls180.v:5459.50-5459.105" - cell $add $add$ls180.v:5459$1003 + attribute \src "ls180.v:5455.50-5455.105" + cell $add $add$ls180.v:5455$1002 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -83005,10 +83001,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdmem2block_dma_base connect \B \main_sdmem2block_dma_offset - connect \Y $add$ls180.v:5459$1003_Y + connect \Y $add$ls180.v:5455$1002_Y end - attribute \src "ls180.v:5461.77-5461.111" - cell $add $add$ls180.v:5461$1004 + attribute \src "ls180.v:5457.77-5457.111" + cell $add $add$ls180.v:5457$1003 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -83016,10 +83012,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdmem2block_dma_offset connect \B 1'1 - connect \Y $add$ls180.v:5461$1004_Y + connect \Y $add$ls180.v:5457$1003_Y end - attribute \src "ls180.v:5573.49-5573.73" - cell $add $add$ls180.v:5573$1023 + attribute \src "ls180.v:5569.49-5569.73" + cell $add $add$ls180.v:5569$1022 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -83027,10 +83023,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \libresocsim_count connect \B 1'1 - connect \Y $add$ls180.v:5573$1023_Y + connect \Y $add$ls180.v:5569$1022_Y end - attribute \src "ls180.v:7438.36-7438.70" - cell $add $add$ls180.v:7438$2407 + attribute \src "ls180.v:7437.36-7437.70" + cell $add $add$ls180.v:7437$2405 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -83038,10 +83034,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_libresocsim_bus_errors connect \B 1'1 - connect \Y $add$ls180.v:7438$2407_Y + connect \Y $add$ls180.v:7437$2405_Y end - attribute \src "ls180.v:7525.37-7525.72" - cell $add $add$ls180.v:7525$2428 + attribute \src "ls180.v:7522.37-7522.72" + cell $add $add$ls180.v:7522$2426 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -83049,10 +83045,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_sequencer_counter connect \B 1'1 - connect \Y $add$ls180.v:7525$2428_Y + connect \Y $add$ls180.v:7522$2426_Y end - attribute \src "ls180.v:7542.60-7542.119" - cell $add $add$ls180.v:7542$2432 + attribute \src "ls180.v:7539.60-7539.119" + cell $add $add$ls180.v:7539$2430 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -83060,10 +83056,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $add$ls180.v:7542$2432_Y + connect \Y $add$ls180.v:7539$2430_Y end - attribute \src "ls180.v:7545.60-7545.119" - cell $add $add$ls180.v:7545$2433 + attribute \src "ls180.v:7542.60-7542.119" + cell $add $add$ls180.v:7542$2431 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -83071,10 +83067,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_consume connect \B 1'1 - connect \Y $add$ls180.v:7545$2433_Y + connect \Y $add$ls180.v:7542$2431_Y end - attribute \src "ls180.v:7549.59-7549.116" - cell $add $add$ls180.v:7549$2438 + attribute \src "ls180.v:7546.59-7546.116" + cell $add $add$ls180.v:7546$2436 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -83082,10 +83078,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $add$ls180.v:7549$2438_Y + connect \Y $add$ls180.v:7546$2436_Y end - attribute \src "ls180.v:7588.60-7588.119" - cell $add $add$ls180.v:7588$2448 + attribute \src "ls180.v:7585.60-7585.119" + cell $add $add$ls180.v:7585$2446 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -83093,10 +83089,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $add$ls180.v:7588$2448_Y + connect \Y $add$ls180.v:7585$2446_Y end - attribute \src "ls180.v:7591.60-7591.119" - cell $add $add$ls180.v:7591$2449 + attribute \src "ls180.v:7588.60-7588.119" + cell $add $add$ls180.v:7588$2447 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -83104,10 +83100,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_consume connect \B 1'1 - connect \Y $add$ls180.v:7591$2449_Y + connect \Y $add$ls180.v:7588$2447_Y end - attribute \src "ls180.v:7595.59-7595.116" - cell $add $add$ls180.v:7595$2454 + attribute \src "ls180.v:7592.59-7592.116" + cell $add $add$ls180.v:7592$2452 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -83115,10 +83111,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $add$ls180.v:7595$2454_Y + connect \Y $add$ls180.v:7592$2452_Y end - attribute \src "ls180.v:7634.60-7634.119" - cell $add $add$ls180.v:7634$2464 + attribute \src "ls180.v:7631.60-7631.119" + cell $add $add$ls180.v:7631$2462 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -83126,10 +83122,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $add$ls180.v:7634$2464_Y + connect \Y $add$ls180.v:7631$2462_Y end - attribute \src "ls180.v:7637.60-7637.119" - cell $add $add$ls180.v:7637$2465 + attribute \src "ls180.v:7634.60-7634.119" + cell $add $add$ls180.v:7634$2463 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -83137,10 +83133,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_consume connect \B 1'1 - connect \Y $add$ls180.v:7637$2465_Y + connect \Y $add$ls180.v:7634$2463_Y end - attribute \src "ls180.v:7641.59-7641.116" - cell $add $add$ls180.v:7641$2470 + attribute \src "ls180.v:7638.59-7638.116" + cell $add $add$ls180.v:7638$2468 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -83148,10 +83144,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $add$ls180.v:7641$2470_Y + connect \Y $add$ls180.v:7638$2468_Y end - attribute \src "ls180.v:7680.60-7680.119" - cell $add $add$ls180.v:7680$2480 + attribute \src "ls180.v:7677.60-7677.119" + cell $add $add$ls180.v:7677$2478 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -83159,10 +83155,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $add$ls180.v:7680$2480_Y + connect \Y $add$ls180.v:7677$2478_Y end - attribute \src "ls180.v:7683.60-7683.119" - cell $add $add$ls180.v:7683$2481 + attribute \src "ls180.v:7680.60-7680.119" + cell $add $add$ls180.v:7680$2479 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -83170,10 +83166,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_consume connect \B 1'1 - connect \Y $add$ls180.v:7683$2481_Y + connect \Y $add$ls180.v:7680$2479_Y end - attribute \src "ls180.v:7687.59-7687.116" - cell $add $add$ls180.v:7687$2486 + attribute \src "ls180.v:7684.59-7684.116" + cell $add $add$ls180.v:7684$2484 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -83181,10 +83177,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $add$ls180.v:7687$2486_Y + connect \Y $add$ls180.v:7684$2484_Y end - attribute \src "ls180.v:7917.25-7917.48" - cell $add $add$ls180.v:7917$2540 + attribute \src "ls180.v:7914.25-7914.48" + cell $add $add$ls180.v:7914$2538 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -83192,10 +83188,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_tx_bitcount connect \B 1'1 - connect \Y $add$ls180.v:7917$2540_Y + connect \Y $add$ls180.v:7914$2538_Y end - attribute \src "ls180.v:7933.55-7933.95" - cell $add $add$ls180.v:7933$2543 + attribute \src "ls180.v:7930.55-7930.95" + cell $add $add$ls180.v:7930$2541 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -83203,10 +83199,10 @@ module \ls180 parameter \Y_WIDTH 33 connect \A \main_phase_accumulator_tx connect \B \main_storage - connect \Y $add$ls180.v:7933$2543_Y + connect \Y $add$ls180.v:7930$2541_Y end - attribute \src "ls180.v:7946.25-7946.48" - cell $add $add$ls180.v:7946$2547 + attribute \src "ls180.v:7943.25-7943.48" + cell $add $add$ls180.v:7943$2545 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -83214,10 +83210,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_rx_bitcount connect \B 1'1 - connect \Y $add$ls180.v:7946$2547_Y + connect \Y $add$ls180.v:7943$2545_Y end - attribute \src "ls180.v:7965.55-7965.95" - cell $add $add$ls180.v:7965$2550 + attribute \src "ls180.v:7962.55-7962.95" + cell $add $add$ls180.v:7962$2548 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -83225,10 +83221,10 @@ module \ls180 parameter \Y_WIDTH 33 connect \A \main_phase_accumulator_rx connect \B \main_storage - connect \Y $add$ls180.v:7965$2550_Y + connect \Y $add$ls180.v:7962$2548_Y end - attribute \src "ls180.v:7991.33-7991.65" - cell $add $add$ls180.v:7991$2558 + attribute \src "ls180.v:7988.33-7988.65" + cell $add $add$ls180.v:7988$2556 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -83236,10 +83232,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_uart_tx_fifo_produce connect \B 1'1 - connect \Y $add$ls180.v:7991$2558_Y + connect \Y $add$ls180.v:7988$2556_Y end - attribute \src "ls180.v:7994.33-7994.65" - cell $add $add$ls180.v:7994$2559 + attribute \src "ls180.v:7991.33-7991.65" + cell $add $add$ls180.v:7991$2557 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -83247,10 +83243,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_uart_tx_fifo_consume connect \B 1'1 - connect \Y $add$ls180.v:7994$2559_Y + connect \Y $add$ls180.v:7991$2557_Y end - attribute \src "ls180.v:7998.33-7998.64" - cell $add $add$ls180.v:7998$2564 + attribute \src "ls180.v:7995.33-7995.64" + cell $add $add$ls180.v:7995$2562 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -83258,10 +83254,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_uart_tx_fifo_level0 connect \B 1'1 - connect \Y $add$ls180.v:7998$2564_Y + connect \Y $add$ls180.v:7995$2562_Y end - attribute \src "ls180.v:8013.33-8013.65" - cell $add $add$ls180.v:8013$2569 + attribute \src "ls180.v:8010.33-8010.65" + cell $add $add$ls180.v:8010$2567 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -83269,10 +83265,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_uart_rx_fifo_produce connect \B 1'1 - connect \Y $add$ls180.v:8013$2569_Y + connect \Y $add$ls180.v:8010$2567_Y end - attribute \src "ls180.v:8016.33-8016.65" - cell $add $add$ls180.v:8016$2570 + attribute \src "ls180.v:8013.33-8013.65" + cell $add $add$ls180.v:8013$2568 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -83280,10 +83276,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_uart_rx_fifo_consume connect \B 1'1 - connect \Y $add$ls180.v:8016$2570_Y + connect \Y $add$ls180.v:8013$2568_Y end - attribute \src "ls180.v:8020.33-8020.64" - cell $add $add$ls180.v:8020$2575 + attribute \src "ls180.v:8017.33-8017.64" + cell $add $add$ls180.v:8017$2573 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -83291,10 +83287,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_uart_rx_fifo_level0 connect \B 1'1 - connect \Y $add$ls180.v:8020$2575_Y + connect \Y $add$ls180.v:8017$2573_Y end - attribute \src "ls180.v:8041.35-8041.70" - cell $add $add$ls180.v:8041$2577 + attribute \src "ls180.v:8038.35-8038.70" + cell $add $add$ls180.v:8038$2575 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -83302,10 +83298,10 @@ module \ls180 parameter \Y_WIDTH 16 connect \A \main_spi_master_clk_divider1 connect \B 1'1 - connect \Y $add$ls180.v:8041$2577_Y + connect \Y $add$ls180.v:8038$2575_Y end - attribute \src "ls180.v:8077.25-8077.49" - cell $add $add$ls180.v:8077$2582 + attribute \src "ls180.v:8074.25-8074.49" + cell $add $add$ls180.v:8074$2580 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -83313,10 +83309,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_pwm0_counter connect \B 1'1 - connect \Y $add$ls180.v:8077$2582_Y + connect \Y $add$ls180.v:8074$2580_Y end - attribute \src "ls180.v:8091.25-8091.49" - cell $add $add$ls180.v:8091$2586 + attribute \src "ls180.v:8088.25-8088.49" + cell $add $add$ls180.v:8088$2584 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -83324,10 +83320,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_pwm1_counter connect \B 1'1 - connect \Y $add$ls180.v:8091$2586_Y + connect \Y $add$ls180.v:8088$2584_Y end - attribute \src "ls180.v:8105.31-8105.61" - cell $add $add$ls180.v:8105$2591 + attribute \src "ls180.v:8102.31-8102.61" + cell $add $add$ls180.v:8102$2589 parameter \A_SIGNED 0 parameter \A_WIDTH 9 parameter \B_SIGNED 0 @@ -83335,10 +83331,10 @@ module \ls180 parameter \Y_WIDTH 9 connect \A \main_sdphy_clocker_clks connect \B 1'1 - connect \Y $add$ls180.v:8105$2591_Y + connect \Y $add$ls180.v:8102$2589_Y end - attribute \src "ls180.v:8128.45-8128.88" - cell $add $add$ls180.v:8128$2595 + attribute \src "ls180.v:8125.45-8125.88" + cell $add $add$ls180.v:8125$2593 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -83346,10 +83342,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdphy_cmdr_cmdr_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8128$2595_Y + connect \Y $add$ls180.v:8125$2593_Y end - attribute \src "ls180.v:8174.71-8174.114" - cell $add $add$ls180.v:8174$2601 + attribute \src "ls180.v:8171.71-8171.114" + cell $add $add$ls180.v:8171$2599 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -83357,10 +83353,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdphy_cmdr_cmdr_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8174$2601_Y + connect \Y $add$ls180.v:8171$2599_Y end - attribute \src "ls180.v:8209.46-8209.90" - cell $add $add$ls180.v:8209$2607 + attribute \src "ls180.v:8206.46-8206.90" + cell $add $add$ls180.v:8206$2605 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -83368,10 +83364,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdphy_dataw_crcr_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8209$2607_Y + connect \Y $add$ls180.v:8206$2605_Y end - attribute \src "ls180.v:8255.72-8255.116" - cell $add $add$ls180.v:8255$2613 + attribute \src "ls180.v:8252.72-8252.116" + cell $add $add$ls180.v:8252$2611 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -83379,10 +83375,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdphy_dataw_crcr_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8255$2613_Y + connect \Y $add$ls180.v:8252$2611_Y end - attribute \src "ls180.v:8288.47-8288.92" - cell $add $add$ls180.v:8288$2619 + attribute \src "ls180.v:8285.47-8285.92" + cell $add $add$ls180.v:8285$2617 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -83390,10 +83386,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8288$2619_Y + connect \Y $add$ls180.v:8285$2617_Y end - attribute \src "ls180.v:8316.73-8316.118" - cell $add $add$ls180.v:8316$2625 + attribute \src "ls180.v:8313.73-8313.118" + cell $add $add$ls180.v:8313$2623 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -83401,10 +83397,10 @@ module \ls180 parameter \Y_WIDTH 2 connect \A \main_sdphy_datar_datar_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8316$2625_Y + connect \Y $add$ls180.v:8313$2623_Y end - attribute \src "ls180.v:8428.39-8428.75" - cell $add $add$ls180.v:8428$2638 + attribute \src "ls180.v:8425.39-8425.75" + cell $add $add$ls180.v:8425$2636 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -83412,10 +83408,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdcore_crc16_checker_cnt connect \B 1'1 - connect \Y $add$ls180.v:8428$2638_Y + connect \Y $add$ls180.v:8425$2636_Y end - attribute \src "ls180.v:8489.37-8489.73" - cell $add $add$ls180.v:8489$2642 + attribute \src "ls180.v:8486.37-8486.73" + cell $add $add$ls180.v:8486$2640 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -83423,10 +83419,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_sdblock2mem_fifo_produce connect \B 1'1 - connect \Y $add$ls180.v:8489$2642_Y + connect \Y $add$ls180.v:8486$2640_Y end - attribute \src "ls180.v:8492.37-8492.73" - cell $add $add$ls180.v:8492$2643 + attribute \src "ls180.v:8489.37-8489.73" + cell $add $add$ls180.v:8489$2641 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -83434,10 +83430,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_sdblock2mem_fifo_consume connect \B 1'1 - connect \Y $add$ls180.v:8492$2643_Y + connect \Y $add$ls180.v:8489$2641_Y end - attribute \src "ls180.v:8496.36-8496.70" - cell $add $add$ls180.v:8496$2648 + attribute \src "ls180.v:8493.36-8493.70" + cell $add $add$ls180.v:8493$2646 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -83445,10 +83441,10 @@ module \ls180 parameter \Y_WIDTH 6 connect \A \main_sdblock2mem_fifo_level connect \B 1'1 - connect \Y $add$ls180.v:8496$2648_Y + connect \Y $add$ls180.v:8493$2646_Y end - attribute \src "ls180.v:8511.41-8511.80" - cell $add $add$ls180.v:8511$2652 + attribute \src "ls180.v:8508.41-8508.80" + cell $add $add$ls180.v:8508$2650 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -83456,10 +83452,10 @@ module \ls180 parameter \Y_WIDTH 2 connect \A \main_sdblock2mem_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8511$2652_Y + connect \Y $add$ls180.v:8508$2650_Y end - attribute \src "ls180.v:8545.67-8545.106" - cell $add $add$ls180.v:8545$2658 + attribute \src "ls180.v:8542.67-8542.106" + cell $add $add$ls180.v:8542$2656 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -83467,10 +83463,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdblock2mem_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8545$2658_Y + connect \Y $add$ls180.v:8542$2656_Y end - attribute \src "ls180.v:8571.39-8571.76" - cell $add $add$ls180.v:8571$2660 + attribute \src "ls180.v:8568.39-8568.76" + cell $add $add$ls180.v:8568$2658 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -83478,10 +83474,10 @@ module \ls180 parameter \Y_WIDTH 2 connect \A \main_sdmem2block_converter_mux connect \B 1'1 - connect \Y $add$ls180.v:8571$2660_Y + connect \Y $add$ls180.v:8568$2658_Y end - attribute \src "ls180.v:8575.37-8575.73" - cell $add $add$ls180.v:8575$2664 + attribute \src "ls180.v:8572.37-8572.73" + cell $add $add$ls180.v:8572$2662 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -83489,10 +83485,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_sdmem2block_fifo_produce connect \B 1'1 - connect \Y $add$ls180.v:8575$2664_Y + connect \Y $add$ls180.v:8572$2662_Y end - attribute \src "ls180.v:8578.37-8578.73" - cell $add $add$ls180.v:8578$2665 + attribute \src "ls180.v:8575.37-8575.73" + cell $add $add$ls180.v:8575$2663 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -83500,10 +83496,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_sdmem2block_fifo_consume connect \B 1'1 - connect \Y $add$ls180.v:8578$2665_Y + connect \Y $add$ls180.v:8575$2663_Y end - attribute \src "ls180.v:8582.36-8582.70" - cell $add $add$ls180.v:8582$2670 + attribute \src "ls180.v:8579.36-8579.70" + cell $add $add$ls180.v:8579$2668 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -83511,10 +83507,10 @@ module \ls180 parameter \Y_WIDTH 6 connect \A \main_sdmem2block_fifo_level connect \B 1'1 - connect \Y $add$ls180.v:8582$2670_Y + connect \Y $add$ls180.v:8579$2668_Y end - attribute \src "ls180.v:8589.31-8589.62" - cell $add $add$ls180.v:8589$2672 + attribute \src "ls180.v:8586.31-8586.62" + cell $add $add$ls180.v:8586$2670 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -83522,10 +83518,10 @@ module \ls180 parameter \Y_WIDTH 16 connect \A \libresocsim_clk_divider1 connect \B 1'1 - connect \Y $add$ls180.v:8589$2672_Y + connect \Y $add$ls180.v:8586$2670_Y end - attribute \src "ls180.v:2761.9-2761.80" - cell $and $and$ls180.v:2761$17 + attribute \src "ls180.v:2762.9-2762.80" + cell $and $and$ls180.v:2762$17 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -83533,10 +83529,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_libresoc_ibus_stb connect \B \main_libresocsim_libresoc_ibus_cyc - connect \Y $and$ls180.v:2761$17_Y + connect \Y $and$ls180.v:2762$17_Y end - attribute \src "ls180.v:2779.9-2779.80" - cell $and $and$ls180.v:2779$24 + attribute \src "ls180.v:2780.9-2780.80" + cell $and $and$ls180.v:2780$24 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -83544,10 +83540,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_libresoc_ibus_stb connect \B \main_libresocsim_libresoc_ibus_cyc - connect \Y $and$ls180.v:2779$24_Y + connect \Y $and$ls180.v:2780$24_Y end - attribute \src "ls180.v:2821.9-2821.80" - cell $and $and$ls180.v:2821$28 + attribute \src "ls180.v:2822.9-2822.80" + cell $and $and$ls180.v:2822$28 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -83555,10 +83551,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_libresoc_dbus_stb connect \B \main_libresocsim_libresoc_dbus_cyc - connect \Y $and$ls180.v:2821$28_Y + connect \Y $and$ls180.v:2822$28_Y end - attribute \src "ls180.v:2839.9-2839.80" - cell $and $and$ls180.v:2839$35 + attribute \src "ls180.v:2840.9-2840.80" + cell $and $and$ls180.v:2840$35 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -83566,10 +83562,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_libresoc_dbus_stb connect \B \main_libresocsim_libresoc_dbus_cyc - connect \Y $and$ls180.v:2839$35_Y + connect \Y $and$ls180.v:2840$35_Y end - attribute \src "ls180.v:2881.9-2881.86" - cell $and $and$ls180.v:2881$39 + attribute \src "ls180.v:2882.9-2882.86" + cell $and $and$ls180.v:2882$39 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -83577,10 +83573,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_libresoc_jtag_wb_stb connect \B \main_libresocsim_libresoc_jtag_wb_cyc - connect \Y $and$ls180.v:2881$39_Y + connect \Y $and$ls180.v:2882$39_Y end - attribute \src "ls180.v:2899.9-2899.86" - cell $and $and$ls180.v:2899$46 + attribute \src "ls180.v:2900.9-2900.86" + cell $and $and$ls180.v:2900$46 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -83588,10 +83584,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_libresoc_jtag_wb_stb connect \B \main_libresocsim_libresoc_jtag_wb_cyc - connect \Y $and$ls180.v:2899$46_Y + connect \Y $and$ls180.v:2900$46_Y end - attribute \src "ls180.v:2909.31-2909.90" - cell $and $and$ls180.v:2909$48 + attribute \src "ls180.v:2910.31-2910.90" + cell $and $and$ls180.v:2910$48 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -83599,32 +83595,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_cyc connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:2909$48_Y + connect \Y $and$ls180.v:2910$48_Y end - attribute \src "ls180.v:2909.30-2909.121" - cell $and $and$ls180.v:2909$49 + attribute \src "ls180.v:2910.30-2910.121" + cell $and $and$ls180.v:2910$49 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2909$48_Y + connect \A $and$ls180.v:2910$48_Y connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:2909$49_Y + connect \Y $and$ls180.v:2910$49_Y end - attribute \src "ls180.v:2909.29-2909.156" - cell $and $and$ls180.v:2909$50 + attribute \src "ls180.v:2910.29-2910.156" + cell $and $and$ls180.v:2910$50 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2909$49_Y + connect \A $and$ls180.v:2910$49_Y connect \B \main_libresocsim_ram_bus_sel [0] - connect \Y $and$ls180.v:2909$50_Y + connect \Y $and$ls180.v:2910$50_Y end - attribute \src "ls180.v:2910.31-2910.90" - cell $and $and$ls180.v:2910$51 + attribute \src "ls180.v:2911.31-2911.90" + cell $and $and$ls180.v:2911$51 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -83632,32 +83628,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_cyc connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:2910$51_Y + connect \Y $and$ls180.v:2911$51_Y end - attribute \src "ls180.v:2910.30-2910.121" - cell $and $and$ls180.v:2910$52 + attribute \src "ls180.v:2911.30-2911.121" + cell $and $and$ls180.v:2911$52 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2910$51_Y + connect \A $and$ls180.v:2911$51_Y connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:2910$52_Y + connect \Y $and$ls180.v:2911$52_Y end - attribute \src "ls180.v:2910.29-2910.156" - cell $and $and$ls180.v:2910$53 + attribute \src "ls180.v:2911.29-2911.156" + cell $and $and$ls180.v:2911$53 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2910$52_Y + connect \A $and$ls180.v:2911$52_Y connect \B \main_libresocsim_ram_bus_sel [1] - connect \Y $and$ls180.v:2910$53_Y + connect \Y $and$ls180.v:2911$53_Y end - attribute \src "ls180.v:2911.31-2911.90" - cell $and $and$ls180.v:2911$54 + attribute \src "ls180.v:2912.31-2912.90" + cell $and $and$ls180.v:2912$54 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -83665,32 +83661,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_cyc connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:2911$54_Y + connect \Y $and$ls180.v:2912$54_Y end - attribute \src "ls180.v:2911.30-2911.121" - cell $and $and$ls180.v:2911$55 + attribute \src "ls180.v:2912.30-2912.121" + cell $and $and$ls180.v:2912$55 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2911$54_Y + connect \A $and$ls180.v:2912$54_Y connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:2911$55_Y + connect \Y $and$ls180.v:2912$55_Y end - attribute \src "ls180.v:2911.29-2911.156" - cell $and $and$ls180.v:2911$56 + attribute \src "ls180.v:2912.29-2912.156" + cell $and $and$ls180.v:2912$56 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2911$55_Y + connect \A $and$ls180.v:2912$55_Y connect \B \main_libresocsim_ram_bus_sel [2] - connect \Y $and$ls180.v:2911$56_Y + connect \Y $and$ls180.v:2912$56_Y end - attribute \src "ls180.v:2912.31-2912.90" - cell $and $and$ls180.v:2912$57 + attribute \src "ls180.v:2913.31-2913.90" + cell $and $and$ls180.v:2913$57 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -83698,32 +83694,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_cyc connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:2912$57_Y + connect \Y $and$ls180.v:2913$57_Y end - attribute \src "ls180.v:2912.30-2912.121" - cell $and $and$ls180.v:2912$58 + attribute \src "ls180.v:2913.30-2913.121" + cell $and $and$ls180.v:2913$58 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2912$57_Y + connect \A $and$ls180.v:2913$57_Y connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:2912$58_Y + connect \Y $and$ls180.v:2913$58_Y end - attribute \src "ls180.v:2912.29-2912.156" - cell $and $and$ls180.v:2912$59 + attribute \src "ls180.v:2913.29-2913.156" + cell $and $and$ls180.v:2913$59 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2912$58_Y + connect \A $and$ls180.v:2913$58_Y connect \B \main_libresocsim_ram_bus_sel [3] - connect \Y $and$ls180.v:2912$59_Y + connect \Y $and$ls180.v:2913$59_Y end - attribute \src "ls180.v:2921.7-2921.89" - cell $and $and$ls180.v:2921$62 + attribute \src "ls180.v:2922.7-2922.89" + cell $and $and$ls180.v:2922$62 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -83731,10 +83727,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_eventmanager_pending_re connect \B \main_libresocsim_eventmanager_pending_r - connect \Y $and$ls180.v:2921$62_Y + connect \Y $and$ls180.v:2922$62_Y end - attribute \src "ls180.v:2926.32-2926.111" - cell $and $and$ls180.v:2926$63 + attribute \src "ls180.v:2927.32-2927.111" + cell $and $and$ls180.v:2927$63 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -83742,10 +83738,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_eventmanager_pending_w connect \B \main_libresocsim_eventmanager_storage - connect \Y $and$ls180.v:2926$63_Y + connect \Y $and$ls180.v:2927$63_Y end - attribute \src "ls180.v:3045.40-3045.99" - cell $and $and$ls180.v:3045$71 + attribute \src "ls180.v:3041.40-3041.99" + cell $and $and$ls180.v:3041$70 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -83753,10 +83749,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_command_issue_re connect \B \main_sdram_command_storage [4] - connect \Y $and$ls180.v:3045$71_Y + connect \Y $and$ls180.v:3041$70_Y end - attribute \src "ls180.v:3046.40-3046.99" - cell $and $and$ls180.v:3046$72 + attribute \src "ls180.v:3042.40-3042.99" + cell $and $and$ls180.v:3042$71 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -83764,21 +83760,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_command_issue_re connect \B \main_sdram_command_storage [5] - connect \Y $and$ls180.v:3046$72_Y + connect \Y $and$ls180.v:3042$71_Y end - attribute \src "ls180.v:3084.38-3084.103" - cell $and $and$ls180.v:3084$78 + attribute \src "ls180.v:3080.38-3080.103" + cell $and $and$ls180.v:3080$77 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_done1 - connect \B $eq$ls180.v:3084$77_Y - connect \Y $and$ls180.v:3084$78_Y + connect \B $eq$ls180.v:3080$76_Y + connect \Y $and$ls180.v:3080$77_Y end - attribute \src "ls180.v:3138.50-3138.119" - cell $and $and$ls180.v:3138$86 + attribute \src "ls180.v:3134.50-3134.119" + cell $and $and$ls180.v:3134$85 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -83786,21 +83782,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_valid connect \B \main_sdram_bankmachine0_cmd_ready - connect \Y $and$ls180.v:3138$86_Y + connect \Y $and$ls180.v:3134$85_Y end - attribute \src "ls180.v:3138.49-3138.167" - cell $and $and$ls180.v:3138$87 + attribute \src "ls180.v:3134.49-3134.167" + cell $and $and$ls180.v:3134$86 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3138$86_Y + connect \A $and$ls180.v:3134$85_Y connect \B \main_sdram_bankmachine0_cmd_payload_is_write - connect \Y $and$ls180.v:3138$87_Y + connect \Y $and$ls180.v:3134$86_Y end - attribute \src "ls180.v:3139.49-3139.118" - cell $and $and$ls180.v:3139$88 + attribute \src "ls180.v:3135.49-3135.118" + cell $and $and$ls180.v:3135$87 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -83808,21 +83804,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_valid connect \B \main_sdram_bankmachine0_cmd_ready - connect \Y $and$ls180.v:3139$88_Y + connect \Y $and$ls180.v:3135$87_Y end - attribute \src "ls180.v:3139.48-3139.154" - cell $and $and$ls180.v:3139$89 + attribute \src "ls180.v:3135.48-3135.154" + cell $and $and$ls180.v:3135$88 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3139$88_Y + connect \A $and$ls180.v:3135$87_Y connect \B \main_sdram_bankmachine0_row_open - connect \Y $and$ls180.v:3139$89_Y + connect \Y $and$ls180.v:3135$88_Y end - attribute \src "ls180.v:3140.50-3140.119" - cell $and $and$ls180.v:3140$90 + attribute \src "ls180.v:3136.50-3136.119" + cell $and $and$ls180.v:3136$89 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -83830,21 +83826,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_valid connect \B \main_sdram_bankmachine0_cmd_ready - connect \Y $and$ls180.v:3140$90_Y + connect \Y $and$ls180.v:3136$89_Y end - attribute \src "ls180.v:3140.49-3140.155" - cell $and $and$ls180.v:3140$91 + attribute \src "ls180.v:3136.49-3136.155" + cell $and $and$ls180.v:3136$90 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3140$90_Y + connect \A $and$ls180.v:3136$89_Y connect \B \main_sdram_bankmachine0_row_open - connect \Y $and$ls180.v:3140$91_Y + connect \Y $and$ls180.v:3136$90_Y end - attribute \src "ls180.v:3143.7-3143.114" - cell $and $and$ls180.v:3143$93 + attribute \src "ls180.v:3139.7-3139.114" + cell $and $and$ls180.v:3139$92 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -83852,21 +83848,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid connect \B \main_sdram_bankmachine0_cmd_buffer_source_valid - connect \Y $and$ls180.v:3143$93_Y + connect \Y $and$ls180.v:3139$92_Y end - attribute \src "ls180.v:3172.66-3172.246" - cell $and $and$ls180.v:3172$99 + attribute \src "ls180.v:3168.66-3168.246" + cell $and $and$ls180.v:3168$98 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we - connect \B $or$ls180.v:3172$98_Y - connect \Y $and$ls180.v:3172$99_Y + connect \B $or$ls180.v:3168$97_Y + connect \Y $and$ls180.v:3168$98_Y end - attribute \src "ls180.v:3173.64-3173.187" - cell $and $and$ls180.v:3173$100 + attribute \src "ls180.v:3169.64-3169.187" + cell $and $and$ls180.v:3169$99 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -83874,10 +83870,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re - connect \Y $and$ls180.v:3173$100_Y + connect \Y $and$ls180.v:3169$99_Y end - attribute \src "ls180.v:3197.9-3197.86" - cell $and $and$ls180.v:3197$106 + attribute \src "ls180.v:3193.9-3193.86" + cell $and $and$ls180.v:3193$105 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -83885,10 +83881,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_twtpcon_ready connect \B \main_sdram_bankmachine0_trascon_ready - connect \Y $and$ls180.v:3197$106_Y + connect \Y $and$ls180.v:3193$105_Y end - attribute \src "ls180.v:3209.9-3209.86" - cell $and $and$ls180.v:3209$107 + attribute \src "ls180.v:3205.9-3205.86" + cell $and $and$ls180.v:3205$106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -83896,10 +83892,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_twtpcon_ready connect \B \main_sdram_bankmachine0_trascon_ready - connect \Y $and$ls180.v:3209$107_Y + connect \Y $and$ls180.v:3205$106_Y end - attribute \src "ls180.v:3259.13-3259.87" - cell $and $and$ls180.v:3259$109 + attribute \src "ls180.v:3255.13-3255.87" + cell $and $and$ls180.v:3255$108 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -83907,10 +83903,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_ready connect \B \main_sdram_bankmachine0_auto_precharge - connect \Y $and$ls180.v:3259$109_Y + connect \Y $and$ls180.v:3255$108_Y end - attribute \src "ls180.v:3295.50-3295.119" - cell $and $and$ls180.v:3295$116 + attribute \src "ls180.v:3291.50-3291.119" + cell $and $and$ls180.v:3291$115 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -83918,21 +83914,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_valid connect \B \main_sdram_bankmachine1_cmd_ready - connect \Y $and$ls180.v:3295$116_Y + connect \Y $and$ls180.v:3291$115_Y end - attribute \src "ls180.v:3295.49-3295.167" - cell $and $and$ls180.v:3295$117 + attribute \src "ls180.v:3291.49-3291.167" + cell $and $and$ls180.v:3291$116 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3295$116_Y + connect \A $and$ls180.v:3291$115_Y connect \B \main_sdram_bankmachine1_cmd_payload_is_write - connect \Y $and$ls180.v:3295$117_Y + connect \Y $and$ls180.v:3291$116_Y end - attribute \src "ls180.v:3296.49-3296.118" - cell $and $and$ls180.v:3296$118 + attribute \src "ls180.v:3292.49-3292.118" + cell $and $and$ls180.v:3292$117 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -83940,21 +83936,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_valid connect \B \main_sdram_bankmachine1_cmd_ready - connect \Y $and$ls180.v:3296$118_Y + connect \Y $and$ls180.v:3292$117_Y end - attribute \src "ls180.v:3296.48-3296.154" - cell $and $and$ls180.v:3296$119 + attribute \src "ls180.v:3292.48-3292.154" + cell $and $and$ls180.v:3292$118 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3296$118_Y + connect \A $and$ls180.v:3292$117_Y connect \B \main_sdram_bankmachine1_row_open - connect \Y $and$ls180.v:3296$119_Y + connect \Y $and$ls180.v:3292$118_Y end - attribute \src "ls180.v:3297.50-3297.119" - cell $and $and$ls180.v:3297$120 + attribute \src "ls180.v:3293.50-3293.119" + cell $and $and$ls180.v:3293$119 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -83962,21 +83958,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_valid connect \B \main_sdram_bankmachine1_cmd_ready - connect \Y $and$ls180.v:3297$120_Y + connect \Y $and$ls180.v:3293$119_Y end - attribute \src "ls180.v:3297.49-3297.155" - cell $and $and$ls180.v:3297$121 + attribute \src "ls180.v:3293.49-3293.155" + cell $and $and$ls180.v:3293$120 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3297$120_Y + connect \A $and$ls180.v:3293$119_Y connect \B \main_sdram_bankmachine1_row_open - connect \Y $and$ls180.v:3297$121_Y + connect \Y $and$ls180.v:3293$120_Y end - attribute \src "ls180.v:3300.7-3300.114" - cell $and $and$ls180.v:3300$123 + attribute \src "ls180.v:3296.7-3296.114" + cell $and $and$ls180.v:3296$122 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -83984,21 +83980,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid connect \B \main_sdram_bankmachine1_cmd_buffer_source_valid - connect \Y $and$ls180.v:3300$123_Y + connect \Y $and$ls180.v:3296$122_Y end - attribute \src "ls180.v:3329.66-3329.246" - cell $and $and$ls180.v:3329$129 + attribute \src "ls180.v:3325.66-3325.246" + cell $and $and$ls180.v:3325$128 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we - connect \B $or$ls180.v:3329$128_Y - connect \Y $and$ls180.v:3329$129_Y + connect \B $or$ls180.v:3325$127_Y + connect \Y $and$ls180.v:3325$128_Y end - attribute \src "ls180.v:3330.64-3330.187" - cell $and $and$ls180.v:3330$130 + attribute \src "ls180.v:3326.64-3326.187" + cell $and $and$ls180.v:3326$129 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -84006,10 +84002,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re - connect \Y $and$ls180.v:3330$130_Y + connect \Y $and$ls180.v:3326$129_Y end - attribute \src "ls180.v:3354.9-3354.86" - cell $and $and$ls180.v:3354$136 + attribute \src "ls180.v:3350.9-3350.86" + cell $and $and$ls180.v:3350$135 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -84017,10 +84013,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_twtpcon_ready connect \B \main_sdram_bankmachine1_trascon_ready - connect \Y $and$ls180.v:3354$136_Y + connect \Y $and$ls180.v:3350$135_Y end - attribute \src "ls180.v:3366.9-3366.86" - cell $and $and$ls180.v:3366$137 + attribute \src "ls180.v:3362.9-3362.86" + cell $and $and$ls180.v:3362$136 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -84028,10 +84024,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_twtpcon_ready connect \B \main_sdram_bankmachine1_trascon_ready - connect \Y $and$ls180.v:3366$137_Y + connect \Y $and$ls180.v:3362$136_Y end - attribute \src "ls180.v:3416.13-3416.87" - cell $and $and$ls180.v:3416$139 + attribute \src "ls180.v:3412.13-3412.87" + cell $and $and$ls180.v:3412$138 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -84039,10 +84035,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_ready connect \B \main_sdram_bankmachine1_auto_precharge - connect \Y $and$ls180.v:3416$139_Y + connect \Y $and$ls180.v:3412$138_Y end - attribute \src "ls180.v:3452.50-3452.119" - cell $and $and$ls180.v:3452$146 + attribute \src "ls180.v:3448.50-3448.119" + cell $and $and$ls180.v:3448$145 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -84050,21 +84046,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_valid connect \B \main_sdram_bankmachine2_cmd_ready - connect \Y $and$ls180.v:3452$146_Y + connect \Y $and$ls180.v:3448$145_Y end - attribute \src "ls180.v:3452.49-3452.167" - cell $and $and$ls180.v:3452$147 + attribute \src "ls180.v:3448.49-3448.167" + cell $and $and$ls180.v:3448$146 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3452$146_Y + connect \A $and$ls180.v:3448$145_Y connect \B \main_sdram_bankmachine2_cmd_payload_is_write - connect \Y $and$ls180.v:3452$147_Y + connect \Y $and$ls180.v:3448$146_Y end - attribute \src "ls180.v:3453.49-3453.118" - cell $and $and$ls180.v:3453$148 + attribute \src "ls180.v:3449.49-3449.118" + cell $and $and$ls180.v:3449$147 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -84072,21 +84068,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_valid connect \B \main_sdram_bankmachine2_cmd_ready - connect \Y $and$ls180.v:3453$148_Y + connect \Y $and$ls180.v:3449$147_Y end - attribute \src "ls180.v:3453.48-3453.154" - cell $and $and$ls180.v:3453$149 + attribute \src "ls180.v:3449.48-3449.154" + cell $and $and$ls180.v:3449$148 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3453$148_Y + connect \A $and$ls180.v:3449$147_Y connect \B \main_sdram_bankmachine2_row_open - connect \Y $and$ls180.v:3453$149_Y + connect \Y $and$ls180.v:3449$148_Y end - attribute \src "ls180.v:3454.50-3454.119" - cell $and $and$ls180.v:3454$150 + attribute \src "ls180.v:3450.50-3450.119" + cell $and $and$ls180.v:3450$149 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -84094,21 +84090,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_valid connect \B \main_sdram_bankmachine2_cmd_ready - connect \Y $and$ls180.v:3454$150_Y + connect \Y $and$ls180.v:3450$149_Y end - attribute \src "ls180.v:3454.49-3454.155" - cell $and $and$ls180.v:3454$151 + attribute \src "ls180.v:3450.49-3450.155" + cell $and $and$ls180.v:3450$150 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3454$150_Y + connect \A $and$ls180.v:3450$149_Y connect \B \main_sdram_bankmachine2_row_open - connect \Y $and$ls180.v:3454$151_Y + connect \Y $and$ls180.v:3450$150_Y end - attribute \src "ls180.v:3457.7-3457.114" - cell $and $and$ls180.v:3457$153 + attribute \src "ls180.v:3453.7-3453.114" + cell $and $and$ls180.v:3453$152 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -84116,21 +84112,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid connect \B \main_sdram_bankmachine2_cmd_buffer_source_valid - connect \Y $and$ls180.v:3457$153_Y + connect \Y $and$ls180.v:3453$152_Y end - attribute \src "ls180.v:3486.66-3486.246" - cell $and $and$ls180.v:3486$159 + attribute \src "ls180.v:3482.66-3482.246" + cell $and $and$ls180.v:3482$158 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we - connect \B $or$ls180.v:3486$158_Y - connect \Y $and$ls180.v:3486$159_Y + connect \B $or$ls180.v:3482$157_Y + connect \Y $and$ls180.v:3482$158_Y end - attribute \src "ls180.v:3487.64-3487.187" - cell $and $and$ls180.v:3487$160 + attribute \src "ls180.v:3483.64-3483.187" + cell $and $and$ls180.v:3483$159 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -84138,10 +84134,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re - connect \Y $and$ls180.v:3487$160_Y + connect \Y $and$ls180.v:3483$159_Y end - attribute \src "ls180.v:3511.9-3511.86" - cell $and $and$ls180.v:3511$166 + attribute \src "ls180.v:3507.9-3507.86" + cell $and $and$ls180.v:3507$165 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -84149,10 +84145,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_twtpcon_ready connect \B \main_sdram_bankmachine2_trascon_ready - connect \Y $and$ls180.v:3511$166_Y + connect \Y $and$ls180.v:3507$165_Y end - attribute \src "ls180.v:3523.9-3523.86" - cell $and $and$ls180.v:3523$167 + attribute \src "ls180.v:3519.9-3519.86" + cell $and $and$ls180.v:3519$166 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -84160,10 +84156,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_twtpcon_ready connect \B \main_sdram_bankmachine2_trascon_ready - connect \Y $and$ls180.v:3523$167_Y + connect \Y $and$ls180.v:3519$166_Y end - attribute \src "ls180.v:3573.13-3573.87" - cell $and $and$ls180.v:3573$169 + attribute \src "ls180.v:3569.13-3569.87" + cell $and $and$ls180.v:3569$168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -84171,10 +84167,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_ready connect \B \main_sdram_bankmachine2_auto_precharge - connect \Y $and$ls180.v:3573$169_Y + connect \Y $and$ls180.v:3569$168_Y end - attribute \src "ls180.v:3609.50-3609.119" - cell $and $and$ls180.v:3609$176 + attribute \src "ls180.v:3605.50-3605.119" + cell $and $and$ls180.v:3605$175 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -84182,21 +84178,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_valid connect \B \main_sdram_bankmachine3_cmd_ready - connect \Y $and$ls180.v:3609$176_Y + connect \Y $and$ls180.v:3605$175_Y end - attribute \src "ls180.v:3609.49-3609.167" - cell $and $and$ls180.v:3609$177 + attribute \src "ls180.v:3605.49-3605.167" + cell $and $and$ls180.v:3605$176 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3609$176_Y + connect \A $and$ls180.v:3605$175_Y connect \B \main_sdram_bankmachine3_cmd_payload_is_write - connect \Y $and$ls180.v:3609$177_Y + connect \Y $and$ls180.v:3605$176_Y end - attribute \src "ls180.v:3610.49-3610.118" - cell $and $and$ls180.v:3610$178 + attribute \src "ls180.v:3606.49-3606.118" + cell $and $and$ls180.v:3606$177 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -84204,21 +84200,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_valid connect \B \main_sdram_bankmachine3_cmd_ready - connect \Y $and$ls180.v:3610$178_Y + connect \Y $and$ls180.v:3606$177_Y end - attribute \src "ls180.v:3610.48-3610.154" - cell $and $and$ls180.v:3610$179 + attribute \src "ls180.v:3606.48-3606.154" + cell $and $and$ls180.v:3606$178 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3610$178_Y + connect \A $and$ls180.v:3606$177_Y connect \B \main_sdram_bankmachine3_row_open - connect \Y $and$ls180.v:3610$179_Y + connect \Y $and$ls180.v:3606$178_Y end - attribute \src "ls180.v:3611.50-3611.119" - cell $and $and$ls180.v:3611$180 + attribute \src "ls180.v:3607.50-3607.119" + cell $and $and$ls180.v:3607$179 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -84226,21 +84222,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_valid connect \B \main_sdram_bankmachine3_cmd_ready - connect \Y $and$ls180.v:3611$180_Y + connect \Y $and$ls180.v:3607$179_Y end - attribute \src "ls180.v:3611.49-3611.155" - cell $and $and$ls180.v:3611$181 + attribute \src "ls180.v:3607.49-3607.155" + cell $and $and$ls180.v:3607$180 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3611$180_Y + connect \A $and$ls180.v:3607$179_Y connect \B \main_sdram_bankmachine3_row_open - connect \Y $and$ls180.v:3611$181_Y + connect \Y $and$ls180.v:3607$180_Y end - attribute \src "ls180.v:3614.7-3614.114" - cell $and $and$ls180.v:3614$183 + attribute \src "ls180.v:3610.7-3610.114" + cell $and $and$ls180.v:3610$182 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -84248,21 +84244,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid connect \B \main_sdram_bankmachine3_cmd_buffer_source_valid - connect \Y $and$ls180.v:3614$183_Y + connect \Y $and$ls180.v:3610$182_Y end - attribute \src "ls180.v:3643.66-3643.246" - cell $and $and$ls180.v:3643$189 + attribute \src "ls180.v:3639.66-3639.246" + cell $and $and$ls180.v:3639$188 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we - connect \B $or$ls180.v:3643$188_Y - connect \Y $and$ls180.v:3643$189_Y + connect \B $or$ls180.v:3639$187_Y + connect \Y $and$ls180.v:3639$188_Y end - attribute \src "ls180.v:3644.64-3644.187" - cell $and $and$ls180.v:3644$190 + attribute \src "ls180.v:3640.64-3640.187" + cell $and $and$ls180.v:3640$189 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -84270,10 +84266,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re - connect \Y $and$ls180.v:3644$190_Y + connect \Y $and$ls180.v:3640$189_Y end - attribute \src "ls180.v:3668.9-3668.86" - cell $and $and$ls180.v:3668$196 + attribute \src "ls180.v:3664.9-3664.86" + cell $and $and$ls180.v:3664$195 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -84281,10 +84277,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_twtpcon_ready connect \B \main_sdram_bankmachine3_trascon_ready - connect \Y $and$ls180.v:3668$196_Y + connect \Y $and$ls180.v:3664$195_Y end - attribute \src "ls180.v:3680.9-3680.86" - cell $and $and$ls180.v:3680$197 + attribute \src "ls180.v:3676.9-3676.86" + cell $and $and$ls180.v:3676$196 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -84292,10 +84288,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_twtpcon_ready connect \B \main_sdram_bankmachine3_trascon_ready - connect \Y $and$ls180.v:3680$197_Y + connect \Y $and$ls180.v:3676$196_Y end - attribute \src "ls180.v:3730.13-3730.87" - cell $and $and$ls180.v:3730$199 + attribute \src "ls180.v:3726.13-3726.87" + cell $and $and$ls180.v:3726$198 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -84303,10 +84299,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_ready connect \B \main_sdram_bankmachine3_auto_precharge - connect \Y $and$ls180.v:3730$199_Y + connect \Y $and$ls180.v:3726$198_Y end - attribute \src "ls180.v:3745.37-3745.102" - cell $and $and$ls180.v:3745$200 + attribute \src "ls180.v:3741.37-3741.102" + cell $and $and$ls180.v:3741$199 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -84314,43 +84310,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3745$200_Y + connect \Y $and$ls180.v:3741$199_Y end - attribute \src "ls180.v:3745.108-3745.188" - cell $and $and$ls180.v:3745$202 + attribute \src "ls180.v:3741.108-3741.188" + cell $and $and$ls180.v:3741$201 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_ras - connect \B $not$ls180.v:3745$201_Y - connect \Y $and$ls180.v:3745$202_Y + connect \B $not$ls180.v:3741$200_Y + connect \Y $and$ls180.v:3741$201_Y end - attribute \src "ls180.v:3745.107-3745.231" - cell $and $and$ls180.v:3745$204 + attribute \src "ls180.v:3741.107-3741.231" + cell $and $and$ls180.v:3741$203 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3745$202_Y - connect \B $not$ls180.v:3745$203_Y - connect \Y $and$ls180.v:3745$204_Y + connect \A $and$ls180.v:3741$201_Y + connect \B $not$ls180.v:3741$202_Y + connect \Y $and$ls180.v:3741$203_Y end - attribute \src "ls180.v:3745.36-3745.232" - cell $and $and$ls180.v:3745$205 + attribute \src "ls180.v:3741.36-3741.232" + cell $and $and$ls180.v:3741$204 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3745$200_Y - connect \B $and$ls180.v:3745$204_Y - connect \Y $and$ls180.v:3745$205_Y + connect \A $and$ls180.v:3741$199_Y + connect \B $and$ls180.v:3741$203_Y + connect \Y $and$ls180.v:3741$204_Y end - attribute \src "ls180.v:3746.37-3746.102" - cell $and $and$ls180.v:3746$206 + attribute \src "ls180.v:3742.37-3742.102" + cell $and $and$ls180.v:3742$205 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -84358,43 +84354,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3746$206_Y + connect \Y $and$ls180.v:3742$205_Y end - attribute \src "ls180.v:3746.108-3746.188" - cell $and $and$ls180.v:3746$208 + attribute \src "ls180.v:3742.108-3742.188" + cell $and $and$ls180.v:3742$207 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_ras - connect \B $not$ls180.v:3746$207_Y - connect \Y $and$ls180.v:3746$208_Y + connect \B $not$ls180.v:3742$206_Y + connect \Y $and$ls180.v:3742$207_Y end - attribute \src "ls180.v:3746.107-3746.231" - cell $and $and$ls180.v:3746$210 + attribute \src "ls180.v:3742.107-3742.231" + cell $and $and$ls180.v:3742$209 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3746$208_Y - connect \B $not$ls180.v:3746$209_Y - connect \Y $and$ls180.v:3746$210_Y + connect \A $and$ls180.v:3742$207_Y + connect \B $not$ls180.v:3742$208_Y + connect \Y $and$ls180.v:3742$209_Y end - attribute \src "ls180.v:3746.36-3746.232" - cell $and $and$ls180.v:3746$211 + attribute \src "ls180.v:3742.36-3742.232" + cell $and $and$ls180.v:3742$210 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3746$206_Y - connect \B $and$ls180.v:3746$210_Y - connect \Y $and$ls180.v:3746$211_Y + connect \A $and$ls180.v:3742$205_Y + connect \B $and$ls180.v:3742$209_Y + connect \Y $and$ls180.v:3742$210_Y end - attribute \src "ls180.v:3747.34-3747.85" - cell $and $and$ls180.v:3747$212 + attribute \src "ls180.v:3743.34-3743.85" + cell $and $and$ls180.v:3743$211 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -84402,10 +84398,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_trrdcon_ready connect \B \main_sdram_tfawcon_ready - connect \Y $and$ls180.v:3747$212_Y + connect \Y $and$ls180.v:3743$211_Y end - attribute \src "ls180.v:3748.37-3748.102" - cell $and $and$ls180.v:3748$213 + attribute \src "ls180.v:3744.37-3744.102" + cell $and $and$ls180.v:3744$212 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -84413,21 +84409,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3748$213_Y + connect \Y $and$ls180.v:3744$212_Y end - attribute \src "ls180.v:3748.36-3748.194" - cell $and $and$ls180.v:3748$215 + attribute \src "ls180.v:3744.36-3744.194" + cell $and $and$ls180.v:3744$214 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3748$213_Y - connect \B $or$ls180.v:3748$214_Y - connect \Y $and$ls180.v:3748$215_Y + connect \A $and$ls180.v:3744$212_Y + connect \B $or$ls180.v:3744$213_Y + connect \Y $and$ls180.v:3744$214_Y end - attribute \src "ls180.v:3750.37-3750.102" - cell $and $and$ls180.v:3750$216 + attribute \src "ls180.v:3746.37-3746.102" + cell $and $and$ls180.v:3746$215 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -84435,21 +84431,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3750$216_Y + connect \Y $and$ls180.v:3746$215_Y end - attribute \src "ls180.v:3750.36-3750.148" - cell $and $and$ls180.v:3750$217 + attribute \src "ls180.v:3746.36-3746.148" + cell $and $and$ls180.v:3746$216 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3750$216_Y + connect \A $and$ls180.v:3746$215_Y connect \B \main_sdram_choose_req_cmd_payload_is_write - connect \Y $and$ls180.v:3750$217_Y + connect \Y $and$ls180.v:3746$216_Y end - attribute \src "ls180.v:3751.40-3751.119" - cell $and $and$ls180.v:3751$218 + attribute \src "ls180.v:3747.40-3747.119" + cell $and $and$ls180.v:3747$217 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -84457,10 +84453,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_valid connect \B \main_sdram_bankmachine0_cmd_payload_is_read - connect \Y $and$ls180.v:3751$218_Y + connect \Y $and$ls180.v:3747$217_Y end - attribute \src "ls180.v:3751.124-3751.203" - cell $and $and$ls180.v:3751$219 + attribute \src "ls180.v:3747.124-3747.203" + cell $and $and$ls180.v:3747$218 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -84468,10 +84464,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_valid connect \B \main_sdram_bankmachine1_cmd_payload_is_read - connect \Y $and$ls180.v:3751$219_Y + connect \Y $and$ls180.v:3747$218_Y end - attribute \src "ls180.v:3751.209-3751.288" - cell $and $and$ls180.v:3751$221 + attribute \src "ls180.v:3747.209-3747.288" + cell $and $and$ls180.v:3747$220 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -84479,10 +84475,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_valid connect \B \main_sdram_bankmachine2_cmd_payload_is_read - connect \Y $and$ls180.v:3751$221_Y + connect \Y $and$ls180.v:3747$220_Y end - attribute \src "ls180.v:3751.294-3751.373" - cell $and $and$ls180.v:3751$223 + attribute \src "ls180.v:3747.294-3747.373" + cell $and $and$ls180.v:3747$222 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -84490,10 +84486,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_valid connect \B \main_sdram_bankmachine3_cmd_payload_is_read - connect \Y $and$ls180.v:3751$223_Y + connect \Y $and$ls180.v:3747$222_Y end - attribute \src "ls180.v:3752.41-3752.121" - cell $and $and$ls180.v:3752$225 + attribute \src "ls180.v:3748.41-3748.121" + cell $and $and$ls180.v:3748$224 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -84501,10 +84497,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_valid connect \B \main_sdram_bankmachine0_cmd_payload_is_write - connect \Y $and$ls180.v:3752$225_Y + connect \Y $and$ls180.v:3748$224_Y end - attribute \src "ls180.v:3752.126-3752.206" - cell $and $and$ls180.v:3752$226 + attribute \src "ls180.v:3748.126-3748.206" + cell $and $and$ls180.v:3748$225 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -84512,10 +84508,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_valid connect \B \main_sdram_bankmachine1_cmd_payload_is_write - connect \Y $and$ls180.v:3752$226_Y + connect \Y $and$ls180.v:3748$225_Y end - attribute \src "ls180.v:3752.212-3752.292" - cell $and $and$ls180.v:3752$228 + attribute \src "ls180.v:3748.212-3748.292" + cell $and $and$ls180.v:3748$227 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -84523,10 +84519,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_valid connect \B \main_sdram_bankmachine2_cmd_payload_is_write - connect \Y $and$ls180.v:3752$228_Y + connect \Y $and$ls180.v:3748$227_Y end - attribute \src "ls180.v:3752.298-3752.378" - cell $and $and$ls180.v:3752$230 + attribute \src "ls180.v:3748.298-3748.378" + cell $and $and$ls180.v:3748$229 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -84534,10 +84530,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_valid connect \B \main_sdram_bankmachine3_cmd_payload_is_write - connect \Y $and$ls180.v:3752$230_Y + connect \Y $and$ls180.v:3748$229_Y end - attribute \src "ls180.v:3759.38-3759.111" - cell $and $and$ls180.v:3759$234 + attribute \src "ls180.v:3755.38-3755.111" + cell $and $and$ls180.v:3755$233 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -84545,32 +84541,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_refresh_gnt connect \B \main_sdram_bankmachine1_refresh_gnt - connect \Y $and$ls180.v:3759$234_Y + connect \Y $and$ls180.v:3755$233_Y end - attribute \src "ls180.v:3759.37-3759.150" - cell $and $and$ls180.v:3759$235 + attribute \src "ls180.v:3755.37-3755.150" + cell $and $and$ls180.v:3755$234 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3759$234_Y + connect \A $and$ls180.v:3755$233_Y connect \B \main_sdram_bankmachine2_refresh_gnt - connect \Y $and$ls180.v:3759$235_Y + connect \Y $and$ls180.v:3755$234_Y end - attribute \src "ls180.v:3759.36-3759.189" - cell $and $and$ls180.v:3759$236 + attribute \src "ls180.v:3755.36-3755.189" + cell $and $and$ls180.v:3755$235 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3759$235_Y + connect \A $and$ls180.v:3755$234_Y connect \B \main_sdram_bankmachine3_refresh_gnt - connect \Y $and$ls180.v:3759$236_Y + connect \Y $and$ls180.v:3755$235_Y end - attribute \src "ls180.v:3765.77-3765.153" - cell $and $and$ls180.v:3765$239 + attribute \src "ls180.v:3761.77-3761.153" + cell $and $and$ls180.v:3761$238 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -84578,65 +84574,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_is_cmd connect \B \main_sdram_choose_cmd_want_cmds - connect \Y $and$ls180.v:3765$239_Y + connect \Y $and$ls180.v:3761$238_Y end - attribute \src "ls180.v:3765.162-3765.246" - cell $and $and$ls180.v:3765$241 + attribute \src "ls180.v:3761.162-3761.246" + cell $and $and$ls180.v:3761$240 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_ras - connect \B $not$ls180.v:3765$240_Y - connect \Y $and$ls180.v:3765$241_Y + connect \B $not$ls180.v:3761$239_Y + connect \Y $and$ls180.v:3761$240_Y end - attribute \src "ls180.v:3765.161-3765.291" - cell $and $and$ls180.v:3765$243 + attribute \src "ls180.v:3761.161-3761.291" + cell $and $and$ls180.v:3761$242 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3765$241_Y - connect \B $not$ls180.v:3765$242_Y - connect \Y $and$ls180.v:3765$243_Y + connect \A $and$ls180.v:3761$240_Y + connect \B $not$ls180.v:3761$241_Y + connect \Y $and$ls180.v:3761$242_Y end - attribute \src "ls180.v:3765.76-3765.333" - cell $and $and$ls180.v:3765$246 + attribute \src "ls180.v:3761.76-3761.333" + cell $and $and$ls180.v:3761$245 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3765$239_Y - connect \B $or$ls180.v:3765$245_Y - connect \Y $and$ls180.v:3765$246_Y + connect \A $and$ls180.v:3761$238_Y + connect \B $or$ls180.v:3761$244_Y + connect \Y $and$ls180.v:3761$245_Y end - attribute \src "ls180.v:3765.338-3765.505" - cell $and $and$ls180.v:3765$249 + attribute \src "ls180.v:3761.338-3761.505" + cell $and $and$ls180.v:3761$248 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3765$247_Y - connect \B $eq$ls180.v:3765$248_Y - connect \Y $and$ls180.v:3765$249_Y + connect \A $eq$ls180.v:3761$246_Y + connect \B $eq$ls180.v:3761$247_Y + connect \Y $and$ls180.v:3761$248_Y end - attribute \src "ls180.v:3765.38-3765.507" - cell $and $and$ls180.v:3765$251 + attribute \src "ls180.v:3761.38-3761.507" + cell $and $and$ls180.v:3761$250 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_valid - connect \B $or$ls180.v:3765$250_Y - connect \Y $and$ls180.v:3765$251_Y + connect \B $or$ls180.v:3761$249_Y + connect \Y $and$ls180.v:3761$250_Y end - attribute \src "ls180.v:3766.77-3766.153" - cell $and $and$ls180.v:3766$252 + attribute \src "ls180.v:3762.77-3762.153" + cell $and $and$ls180.v:3762$251 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -84644,65 +84640,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_is_cmd connect \B \main_sdram_choose_cmd_want_cmds - connect \Y $and$ls180.v:3766$252_Y + connect \Y $and$ls180.v:3762$251_Y end - attribute \src "ls180.v:3766.162-3766.246" - cell $and $and$ls180.v:3766$254 + attribute \src "ls180.v:3762.162-3762.246" + cell $and $and$ls180.v:3762$253 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_ras - connect \B $not$ls180.v:3766$253_Y - connect \Y $and$ls180.v:3766$254_Y + connect \B $not$ls180.v:3762$252_Y + connect \Y $and$ls180.v:3762$253_Y end - attribute \src "ls180.v:3766.161-3766.291" - cell $and $and$ls180.v:3766$256 + attribute \src "ls180.v:3762.161-3762.291" + cell $and $and$ls180.v:3762$255 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3766$254_Y - connect \B $not$ls180.v:3766$255_Y - connect \Y $and$ls180.v:3766$256_Y + connect \A $and$ls180.v:3762$253_Y + connect \B $not$ls180.v:3762$254_Y + connect \Y $and$ls180.v:3762$255_Y end - attribute \src "ls180.v:3766.76-3766.333" - cell $and $and$ls180.v:3766$259 + attribute \src "ls180.v:3762.76-3762.333" + cell $and $and$ls180.v:3762$258 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3766$252_Y - connect \B $or$ls180.v:3766$258_Y - connect \Y $and$ls180.v:3766$259_Y + connect \A $and$ls180.v:3762$251_Y + connect \B $or$ls180.v:3762$257_Y + connect \Y $and$ls180.v:3762$258_Y end - attribute \src "ls180.v:3766.338-3766.505" - cell $and $and$ls180.v:3766$262 + attribute \src "ls180.v:3762.338-3762.505" + cell $and $and$ls180.v:3762$261 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3766$260_Y - connect \B $eq$ls180.v:3766$261_Y - connect \Y $and$ls180.v:3766$262_Y + connect \A $eq$ls180.v:3762$259_Y + connect \B $eq$ls180.v:3762$260_Y + connect \Y $and$ls180.v:3762$261_Y end - attribute \src "ls180.v:3766.38-3766.507" - cell $and $and$ls180.v:3766$264 + attribute \src "ls180.v:3762.38-3762.507" + cell $and $and$ls180.v:3762$263 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_valid - connect \B $or$ls180.v:3766$263_Y - connect \Y $and$ls180.v:3766$264_Y + connect \B $or$ls180.v:3762$262_Y + connect \Y $and$ls180.v:3762$263_Y end - attribute \src "ls180.v:3767.77-3767.153" - cell $and $and$ls180.v:3767$265 + attribute \src "ls180.v:3763.77-3763.153" + cell $and $and$ls180.v:3763$264 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -84710,65 +84706,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_is_cmd connect \B \main_sdram_choose_cmd_want_cmds - connect \Y $and$ls180.v:3767$265_Y + connect \Y $and$ls180.v:3763$264_Y end - attribute \src "ls180.v:3767.162-3767.246" - cell $and $and$ls180.v:3767$267 + attribute \src "ls180.v:3763.162-3763.246" + cell $and $and$ls180.v:3763$266 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_ras - connect \B $not$ls180.v:3767$266_Y - connect \Y $and$ls180.v:3767$267_Y + connect \B $not$ls180.v:3763$265_Y + connect \Y $and$ls180.v:3763$266_Y end - attribute \src "ls180.v:3767.161-3767.291" - cell $and $and$ls180.v:3767$269 + attribute \src "ls180.v:3763.161-3763.291" + cell $and $and$ls180.v:3763$268 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3767$267_Y - connect \B $not$ls180.v:3767$268_Y - connect \Y $and$ls180.v:3767$269_Y + connect \A $and$ls180.v:3763$266_Y + connect \B $not$ls180.v:3763$267_Y + connect \Y $and$ls180.v:3763$268_Y end - attribute \src "ls180.v:3767.76-3767.333" - cell $and $and$ls180.v:3767$272 + attribute \src "ls180.v:3763.76-3763.333" + cell $and $and$ls180.v:3763$271 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3767$265_Y - connect \B $or$ls180.v:3767$271_Y - connect \Y $and$ls180.v:3767$272_Y + connect \A $and$ls180.v:3763$264_Y + connect \B $or$ls180.v:3763$270_Y + connect \Y $and$ls180.v:3763$271_Y end - attribute \src "ls180.v:3767.338-3767.505" - cell $and $and$ls180.v:3767$275 + attribute \src "ls180.v:3763.338-3763.505" + cell $and $and$ls180.v:3763$274 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3767$273_Y - connect \B $eq$ls180.v:3767$274_Y - connect \Y $and$ls180.v:3767$275_Y + connect \A $eq$ls180.v:3763$272_Y + connect \B $eq$ls180.v:3763$273_Y + connect \Y $and$ls180.v:3763$274_Y end - attribute \src "ls180.v:3767.38-3767.507" - cell $and $and$ls180.v:3767$277 + attribute \src "ls180.v:3763.38-3763.507" + cell $and $and$ls180.v:3763$276 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_valid - connect \B $or$ls180.v:3767$276_Y - connect \Y $and$ls180.v:3767$277_Y + connect \B $or$ls180.v:3763$275_Y + connect \Y $and$ls180.v:3763$276_Y end - attribute \src "ls180.v:3768.77-3768.153" - cell $and $and$ls180.v:3768$278 + attribute \src "ls180.v:3764.77-3764.153" + cell $and $and$ls180.v:3764$277 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -84776,65 +84772,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_is_cmd connect \B \main_sdram_choose_cmd_want_cmds - connect \Y $and$ls180.v:3768$278_Y + connect \Y $and$ls180.v:3764$277_Y end - attribute \src "ls180.v:3768.162-3768.246" - cell $and $and$ls180.v:3768$280 + attribute \src "ls180.v:3764.162-3764.246" + cell $and $and$ls180.v:3764$279 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_ras - connect \B $not$ls180.v:3768$279_Y - connect \Y $and$ls180.v:3768$280_Y + connect \B $not$ls180.v:3764$278_Y + connect \Y $and$ls180.v:3764$279_Y end - attribute \src "ls180.v:3768.161-3768.291" - cell $and $and$ls180.v:3768$282 + attribute \src "ls180.v:3764.161-3764.291" + cell $and $and$ls180.v:3764$281 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3768$280_Y - connect \B $not$ls180.v:3768$281_Y - connect \Y $and$ls180.v:3768$282_Y + connect \A $and$ls180.v:3764$279_Y + connect \B $not$ls180.v:3764$280_Y + connect \Y $and$ls180.v:3764$281_Y end - attribute \src "ls180.v:3768.76-3768.333" - cell $and $and$ls180.v:3768$285 + attribute \src "ls180.v:3764.76-3764.333" + cell $and $and$ls180.v:3764$284 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3768$278_Y - connect \B $or$ls180.v:3768$284_Y - connect \Y $and$ls180.v:3768$285_Y + connect \A $and$ls180.v:3764$277_Y + connect \B $or$ls180.v:3764$283_Y + connect \Y $and$ls180.v:3764$284_Y end - attribute \src "ls180.v:3768.338-3768.505" - cell $and $and$ls180.v:3768$288 + attribute \src "ls180.v:3764.338-3764.505" + cell $and $and$ls180.v:3764$287 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3768$286_Y - connect \B $eq$ls180.v:3768$287_Y - connect \Y $and$ls180.v:3768$288_Y + connect \A $eq$ls180.v:3764$285_Y + connect \B $eq$ls180.v:3764$286_Y + connect \Y $and$ls180.v:3764$287_Y end - attribute \src "ls180.v:3768.38-3768.507" - cell $and $and$ls180.v:3768$290 + attribute \src "ls180.v:3764.38-3764.507" + cell $and $and$ls180.v:3764$289 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_valid - connect \B $or$ls180.v:3768$289_Y - connect \Y $and$ls180.v:3768$290_Y + connect \B $or$ls180.v:3764$288_Y + connect \Y $and$ls180.v:3764$289_Y end - attribute \src "ls180.v:3798.77-3798.153" - cell $and $and$ls180.v:3798$297 + attribute \src "ls180.v:3794.77-3794.153" + cell $and $and$ls180.v:3794$296 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -84842,65 +84838,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_is_cmd connect \B \main_sdram_choose_req_want_cmds - connect \Y $and$ls180.v:3798$297_Y + connect \Y $and$ls180.v:3794$296_Y end - attribute \src "ls180.v:3798.162-3798.246" - cell $and $and$ls180.v:3798$299 + attribute \src "ls180.v:3794.162-3794.246" + cell $and $and$ls180.v:3794$298 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_ras - connect \B $not$ls180.v:3798$298_Y - connect \Y $and$ls180.v:3798$299_Y + connect \B $not$ls180.v:3794$297_Y + connect \Y $and$ls180.v:3794$298_Y end - attribute \src "ls180.v:3798.161-3798.291" - cell $and $and$ls180.v:3798$301 + attribute \src "ls180.v:3794.161-3794.291" + cell $and $and$ls180.v:3794$300 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3798$299_Y - connect \B $not$ls180.v:3798$300_Y - connect \Y $and$ls180.v:3798$301_Y + connect \A $and$ls180.v:3794$298_Y + connect \B $not$ls180.v:3794$299_Y + connect \Y $and$ls180.v:3794$300_Y end - attribute \src "ls180.v:3798.76-3798.333" - cell $and $and$ls180.v:3798$304 + attribute \src "ls180.v:3794.76-3794.333" + cell $and $and$ls180.v:3794$303 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3798$297_Y - connect \B $or$ls180.v:3798$303_Y - connect \Y $and$ls180.v:3798$304_Y + connect \A $and$ls180.v:3794$296_Y + connect \B $or$ls180.v:3794$302_Y + connect \Y $and$ls180.v:3794$303_Y end - attribute \src "ls180.v:3798.338-3798.505" - cell $and $and$ls180.v:3798$307 + attribute \src "ls180.v:3794.338-3794.505" + cell $and $and$ls180.v:3794$306 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3798$305_Y - connect \B $eq$ls180.v:3798$306_Y - connect \Y $and$ls180.v:3798$307_Y + connect \A $eq$ls180.v:3794$304_Y + connect \B $eq$ls180.v:3794$305_Y + connect \Y $and$ls180.v:3794$306_Y end - attribute \src "ls180.v:3798.38-3798.507" - cell $and $and$ls180.v:3798$309 + attribute \src "ls180.v:3794.38-3794.507" + cell $and $and$ls180.v:3794$308 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_valid - connect \B $or$ls180.v:3798$308_Y - connect \Y $and$ls180.v:3798$309_Y + connect \B $or$ls180.v:3794$307_Y + connect \Y $and$ls180.v:3794$308_Y end - attribute \src "ls180.v:3799.77-3799.153" - cell $and $and$ls180.v:3799$310 + attribute \src "ls180.v:3795.77-3795.153" + cell $and $and$ls180.v:3795$309 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -84908,65 +84904,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_is_cmd connect \B \main_sdram_choose_req_want_cmds - connect \Y $and$ls180.v:3799$310_Y + connect \Y $and$ls180.v:3795$309_Y end - attribute \src "ls180.v:3799.162-3799.246" - cell $and $and$ls180.v:3799$312 + attribute \src "ls180.v:3795.162-3795.246" + cell $and $and$ls180.v:3795$311 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_ras - connect \B $not$ls180.v:3799$311_Y - connect \Y $and$ls180.v:3799$312_Y + connect \B $not$ls180.v:3795$310_Y + connect \Y $and$ls180.v:3795$311_Y end - attribute \src "ls180.v:3799.161-3799.291" - cell $and $and$ls180.v:3799$314 + attribute \src "ls180.v:3795.161-3795.291" + cell $and $and$ls180.v:3795$313 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3799$312_Y - connect \B $not$ls180.v:3799$313_Y - connect \Y $and$ls180.v:3799$314_Y + connect \A $and$ls180.v:3795$311_Y + connect \B $not$ls180.v:3795$312_Y + connect \Y $and$ls180.v:3795$313_Y end - attribute \src "ls180.v:3799.76-3799.333" - cell $and $and$ls180.v:3799$317 + attribute \src "ls180.v:3795.76-3795.333" + cell $and $and$ls180.v:3795$316 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3799$310_Y - connect \B $or$ls180.v:3799$316_Y - connect \Y $and$ls180.v:3799$317_Y + connect \A $and$ls180.v:3795$309_Y + connect \B $or$ls180.v:3795$315_Y + connect \Y $and$ls180.v:3795$316_Y end - attribute \src "ls180.v:3799.338-3799.505" - cell $and $and$ls180.v:3799$320 + attribute \src "ls180.v:3795.338-3795.505" + cell $and $and$ls180.v:3795$319 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3799$318_Y - connect \B $eq$ls180.v:3799$319_Y - connect \Y $and$ls180.v:3799$320_Y + connect \A $eq$ls180.v:3795$317_Y + connect \B $eq$ls180.v:3795$318_Y + connect \Y $and$ls180.v:3795$319_Y end - attribute \src "ls180.v:3799.38-3799.507" - cell $and $and$ls180.v:3799$322 + attribute \src "ls180.v:3795.38-3795.507" + cell $and $and$ls180.v:3795$321 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_valid - connect \B $or$ls180.v:3799$321_Y - connect \Y $and$ls180.v:3799$322_Y + connect \B $or$ls180.v:3795$320_Y + connect \Y $and$ls180.v:3795$321_Y end - attribute \src "ls180.v:3800.77-3800.153" - cell $and $and$ls180.v:3800$323 + attribute \src "ls180.v:3796.77-3796.153" + cell $and $and$ls180.v:3796$322 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -84974,65 +84970,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_is_cmd connect \B \main_sdram_choose_req_want_cmds - connect \Y $and$ls180.v:3800$323_Y + connect \Y $and$ls180.v:3796$322_Y end - attribute \src "ls180.v:3800.162-3800.246" - cell $and $and$ls180.v:3800$325 + attribute \src "ls180.v:3796.162-3796.246" + cell $and $and$ls180.v:3796$324 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_ras - connect \B $not$ls180.v:3800$324_Y - connect \Y $and$ls180.v:3800$325_Y + connect \B $not$ls180.v:3796$323_Y + connect \Y $and$ls180.v:3796$324_Y end - attribute \src "ls180.v:3800.161-3800.291" - cell $and $and$ls180.v:3800$327 + attribute \src "ls180.v:3796.161-3796.291" + cell $and $and$ls180.v:3796$326 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3800$325_Y - connect \B $not$ls180.v:3800$326_Y - connect \Y $and$ls180.v:3800$327_Y + connect \A $and$ls180.v:3796$324_Y + connect \B $not$ls180.v:3796$325_Y + connect \Y $and$ls180.v:3796$326_Y end - attribute \src "ls180.v:3800.76-3800.333" - cell $and $and$ls180.v:3800$330 + attribute \src "ls180.v:3796.76-3796.333" + cell $and $and$ls180.v:3796$329 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3800$323_Y - connect \B $or$ls180.v:3800$329_Y - connect \Y $and$ls180.v:3800$330_Y + connect \A $and$ls180.v:3796$322_Y + connect \B $or$ls180.v:3796$328_Y + connect \Y $and$ls180.v:3796$329_Y end - attribute \src "ls180.v:3800.338-3800.505" - cell $and $and$ls180.v:3800$333 + attribute \src "ls180.v:3796.338-3796.505" + cell $and $and$ls180.v:3796$332 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3800$331_Y - connect \B $eq$ls180.v:3800$332_Y - connect \Y $and$ls180.v:3800$333_Y + connect \A $eq$ls180.v:3796$330_Y + connect \B $eq$ls180.v:3796$331_Y + connect \Y $and$ls180.v:3796$332_Y end - attribute \src "ls180.v:3800.38-3800.507" - cell $and $and$ls180.v:3800$335 + attribute \src "ls180.v:3796.38-3796.507" + cell $and $and$ls180.v:3796$334 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_valid - connect \B $or$ls180.v:3800$334_Y - connect \Y $and$ls180.v:3800$335_Y + connect \B $or$ls180.v:3796$333_Y + connect \Y $and$ls180.v:3796$334_Y end - attribute \src "ls180.v:3801.77-3801.153" - cell $and $and$ls180.v:3801$336 + attribute \src "ls180.v:3797.77-3797.153" + cell $and $and$ls180.v:3797$335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -85040,65 +85036,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_is_cmd connect \B \main_sdram_choose_req_want_cmds - connect \Y $and$ls180.v:3801$336_Y + connect \Y $and$ls180.v:3797$335_Y end - attribute \src "ls180.v:3801.162-3801.246" - cell $and $and$ls180.v:3801$338 + attribute \src "ls180.v:3797.162-3797.246" + cell $and $and$ls180.v:3797$337 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_ras - connect \B $not$ls180.v:3801$337_Y - connect \Y $and$ls180.v:3801$338_Y + connect \B $not$ls180.v:3797$336_Y + connect \Y $and$ls180.v:3797$337_Y end - attribute \src "ls180.v:3801.161-3801.291" - cell $and $and$ls180.v:3801$340 + attribute \src "ls180.v:3797.161-3797.291" + cell $and $and$ls180.v:3797$339 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3801$338_Y - connect \B $not$ls180.v:3801$339_Y - connect \Y $and$ls180.v:3801$340_Y + connect \A $and$ls180.v:3797$337_Y + connect \B $not$ls180.v:3797$338_Y + connect \Y $and$ls180.v:3797$339_Y end - attribute \src "ls180.v:3801.76-3801.333" - cell $and $and$ls180.v:3801$343 + attribute \src "ls180.v:3797.76-3797.333" + cell $and $and$ls180.v:3797$342 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3801$336_Y - connect \B $or$ls180.v:3801$342_Y - connect \Y $and$ls180.v:3801$343_Y + connect \A $and$ls180.v:3797$335_Y + connect \B $or$ls180.v:3797$341_Y + connect \Y $and$ls180.v:3797$342_Y end - attribute \src "ls180.v:3801.338-3801.505" - cell $and $and$ls180.v:3801$346 + attribute \src "ls180.v:3797.338-3797.505" + cell $and $and$ls180.v:3797$345 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3801$344_Y - connect \B $eq$ls180.v:3801$345_Y - connect \Y $and$ls180.v:3801$346_Y + connect \A $eq$ls180.v:3797$343_Y + connect \B $eq$ls180.v:3797$344_Y + connect \Y $and$ls180.v:3797$345_Y end - attribute \src "ls180.v:3801.38-3801.507" - cell $and $and$ls180.v:3801$348 + attribute \src "ls180.v:3797.38-3797.507" + cell $and $and$ls180.v:3797$347 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_valid - connect \B $or$ls180.v:3801$347_Y - connect \Y $and$ls180.v:3801$348_Y + connect \B $or$ls180.v:3797$346_Y + connect \Y $and$ls180.v:3797$347_Y end - attribute \src "ls180.v:3830.8-3830.73" - cell $and $and$ls180.v:3830$353 + attribute \src "ls180.v:3826.8-3826.73" + cell $and $and$ls180.v:3826$352 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -85106,21 +85102,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_cmd_valid connect \B \main_sdram_choose_cmd_cmd_ready - connect \Y $and$ls180.v:3830$353_Y + connect \Y $and$ls180.v:3826$352_Y end - attribute \src "ls180.v:3830.7-3830.114" - cell $and $and$ls180.v:3830$355 + attribute \src "ls180.v:3826.7-3826.114" + cell $and $and$ls180.v:3826$354 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3830$353_Y - connect \B $eq$ls180.v:3830$354_Y - connect \Y $and$ls180.v:3830$355_Y + connect \A $and$ls180.v:3826$352_Y + connect \B $eq$ls180.v:3826$353_Y + connect \Y $and$ls180.v:3826$354_Y end - attribute \src "ls180.v:3833.8-3833.73" - cell $and $and$ls180.v:3833$356 + attribute \src "ls180.v:3829.8-3829.73" + cell $and $and$ls180.v:3829$355 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -85128,21 +85124,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3833$356_Y + connect \Y $and$ls180.v:3829$355_Y end - attribute \src "ls180.v:3833.7-3833.114" - cell $and $and$ls180.v:3833$358 + attribute \src "ls180.v:3829.7-3829.114" + cell $and $and$ls180.v:3829$357 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3833$356_Y - connect \B $eq$ls180.v:3833$357_Y - connect \Y $and$ls180.v:3833$358_Y + connect \A $and$ls180.v:3829$355_Y + connect \B $eq$ls180.v:3829$356_Y + connect \Y $and$ls180.v:3829$357_Y end - attribute \src "ls180.v:3839.8-3839.73" - cell $and $and$ls180.v:3839$360 + attribute \src "ls180.v:3835.8-3835.73" + cell $and $and$ls180.v:3835$359 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -85150,21 +85146,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_cmd_valid connect \B \main_sdram_choose_cmd_cmd_ready - connect \Y $and$ls180.v:3839$360_Y + connect \Y $and$ls180.v:3835$359_Y end - attribute \src "ls180.v:3839.7-3839.114" - cell $and $and$ls180.v:3839$362 + attribute \src "ls180.v:3835.7-3835.114" + cell $and $and$ls180.v:3835$361 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3839$360_Y - connect \B $eq$ls180.v:3839$361_Y - connect \Y $and$ls180.v:3839$362_Y + connect \A $and$ls180.v:3835$359_Y + connect \B $eq$ls180.v:3835$360_Y + connect \Y $and$ls180.v:3835$361_Y end - attribute \src "ls180.v:3842.8-3842.73" - cell $and $and$ls180.v:3842$363 + attribute \src "ls180.v:3838.8-3838.73" + cell $and $and$ls180.v:3838$362 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -85172,21 +85168,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3842$363_Y + connect \Y $and$ls180.v:3838$362_Y end - attribute \src "ls180.v:3842.7-3842.114" - cell $and $and$ls180.v:3842$365 + attribute \src "ls180.v:3838.7-3838.114" + cell $and $and$ls180.v:3838$364 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3842$363_Y - connect \B $eq$ls180.v:3842$364_Y - connect \Y $and$ls180.v:3842$365_Y + connect \A $and$ls180.v:3838$362_Y + connect \B $eq$ls180.v:3838$363_Y + connect \Y $and$ls180.v:3838$364_Y end - attribute \src "ls180.v:3848.8-3848.73" - cell $and $and$ls180.v:3848$367 + attribute \src "ls180.v:3844.8-3844.73" + cell $and $and$ls180.v:3844$366 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -85194,21 +85190,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_cmd_valid connect \B \main_sdram_choose_cmd_cmd_ready - connect \Y $and$ls180.v:3848$367_Y + connect \Y $and$ls180.v:3844$366_Y end - attribute \src "ls180.v:3848.7-3848.114" - cell $and $and$ls180.v:3848$369 + attribute \src "ls180.v:3844.7-3844.114" + cell $and $and$ls180.v:3844$368 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3848$367_Y - connect \B $eq$ls180.v:3848$368_Y - connect \Y $and$ls180.v:3848$369_Y + connect \A $and$ls180.v:3844$366_Y + connect \B $eq$ls180.v:3844$367_Y + connect \Y $and$ls180.v:3844$368_Y end - attribute \src "ls180.v:3851.8-3851.73" - cell $and $and$ls180.v:3851$370 + attribute \src "ls180.v:3847.8-3847.73" + cell $and $and$ls180.v:3847$369 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -85216,21 +85212,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3851$370_Y + connect \Y $and$ls180.v:3847$369_Y end - attribute \src "ls180.v:3851.7-3851.114" - cell $and $and$ls180.v:3851$372 + attribute \src "ls180.v:3847.7-3847.114" + cell $and $and$ls180.v:3847$371 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3851$370_Y - connect \B $eq$ls180.v:3851$371_Y - connect \Y $and$ls180.v:3851$372_Y + connect \A $and$ls180.v:3847$369_Y + connect \B $eq$ls180.v:3847$370_Y + connect \Y $and$ls180.v:3847$371_Y end - attribute \src "ls180.v:3857.8-3857.73" - cell $and $and$ls180.v:3857$374 + attribute \src "ls180.v:3853.8-3853.73" + cell $and $and$ls180.v:3853$373 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -85238,21 +85234,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_cmd_valid connect \B \main_sdram_choose_cmd_cmd_ready - connect \Y $and$ls180.v:3857$374_Y + connect \Y $and$ls180.v:3853$373_Y end - attribute \src "ls180.v:3857.7-3857.114" - cell $and $and$ls180.v:3857$376 + attribute \src "ls180.v:3853.7-3853.114" + cell $and $and$ls180.v:3853$375 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3857$374_Y - connect \B $eq$ls180.v:3857$375_Y - connect \Y $and$ls180.v:3857$376_Y + connect \A $and$ls180.v:3853$373_Y + connect \B $eq$ls180.v:3853$374_Y + connect \Y $and$ls180.v:3853$375_Y end - attribute \src "ls180.v:3860.8-3860.73" - cell $and $and$ls180.v:3860$377 + attribute \src "ls180.v:3856.8-3856.73" + cell $and $and$ls180.v:3856$376 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -85260,615 +85256,615 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3860$377_Y + connect \Y $and$ls180.v:3856$376_Y end - attribute \src "ls180.v:3860.7-3860.114" - cell $and $and$ls180.v:3860$379 + attribute \src "ls180.v:3856.7-3856.114" + cell $and $and$ls180.v:3856$378 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3860$377_Y - connect \B $eq$ls180.v:3860$378_Y - connect \Y $and$ls180.v:3860$379_Y + connect \A $and$ls180.v:3856$376_Y + connect \B $eq$ls180.v:3856$377_Y + connect \Y $and$ls180.v:3856$378_Y end - attribute \src "ls180.v:3885.71-3885.151" - cell $and $and$ls180.v:3885$384 + attribute \src "ls180.v:3881.71-3881.151" + cell $and $and$ls180.v:3881$383 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_ras - connect \B $not$ls180.v:3885$383_Y - connect \Y $and$ls180.v:3885$384_Y + connect \B $not$ls180.v:3881$382_Y + connect \Y $and$ls180.v:3881$383_Y end - attribute \src "ls180.v:3885.70-3885.194" - cell $and $and$ls180.v:3885$386 + attribute \src "ls180.v:3881.70-3881.194" + cell $and $and$ls180.v:3881$385 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3885$384_Y - connect \B $not$ls180.v:3885$385_Y - connect \Y $and$ls180.v:3885$386_Y + connect \A $and$ls180.v:3881$383_Y + connect \B $not$ls180.v:3881$384_Y + connect \Y $and$ls180.v:3881$385_Y end - attribute \src "ls180.v:3885.41-3885.222" - cell $and $and$ls180.v:3885$389 + attribute \src "ls180.v:3881.41-3881.222" + cell $and $and$ls180.v:3881$388 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_cas_allowed - connect \B $or$ls180.v:3885$388_Y - connect \Y $and$ls180.v:3885$389_Y + connect \B $or$ls180.v:3881$387_Y + connect \Y $and$ls180.v:3881$388_Y end - attribute \src "ls180.v:3923.71-3923.151" - cell $and $and$ls180.v:3923$393 + attribute \src "ls180.v:3919.71-3919.151" + cell $and $and$ls180.v:3919$392 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_ras - connect \B $not$ls180.v:3923$392_Y - connect \Y $and$ls180.v:3923$393_Y + connect \B $not$ls180.v:3919$391_Y + connect \Y $and$ls180.v:3919$392_Y end - attribute \src "ls180.v:3923.70-3923.194" - cell $and $and$ls180.v:3923$395 + attribute \src "ls180.v:3919.70-3919.194" + cell $and $and$ls180.v:3919$394 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3923$393_Y - connect \B $not$ls180.v:3923$394_Y - connect \Y $and$ls180.v:3923$395_Y + connect \A $and$ls180.v:3919$392_Y + connect \B $not$ls180.v:3919$393_Y + connect \Y $and$ls180.v:3919$394_Y end - attribute \src "ls180.v:3923.41-3923.222" - cell $and $and$ls180.v:3923$398 + attribute \src "ls180.v:3919.41-3919.222" + cell $and $and$ls180.v:3919$397 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_cas_allowed - connect \B $or$ls180.v:3923$397_Y - connect \Y $and$ls180.v:3923$398_Y + connect \B $or$ls180.v:3919$396_Y + connect \Y $and$ls180.v:3919$397_Y end - attribute \src "ls180.v:3941.110-3941.179" - cell $and $and$ls180.v:3941$403 + attribute \src "ls180.v:3937.110-3937.179" + cell $and $and$ls180.v:3937$402 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:3941$402_Y - connect \Y $and$ls180.v:3941$403_Y + connect \B $eq$ls180.v:3937$401_Y + connect \Y $and$ls180.v:3937$402_Y end - attribute \src "ls180.v:3941.185-3941.254" - cell $and $and$ls180.v:3941$406 + attribute \src "ls180.v:3937.185-3937.254" + cell $and $and$ls180.v:3937$405 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:3941$405_Y - connect \Y $and$ls180.v:3941$406_Y + connect \B $eq$ls180.v:3937$404_Y + connect \Y $and$ls180.v:3937$405_Y end - attribute \src "ls180.v:3941.260-3941.329" - cell $and $and$ls180.v:3941$409 + attribute \src "ls180.v:3937.260-3937.329" + cell $and $and$ls180.v:3937$408 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:3941$408_Y - connect \Y $and$ls180.v:3941$409_Y + connect \B $eq$ls180.v:3937$407_Y + connect \Y $and$ls180.v:3937$408_Y end - attribute \src "ls180.v:3941.41-3941.332" - cell $and $and$ls180.v:3941$412 + attribute \src "ls180.v:3937.41-3937.332" + cell $and $and$ls180.v:3937$411 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3941$401_Y - connect \B $not$ls180.v:3941$411_Y - connect \Y $and$ls180.v:3941$412_Y + connect \A $eq$ls180.v:3937$400_Y + connect \B $not$ls180.v:3937$410_Y + connect \Y $and$ls180.v:3937$411_Y end - attribute \src "ls180.v:3941.40-3941.355" - cell $and $and$ls180.v:3941$413 + attribute \src "ls180.v:3937.40-3937.355" + cell $and $and$ls180.v:3937$412 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3941$412_Y + connect \A $and$ls180.v:3937$411_Y connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:3941$413_Y + connect \Y $and$ls180.v:3937$412_Y end - attribute \src "ls180.v:3942.34-3942.106" - cell $and $and$ls180.v:3942$416 + attribute \src "ls180.v:3938.34-3938.106" + cell $and $and$ls180.v:3938$415 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3942$414_Y - connect \B $not$ls180.v:3942$415_Y - connect \Y $and$ls180.v:3942$416_Y + connect \A $not$ls180.v:3938$413_Y + connect \B $not$ls180.v:3938$414_Y + connect \Y $and$ls180.v:3938$415_Y end - attribute \src "ls180.v:3946.110-3946.179" - cell $and $and$ls180.v:3946$419 + attribute \src "ls180.v:3942.110-3942.179" + cell $and $and$ls180.v:3942$418 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:3946$418_Y - connect \Y $and$ls180.v:3946$419_Y + connect \B $eq$ls180.v:3942$417_Y + connect \Y $and$ls180.v:3942$418_Y end - attribute \src "ls180.v:3946.185-3946.254" - cell $and $and$ls180.v:3946$422 + attribute \src "ls180.v:3942.185-3942.254" + cell $and $and$ls180.v:3942$421 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:3946$421_Y - connect \Y $and$ls180.v:3946$422_Y + connect \B $eq$ls180.v:3942$420_Y + connect \Y $and$ls180.v:3942$421_Y end - attribute \src "ls180.v:3946.260-3946.329" - cell $and $and$ls180.v:3946$425 + attribute \src "ls180.v:3942.260-3942.329" + cell $and $and$ls180.v:3942$424 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:3946$424_Y - connect \Y $and$ls180.v:3946$425_Y + connect \B $eq$ls180.v:3942$423_Y + connect \Y $and$ls180.v:3942$424_Y end - attribute \src "ls180.v:3946.41-3946.332" - cell $and $and$ls180.v:3946$428 + attribute \src "ls180.v:3942.41-3942.332" + cell $and $and$ls180.v:3942$427 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3946$417_Y - connect \B $not$ls180.v:3946$427_Y - connect \Y $and$ls180.v:3946$428_Y + connect \A $eq$ls180.v:3942$416_Y + connect \B $not$ls180.v:3942$426_Y + connect \Y $and$ls180.v:3942$427_Y end - attribute \src "ls180.v:3946.40-3946.355" - cell $and $and$ls180.v:3946$429 + attribute \src "ls180.v:3942.40-3942.355" + cell $and $and$ls180.v:3942$428 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3946$428_Y + connect \A $and$ls180.v:3942$427_Y connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:3946$429_Y + connect \Y $and$ls180.v:3942$428_Y end - attribute \src "ls180.v:3947.34-3947.106" - cell $and $and$ls180.v:3947$432 + attribute \src "ls180.v:3943.34-3943.106" + cell $and $and$ls180.v:3943$431 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3947$430_Y - connect \B $not$ls180.v:3947$431_Y - connect \Y $and$ls180.v:3947$432_Y + connect \A $not$ls180.v:3943$429_Y + connect \B $not$ls180.v:3943$430_Y + connect \Y $and$ls180.v:3943$431_Y end - attribute \src "ls180.v:3951.110-3951.179" - cell $and $and$ls180.v:3951$435 + attribute \src "ls180.v:3947.110-3947.179" + cell $and $and$ls180.v:3947$434 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:3951$434_Y - connect \Y $and$ls180.v:3951$435_Y + connect \B $eq$ls180.v:3947$433_Y + connect \Y $and$ls180.v:3947$434_Y end - attribute \src "ls180.v:3951.185-3951.254" - cell $and $and$ls180.v:3951$438 + attribute \src "ls180.v:3947.185-3947.254" + cell $and $and$ls180.v:3947$437 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:3951$437_Y - connect \Y $and$ls180.v:3951$438_Y + connect \B $eq$ls180.v:3947$436_Y + connect \Y $and$ls180.v:3947$437_Y end - attribute \src "ls180.v:3951.260-3951.329" - cell $and $and$ls180.v:3951$441 + attribute \src "ls180.v:3947.260-3947.329" + cell $and $and$ls180.v:3947$440 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:3951$440_Y - connect \Y $and$ls180.v:3951$441_Y + connect \B $eq$ls180.v:3947$439_Y + connect \Y $and$ls180.v:3947$440_Y end - attribute \src "ls180.v:3951.41-3951.332" - cell $and $and$ls180.v:3951$444 + attribute \src "ls180.v:3947.41-3947.332" + cell $and $and$ls180.v:3947$443 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3951$433_Y - connect \B $not$ls180.v:3951$443_Y - connect \Y $and$ls180.v:3951$444_Y + connect \A $eq$ls180.v:3947$432_Y + connect \B $not$ls180.v:3947$442_Y + connect \Y $and$ls180.v:3947$443_Y end - attribute \src "ls180.v:3951.40-3951.355" - cell $and $and$ls180.v:3951$445 + attribute \src "ls180.v:3947.40-3947.355" + cell $and $and$ls180.v:3947$444 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3951$444_Y + connect \A $and$ls180.v:3947$443_Y connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:3951$445_Y + connect \Y $and$ls180.v:3947$444_Y end - attribute \src "ls180.v:3952.34-3952.106" - cell $and $and$ls180.v:3952$448 + attribute \src "ls180.v:3948.34-3948.106" + cell $and $and$ls180.v:3948$447 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3952$446_Y - connect \B $not$ls180.v:3952$447_Y - connect \Y $and$ls180.v:3952$448_Y + connect \A $not$ls180.v:3948$445_Y + connect \B $not$ls180.v:3948$446_Y + connect \Y $and$ls180.v:3948$447_Y end - attribute \src "ls180.v:3956.110-3956.179" - cell $and $and$ls180.v:3956$451 + attribute \src "ls180.v:3952.110-3952.179" + cell $and $and$ls180.v:3952$450 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:3956$450_Y - connect \Y $and$ls180.v:3956$451_Y + connect \B $eq$ls180.v:3952$449_Y + connect \Y $and$ls180.v:3952$450_Y end - attribute \src "ls180.v:3956.185-3956.254" - cell $and $and$ls180.v:3956$454 + attribute \src "ls180.v:3952.185-3952.254" + cell $and $and$ls180.v:3952$453 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:3956$453_Y - connect \Y $and$ls180.v:3956$454_Y + connect \B $eq$ls180.v:3952$452_Y + connect \Y $and$ls180.v:3952$453_Y end - attribute \src "ls180.v:3956.260-3956.329" - cell $and $and$ls180.v:3956$457 + attribute \src "ls180.v:3952.260-3952.329" + cell $and $and$ls180.v:3952$456 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:3956$456_Y - connect \Y $and$ls180.v:3956$457_Y + connect \B $eq$ls180.v:3952$455_Y + connect \Y $and$ls180.v:3952$456_Y end - attribute \src "ls180.v:3956.41-3956.332" - cell $and $and$ls180.v:3956$460 + attribute \src "ls180.v:3952.41-3952.332" + cell $and $and$ls180.v:3952$459 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3956$449_Y - connect \B $not$ls180.v:3956$459_Y - connect \Y $and$ls180.v:3956$460_Y + connect \A $eq$ls180.v:3952$448_Y + connect \B $not$ls180.v:3952$458_Y + connect \Y $and$ls180.v:3952$459_Y end - attribute \src "ls180.v:3956.40-3956.355" - cell $and $and$ls180.v:3956$461 + attribute \src "ls180.v:3952.40-3952.355" + cell $and $and$ls180.v:3952$460 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3956$460_Y + connect \A $and$ls180.v:3952$459_Y connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:3956$461_Y + connect \Y $and$ls180.v:3952$460_Y end - attribute \src "ls180.v:3957.34-3957.106" - cell $and $and$ls180.v:3957$464 + attribute \src "ls180.v:3953.34-3953.106" + cell $and $and$ls180.v:3953$463 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3957$462_Y - connect \B $not$ls180.v:3957$463_Y - connect \Y $and$ls180.v:3957$464_Y + connect \A $not$ls180.v:3953$461_Y + connect \B $not$ls180.v:3953$462_Y + connect \Y $and$ls180.v:3953$463_Y end - attribute \src "ls180.v:3961.151-3961.220" - cell $and $and$ls180.v:3961$468 + attribute \src "ls180.v:3957.151-3957.220" + cell $and $and$ls180.v:3957$467 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:3961$467_Y - connect \Y $and$ls180.v:3961$468_Y + connect \B $eq$ls180.v:3957$466_Y + connect \Y $and$ls180.v:3957$467_Y end - attribute \src "ls180.v:3961.226-3961.295" - cell $and $and$ls180.v:3961$471 + attribute \src "ls180.v:3957.226-3957.295" + cell $and $and$ls180.v:3957$470 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:3961$470_Y - connect \Y $and$ls180.v:3961$471_Y + connect \B $eq$ls180.v:3957$469_Y + connect \Y $and$ls180.v:3957$470_Y end - attribute \src "ls180.v:3961.301-3961.370" - cell $and $and$ls180.v:3961$474 + attribute \src "ls180.v:3957.301-3957.370" + cell $and $and$ls180.v:3957$473 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:3961$473_Y - connect \Y $and$ls180.v:3961$474_Y + connect \B $eq$ls180.v:3957$472_Y + connect \Y $and$ls180.v:3957$473_Y end - attribute \src "ls180.v:3961.82-3961.373" - cell $and $and$ls180.v:3961$477 + attribute \src "ls180.v:3957.82-3957.373" + cell $and $and$ls180.v:3957$476 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3961$466_Y - connect \B $not$ls180.v:3961$476_Y - connect \Y $and$ls180.v:3961$477_Y + connect \A $eq$ls180.v:3957$465_Y + connect \B $not$ls180.v:3957$475_Y + connect \Y $and$ls180.v:3957$476_Y end - attribute \src "ls180.v:3961.43-3961.374" - cell $and $and$ls180.v:3961$478 + attribute \src "ls180.v:3957.43-3957.374" + cell $and $and$ls180.v:3957$477 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3961$465_Y - connect \B $and$ls180.v:3961$477_Y - connect \Y $and$ls180.v:3961$478_Y + connect \A $eq$ls180.v:3957$464_Y + connect \B $and$ls180.v:3957$476_Y + connect \Y $and$ls180.v:3957$477_Y end - attribute \src "ls180.v:3961.42-3961.410" - cell $and $and$ls180.v:3961$479 + attribute \src "ls180.v:3957.42-3957.410" + cell $and $and$ls180.v:3957$478 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3961$478_Y + connect \A $and$ls180.v:3957$477_Y connect \B \main_sdram_interface_bank0_ready - connect \Y $and$ls180.v:3961$479_Y + connect \Y $and$ls180.v:3957$478_Y end - attribute \src "ls180.v:3961.525-3961.594" - cell $and $and$ls180.v:3961$484 + attribute \src "ls180.v:3957.525-3957.594" + cell $and $and$ls180.v:3957$483 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:3961$483_Y - connect \Y $and$ls180.v:3961$484_Y + connect \B $eq$ls180.v:3957$482_Y + connect \Y $and$ls180.v:3957$483_Y end - attribute \src "ls180.v:3961.600-3961.669" - cell $and $and$ls180.v:3961$487 + attribute \src "ls180.v:3957.600-3957.669" + cell $and $and$ls180.v:3957$486 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:3961$486_Y - connect \Y $and$ls180.v:3961$487_Y + connect \B $eq$ls180.v:3957$485_Y + connect \Y $and$ls180.v:3957$486_Y end - attribute \src "ls180.v:3961.675-3961.744" - cell $and $and$ls180.v:3961$490 + attribute \src "ls180.v:3957.675-3957.744" + cell $and $and$ls180.v:3957$489 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:3961$489_Y - connect \Y $and$ls180.v:3961$490_Y + connect \B $eq$ls180.v:3957$488_Y + connect \Y $and$ls180.v:3957$489_Y end - attribute \src "ls180.v:3961.456-3961.747" - cell $and $and$ls180.v:3961$493 + attribute \src "ls180.v:3957.456-3957.747" + cell $and $and$ls180.v:3957$492 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3961$482_Y - connect \B $not$ls180.v:3961$492_Y - connect \Y $and$ls180.v:3961$493_Y + connect \A $eq$ls180.v:3957$481_Y + connect \B $not$ls180.v:3957$491_Y + connect \Y $and$ls180.v:3957$492_Y end - attribute \src "ls180.v:3961.417-3961.748" - cell $and $and$ls180.v:3961$494 + attribute \src "ls180.v:3957.417-3957.748" + cell $and $and$ls180.v:3957$493 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3961$481_Y - connect \B $and$ls180.v:3961$493_Y - connect \Y $and$ls180.v:3961$494_Y + connect \A $eq$ls180.v:3957$480_Y + connect \B $and$ls180.v:3957$492_Y + connect \Y $and$ls180.v:3957$493_Y end - attribute \src "ls180.v:3961.416-3961.784" - cell $and $and$ls180.v:3961$495 + attribute \src "ls180.v:3957.416-3957.784" + cell $and $and$ls180.v:3957$494 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3961$494_Y + connect \A $and$ls180.v:3957$493_Y connect \B \main_sdram_interface_bank1_ready - connect \Y $and$ls180.v:3961$495_Y + connect \Y $and$ls180.v:3957$494_Y end - attribute \src "ls180.v:3961.899-3961.968" - cell $and $and$ls180.v:3961$500 + attribute \src "ls180.v:3957.899-3957.968" + cell $and $and$ls180.v:3957$499 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:3961$499_Y - connect \Y $and$ls180.v:3961$500_Y + connect \B $eq$ls180.v:3957$498_Y + connect \Y $and$ls180.v:3957$499_Y end - attribute \src "ls180.v:3961.974-3961.1043" - cell $and $and$ls180.v:3961$503 + attribute \src "ls180.v:3957.974-3957.1043" + cell $and $and$ls180.v:3957$502 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:3961$502_Y - connect \Y $and$ls180.v:3961$503_Y + connect \B $eq$ls180.v:3957$501_Y + connect \Y $and$ls180.v:3957$502_Y end - attribute \src "ls180.v:3961.1049-3961.1118" - cell $and $and$ls180.v:3961$506 + attribute \src "ls180.v:3957.1049-3957.1118" + cell $and $and$ls180.v:3957$505 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:3961$505_Y - connect \Y $and$ls180.v:3961$506_Y + connect \B $eq$ls180.v:3957$504_Y + connect \Y $and$ls180.v:3957$505_Y end - attribute \src "ls180.v:3961.830-3961.1121" - cell $and $and$ls180.v:3961$509 + attribute \src "ls180.v:3957.830-3957.1121" + cell $and $and$ls180.v:3957$508 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3961$498_Y - connect \B $not$ls180.v:3961$508_Y - connect \Y $and$ls180.v:3961$509_Y + connect \A $eq$ls180.v:3957$497_Y + connect \B $not$ls180.v:3957$507_Y + connect \Y $and$ls180.v:3957$508_Y end - attribute \src "ls180.v:3961.791-3961.1122" - cell $and $and$ls180.v:3961$510 + attribute \src "ls180.v:3957.791-3957.1122" + cell $and $and$ls180.v:3957$509 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3961$497_Y - connect \B $and$ls180.v:3961$509_Y - connect \Y $and$ls180.v:3961$510_Y + connect \A $eq$ls180.v:3957$496_Y + connect \B $and$ls180.v:3957$508_Y + connect \Y $and$ls180.v:3957$509_Y end - attribute \src "ls180.v:3961.790-3961.1158" - cell $and $and$ls180.v:3961$511 + attribute \src "ls180.v:3957.790-3957.1158" + cell $and $and$ls180.v:3957$510 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3961$510_Y + connect \A $and$ls180.v:3957$509_Y connect \B \main_sdram_interface_bank2_ready - connect \Y $and$ls180.v:3961$511_Y + connect \Y $and$ls180.v:3957$510_Y end - attribute \src "ls180.v:3961.1273-3961.1342" - cell $and $and$ls180.v:3961$516 + attribute \src "ls180.v:3957.1273-3957.1342" + cell $and $and$ls180.v:3957$515 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:3961$515_Y - connect \Y $and$ls180.v:3961$516_Y + connect \B $eq$ls180.v:3957$514_Y + connect \Y $and$ls180.v:3957$515_Y end - attribute \src "ls180.v:3961.1348-3961.1417" - cell $and $and$ls180.v:3961$519 + attribute \src "ls180.v:3957.1348-3957.1417" + cell $and $and$ls180.v:3957$518 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:3961$518_Y - connect \Y $and$ls180.v:3961$519_Y + connect \B $eq$ls180.v:3957$517_Y + connect \Y $and$ls180.v:3957$518_Y end - attribute \src "ls180.v:3961.1423-3961.1492" - cell $and $and$ls180.v:3961$522 + attribute \src "ls180.v:3957.1423-3957.1492" + cell $and $and$ls180.v:3957$521 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:3961$521_Y - connect \Y $and$ls180.v:3961$522_Y + connect \B $eq$ls180.v:3957$520_Y + connect \Y $and$ls180.v:3957$521_Y end - attribute \src "ls180.v:3961.1204-3961.1495" - cell $and $and$ls180.v:3961$525 + attribute \src "ls180.v:3957.1204-3957.1495" + cell $and $and$ls180.v:3957$524 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3961$514_Y - connect \B $not$ls180.v:3961$524_Y - connect \Y $and$ls180.v:3961$525_Y + connect \A $eq$ls180.v:3957$513_Y + connect \B $not$ls180.v:3957$523_Y + connect \Y $and$ls180.v:3957$524_Y end - attribute \src "ls180.v:3961.1165-3961.1496" - cell $and $and$ls180.v:3961$526 + attribute \src "ls180.v:3957.1165-3957.1496" + cell $and $and$ls180.v:3957$525 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3961$513_Y - connect \B $and$ls180.v:3961$525_Y - connect \Y $and$ls180.v:3961$526_Y + connect \A $eq$ls180.v:3957$512_Y + connect \B $and$ls180.v:3957$524_Y + connect \Y $and$ls180.v:3957$525_Y end - attribute \src "ls180.v:3961.1164-3961.1532" - cell $and $and$ls180.v:3961$527 + attribute \src "ls180.v:3957.1164-3957.1532" + cell $and $and$ls180.v:3957$526 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3961$526_Y + connect \A $and$ls180.v:3957$525_Y connect \B \main_sdram_interface_bank3_ready - connect \Y $and$ls180.v:3961$527_Y + connect \Y $and$ls180.v:3957$526_Y end - attribute \src "ls180.v:4019.9-4019.46" - cell $and $and$ls180.v:4019$533 + attribute \src "ls180.v:4015.9-4015.46" + cell $and $and$ls180.v:4015$532 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -85876,10 +85872,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_wb_sdram_stb connect \B \main_wb_sdram_cyc - connect \Y $and$ls180.v:4019$533_Y + connect \Y $and$ls180.v:4015$532_Y end - attribute \src "ls180.v:4037.9-4037.46" - cell $and $and$ls180.v:4037$540 + attribute \src "ls180.v:4033.9-4033.46" + cell $and $and$ls180.v:4033$539 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -85887,10 +85883,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_wb_sdram_stb connect \B \main_wb_sdram_cyc - connect \Y $and$ls180.v:4037$540_Y + connect \Y $and$ls180.v:4033$539_Y end - attribute \src "ls180.v:4050.32-4050.75" - cell $and $and$ls180.v:4050$544 + attribute \src "ls180.v:4046.32-4046.75" + cell $and $and$ls180.v:4046$543 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -85898,54 +85894,54 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_litedram_wb_cyc connect \B \main_litedram_wb_stb - connect \Y $and$ls180.v:4050$544_Y + connect \Y $and$ls180.v:4046$543_Y end - attribute \src "ls180.v:4050.31-4050.99" - cell $and $and$ls180.v:4050$546 + attribute \src "ls180.v:4046.31-4046.99" + cell $and $and$ls180.v:4046$545 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4050$544_Y - connect \B $not$ls180.v:4050$545_Y - connect \Y $and$ls180.v:4050$546_Y + connect \A $and$ls180.v:4046$543_Y + connect \B $not$ls180.v:4046$544_Y + connect \Y $and$ls180.v:4046$545_Y end - attribute \src "ls180.v:4051.34-4051.102" - cell $and $and$ls180.v:4051$548 + attribute \src "ls180.v:4047.34-4047.102" + cell $and $and$ls180.v:4047$547 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4051$547_Y + connect \A $or$ls180.v:4047$546_Y connect \B \main_port_cmd_payload_we - connect \Y $and$ls180.v:4051$548_Y + connect \Y $and$ls180.v:4047$547_Y end - attribute \src "ls180.v:4051.33-4051.128" - cell $and $and$ls180.v:4051$550 + attribute \src "ls180.v:4047.33-4047.128" + cell $and $and$ls180.v:4047$549 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4051$548_Y - connect \B $not$ls180.v:4051$549_Y - connect \Y $and$ls180.v:4051$550_Y + connect \A $and$ls180.v:4047$547_Y + connect \B $not$ls180.v:4047$548_Y + connect \Y $and$ls180.v:4047$549_Y end - attribute \src "ls180.v:4052.33-4052.104" - cell $and $and$ls180.v:4052$553 + attribute \src "ls180.v:4048.33-4048.104" + cell $and $and$ls180.v:4048$552 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4052$551_Y - connect \B $not$ls180.v:4052$552_Y - connect \Y $and$ls180.v:4052$553_Y + connect \A $or$ls180.v:4048$550_Y + connect \B $not$ls180.v:4048$551_Y + connect \Y $and$ls180.v:4048$552_Y end - attribute \src "ls180.v:4053.49-4053.85" - cell $and $and$ls180.v:4053$554 + attribute \src "ls180.v:4049.49-4049.85" + cell $and $and$ls180.v:4049$553 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -85953,32 +85949,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_litedram_wb_we connect \B \main_ack_wdata - connect \Y $and$ls180.v:4053$554_Y + connect \Y $and$ls180.v:4049$553_Y end - attribute \src "ls180.v:4053.90-4053.129" - cell $and $and$ls180.v:4053$556 + attribute \src "ls180.v:4049.90-4049.129" + cell $and $and$ls180.v:4049$555 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4053$555_Y + connect \A $not$ls180.v:4049$554_Y connect \B \main_ack_rdata - connect \Y $and$ls180.v:4053$556_Y + connect \Y $and$ls180.v:4049$555_Y end - attribute \src "ls180.v:4053.32-4053.131" - cell $and $and$ls180.v:4053$558 + attribute \src "ls180.v:4049.32-4049.131" + cell $and $and$ls180.v:4049$557 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_ack_cmd - connect \B $or$ls180.v:4053$557_Y - connect \Y $and$ls180.v:4053$558_Y + connect \B $or$ls180.v:4049$556_Y + connect \Y $and$ls180.v:4049$557_Y end - attribute \src "ls180.v:4054.25-4054.66" - cell $and $and$ls180.v:4054$559 + attribute \src "ls180.v:4050.25-4050.66" + cell $and $and$ls180.v:4050$558 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -85986,10 +85982,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_valid connect \B \main_port_cmd_ready - connect \Y $and$ls180.v:4054$559_Y + connect \Y $and$ls180.v:4050$558_Y end - attribute \src "ls180.v:4055.27-4055.72" - cell $and $and$ls180.v:4055$561 + attribute \src "ls180.v:4051.27-4051.72" + cell $and $and$ls180.v:4051$560 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -85997,10 +85993,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_wdata_valid connect \B \main_port_wdata_ready - connect \Y $and$ls180.v:4055$561_Y + connect \Y $and$ls180.v:4051$560_Y end - attribute \src "ls180.v:4056.26-4056.71" - cell $and $and$ls180.v:4056$563 + attribute \src "ls180.v:4052.26-4052.71" + cell $and $and$ls180.v:4052$562 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86008,10 +86004,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_rdata_valid connect \B \main_port_rdata_ready - connect \Y $and$ls180.v:4056$563_Y + connect \Y $and$ls180.v:4052$562_Y end - attribute \src "ls180.v:4085.64-4085.88" - cell $and $and$ls180.v:4085$569 + attribute \src "ls180.v:4081.64-4081.88" + cell $and $and$ls180.v:4081$568 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86019,10 +86015,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A 1'0 connect \B \main_uart_rxtx_we - connect \Y $and$ls180.v:4085$569_Y + connect \Y $and$ls180.v:4081$568_Y end - attribute \src "ls180.v:4089.7-4089.78" - cell $and $and$ls180.v:4089$573 + attribute \src "ls180.v:4085.7-4085.78" + cell $and $and$ls180.v:4085$572 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86030,10 +86026,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_eventmanager_pending_re connect \B \main_uart_eventmanager_pending_r [0] - connect \Y $and$ls180.v:4089$573_Y + connect \Y $and$ls180.v:4085$572_Y end - attribute \src "ls180.v:4100.7-4100.78" - cell $and $and$ls180.v:4100$576 + attribute \src "ls180.v:4096.7-4096.78" + cell $and $and$ls180.v:4096$575 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86041,10 +86037,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_eventmanager_pending_re connect \B \main_uart_eventmanager_pending_r [1] - connect \Y $and$ls180.v:4100$576_Y + connect \Y $and$ls180.v:4096$575_Y end - attribute \src "ls180.v:4109.26-4109.97" - cell $and $and$ls180.v:4109$578 + attribute \src "ls180.v:4105.26-4105.97" + cell $and $and$ls180.v:4105$577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86052,10 +86048,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_eventmanager_pending_w [0] connect \B \main_uart_eventmanager_storage [0] - connect \Y $and$ls180.v:4109$578_Y + connect \Y $and$ls180.v:4105$577_Y end - attribute \src "ls180.v:4109.102-4109.173" - cell $and $and$ls180.v:4109$579 + attribute \src "ls180.v:4105.102-4105.173" + cell $and $and$ls180.v:4105$578 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86063,32 +86059,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_eventmanager_pending_w [1] connect \B \main_uart_eventmanager_storage [1] - connect \Y $and$ls180.v:4109$579_Y + connect \Y $and$ls180.v:4105$578_Y end - attribute \src "ls180.v:4124.41-4124.133" - cell $and $and$ls180.v:4124$583 + attribute \src "ls180.v:4120.41-4120.133" + cell $and $and$ls180.v:4120$582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_syncfifo_readable - connect \B $or$ls180.v:4124$582_Y - connect \Y $and$ls180.v:4124$583_Y + connect \B $or$ls180.v:4120$581_Y + connect \Y $and$ls180.v:4120$582_Y end - attribute \src "ls180.v:4135.39-4135.136" - cell $and $and$ls180.v:4135$588 + attribute \src "ls180.v:4131.39-4131.136" + cell $and $and$ls180.v:4131$587 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_syncfifo_we - connect \B $or$ls180.v:4135$587_Y - connect \Y $and$ls180.v:4135$588_Y + connect \B $or$ls180.v:4131$586_Y + connect \Y $and$ls180.v:4131$587_Y end - attribute \src "ls180.v:4136.37-4136.104" - cell $and $and$ls180.v:4136$589 + attribute \src "ls180.v:4132.37-4132.104" + cell $and $and$ls180.v:4132$588 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86096,32 +86092,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_syncfifo_readable connect \B \main_uart_tx_fifo_syncfifo_re - connect \Y $and$ls180.v:4136$589_Y + connect \Y $and$ls180.v:4132$588_Y end - attribute \src "ls180.v:4154.41-4154.133" - cell $and $and$ls180.v:4154$594 + attribute \src "ls180.v:4150.41-4150.133" + cell $and $and$ls180.v:4150$593 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_syncfifo_readable - connect \B $or$ls180.v:4154$593_Y - connect \Y $and$ls180.v:4154$594_Y + connect \B $or$ls180.v:4150$592_Y + connect \Y $and$ls180.v:4150$593_Y end - attribute \src "ls180.v:4165.39-4165.136" - cell $and $and$ls180.v:4165$599 + attribute \src "ls180.v:4161.39-4161.136" + cell $and $and$ls180.v:4161$598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_syncfifo_we - connect \B $or$ls180.v:4165$598_Y - connect \Y $and$ls180.v:4165$599_Y + connect \B $or$ls180.v:4161$597_Y + connect \Y $and$ls180.v:4161$598_Y end - attribute \src "ls180.v:4166.37-4166.104" - cell $and $and$ls180.v:4166$600 + attribute \src "ls180.v:4162.37-4162.104" + cell $and $and$ls180.v:4162$599 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86129,21 +86125,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_syncfifo_readable connect \B \main_uart_rx_fifo_syncfifo_re - connect \Y $and$ls180.v:4166$600_Y + connect \Y $and$ls180.v:4162$599_Y end - attribute \src "ls180.v:4291.33-4291.86" - cell $and $and$ls180.v:4291$634 + attribute \src "ls180.v:4287.33-4287.86" + cell $and $and$ls180.v:4287$633 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_clocker_clk1 - connect \B $not$ls180.v:4291$633_Y - connect \Y $and$ls180.v:4291$634_Y + connect \B $not$ls180.v:4287$632_Y + connect \Y $and$ls180.v:4287$633_Y end - attribute \src "ls180.v:4395.9-4395.68" - cell $and $and$ls180.v:4395$643 + attribute \src "ls180.v:4391.9-4391.68" + cell $and $and$ls180.v:4391$642 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86151,21 +86147,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdw_sink_valid connect \B \main_sdphy_cmdw_pads_out_ready - connect \Y $and$ls180.v:4395$643_Y + connect \Y $and$ls180.v:4391$642_Y end - attribute \src "ls180.v:4415.53-4415.145" - cell $and $and$ls180.v:4415$646 + attribute \src "ls180.v:4411.53-4411.145" + cell $and $and$ls180.v:4411$645 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_pads_in_valid - connect \B $or$ls180.v:4415$645_Y - connect \Y $and$ls180.v:4415$646_Y + connect \B $or$ls180.v:4411$644_Y + connect \Y $and$ls180.v:4411$645_Y end - attribute \src "ls180.v:4434.52-4434.137" - cell $and $and$ls180.v:4434$649 + attribute \src "ls180.v:4430.52-4430.137" + cell $and $and$ls180.v:4430$648 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86173,10 +86169,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready - connect \Y $and$ls180.v:4434$649_Y + connect \Y $and$ls180.v:4430$648_Y end - attribute \src "ls180.v:4475.9-4475.68" - cell $and $and$ls180.v:4475$657 + attribute \src "ls180.v:4471.9-4471.68" + cell $and $and$ls180.v:4471$656 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86184,10 +86180,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_source_valid connect \B \main_sdphy_cmdr_source_ready - connect \Y $and$ls180.v:4475$657_Y + connect \Y $and$ls180.v:4471$656_Y end - attribute \src "ls180.v:4513.9-4513.68" - cell $and $and$ls180.v:4513$663 + attribute \src "ls180.v:4509.9-4509.68" + cell $and $and$ls180.v:4509$662 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86195,10 +86191,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_source_valid connect \B \main_sdphy_cmdr_source_ready - connect \Y $and$ls180.v:4513$663_Y + connect \Y $and$ls180.v:4509$662_Y end - attribute \src "ls180.v:4522.10-4522.69" - cell $and $and$ls180.v:4522$664 + attribute \src "ls180.v:4518.10-4518.69" + cell $and $and$ls180.v:4518$663 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86206,21 +86202,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_sink_valid connect \B \main_sdphy_cmdr_pads_out_ready - connect \Y $and$ls180.v:4522$664_Y + connect \Y $and$ls180.v:4518$663_Y end - attribute \src "ls180.v:4522.9-4522.93" - cell $and $and$ls180.v:4522$665 + attribute \src "ls180.v:4518.9-4518.93" + cell $and $and$ls180.v:4518$664 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4522$664_Y + connect \A $and$ls180.v:4518$663_Y connect \B \main_sdphy_cmdw_done - connect \Y $and$ls180.v:4522$665_Y + connect \Y $and$ls180.v:4518$664_Y end - attribute \src "ls180.v:4542.54-4542.117" - cell $and $and$ls180.v:4542$667 + attribute \src "ls180.v:4538.54-4538.117" + cell $and $and$ls180.v:4538$666 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86228,10 +86224,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_pads_in_valid connect \B \main_sdphy_dataw_crcr_run - connect \Y $and$ls180.v:4542$667_Y + connect \Y $and$ls180.v:4538$666_Y end - attribute \src "ls180.v:4561.53-4561.140" - cell $and $and$ls180.v:4561$670 + attribute \src "ls180.v:4557.53-4557.140" + cell $and $and$ls180.v:4557$669 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86239,10 +86235,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_sink_valid connect \B \main_sdphy_dataw_crcr_converter_sink_ready - connect \Y $and$ls180.v:4561$670_Y + connect \Y $and$ls180.v:4557$669_Y end - attribute \src "ls180.v:4658.9-4658.70" - cell $and $and$ls180.v:4658$680 + attribute \src "ls180.v:4654.9-4654.70" + cell $and $and$ls180.v:4654$679 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86250,10 +86246,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_sink_valid connect \B \main_sdphy_dataw_pads_out_ready - connect \Y $and$ls180.v:4658$680_Y + connect \Y $and$ls180.v:4654$679_Y end - attribute \src "ls180.v:4676.55-4676.120" - cell $and $and$ls180.v:4676$682 + attribute \src "ls180.v:4672.55-4672.120" + cell $and $and$ls180.v:4672$681 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86261,10 +86257,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_pads_in_valid connect \B \main_sdphy_datar_datar_run - connect \Y $and$ls180.v:4676$682_Y + connect \Y $and$ls180.v:4672$681_Y end - attribute \src "ls180.v:4695.54-4695.143" - cell $and $and$ls180.v:4695$685 + attribute \src "ls180.v:4691.54-4691.143" + cell $and $and$ls180.v:4691$684 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86272,10 +86268,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_sink_valid connect \B \main_sdphy_datar_datar_converter_sink_ready - connect \Y $and$ls180.v:4695$685_Y + connect \Y $and$ls180.v:4691$684_Y end - attribute \src "ls180.v:4777.9-4777.70" - cell $and $and$ls180.v:4777$700 + attribute \src "ls180.v:4773.9-4773.70" + cell $and $and$ls180.v:4773$699 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86283,10 +86279,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_source_valid connect \B \main_sdphy_datar_source_ready - connect \Y $and$ls180.v:4777$700_Y + connect \Y $and$ls180.v:4773$699_Y end - attribute \src "ls180.v:4784.9-4784.70" - cell $and $and$ls180.v:4784$701 + attribute \src "ls180.v:4780.9-4780.70" + cell $and $and$ls180.v:4780$700 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86294,10 +86290,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_sink_valid connect \B \main_sdphy_datar_pads_out_ready - connect \Y $and$ls180.v:4784$701_Y + connect \Y $and$ls180.v:4780$700_Y end - attribute \src "ls180.v:4865.48-4865.124" - cell $and $and$ls180.v:4865$824 + attribute \src "ls180.v:4861.48-4861.124" + cell $and $and$ls180.v:4861$823 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86305,21 +86301,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_sink_last connect \B \main_sdcore_crc16_inserter_sink_valid - connect \Y $and$ls180.v:4865$824_Y + connect \Y $and$ls180.v:4861$823_Y end - attribute \src "ls180.v:4865.47-4865.165" - cell $and $and$ls180.v:4865$825 + attribute \src "ls180.v:4861.47-4861.165" + cell $and $and$ls180.v:4861$824 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4865$824_Y + connect \A $and$ls180.v:4861$823_Y connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:4865$825_Y + connect \Y $and$ls180.v:4861$824_Y end - attribute \src "ls180.v:4866.50-4866.127" - cell $and $and$ls180.v:4866$826 + attribute \src "ls180.v:4862.50-4862.127" + cell $and $and$ls180.v:4862$825 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86327,10 +86323,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_sink_valid connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:4866$826_Y + connect \Y $and$ls180.v:4862$825_Y end - attribute \src "ls180.v:4868.48-4868.124" - cell $and $and$ls180.v:4868$827 + attribute \src "ls180.v:4864.48-4864.124" + cell $and $and$ls180.v:4864$826 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86338,21 +86334,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_sink_last connect \B \main_sdcore_crc16_inserter_sink_valid - connect \Y $and$ls180.v:4868$827_Y + connect \Y $and$ls180.v:4864$826_Y end - attribute \src "ls180.v:4868.47-4868.165" - cell $and $and$ls180.v:4868$828 + attribute \src "ls180.v:4864.47-4864.165" + cell $and $and$ls180.v:4864$827 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4868$827_Y + connect \A $and$ls180.v:4864$826_Y connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:4868$828_Y + connect \Y $and$ls180.v:4864$827_Y end - attribute \src "ls180.v:4869.50-4869.127" - cell $and $and$ls180.v:4869$829 + attribute \src "ls180.v:4865.50-4865.127" + cell $and $and$ls180.v:4865$828 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86360,10 +86356,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_sink_valid connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:4869$829_Y + connect \Y $and$ls180.v:4865$828_Y end - attribute \src "ls180.v:4871.48-4871.124" - cell $and $and$ls180.v:4871$830 + attribute \src "ls180.v:4867.48-4867.124" + cell $and $and$ls180.v:4867$829 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86371,21 +86367,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_sink_last connect \B \main_sdcore_crc16_inserter_sink_valid - connect \Y $and$ls180.v:4871$830_Y + connect \Y $and$ls180.v:4867$829_Y end - attribute \src "ls180.v:4871.47-4871.165" - cell $and $and$ls180.v:4871$831 + attribute \src "ls180.v:4867.47-4867.165" + cell $and $and$ls180.v:4867$830 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4871$830_Y + connect \A $and$ls180.v:4867$829_Y connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:4871$831_Y + connect \Y $and$ls180.v:4867$830_Y end - attribute \src "ls180.v:4872.50-4872.127" - cell $and $and$ls180.v:4872$832 + attribute \src "ls180.v:4868.50-4868.127" + cell $and $and$ls180.v:4868$831 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86393,10 +86389,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_sink_valid connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:4872$832_Y + connect \Y $and$ls180.v:4868$831_Y end - attribute \src "ls180.v:4874.48-4874.124" - cell $and $and$ls180.v:4874$833 + attribute \src "ls180.v:4870.48-4870.124" + cell $and $and$ls180.v:4870$832 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86404,21 +86400,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_sink_last connect \B \main_sdcore_crc16_inserter_sink_valid - connect \Y $and$ls180.v:4874$833_Y + connect \Y $and$ls180.v:4870$832_Y end - attribute \src "ls180.v:4874.47-4874.165" - cell $and $and$ls180.v:4874$834 + attribute \src "ls180.v:4870.47-4870.165" + cell $and $and$ls180.v:4870$833 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4874$833_Y + connect \A $and$ls180.v:4870$832_Y connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:4874$834_Y + connect \Y $and$ls180.v:4870$833_Y end - attribute \src "ls180.v:4875.50-4875.127" - cell $and $and$ls180.v:4875$835 + attribute \src "ls180.v:4871.50-4871.127" + cell $and $and$ls180.v:4871$834 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86426,10 +86422,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_sink_valid connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:4875$835_Y + connect \Y $and$ls180.v:4871$834_Y end - attribute \src "ls180.v:4988.10-4988.86" - cell $and $and$ls180.v:4988$884 + attribute \src "ls180.v:4984.10-4984.86" + cell $and $and$ls180.v:4984$883 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86437,54 +86433,54 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_sink_valid connect \B \main_sdcore_crc16_inserter_sink_last - connect \Y $and$ls180.v:4988$884_Y + connect \Y $and$ls180.v:4984$883_Y end - attribute \src "ls180.v:4988.9-4988.127" - cell $and $and$ls180.v:4988$885 + attribute \src "ls180.v:4984.9-4984.127" + cell $and $and$ls180.v:4984$884 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4988$884_Y + connect \A $and$ls180.v:4984$883_Y connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:4988$885_Y + connect \Y $and$ls180.v:4984$884_Y end - attribute \src "ls180.v:4998.9-4998.152" - cell $and $and$ls180.v:4998$889 + attribute \src "ls180.v:4994.9-4994.152" + cell $and $and$ls180.v:4994$888 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4998$887_Y - connect \B $eq$ls180.v:4998$888_Y - connect \Y $and$ls180.v:4998$889_Y + connect \A $eq$ls180.v:4994$886_Y + connect \B $eq$ls180.v:4994$887_Y + connect \Y $and$ls180.v:4994$888_Y end - attribute \src "ls180.v:4998.8-4998.226" - cell $and $and$ls180.v:4998$891 + attribute \src "ls180.v:4994.8-4994.226" + cell $and $and$ls180.v:4994$890 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4998$889_Y - connect \B $eq$ls180.v:4998$890_Y - connect \Y $and$ls180.v:4998$891_Y + connect \A $and$ls180.v:4994$888_Y + connect \B $eq$ls180.v:4994$889_Y + connect \Y $and$ls180.v:4994$890_Y end - attribute \src "ls180.v:4998.7-4998.300" - cell $and $and$ls180.v:4998$893 + attribute \src "ls180.v:4994.7-4994.300" + cell $and $and$ls180.v:4994$892 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4998$891_Y - connect \B $eq$ls180.v:4998$892_Y - connect \Y $and$ls180.v:4998$893_Y + connect \A $and$ls180.v:4994$890_Y + connect \B $eq$ls180.v:4994$891_Y + connect \Y $and$ls180.v:4994$892_Y end - attribute \src "ls180.v:5003.49-5003.124" - cell $and $and$ls180.v:5003$894 + attribute \src "ls180.v:4999.49-4999.124" + cell $and $and$ls180.v:4999$893 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86492,10 +86488,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:5003$894_Y + connect \Y $and$ls180.v:4999$893_Y end - attribute \src "ls180.v:5013.49-5013.124" - cell $and $and$ls180.v:5013$897 + attribute \src "ls180.v:5009.49-5009.124" + cell $and $and$ls180.v:5009$896 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86503,10 +86499,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:5013$897_Y + connect \Y $and$ls180.v:5009$896_Y end - attribute \src "ls180.v:5023.49-5023.124" - cell $and $and$ls180.v:5023$900 + attribute \src "ls180.v:5019.49-5019.124" + cell $and $and$ls180.v:5019$899 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86514,10 +86510,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:5023$900_Y + connect \Y $and$ls180.v:5019$899_Y end - attribute \src "ls180.v:5033.49-5033.124" - cell $and $and$ls180.v:5033$903 + attribute \src "ls180.v:5029.49-5029.124" + cell $and $and$ls180.v:5029$902 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86525,21 +86521,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:5033$903_Y + connect \Y $and$ls180.v:5029$902_Y end - attribute \src "ls180.v:5045.7-5045.84" - cell $and $and$ls180.v:5045$908 + attribute \src "ls180.v:5041.7-5041.84" + cell $and $and$ls180.v:5041$907 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid - connect \B $gt$ls180.v:5045$907_Y - connect \Y $and$ls180.v:5045$908_Y + connect \B $gt$ls180.v:5041$906_Y + connect \Y $and$ls180.v:5041$907_Y end - attribute \src "ls180.v:5163.9-5163.64" - cell $and $and$ls180.v:5163$957 + attribute \src "ls180.v:5159.9-5159.64" + cell $and $and$ls180.v:5159$956 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86547,10 +86543,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdw_sink_valid connect \B \main_sdphy_cmdw_sink_ready - connect \Y $and$ls180.v:5163$957_Y + connect \Y $and$ls180.v:5159$956_Y end - attribute \src "ls180.v:5215.10-5215.66" - cell $and $and$ls180.v:5215$966 + attribute \src "ls180.v:5211.10-5211.66" + cell $and $and$ls180.v:5211$965 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86558,21 +86554,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_sink_valid connect \B \main_sdphy_dataw_sink_last - connect \Y $and$ls180.v:5215$966_Y + connect \Y $and$ls180.v:5211$965_Y end - attribute \src "ls180.v:5215.9-5215.97" - cell $and $and$ls180.v:5215$967 + attribute \src "ls180.v:5211.9-5211.97" + cell $and $and$ls180.v:5211$966 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5215$966_Y + connect \A $and$ls180.v:5211$965_Y connect \B \main_sdphy_dataw_sink_ready - connect \Y $and$ls180.v:5215$967_Y + connect \Y $and$ls180.v:5211$966_Y end - attribute \src "ls180.v:5241.11-5241.71" - cell $and $and$ls180.v:5241$975 + attribute \src "ls180.v:5237.11-5237.71" + cell $and $and$ls180.v:5237$974 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86580,21 +86576,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_source_last connect \B \main_sdphy_datar_source_ready - connect \Y $and$ls180.v:5241$975_Y + connect \Y $and$ls180.v:5237$974_Y end - attribute \src "ls180.v:5325.43-5325.152" - cell $and $and$ls180.v:5325$983 + attribute \src "ls180.v:5321.43-5321.152" + cell $and $and$ls180.v:5321$982 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_syncfifo_we - connect \B $or$ls180.v:5325$982_Y - connect \Y $and$ls180.v:5325$983_Y + connect \B $or$ls180.v:5321$981_Y + connect \Y $and$ls180.v:5321$982_Y end - attribute \src "ls180.v:5326.41-5326.116" - cell $and $and$ls180.v:5326$984 + attribute \src "ls180.v:5322.41-5322.116" + cell $and $and$ls180.v:5322$983 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86602,10 +86598,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_syncfifo_readable connect \B \main_sdblock2mem_fifo_syncfifo_re - connect \Y $and$ls180.v:5326$984_Y + connect \Y $and$ls180.v:5322$983_Y end - attribute \src "ls180.v:5338.48-5338.125" - cell $and $and$ls180.v:5338$989 + attribute \src "ls180.v:5334.48-5334.125" + cell $and $and$ls180.v:5334$988 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86613,10 +86609,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_sink_valid connect \B \main_sdblock2mem_converter_sink_ready - connect \Y $and$ls180.v:5338$989_Y + connect \Y $and$ls180.v:5334$988_Y end - attribute \src "ls180.v:5365.9-5365.102" - cell $and $and$ls180.v:5365$993 + attribute \src "ls180.v:5361.9-5361.102" + cell $and $and$ls180.v:5361$992 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86624,10 +86620,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_wishbonedmawriter_sink_valid connect \B \main_sdblock2mem_wishbonedmawriter_sink_ready - connect \Y $and$ls180.v:5365$993_Y + connect \Y $and$ls180.v:5361$992_Y end - attribute \src "ls180.v:5438.9-5438.58" - cell $and $and$ls180.v:5438$999 + attribute \src "ls180.v:5434.9-5434.58" + cell $and $and$ls180.v:5434$998 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86635,10 +86631,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface1_bus_stb connect \B \main_interface1_bus_ack - connect \Y $and$ls180.v:5438$999_Y + connect \Y $and$ls180.v:5434$998_Y end - attribute \src "ls180.v:5491.51-5491.123" - cell $and $and$ls180.v:5491$1007 + attribute \src "ls180.v:5487.51-5487.123" + cell $and $and$ls180.v:5487$1006 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86646,10 +86642,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_converter_sink_first connect \B \main_sdmem2block_converter_first - connect \Y $and$ls180.v:5491$1007_Y + connect \Y $and$ls180.v:5487$1006_Y end - attribute \src "ls180.v:5492.50-5492.120" - cell $and $and$ls180.v:5492$1008 + attribute \src "ls180.v:5488.50-5488.120" + cell $and $and$ls180.v:5488$1007 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86657,10 +86653,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_converter_sink_last connect \B \main_sdmem2block_converter_last - connect \Y $and$ls180.v:5492$1008_Y + connect \Y $and$ls180.v:5488$1007_Y end - attribute \src "ls180.v:5493.49-5493.122" - cell $and $and$ls180.v:5493$1009 + attribute \src "ls180.v:5489.49-5489.122" + cell $and $and$ls180.v:5489$1008 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86668,21 +86664,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_converter_last connect \B \main_sdmem2block_converter_source_ready - connect \Y $and$ls180.v:5493$1009_Y + connect \Y $and$ls180.v:5489$1008_Y end - attribute \src "ls180.v:5533.43-5533.152" - cell $and $and$ls180.v:5533$1014 + attribute \src "ls180.v:5529.43-5529.152" + cell $and $and$ls180.v:5529$1013 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_syncfifo_we - connect \B $or$ls180.v:5533$1013_Y - connect \Y $and$ls180.v:5533$1014_Y + connect \B $or$ls180.v:5529$1012_Y + connect \Y $and$ls180.v:5529$1013_Y end - attribute \src "ls180.v:5534.41-5534.116" - cell $and $and$ls180.v:5534$1015 + attribute \src "ls180.v:5530.41-5530.116" + cell $and $and$ls180.v:5530$1014 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86690,10 +86686,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_syncfifo_readable connect \B \main_sdmem2block_fifo_syncfifo_re - connect \Y $and$ls180.v:5534$1015_Y + connect \Y $and$ls180.v:5530$1014_Y end - attribute \src "ls180.v:5625.9-5625.76" - cell $and $and$ls180.v:5625$1027 + attribute \src "ls180.v:5621.9-5621.76" + cell $and $and$ls180.v:5621$1026 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86701,131 +86697,131 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_libresocsim_wishbone_cyc connect \B \builder_libresocsim_wishbone_stb - connect \Y $and$ls180.v:5625$1027_Y + connect \Y $and$ls180.v:5621$1026_Y end - attribute \src "ls180.v:5628.44-5628.120" - cell $and $and$ls180.v:5628$1029 + attribute \src "ls180.v:5624.44-5624.120" + cell $and $and$ls180.v:5624$1028 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_libresocsim_wishbone_we - connect \B $ne$ls180.v:5628$1028_Y - connect \Y $and$ls180.v:5628$1029_Y + connect \B $ne$ls180.v:5624$1027_Y + connect \Y $and$ls180.v:5624$1028_Y end - attribute \src "ls180.v:5648.63-5648.107" - cell $and $and$ls180.v:5648$1031 + attribute \src "ls180.v:5644.63-5644.107" + cell $and $and$ls180.v:5644$1030 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_ack - connect \B $eq$ls180.v:5648$1030_Y - connect \Y $and$ls180.v:5648$1031_Y + connect \B $eq$ls180.v:5644$1029_Y + connect \Y $and$ls180.v:5644$1030_Y end - attribute \src "ls180.v:5649.63-5649.107" - cell $and $and$ls180.v:5649$1033 + attribute \src "ls180.v:5645.63-5645.107" + cell $and $and$ls180.v:5645$1032 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_ack - connect \B $eq$ls180.v:5649$1032_Y - connect \Y $and$ls180.v:5649$1033_Y + connect \B $eq$ls180.v:5645$1031_Y + connect \Y $and$ls180.v:5645$1032_Y end - attribute \src "ls180.v:5650.63-5650.107" - cell $and $and$ls180.v:5650$1035 + attribute \src "ls180.v:5646.63-5646.107" + cell $and $and$ls180.v:5646$1034 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_ack - connect \B $eq$ls180.v:5650$1034_Y - connect \Y $and$ls180.v:5650$1035_Y + connect \B $eq$ls180.v:5646$1033_Y + connect \Y $and$ls180.v:5646$1034_Y end - attribute \src "ls180.v:5651.35-5651.79" - cell $and $and$ls180.v:5651$1037 + attribute \src "ls180.v:5647.35-5647.79" + cell $and $and$ls180.v:5647$1036 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_ack - connect \B $eq$ls180.v:5651$1036_Y - connect \Y $and$ls180.v:5651$1037_Y + connect \B $eq$ls180.v:5647$1035_Y + connect \Y $and$ls180.v:5647$1036_Y end - attribute \src "ls180.v:5652.35-5652.79" - cell $and $and$ls180.v:5652$1039 + attribute \src "ls180.v:5648.35-5648.79" + cell $and $and$ls180.v:5648$1038 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_ack - connect \B $eq$ls180.v:5652$1038_Y - connect \Y $and$ls180.v:5652$1039_Y + connect \B $eq$ls180.v:5648$1037_Y + connect \Y $and$ls180.v:5648$1038_Y end - attribute \src "ls180.v:5653.63-5653.107" - cell $and $and$ls180.v:5653$1041 + attribute \src "ls180.v:5649.63-5649.107" + cell $and $and$ls180.v:5649$1040 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_err - connect \B $eq$ls180.v:5653$1040_Y - connect \Y $and$ls180.v:5653$1041_Y + connect \B $eq$ls180.v:5649$1039_Y + connect \Y $and$ls180.v:5649$1040_Y end - attribute \src "ls180.v:5654.63-5654.107" - cell $and $and$ls180.v:5654$1043 + attribute \src "ls180.v:5650.63-5650.107" + cell $and $and$ls180.v:5650$1042 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_err - connect \B $eq$ls180.v:5654$1042_Y - connect \Y $and$ls180.v:5654$1043_Y + connect \B $eq$ls180.v:5650$1041_Y + connect \Y $and$ls180.v:5650$1042_Y end - attribute \src "ls180.v:5655.63-5655.107" - cell $and $and$ls180.v:5655$1045 + attribute \src "ls180.v:5651.63-5651.107" + cell $and $and$ls180.v:5651$1044 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_err - connect \B $eq$ls180.v:5655$1044_Y - connect \Y $and$ls180.v:5655$1045_Y + connect \B $eq$ls180.v:5651$1043_Y + connect \Y $and$ls180.v:5651$1044_Y end - attribute \src "ls180.v:5656.35-5656.79" - cell $and $and$ls180.v:5656$1047 + attribute \src "ls180.v:5652.35-5652.79" + cell $and $and$ls180.v:5652$1046 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_err - connect \B $eq$ls180.v:5656$1046_Y - connect \Y $and$ls180.v:5656$1047_Y + connect \B $eq$ls180.v:5652$1045_Y + connect \Y $and$ls180.v:5652$1046_Y end - attribute \src "ls180.v:5657.35-5657.79" - cell $and $and$ls180.v:5657$1049 + attribute \src "ls180.v:5653.35-5653.79" + cell $and $and$ls180.v:5653$1048 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_err - connect \B $eq$ls180.v:5657$1048_Y - connect \Y $and$ls180.v:5657$1049_Y + connect \B $eq$ls180.v:5653$1047_Y + connect \Y $and$ls180.v:5653$1048_Y end - attribute \src "ls180.v:5702.40-5702.81" - cell $and $and$ls180.v:5702$1056 + attribute \src "ls180.v:5698.40-5698.81" + cell $and $and$ls180.v:5698$1055 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86833,10 +86829,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_cyc connect \B \builder_slave_sel [0] - connect \Y $and$ls180.v:5702$1056_Y + connect \Y $and$ls180.v:5698$1055_Y end - attribute \src "ls180.v:5703.50-5703.91" - cell $and $and$ls180.v:5703$1057 + attribute \src "ls180.v:5699.50-5699.91" + cell $and $and$ls180.v:5699$1056 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86844,10 +86840,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_cyc connect \B \builder_slave_sel [1] - connect \Y $and$ls180.v:5703$1057_Y + connect \Y $and$ls180.v:5699$1056_Y end - attribute \src "ls180.v:5704.50-5704.91" - cell $and $and$ls180.v:5704$1058 + attribute \src "ls180.v:5700.50-5700.91" + cell $and $and$ls180.v:5700$1057 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86855,10 +86851,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_cyc connect \B \builder_slave_sel [2] - connect \Y $and$ls180.v:5704$1058_Y + connect \Y $and$ls180.v:5700$1057_Y end - attribute \src "ls180.v:5705.29-5705.70" - cell $and $and$ls180.v:5705$1059 + attribute \src "ls180.v:5701.29-5701.70" + cell $and $and$ls180.v:5701$1058 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86866,10 +86862,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_cyc connect \B \builder_slave_sel [3] - connect \Y $and$ls180.v:5705$1059_Y + connect \Y $and$ls180.v:5701$1058_Y end - attribute \src "ls180.v:5706.44-5706.85" - cell $and $and$ls180.v:5706$1060 + attribute \src "ls180.v:5702.44-5702.85" + cell $and $and$ls180.v:5702$1059 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86877,10 +86873,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_cyc connect \B \builder_slave_sel [4] - connect \Y $and$ls180.v:5706$1060_Y + connect \Y $and$ls180.v:5702$1059_Y end - attribute \src "ls180.v:5708.25-5708.64" - cell $and $and$ls180.v:5708$1065 + attribute \src "ls180.v:5704.25-5704.64" + cell $and $and$ls180.v:5704$1064 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86888,21 +86884,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_stb connect \B \builder_shared_cyc - connect \Y $and$ls180.v:5708$1065_Y + connect \Y $and$ls180.v:5704$1064_Y end - attribute \src "ls180.v:5708.24-5708.89" - cell $and $and$ls180.v:5708$1067 + attribute \src "ls180.v:5704.24-5704.89" + cell $and $and$ls180.v:5704$1066 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5708$1065_Y - connect \B $not$ls180.v:5708$1066_Y - connect \Y $and$ls180.v:5708$1067_Y + connect \A $and$ls180.v:5704$1064_Y + connect \B $not$ls180.v:5704$1065_Y + connect \Y $and$ls180.v:5704$1066_Y end - attribute \src "ls180.v:5714.31-5714.92" - cell $and $and$ls180.v:5714$1073 + attribute \src "ls180.v:5710.31-5710.92" + cell $and $and$ls180.v:5710$1072 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -86910,10 +86906,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A { \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] } connect \B \main_libresocsim_ram_bus_dat_r - connect \Y $and$ls180.v:5714$1073_Y + connect \Y $and$ls180.v:5710$1072_Y end - attribute \src "ls180.v:5714.97-5714.168" - cell $and $and$ls180.v:5714$1074 + attribute \src "ls180.v:5710.97-5710.168" + cell $and $and$ls180.v:5710$1073 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -86921,10 +86917,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A { \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] } connect \B \main_libresocsim_libresoc_xics_icp_dat_r - connect \Y $and$ls180.v:5714$1074_Y + connect \Y $and$ls180.v:5710$1073_Y end - attribute \src "ls180.v:5714.174-5714.245" - cell $and $and$ls180.v:5714$1076 + attribute \src "ls180.v:5710.174-5710.245" + cell $and $and$ls180.v:5710$1075 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -86932,10 +86928,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A { \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] } connect \B \main_libresocsim_libresoc_xics_ics_dat_r - connect \Y $and$ls180.v:5714$1076_Y + connect \Y $and$ls180.v:5710$1075_Y end - attribute \src "ls180.v:5714.251-5714.301" - cell $and $and$ls180.v:5714$1078 + attribute \src "ls180.v:5710.251-5710.301" + cell $and $and$ls180.v:5710$1077 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -86943,10 +86939,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A { \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] } connect \B \main_wb_sdram_dat_r - connect \Y $and$ls180.v:5714$1078_Y + connect \Y $and$ls180.v:5710$1077_Y end - attribute \src "ls180.v:5714.307-5714.372" - cell $and $and$ls180.v:5714$1080 + attribute \src "ls180.v:5710.307-5710.372" + cell $and $and$ls180.v:5710$1079 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -86954,10 +86950,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A { \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] } connect \B \builder_libresocsim_wishbone_dat_r - connect \Y $and$ls180.v:5714$1080_Y + connect \Y $and$ls180.v:5710$1079_Y end - attribute \src "ls180.v:5724.39-5724.92" - cell $and $and$ls180.v:5724$1084 + attribute \src "ls180.v:5720.39-5720.92" + cell $and $and$ls180.v:5720$1083 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86965,43 +86961,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5724$1084_Y + connect \Y $and$ls180.v:5720$1083_Y end - attribute \src "ls180.v:5724.38-5724.142" - cell $and $and$ls180.v:5724$1086 + attribute \src "ls180.v:5720.38-5720.142" + cell $and $and$ls180.v:5720$1085 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5724$1084_Y - connect \B $eq$ls180.v:5724$1085_Y - connect \Y $and$ls180.v:5724$1086_Y + connect \A $and$ls180.v:5720$1083_Y + connect \B $eq$ls180.v:5720$1084_Y + connect \Y $and$ls180.v:5720$1085_Y end - attribute \src "ls180.v:5725.39-5725.95" - cell $and $and$ls180.v:5725$1088 + attribute \src "ls180.v:5721.39-5721.95" + cell $and $and$ls180.v:5721$1087 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5725$1087_Y - connect \Y $and$ls180.v:5725$1088_Y + connect \B $not$ls180.v:5721$1086_Y + connect \Y $and$ls180.v:5721$1087_Y end - attribute \src "ls180.v:5725.38-5725.145" - cell $and $and$ls180.v:5725$1090 + attribute \src "ls180.v:5721.38-5721.145" + cell $and $and$ls180.v:5721$1089 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5725$1088_Y - connect \B $eq$ls180.v:5725$1089_Y - connect \Y $and$ls180.v:5725$1090_Y + connect \A $and$ls180.v:5721$1087_Y + connect \B $eq$ls180.v:5721$1088_Y + connect \Y $and$ls180.v:5721$1089_Y end - attribute \src "ls180.v:5727.41-5727.94" - cell $and $and$ls180.v:5727$1091 + attribute \src "ls180.v:5723.41-5723.94" + cell $and $and$ls180.v:5723$1090 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87009,43 +87005,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5727$1091_Y + connect \Y $and$ls180.v:5723$1090_Y end - attribute \src "ls180.v:5727.40-5727.144" - cell $and $and$ls180.v:5727$1093 + attribute \src "ls180.v:5723.40-5723.144" + cell $and $and$ls180.v:5723$1092 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5727$1091_Y - connect \B $eq$ls180.v:5727$1092_Y - connect \Y $and$ls180.v:5727$1093_Y + connect \A $and$ls180.v:5723$1090_Y + connect \B $eq$ls180.v:5723$1091_Y + connect \Y $and$ls180.v:5723$1092_Y end - attribute \src "ls180.v:5728.41-5728.97" - cell $and $and$ls180.v:5728$1095 + attribute \src "ls180.v:5724.41-5724.97" + cell $and $and$ls180.v:5724$1094 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5728$1094_Y - connect \Y $and$ls180.v:5728$1095_Y + connect \B $not$ls180.v:5724$1093_Y + connect \Y $and$ls180.v:5724$1094_Y end - attribute \src "ls180.v:5728.40-5728.147" - cell $and $and$ls180.v:5728$1097 + attribute \src "ls180.v:5724.40-5724.147" + cell $and $and$ls180.v:5724$1096 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5728$1095_Y - connect \B $eq$ls180.v:5728$1096_Y - connect \Y $and$ls180.v:5728$1097_Y + connect \A $and$ls180.v:5724$1094_Y + connect \B $eq$ls180.v:5724$1095_Y + connect \Y $and$ls180.v:5724$1096_Y end - attribute \src "ls180.v:5730.41-5730.94" - cell $and $and$ls180.v:5730$1098 + attribute \src "ls180.v:5726.41-5726.94" + cell $and $and$ls180.v:5726$1097 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87053,43 +87049,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5730$1098_Y + connect \Y $and$ls180.v:5726$1097_Y end - attribute \src "ls180.v:5730.40-5730.144" - cell $and $and$ls180.v:5730$1100 + attribute \src "ls180.v:5726.40-5726.144" + cell $and $and$ls180.v:5726$1099 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5730$1098_Y - connect \B $eq$ls180.v:5730$1099_Y - connect \Y $and$ls180.v:5730$1100_Y + connect \A $and$ls180.v:5726$1097_Y + connect \B $eq$ls180.v:5726$1098_Y + connect \Y $and$ls180.v:5726$1099_Y end - attribute \src "ls180.v:5731.41-5731.97" - cell $and $and$ls180.v:5731$1102 + attribute \src "ls180.v:5727.41-5727.97" + cell $and $and$ls180.v:5727$1101 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5731$1101_Y - connect \Y $and$ls180.v:5731$1102_Y + connect \B $not$ls180.v:5727$1100_Y + connect \Y $and$ls180.v:5727$1101_Y end - attribute \src "ls180.v:5731.40-5731.147" - cell $and $and$ls180.v:5731$1104 + attribute \src "ls180.v:5727.40-5727.147" + cell $and $and$ls180.v:5727$1103 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5731$1102_Y - connect \B $eq$ls180.v:5731$1103_Y - connect \Y $and$ls180.v:5731$1104_Y + connect \A $and$ls180.v:5727$1101_Y + connect \B $eq$ls180.v:5727$1102_Y + connect \Y $and$ls180.v:5727$1103_Y end - attribute \src "ls180.v:5733.41-5733.94" - cell $and $and$ls180.v:5733$1105 + attribute \src "ls180.v:5729.41-5729.94" + cell $and $and$ls180.v:5729$1104 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87097,43 +87093,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5733$1105_Y + connect \Y $and$ls180.v:5729$1104_Y end - attribute \src "ls180.v:5733.40-5733.144" - cell $and $and$ls180.v:5733$1107 + attribute \src "ls180.v:5729.40-5729.144" + cell $and $and$ls180.v:5729$1106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5733$1105_Y - connect \B $eq$ls180.v:5733$1106_Y - connect \Y $and$ls180.v:5733$1107_Y + connect \A $and$ls180.v:5729$1104_Y + connect \B $eq$ls180.v:5729$1105_Y + connect \Y $and$ls180.v:5729$1106_Y end - attribute \src "ls180.v:5734.41-5734.97" - cell $and $and$ls180.v:5734$1109 + attribute \src "ls180.v:5730.41-5730.97" + cell $and $and$ls180.v:5730$1108 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5734$1108_Y - connect \Y $and$ls180.v:5734$1109_Y + connect \B $not$ls180.v:5730$1107_Y + connect \Y $and$ls180.v:5730$1108_Y end - attribute \src "ls180.v:5734.40-5734.147" - cell $and $and$ls180.v:5734$1111 + attribute \src "ls180.v:5730.40-5730.147" + cell $and $and$ls180.v:5730$1110 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5734$1109_Y - connect \B $eq$ls180.v:5734$1110_Y - connect \Y $and$ls180.v:5734$1111_Y + connect \A $and$ls180.v:5730$1108_Y + connect \B $eq$ls180.v:5730$1109_Y + connect \Y $and$ls180.v:5730$1110_Y end - attribute \src "ls180.v:5736.41-5736.94" - cell $and $and$ls180.v:5736$1112 + attribute \src "ls180.v:5732.41-5732.94" + cell $and $and$ls180.v:5732$1111 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87141,43 +87137,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5736$1112_Y + connect \Y $and$ls180.v:5732$1111_Y end - attribute \src "ls180.v:5736.40-5736.144" - cell $and $and$ls180.v:5736$1114 + attribute \src "ls180.v:5732.40-5732.144" + cell $and $and$ls180.v:5732$1113 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5736$1112_Y - connect \B $eq$ls180.v:5736$1113_Y - connect \Y $and$ls180.v:5736$1114_Y + connect \A $and$ls180.v:5732$1111_Y + connect \B $eq$ls180.v:5732$1112_Y + connect \Y $and$ls180.v:5732$1113_Y end - attribute \src "ls180.v:5737.41-5737.97" - cell $and $and$ls180.v:5737$1116 + attribute \src "ls180.v:5733.41-5733.97" + cell $and $and$ls180.v:5733$1115 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5737$1115_Y - connect \Y $and$ls180.v:5737$1116_Y + connect \B $not$ls180.v:5733$1114_Y + connect \Y $and$ls180.v:5733$1115_Y end - attribute \src "ls180.v:5737.40-5737.147" - cell $and $and$ls180.v:5737$1118 + attribute \src "ls180.v:5733.40-5733.147" + cell $and $and$ls180.v:5733$1117 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5737$1116_Y - connect \B $eq$ls180.v:5737$1117_Y - connect \Y $and$ls180.v:5737$1118_Y + connect \A $and$ls180.v:5733$1115_Y + connect \B $eq$ls180.v:5733$1116_Y + connect \Y $and$ls180.v:5733$1117_Y end - attribute \src "ls180.v:5739.44-5739.97" - cell $and $and$ls180.v:5739$1119 + attribute \src "ls180.v:5735.44-5735.97" + cell $and $and$ls180.v:5735$1118 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87185,43 +87181,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5739$1119_Y + connect \Y $and$ls180.v:5735$1118_Y end - attribute \src "ls180.v:5739.43-5739.147" - cell $and $and$ls180.v:5739$1121 + attribute \src "ls180.v:5735.43-5735.147" + cell $and $and$ls180.v:5735$1120 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5739$1119_Y - connect \B $eq$ls180.v:5739$1120_Y - connect \Y $and$ls180.v:5739$1121_Y + connect \A $and$ls180.v:5735$1118_Y + connect \B $eq$ls180.v:5735$1119_Y + connect \Y $and$ls180.v:5735$1120_Y end - attribute \src "ls180.v:5740.44-5740.100" - cell $and $and$ls180.v:5740$1123 + attribute \src "ls180.v:5736.44-5736.100" + cell $and $and$ls180.v:5736$1122 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5740$1122_Y - connect \Y $and$ls180.v:5740$1123_Y + connect \B $not$ls180.v:5736$1121_Y + connect \Y $and$ls180.v:5736$1122_Y end - attribute \src "ls180.v:5740.43-5740.150" - cell $and $and$ls180.v:5740$1125 + attribute \src "ls180.v:5736.43-5736.150" + cell $and $and$ls180.v:5736$1124 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5740$1123_Y - connect \B $eq$ls180.v:5740$1124_Y - connect \Y $and$ls180.v:5740$1125_Y + connect \A $and$ls180.v:5736$1122_Y + connect \B $eq$ls180.v:5736$1123_Y + connect \Y $and$ls180.v:5736$1124_Y end - attribute \src "ls180.v:5742.44-5742.97" - cell $and $and$ls180.v:5742$1126 + attribute \src "ls180.v:5738.44-5738.97" + cell $and $and$ls180.v:5738$1125 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87229,43 +87225,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5742$1126_Y + connect \Y $and$ls180.v:5738$1125_Y end - attribute \src "ls180.v:5742.43-5742.147" - cell $and $and$ls180.v:5742$1128 + attribute \src "ls180.v:5738.43-5738.147" + cell $and $and$ls180.v:5738$1127 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5742$1126_Y - connect \B $eq$ls180.v:5742$1127_Y - connect \Y $and$ls180.v:5742$1128_Y + connect \A $and$ls180.v:5738$1125_Y + connect \B $eq$ls180.v:5738$1126_Y + connect \Y $and$ls180.v:5738$1127_Y end - attribute \src "ls180.v:5743.44-5743.100" - cell $and $and$ls180.v:5743$1130 + attribute \src "ls180.v:5739.44-5739.100" + cell $and $and$ls180.v:5739$1129 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5743$1129_Y - connect \Y $and$ls180.v:5743$1130_Y + connect \B $not$ls180.v:5739$1128_Y + connect \Y $and$ls180.v:5739$1129_Y end - attribute \src "ls180.v:5743.43-5743.150" - cell $and $and$ls180.v:5743$1132 + attribute \src "ls180.v:5739.43-5739.150" + cell $and $and$ls180.v:5739$1131 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5743$1130_Y - connect \B $eq$ls180.v:5743$1131_Y - connect \Y $and$ls180.v:5743$1132_Y + connect \A $and$ls180.v:5739$1129_Y + connect \B $eq$ls180.v:5739$1130_Y + connect \Y $and$ls180.v:5739$1131_Y end - attribute \src "ls180.v:5745.44-5745.97" - cell $and $and$ls180.v:5745$1133 + attribute \src "ls180.v:5741.44-5741.97" + cell $and $and$ls180.v:5741$1132 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87273,43 +87269,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5745$1133_Y + connect \Y $and$ls180.v:5741$1132_Y end - attribute \src "ls180.v:5745.43-5745.147" - cell $and $and$ls180.v:5745$1135 + attribute \src "ls180.v:5741.43-5741.147" + cell $and $and$ls180.v:5741$1134 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5745$1133_Y - connect \B $eq$ls180.v:5745$1134_Y - connect \Y $and$ls180.v:5745$1135_Y + connect \A $and$ls180.v:5741$1132_Y + connect \B $eq$ls180.v:5741$1133_Y + connect \Y $and$ls180.v:5741$1134_Y end - attribute \src "ls180.v:5746.44-5746.100" - cell $and $and$ls180.v:5746$1137 + attribute \src "ls180.v:5742.44-5742.100" + cell $and $and$ls180.v:5742$1136 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5746$1136_Y - connect \Y $and$ls180.v:5746$1137_Y + connect \B $not$ls180.v:5742$1135_Y + connect \Y $and$ls180.v:5742$1136_Y end - attribute \src "ls180.v:5746.43-5746.150" - cell $and $and$ls180.v:5746$1139 + attribute \src "ls180.v:5742.43-5742.150" + cell $and $and$ls180.v:5742$1138 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5746$1137_Y - connect \B $eq$ls180.v:5746$1138_Y - connect \Y $and$ls180.v:5746$1139_Y + connect \A $and$ls180.v:5742$1136_Y + connect \B $eq$ls180.v:5742$1137_Y + connect \Y $and$ls180.v:5742$1138_Y end - attribute \src "ls180.v:5748.44-5748.97" - cell $and $and$ls180.v:5748$1140 + attribute \src "ls180.v:5744.44-5744.97" + cell $and $and$ls180.v:5744$1139 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87317,43 +87313,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5748$1140_Y + connect \Y $and$ls180.v:5744$1139_Y end - attribute \src "ls180.v:5748.43-5748.147" - cell $and $and$ls180.v:5748$1142 + attribute \src "ls180.v:5744.43-5744.147" + cell $and $and$ls180.v:5744$1141 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5748$1140_Y - connect \B $eq$ls180.v:5748$1141_Y - connect \Y $and$ls180.v:5748$1142_Y + connect \A $and$ls180.v:5744$1139_Y + connect \B $eq$ls180.v:5744$1140_Y + connect \Y $and$ls180.v:5744$1141_Y end - attribute \src "ls180.v:5749.44-5749.100" - cell $and $and$ls180.v:5749$1144 + attribute \src "ls180.v:5745.44-5745.100" + cell $and $and$ls180.v:5745$1143 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5749$1143_Y - connect \Y $and$ls180.v:5749$1144_Y + connect \B $not$ls180.v:5745$1142_Y + connect \Y $and$ls180.v:5745$1143_Y end - attribute \src "ls180.v:5749.43-5749.150" - cell $and $and$ls180.v:5749$1146 + attribute \src "ls180.v:5745.43-5745.150" + cell $and $and$ls180.v:5745$1145 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5749$1144_Y - connect \B $eq$ls180.v:5749$1145_Y - connect \Y $and$ls180.v:5749$1146_Y + connect \A $and$ls180.v:5745$1143_Y + connect \B $eq$ls180.v:5745$1144_Y + connect \Y $and$ls180.v:5745$1145_Y end - attribute \src "ls180.v:5762.36-5762.89" - cell $and $and$ls180.v:5762$1148 + attribute \src "ls180.v:5758.36-5758.89" + cell $and $and$ls180.v:5758$1147 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87361,43 +87357,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:5762$1148_Y + connect \Y $and$ls180.v:5758$1147_Y end - attribute \src "ls180.v:5762.35-5762.139" - cell $and $and$ls180.v:5762$1150 + attribute \src "ls180.v:5758.35-5758.139" + cell $and $and$ls180.v:5758$1149 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5762$1148_Y - connect \B $eq$ls180.v:5762$1149_Y - connect \Y $and$ls180.v:5762$1150_Y + connect \A $and$ls180.v:5758$1147_Y + connect \B $eq$ls180.v:5758$1148_Y + connect \Y $and$ls180.v:5758$1149_Y end - attribute \src "ls180.v:5763.36-5763.92" - cell $and $and$ls180.v:5763$1152 + attribute \src "ls180.v:5759.36-5759.92" + cell $and $and$ls180.v:5759$1151 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:5763$1151_Y - connect \Y $and$ls180.v:5763$1152_Y + connect \B $not$ls180.v:5759$1150_Y + connect \Y $and$ls180.v:5759$1151_Y end - attribute \src "ls180.v:5763.35-5763.142" - cell $and $and$ls180.v:5763$1154 + attribute \src "ls180.v:5759.35-5759.142" + cell $and $and$ls180.v:5759$1153 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5763$1152_Y - connect \B $eq$ls180.v:5763$1153_Y - connect \Y $and$ls180.v:5763$1154_Y + connect \A $and$ls180.v:5759$1151_Y + connect \B $eq$ls180.v:5759$1152_Y + connect \Y $and$ls180.v:5759$1153_Y end - attribute \src "ls180.v:5765.36-5765.89" - cell $and $and$ls180.v:5765$1155 + attribute \src "ls180.v:5761.36-5761.89" + cell $and $and$ls180.v:5761$1154 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87405,43 +87401,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:5765$1155_Y + connect \Y $and$ls180.v:5761$1154_Y end - attribute \src "ls180.v:5765.35-5765.139" - cell $and $and$ls180.v:5765$1157 + attribute \src "ls180.v:5761.35-5761.139" + cell $and $and$ls180.v:5761$1156 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5765$1155_Y - connect \B $eq$ls180.v:5765$1156_Y - connect \Y $and$ls180.v:5765$1157_Y + connect \A $and$ls180.v:5761$1154_Y + connect \B $eq$ls180.v:5761$1155_Y + connect \Y $and$ls180.v:5761$1156_Y end - attribute \src "ls180.v:5766.36-5766.92" - cell $and $and$ls180.v:5766$1159 + attribute \src "ls180.v:5762.36-5762.92" + cell $and $and$ls180.v:5762$1158 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:5766$1158_Y - connect \Y $and$ls180.v:5766$1159_Y + connect \B $not$ls180.v:5762$1157_Y + connect \Y $and$ls180.v:5762$1158_Y end - attribute \src "ls180.v:5766.35-5766.142" - cell $and $and$ls180.v:5766$1161 + attribute \src "ls180.v:5762.35-5762.142" + cell $and $and$ls180.v:5762$1160 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5766$1159_Y - connect \B $eq$ls180.v:5766$1160_Y - connect \Y $and$ls180.v:5766$1161_Y + connect \A $and$ls180.v:5762$1158_Y + connect \B $eq$ls180.v:5762$1159_Y + connect \Y $and$ls180.v:5762$1160_Y end - attribute \src "ls180.v:5768.36-5768.89" - cell $and $and$ls180.v:5768$1162 + attribute \src "ls180.v:5764.36-5764.89" + cell $and $and$ls180.v:5764$1161 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87449,43 +87445,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:5768$1162_Y + connect \Y $and$ls180.v:5764$1161_Y end - attribute \src "ls180.v:5768.35-5768.139" - cell $and $and$ls180.v:5768$1164 + attribute \src "ls180.v:5764.35-5764.139" + cell $and $and$ls180.v:5764$1163 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5768$1162_Y - connect \B $eq$ls180.v:5768$1163_Y - connect \Y $and$ls180.v:5768$1164_Y + connect \A $and$ls180.v:5764$1161_Y + connect \B $eq$ls180.v:5764$1162_Y + connect \Y $and$ls180.v:5764$1163_Y end - attribute \src "ls180.v:5769.36-5769.92" - cell $and $and$ls180.v:5769$1166 + attribute \src "ls180.v:5765.36-5765.92" + cell $and $and$ls180.v:5765$1165 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:5769$1165_Y - connect \Y $and$ls180.v:5769$1166_Y + connect \B $not$ls180.v:5765$1164_Y + connect \Y $and$ls180.v:5765$1165_Y end - attribute \src "ls180.v:5769.35-5769.142" - cell $and $and$ls180.v:5769$1168 + attribute \src "ls180.v:5765.35-5765.142" + cell $and $and$ls180.v:5765$1167 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5769$1166_Y - connect \B $eq$ls180.v:5769$1167_Y - connect \Y $and$ls180.v:5769$1168_Y + connect \A $and$ls180.v:5765$1165_Y + connect \B $eq$ls180.v:5765$1166_Y + connect \Y $and$ls180.v:5765$1167_Y end - attribute \src "ls180.v:5771.36-5771.89" - cell $and $and$ls180.v:5771$1169 + attribute \src "ls180.v:5767.36-5767.89" + cell $and $and$ls180.v:5767$1168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87493,43 +87489,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:5771$1169_Y + connect \Y $and$ls180.v:5767$1168_Y end - attribute \src "ls180.v:5771.35-5771.139" - cell $and $and$ls180.v:5771$1171 + attribute \src "ls180.v:5767.35-5767.139" + cell $and $and$ls180.v:5767$1170 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5771$1169_Y - connect \B $eq$ls180.v:5771$1170_Y - connect \Y $and$ls180.v:5771$1171_Y + connect \A $and$ls180.v:5767$1168_Y + connect \B $eq$ls180.v:5767$1169_Y + connect \Y $and$ls180.v:5767$1170_Y end - attribute \src "ls180.v:5772.36-5772.92" - cell $and $and$ls180.v:5772$1173 + attribute \src "ls180.v:5768.36-5768.92" + cell $and $and$ls180.v:5768$1172 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:5772$1172_Y - connect \Y $and$ls180.v:5772$1173_Y + connect \B $not$ls180.v:5768$1171_Y + connect \Y $and$ls180.v:5768$1172_Y end - attribute \src "ls180.v:5772.35-5772.142" - cell $and $and$ls180.v:5772$1175 + attribute \src "ls180.v:5768.35-5768.142" + cell $and $and$ls180.v:5768$1174 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5772$1173_Y - connect \B $eq$ls180.v:5772$1174_Y - connect \Y $and$ls180.v:5772$1175_Y + connect \A $and$ls180.v:5768$1172_Y + connect \B $eq$ls180.v:5768$1173_Y + connect \Y $and$ls180.v:5768$1174_Y end - attribute \src "ls180.v:5774.37-5774.90" - cell $and $and$ls180.v:5774$1176 + attribute \src "ls180.v:5770.37-5770.90" + cell $and $and$ls180.v:5770$1175 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87537,43 +87533,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:5774$1176_Y + connect \Y $and$ls180.v:5770$1175_Y end - attribute \src "ls180.v:5774.36-5774.140" - cell $and $and$ls180.v:5774$1178 + attribute \src "ls180.v:5770.36-5770.140" + cell $and $and$ls180.v:5770$1177 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5774$1176_Y - connect \B $eq$ls180.v:5774$1177_Y - connect \Y $and$ls180.v:5774$1178_Y + connect \A $and$ls180.v:5770$1175_Y + connect \B $eq$ls180.v:5770$1176_Y + connect \Y $and$ls180.v:5770$1177_Y end - attribute \src "ls180.v:5775.37-5775.93" - cell $and $and$ls180.v:5775$1180 + attribute \src "ls180.v:5771.37-5771.93" + cell $and $and$ls180.v:5771$1179 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:5775$1179_Y - connect \Y $and$ls180.v:5775$1180_Y + connect \B $not$ls180.v:5771$1178_Y + connect \Y $and$ls180.v:5771$1179_Y end - attribute \src "ls180.v:5775.36-5775.143" - cell $and $and$ls180.v:5775$1182 + attribute \src "ls180.v:5771.36-5771.143" + cell $and $and$ls180.v:5771$1181 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5775$1180_Y - connect \B $eq$ls180.v:5775$1181_Y - connect \Y $and$ls180.v:5775$1182_Y + connect \A $and$ls180.v:5771$1179_Y + connect \B $eq$ls180.v:5771$1180_Y + connect \Y $and$ls180.v:5771$1181_Y end - attribute \src "ls180.v:5777.37-5777.90" - cell $and $and$ls180.v:5777$1183 + attribute \src "ls180.v:5773.37-5773.90" + cell $and $and$ls180.v:5773$1182 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87581,43 +87577,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:5777$1183_Y + connect \Y $and$ls180.v:5773$1182_Y end - attribute \src "ls180.v:5777.36-5777.140" - cell $and $and$ls180.v:5777$1185 + attribute \src "ls180.v:5773.36-5773.140" + cell $and $and$ls180.v:5773$1184 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5777$1183_Y - connect \B $eq$ls180.v:5777$1184_Y - connect \Y $and$ls180.v:5777$1185_Y + connect \A $and$ls180.v:5773$1182_Y + connect \B $eq$ls180.v:5773$1183_Y + connect \Y $and$ls180.v:5773$1184_Y end - attribute \src "ls180.v:5778.37-5778.93" - cell $and $and$ls180.v:5778$1187 + attribute \src "ls180.v:5774.37-5774.93" + cell $and $and$ls180.v:5774$1186 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:5778$1186_Y - connect \Y $and$ls180.v:5778$1187_Y + connect \B $not$ls180.v:5774$1185_Y + connect \Y $and$ls180.v:5774$1186_Y end - attribute \src "ls180.v:5778.36-5778.143" - cell $and $and$ls180.v:5778$1189 + attribute \src "ls180.v:5774.36-5774.143" + cell $and $and$ls180.v:5774$1188 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5778$1187_Y - connect \B $eq$ls180.v:5778$1188_Y - connect \Y $and$ls180.v:5778$1189_Y + connect \A $and$ls180.v:5774$1186_Y + connect \B $eq$ls180.v:5774$1187_Y + connect \Y $and$ls180.v:5774$1188_Y end - attribute \src "ls180.v:5788.40-5788.93" - cell $and $and$ls180.v:5788$1191 + attribute \src "ls180.v:5784.40-5784.93" + cell $and $and$ls180.v:5784$1190 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87625,43 +87621,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank2_sel connect \B \builder_interface2_bank_bus_we - connect \Y $and$ls180.v:5788$1191_Y + connect \Y $and$ls180.v:5784$1190_Y end - attribute \src "ls180.v:5788.39-5788.143" - cell $and $and$ls180.v:5788$1193 + attribute \src "ls180.v:5784.39-5784.143" + cell $and $and$ls180.v:5784$1192 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5788$1191_Y - connect \B $eq$ls180.v:5788$1192_Y - connect \Y $and$ls180.v:5788$1193_Y + connect \A $and$ls180.v:5784$1190_Y + connect \B $eq$ls180.v:5784$1191_Y + connect \Y $and$ls180.v:5784$1192_Y end - attribute \src "ls180.v:5789.40-5789.96" - cell $and $and$ls180.v:5789$1195 + attribute \src "ls180.v:5785.40-5785.96" + cell $and $and$ls180.v:5785$1194 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank2_sel - connect \B $not$ls180.v:5789$1194_Y - connect \Y $and$ls180.v:5789$1195_Y + connect \B $not$ls180.v:5785$1193_Y + connect \Y $and$ls180.v:5785$1194_Y end - attribute \src "ls180.v:5789.39-5789.146" - cell $and $and$ls180.v:5789$1197 + attribute \src "ls180.v:5785.39-5785.146" + cell $and $and$ls180.v:5785$1196 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5789$1195_Y - connect \B $eq$ls180.v:5789$1196_Y - connect \Y $and$ls180.v:5789$1197_Y + connect \A $and$ls180.v:5785$1194_Y + connect \B $eq$ls180.v:5785$1195_Y + connect \Y $and$ls180.v:5785$1196_Y end - attribute \src "ls180.v:5791.39-5791.92" - cell $and $and$ls180.v:5791$1198 + attribute \src "ls180.v:5787.39-5787.92" + cell $and $and$ls180.v:5787$1197 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87669,43 +87665,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank2_sel connect \B \builder_interface2_bank_bus_we - connect \Y $and$ls180.v:5791$1198_Y + connect \Y $and$ls180.v:5787$1197_Y end - attribute \src "ls180.v:5791.38-5791.142" - cell $and $and$ls180.v:5791$1200 + attribute \src "ls180.v:5787.38-5787.142" + cell $and $and$ls180.v:5787$1199 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5791$1198_Y - connect \B $eq$ls180.v:5791$1199_Y - connect \Y $and$ls180.v:5791$1200_Y + connect \A $and$ls180.v:5787$1197_Y + connect \B $eq$ls180.v:5787$1198_Y + connect \Y $and$ls180.v:5787$1199_Y end - attribute \src "ls180.v:5792.39-5792.95" - cell $and $and$ls180.v:5792$1202 + attribute \src "ls180.v:5788.39-5788.95" + cell $and $and$ls180.v:5788$1201 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank2_sel - connect \B $not$ls180.v:5792$1201_Y - connect \Y $and$ls180.v:5792$1202_Y + connect \B $not$ls180.v:5788$1200_Y + connect \Y $and$ls180.v:5788$1201_Y end - attribute \src "ls180.v:5792.38-5792.145" - cell $and $and$ls180.v:5792$1204 + attribute \src "ls180.v:5788.38-5788.145" + cell $and $and$ls180.v:5788$1203 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5792$1202_Y - connect \B $eq$ls180.v:5792$1203_Y - connect \Y $and$ls180.v:5792$1204_Y + connect \A $and$ls180.v:5788$1201_Y + connect \B $eq$ls180.v:5788$1202_Y + connect \Y $and$ls180.v:5788$1203_Y end - attribute \src "ls180.v:5794.39-5794.92" - cell $and $and$ls180.v:5794$1205 + attribute \src "ls180.v:5790.39-5790.92" + cell $and $and$ls180.v:5790$1204 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87713,43 +87709,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank2_sel connect \B \builder_interface2_bank_bus_we - connect \Y $and$ls180.v:5794$1205_Y + connect \Y $and$ls180.v:5790$1204_Y end - attribute \src "ls180.v:5794.38-5794.142" - cell $and $and$ls180.v:5794$1207 + attribute \src "ls180.v:5790.38-5790.142" + cell $and $and$ls180.v:5790$1206 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5794$1205_Y - connect \B $eq$ls180.v:5794$1206_Y - connect \Y $and$ls180.v:5794$1207_Y + connect \A $and$ls180.v:5790$1204_Y + connect \B $eq$ls180.v:5790$1205_Y + connect \Y $and$ls180.v:5790$1206_Y end - attribute \src "ls180.v:5795.39-5795.95" - cell $and $and$ls180.v:5795$1209 + attribute \src "ls180.v:5791.39-5791.95" + cell $and $and$ls180.v:5791$1208 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank2_sel - connect \B $not$ls180.v:5795$1208_Y - connect \Y $and$ls180.v:5795$1209_Y + connect \B $not$ls180.v:5791$1207_Y + connect \Y $and$ls180.v:5791$1208_Y end - attribute \src "ls180.v:5795.38-5795.145" - cell $and $and$ls180.v:5795$1211 + attribute \src "ls180.v:5791.38-5791.145" + cell $and $and$ls180.v:5791$1210 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5795$1209_Y - connect \B $eq$ls180.v:5795$1210_Y - connect \Y $and$ls180.v:5795$1211_Y + connect \A $and$ls180.v:5791$1208_Y + connect \B $eq$ls180.v:5791$1209_Y + connect \Y $and$ls180.v:5791$1210_Y end - attribute \src "ls180.v:5797.39-5797.92" - cell $and $and$ls180.v:5797$1212 + attribute \src "ls180.v:5793.39-5793.92" + cell $and $and$ls180.v:5793$1211 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87757,43 +87753,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank2_sel connect \B \builder_interface2_bank_bus_we - connect \Y $and$ls180.v:5797$1212_Y + connect \Y $and$ls180.v:5793$1211_Y end - attribute \src "ls180.v:5797.38-5797.142" - cell $and $and$ls180.v:5797$1214 + attribute \src "ls180.v:5793.38-5793.142" + cell $and $and$ls180.v:5793$1213 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5797$1212_Y - connect \B $eq$ls180.v:5797$1213_Y - connect \Y $and$ls180.v:5797$1214_Y + connect \A $and$ls180.v:5793$1211_Y + connect \B $eq$ls180.v:5793$1212_Y + connect \Y $and$ls180.v:5793$1213_Y end - attribute \src "ls180.v:5798.39-5798.95" - cell $and $and$ls180.v:5798$1216 + attribute \src "ls180.v:5794.39-5794.95" + cell $and $and$ls180.v:5794$1215 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank2_sel - connect \B $not$ls180.v:5798$1215_Y - connect \Y $and$ls180.v:5798$1216_Y + connect \B $not$ls180.v:5794$1214_Y + connect \Y $and$ls180.v:5794$1215_Y end - attribute \src "ls180.v:5798.38-5798.145" - cell $and $and$ls180.v:5798$1218 + attribute \src "ls180.v:5794.38-5794.145" + cell $and $and$ls180.v:5794$1217 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5798$1216_Y - connect \B $eq$ls180.v:5798$1217_Y - connect \Y $and$ls180.v:5798$1218_Y + connect \A $and$ls180.v:5794$1215_Y + connect \B $eq$ls180.v:5794$1216_Y + connect \Y $and$ls180.v:5794$1217_Y end - attribute \src "ls180.v:5800.39-5800.92" - cell $and $and$ls180.v:5800$1219 + attribute \src "ls180.v:5796.39-5796.92" + cell $and $and$ls180.v:5796$1218 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87801,43 +87797,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank2_sel connect \B \builder_interface2_bank_bus_we - connect \Y $and$ls180.v:5800$1219_Y + connect \Y $and$ls180.v:5796$1218_Y end - attribute \src "ls180.v:5800.38-5800.142" - cell $and $and$ls180.v:5800$1221 + attribute \src "ls180.v:5796.38-5796.142" + cell $and $and$ls180.v:5796$1220 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5800$1219_Y - connect \B $eq$ls180.v:5800$1220_Y - connect \Y $and$ls180.v:5800$1221_Y + connect \A $and$ls180.v:5796$1218_Y + connect \B $eq$ls180.v:5796$1219_Y + connect \Y $and$ls180.v:5796$1220_Y end - attribute \src "ls180.v:5801.39-5801.95" - cell $and $and$ls180.v:5801$1223 + attribute \src "ls180.v:5797.39-5797.95" + cell $and $and$ls180.v:5797$1222 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank2_sel - connect \B $not$ls180.v:5801$1222_Y - connect \Y $and$ls180.v:5801$1223_Y + connect \B $not$ls180.v:5797$1221_Y + connect \Y $and$ls180.v:5797$1222_Y end - attribute \src "ls180.v:5801.38-5801.145" - cell $and $and$ls180.v:5801$1225 + attribute \src "ls180.v:5797.38-5797.145" + cell $and $and$ls180.v:5797$1224 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5801$1223_Y - connect \B $eq$ls180.v:5801$1224_Y - connect \Y $and$ls180.v:5801$1225_Y + connect \A $and$ls180.v:5797$1222_Y + connect \B $eq$ls180.v:5797$1223_Y + connect \Y $and$ls180.v:5797$1224_Y end - attribute \src "ls180.v:5803.40-5803.93" - cell $and $and$ls180.v:5803$1226 + attribute \src "ls180.v:5799.40-5799.93" + cell $and $and$ls180.v:5799$1225 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87845,43 +87841,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank2_sel connect \B \builder_interface2_bank_bus_we - connect \Y $and$ls180.v:5803$1226_Y + connect \Y $and$ls180.v:5799$1225_Y end - attribute \src "ls180.v:5803.39-5803.143" - cell $and $and$ls180.v:5803$1228 + attribute \src "ls180.v:5799.39-5799.143" + cell $and $and$ls180.v:5799$1227 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5803$1226_Y - connect \B $eq$ls180.v:5803$1227_Y - connect \Y $and$ls180.v:5803$1228_Y + connect \A $and$ls180.v:5799$1225_Y + connect \B $eq$ls180.v:5799$1226_Y + connect \Y $and$ls180.v:5799$1227_Y end - attribute \src "ls180.v:5804.40-5804.96" - cell $and $and$ls180.v:5804$1230 + attribute \src "ls180.v:5800.40-5800.96" + cell $and $and$ls180.v:5800$1229 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank2_sel - connect \B $not$ls180.v:5804$1229_Y - connect \Y $and$ls180.v:5804$1230_Y + connect \B $not$ls180.v:5800$1228_Y + connect \Y $and$ls180.v:5800$1229_Y end - attribute \src "ls180.v:5804.39-5804.146" - cell $and $and$ls180.v:5804$1232 + attribute \src "ls180.v:5800.39-5800.146" + cell $and $and$ls180.v:5800$1231 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5804$1230_Y - connect \B $eq$ls180.v:5804$1231_Y - connect \Y $and$ls180.v:5804$1232_Y + connect \A $and$ls180.v:5800$1229_Y + connect \B $eq$ls180.v:5800$1230_Y + connect \Y $and$ls180.v:5800$1231_Y end - attribute \src "ls180.v:5806.40-5806.93" - cell $and $and$ls180.v:5806$1233 + attribute \src "ls180.v:5802.40-5802.93" + cell $and $and$ls180.v:5802$1232 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87889,43 +87885,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank2_sel connect \B \builder_interface2_bank_bus_we - connect \Y $and$ls180.v:5806$1233_Y + connect \Y $and$ls180.v:5802$1232_Y end - attribute \src "ls180.v:5806.39-5806.143" - cell $and $and$ls180.v:5806$1235 + attribute \src "ls180.v:5802.39-5802.143" + cell $and $and$ls180.v:5802$1234 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5806$1233_Y - connect \B $eq$ls180.v:5806$1234_Y - connect \Y $and$ls180.v:5806$1235_Y + connect \A $and$ls180.v:5802$1232_Y + connect \B $eq$ls180.v:5802$1233_Y + connect \Y $and$ls180.v:5802$1234_Y end - attribute \src "ls180.v:5807.40-5807.96" - cell $and $and$ls180.v:5807$1237 + attribute \src "ls180.v:5803.40-5803.96" + cell $and $and$ls180.v:5803$1236 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank2_sel - connect \B $not$ls180.v:5807$1236_Y - connect \Y $and$ls180.v:5807$1237_Y + connect \B $not$ls180.v:5803$1235_Y + connect \Y $and$ls180.v:5803$1236_Y end - attribute \src "ls180.v:5807.39-5807.146" - cell $and $and$ls180.v:5807$1239 + attribute \src "ls180.v:5803.39-5803.146" + cell $and $and$ls180.v:5803$1238 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5807$1237_Y - connect \B $eq$ls180.v:5807$1238_Y - connect \Y $and$ls180.v:5807$1239_Y + connect \A $and$ls180.v:5803$1236_Y + connect \B $eq$ls180.v:5803$1237_Y + connect \Y $and$ls180.v:5803$1238_Y end - attribute \src "ls180.v:5809.40-5809.93" - cell $and $and$ls180.v:5809$1240 + attribute \src "ls180.v:5805.40-5805.93" + cell $and $and$ls180.v:5805$1239 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87933,43 +87929,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank2_sel connect \B \builder_interface2_bank_bus_we - connect \Y $and$ls180.v:5809$1240_Y + connect \Y $and$ls180.v:5805$1239_Y end - attribute \src "ls180.v:5809.39-5809.143" - cell $and $and$ls180.v:5809$1242 + attribute \src "ls180.v:5805.39-5805.143" + cell $and $and$ls180.v:5805$1241 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5809$1240_Y - connect \B $eq$ls180.v:5809$1241_Y - connect \Y $and$ls180.v:5809$1242_Y + connect \A $and$ls180.v:5805$1239_Y + connect \B $eq$ls180.v:5805$1240_Y + connect \Y $and$ls180.v:5805$1241_Y end - attribute \src "ls180.v:5810.40-5810.96" - cell $and $and$ls180.v:5810$1244 + attribute \src "ls180.v:5806.40-5806.96" + cell $and $and$ls180.v:5806$1243 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank2_sel - connect \B $not$ls180.v:5810$1243_Y - connect \Y $and$ls180.v:5810$1244_Y + connect \B $not$ls180.v:5806$1242_Y + connect \Y $and$ls180.v:5806$1243_Y end - attribute \src "ls180.v:5810.39-5810.146" - cell $and $and$ls180.v:5810$1246 + attribute \src "ls180.v:5806.39-5806.146" + cell $and $and$ls180.v:5806$1245 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5810$1244_Y - connect \B $eq$ls180.v:5810$1245_Y - connect \Y $and$ls180.v:5810$1246_Y + connect \A $and$ls180.v:5806$1243_Y + connect \B $eq$ls180.v:5806$1244_Y + connect \Y $and$ls180.v:5806$1245_Y end - attribute \src "ls180.v:5812.40-5812.93" - cell $and $and$ls180.v:5812$1247 + attribute \src "ls180.v:5808.40-5808.93" + cell $and $and$ls180.v:5808$1246 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87977,43 +87973,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank2_sel connect \B \builder_interface2_bank_bus_we - connect \Y $and$ls180.v:5812$1247_Y + connect \Y $and$ls180.v:5808$1246_Y end - attribute \src "ls180.v:5812.39-5812.143" - cell $and $and$ls180.v:5812$1249 + attribute \src "ls180.v:5808.39-5808.143" + cell $and $and$ls180.v:5808$1248 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5812$1247_Y - connect \B $eq$ls180.v:5812$1248_Y - connect \Y $and$ls180.v:5812$1249_Y + connect \A $and$ls180.v:5808$1246_Y + connect \B $eq$ls180.v:5808$1247_Y + connect \Y $and$ls180.v:5808$1248_Y end - attribute \src "ls180.v:5813.40-5813.96" - cell $and $and$ls180.v:5813$1251 + attribute \src "ls180.v:5809.40-5809.96" + cell $and $and$ls180.v:5809$1250 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank2_sel - connect \B $not$ls180.v:5813$1250_Y - connect \Y $and$ls180.v:5813$1251_Y + connect \B $not$ls180.v:5809$1249_Y + connect \Y $and$ls180.v:5809$1250_Y end - attribute \src "ls180.v:5813.39-5813.146" - cell $and $and$ls180.v:5813$1253 + attribute \src "ls180.v:5809.39-5809.146" + cell $and $and$ls180.v:5809$1252 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5813$1251_Y - connect \B $eq$ls180.v:5813$1252_Y - connect \Y $and$ls180.v:5813$1253_Y + connect \A $and$ls180.v:5809$1250_Y + connect \B $eq$ls180.v:5809$1251_Y + connect \Y $and$ls180.v:5809$1252_Y end - attribute \src "ls180.v:5825.40-5825.93" - cell $and $and$ls180.v:5825$1255 + attribute \src "ls180.v:5821.40-5821.93" + cell $and $and$ls180.v:5821$1254 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88021,43 +88017,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5825$1255_Y + connect \Y $and$ls180.v:5821$1254_Y end - attribute \src "ls180.v:5825.39-5825.143" - cell $and $and$ls180.v:5825$1257 + attribute \src "ls180.v:5821.39-5821.143" + cell $and $and$ls180.v:5821$1256 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5825$1255_Y - connect \B $eq$ls180.v:5825$1256_Y - connect \Y $and$ls180.v:5825$1257_Y + connect \A $and$ls180.v:5821$1254_Y + connect \B $eq$ls180.v:5821$1255_Y + connect \Y $and$ls180.v:5821$1256_Y end - attribute \src "ls180.v:5826.40-5826.96" - cell $and $and$ls180.v:5826$1259 + attribute \src "ls180.v:5822.40-5822.96" + cell $and $and$ls180.v:5822$1258 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5826$1258_Y - connect \Y $and$ls180.v:5826$1259_Y + connect \B $not$ls180.v:5822$1257_Y + connect \Y $and$ls180.v:5822$1258_Y end - attribute \src "ls180.v:5826.39-5826.146" - cell $and $and$ls180.v:5826$1261 + attribute \src "ls180.v:5822.39-5822.146" + cell $and $and$ls180.v:5822$1260 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5826$1259_Y - connect \B $eq$ls180.v:5826$1260_Y - connect \Y $and$ls180.v:5826$1261_Y + connect \A $and$ls180.v:5822$1258_Y + connect \B $eq$ls180.v:5822$1259_Y + connect \Y $and$ls180.v:5822$1260_Y end - attribute \src "ls180.v:5828.39-5828.92" - cell $and $and$ls180.v:5828$1262 + attribute \src "ls180.v:5824.39-5824.92" + cell $and $and$ls180.v:5824$1261 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88065,43 +88061,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5828$1262_Y + connect \Y $and$ls180.v:5824$1261_Y end - attribute \src "ls180.v:5828.38-5828.142" - cell $and $and$ls180.v:5828$1264 + attribute \src "ls180.v:5824.38-5824.142" + cell $and $and$ls180.v:5824$1263 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5828$1262_Y - connect \B $eq$ls180.v:5828$1263_Y - connect \Y $and$ls180.v:5828$1264_Y + connect \A $and$ls180.v:5824$1261_Y + connect \B $eq$ls180.v:5824$1262_Y + connect \Y $and$ls180.v:5824$1263_Y end - attribute \src "ls180.v:5829.39-5829.95" - cell $and $and$ls180.v:5829$1266 + attribute \src "ls180.v:5825.39-5825.95" + cell $and $and$ls180.v:5825$1265 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5829$1265_Y - connect \Y $and$ls180.v:5829$1266_Y + connect \B $not$ls180.v:5825$1264_Y + connect \Y $and$ls180.v:5825$1265_Y end - attribute \src "ls180.v:5829.38-5829.145" - cell $and $and$ls180.v:5829$1268 + attribute \src "ls180.v:5825.38-5825.145" + cell $and $and$ls180.v:5825$1267 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5829$1266_Y - connect \B $eq$ls180.v:5829$1267_Y - connect \Y $and$ls180.v:5829$1268_Y + connect \A $and$ls180.v:5825$1265_Y + connect \B $eq$ls180.v:5825$1266_Y + connect \Y $and$ls180.v:5825$1267_Y end - attribute \src "ls180.v:5831.39-5831.92" - cell $and $and$ls180.v:5831$1269 + attribute \src "ls180.v:5827.39-5827.92" + cell $and $and$ls180.v:5827$1268 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88109,43 +88105,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5831$1269_Y + connect \Y $and$ls180.v:5827$1268_Y end - attribute \src "ls180.v:5831.38-5831.142" - cell $and $and$ls180.v:5831$1271 + attribute \src "ls180.v:5827.38-5827.142" + cell $and $and$ls180.v:5827$1270 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5831$1269_Y - connect \B $eq$ls180.v:5831$1270_Y - connect \Y $and$ls180.v:5831$1271_Y + connect \A $and$ls180.v:5827$1268_Y + connect \B $eq$ls180.v:5827$1269_Y + connect \Y $and$ls180.v:5827$1270_Y end - attribute \src "ls180.v:5832.39-5832.95" - cell $and $and$ls180.v:5832$1273 + attribute \src "ls180.v:5828.39-5828.95" + cell $and $and$ls180.v:5828$1272 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5832$1272_Y - connect \Y $and$ls180.v:5832$1273_Y + connect \B $not$ls180.v:5828$1271_Y + connect \Y $and$ls180.v:5828$1272_Y end - attribute \src "ls180.v:5832.38-5832.145" - cell $and $and$ls180.v:5832$1275 + attribute \src "ls180.v:5828.38-5828.145" + cell $and $and$ls180.v:5828$1274 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5832$1273_Y - connect \B $eq$ls180.v:5832$1274_Y - connect \Y $and$ls180.v:5832$1275_Y + connect \A $and$ls180.v:5828$1272_Y + connect \B $eq$ls180.v:5828$1273_Y + connect \Y $and$ls180.v:5828$1274_Y end - attribute \src "ls180.v:5834.39-5834.92" - cell $and $and$ls180.v:5834$1276 + attribute \src "ls180.v:5830.39-5830.92" + cell $and $and$ls180.v:5830$1275 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88153,43 +88149,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5834$1276_Y + connect \Y $and$ls180.v:5830$1275_Y end - attribute \src "ls180.v:5834.38-5834.142" - cell $and $and$ls180.v:5834$1278 + attribute \src "ls180.v:5830.38-5830.142" + cell $and $and$ls180.v:5830$1277 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5834$1276_Y - connect \B $eq$ls180.v:5834$1277_Y - connect \Y $and$ls180.v:5834$1278_Y + connect \A $and$ls180.v:5830$1275_Y + connect \B $eq$ls180.v:5830$1276_Y + connect \Y $and$ls180.v:5830$1277_Y end - attribute \src "ls180.v:5835.39-5835.95" - cell $and $and$ls180.v:5835$1280 + attribute \src "ls180.v:5831.39-5831.95" + cell $and $and$ls180.v:5831$1279 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5835$1279_Y - connect \Y $and$ls180.v:5835$1280_Y + connect \B $not$ls180.v:5831$1278_Y + connect \Y $and$ls180.v:5831$1279_Y end - attribute \src "ls180.v:5835.38-5835.145" - cell $and $and$ls180.v:5835$1282 + attribute \src "ls180.v:5831.38-5831.145" + cell $and $and$ls180.v:5831$1281 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5835$1280_Y - connect \B $eq$ls180.v:5835$1281_Y - connect \Y $and$ls180.v:5835$1282_Y + connect \A $and$ls180.v:5831$1279_Y + connect \B $eq$ls180.v:5831$1280_Y + connect \Y $and$ls180.v:5831$1281_Y end - attribute \src "ls180.v:5837.39-5837.92" - cell $and $and$ls180.v:5837$1283 + attribute \src "ls180.v:5833.39-5833.92" + cell $and $and$ls180.v:5833$1282 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88197,43 +88193,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5837$1283_Y + connect \Y $and$ls180.v:5833$1282_Y end - attribute \src "ls180.v:5837.38-5837.142" - cell $and $and$ls180.v:5837$1285 + attribute \src "ls180.v:5833.38-5833.142" + cell $and $and$ls180.v:5833$1284 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5837$1283_Y - connect \B $eq$ls180.v:5837$1284_Y - connect \Y $and$ls180.v:5837$1285_Y + connect \A $and$ls180.v:5833$1282_Y + connect \B $eq$ls180.v:5833$1283_Y + connect \Y $and$ls180.v:5833$1284_Y end - attribute \src "ls180.v:5838.39-5838.95" - cell $and $and$ls180.v:5838$1287 + attribute \src "ls180.v:5834.39-5834.95" + cell $and $and$ls180.v:5834$1286 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5838$1286_Y - connect \Y $and$ls180.v:5838$1287_Y + connect \B $not$ls180.v:5834$1285_Y + connect \Y $and$ls180.v:5834$1286_Y end - attribute \src "ls180.v:5838.38-5838.145" - cell $and $and$ls180.v:5838$1289 + attribute \src "ls180.v:5834.38-5834.145" + cell $and $and$ls180.v:5834$1288 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5838$1287_Y - connect \B $eq$ls180.v:5838$1288_Y - connect \Y $and$ls180.v:5838$1289_Y + connect \A $and$ls180.v:5834$1286_Y + connect \B $eq$ls180.v:5834$1287_Y + connect \Y $and$ls180.v:5834$1288_Y end - attribute \src "ls180.v:5840.40-5840.93" - cell $and $and$ls180.v:5840$1290 + attribute \src "ls180.v:5836.40-5836.93" + cell $and $and$ls180.v:5836$1289 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88241,43 +88237,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5840$1290_Y + connect \Y $and$ls180.v:5836$1289_Y end - attribute \src "ls180.v:5840.39-5840.143" - cell $and $and$ls180.v:5840$1292 + attribute \src "ls180.v:5836.39-5836.143" + cell $and $and$ls180.v:5836$1291 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5840$1290_Y - connect \B $eq$ls180.v:5840$1291_Y - connect \Y $and$ls180.v:5840$1292_Y + connect \A $and$ls180.v:5836$1289_Y + connect \B $eq$ls180.v:5836$1290_Y + connect \Y $and$ls180.v:5836$1291_Y end - attribute \src "ls180.v:5841.40-5841.96" - cell $and $and$ls180.v:5841$1294 + attribute \src "ls180.v:5837.40-5837.96" + cell $and $and$ls180.v:5837$1293 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5841$1293_Y - connect \Y $and$ls180.v:5841$1294_Y + connect \B $not$ls180.v:5837$1292_Y + connect \Y $and$ls180.v:5837$1293_Y end - attribute \src "ls180.v:5841.39-5841.146" - cell $and $and$ls180.v:5841$1296 + attribute \src "ls180.v:5837.39-5837.146" + cell $and $and$ls180.v:5837$1295 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5841$1294_Y - connect \B $eq$ls180.v:5841$1295_Y - connect \Y $and$ls180.v:5841$1296_Y + connect \A $and$ls180.v:5837$1293_Y + connect \B $eq$ls180.v:5837$1294_Y + connect \Y $and$ls180.v:5837$1295_Y end - attribute \src "ls180.v:5843.40-5843.93" - cell $and $and$ls180.v:5843$1297 + attribute \src "ls180.v:5839.40-5839.93" + cell $and $and$ls180.v:5839$1296 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88285,43 +88281,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5843$1297_Y + connect \Y $and$ls180.v:5839$1296_Y end - attribute \src "ls180.v:5843.39-5843.143" - cell $and $and$ls180.v:5843$1299 + attribute \src "ls180.v:5839.39-5839.143" + cell $and $and$ls180.v:5839$1298 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5843$1297_Y - connect \B $eq$ls180.v:5843$1298_Y - connect \Y $and$ls180.v:5843$1299_Y + connect \A $and$ls180.v:5839$1296_Y + connect \B $eq$ls180.v:5839$1297_Y + connect \Y $and$ls180.v:5839$1298_Y end - attribute \src "ls180.v:5844.40-5844.96" - cell $and $and$ls180.v:5844$1301 + attribute \src "ls180.v:5840.40-5840.96" + cell $and $and$ls180.v:5840$1300 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5844$1300_Y - connect \Y $and$ls180.v:5844$1301_Y + connect \B $not$ls180.v:5840$1299_Y + connect \Y $and$ls180.v:5840$1300_Y end - attribute \src "ls180.v:5844.39-5844.146" - cell $and $and$ls180.v:5844$1303 + attribute \src "ls180.v:5840.39-5840.146" + cell $and $and$ls180.v:5840$1302 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5844$1301_Y - connect \B $eq$ls180.v:5844$1302_Y - connect \Y $and$ls180.v:5844$1303_Y + connect \A $and$ls180.v:5840$1300_Y + connect \B $eq$ls180.v:5840$1301_Y + connect \Y $and$ls180.v:5840$1302_Y end - attribute \src "ls180.v:5846.40-5846.93" - cell $and $and$ls180.v:5846$1304 + attribute \src "ls180.v:5842.40-5842.93" + cell $and $and$ls180.v:5842$1303 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88329,43 +88325,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5846$1304_Y + connect \Y $and$ls180.v:5842$1303_Y end - attribute \src "ls180.v:5846.39-5846.143" - cell $and $and$ls180.v:5846$1306 + attribute \src "ls180.v:5842.39-5842.143" + cell $and $and$ls180.v:5842$1305 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5846$1304_Y - connect \B $eq$ls180.v:5846$1305_Y - connect \Y $and$ls180.v:5846$1306_Y + connect \A $and$ls180.v:5842$1303_Y + connect \B $eq$ls180.v:5842$1304_Y + connect \Y $and$ls180.v:5842$1305_Y end - attribute \src "ls180.v:5847.40-5847.96" - cell $and $and$ls180.v:5847$1308 + attribute \src "ls180.v:5843.40-5843.96" + cell $and $and$ls180.v:5843$1307 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5847$1307_Y - connect \Y $and$ls180.v:5847$1308_Y + connect \B $not$ls180.v:5843$1306_Y + connect \Y $and$ls180.v:5843$1307_Y end - attribute \src "ls180.v:5847.39-5847.146" - cell $and $and$ls180.v:5847$1310 + attribute \src "ls180.v:5843.39-5843.146" + cell $and $and$ls180.v:5843$1309 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5847$1308_Y - connect \B $eq$ls180.v:5847$1309_Y - connect \Y $and$ls180.v:5847$1310_Y + connect \A $and$ls180.v:5843$1307_Y + connect \B $eq$ls180.v:5843$1308_Y + connect \Y $and$ls180.v:5843$1309_Y end - attribute \src "ls180.v:5849.40-5849.93" - cell $and $and$ls180.v:5849$1311 + attribute \src "ls180.v:5845.40-5845.93" + cell $and $and$ls180.v:5845$1310 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88373,43 +88369,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5849$1311_Y + connect \Y $and$ls180.v:5845$1310_Y end - attribute \src "ls180.v:5849.39-5849.143" - cell $and $and$ls180.v:5849$1313 + attribute \src "ls180.v:5845.39-5845.143" + cell $and $and$ls180.v:5845$1312 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5849$1311_Y - connect \B $eq$ls180.v:5849$1312_Y - connect \Y $and$ls180.v:5849$1313_Y + connect \A $and$ls180.v:5845$1310_Y + connect \B $eq$ls180.v:5845$1311_Y + connect \Y $and$ls180.v:5845$1312_Y end - attribute \src "ls180.v:5850.40-5850.96" - cell $and $and$ls180.v:5850$1315 + attribute \src "ls180.v:5846.40-5846.96" + cell $and $and$ls180.v:5846$1314 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5850$1314_Y - connect \Y $and$ls180.v:5850$1315_Y + connect \B $not$ls180.v:5846$1313_Y + connect \Y $and$ls180.v:5846$1314_Y end - attribute \src "ls180.v:5850.39-5850.146" - cell $and $and$ls180.v:5850$1317 + attribute \src "ls180.v:5846.39-5846.146" + cell $and $and$ls180.v:5846$1316 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5850$1315_Y - connect \B $eq$ls180.v:5850$1316_Y - connect \Y $and$ls180.v:5850$1317_Y + connect \A $and$ls180.v:5846$1314_Y + connect \B $eq$ls180.v:5846$1315_Y + connect \Y $and$ls180.v:5846$1316_Y end - attribute \src "ls180.v:5862.42-5862.95" - cell $and $and$ls180.v:5862$1319 + attribute \src "ls180.v:5858.42-5858.95" + cell $and $and$ls180.v:5858$1318 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88417,43 +88413,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5862$1319_Y + connect \Y $and$ls180.v:5858$1318_Y end - attribute \src "ls180.v:5862.41-5862.145" - cell $and $and$ls180.v:5862$1321 + attribute \src "ls180.v:5858.41-5858.145" + cell $and $and$ls180.v:5858$1320 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5862$1319_Y - connect \B $eq$ls180.v:5862$1320_Y - connect \Y $and$ls180.v:5862$1321_Y + connect \A $and$ls180.v:5858$1318_Y + connect \B $eq$ls180.v:5858$1319_Y + connect \Y $and$ls180.v:5858$1320_Y end - attribute \src "ls180.v:5863.42-5863.98" - cell $and $and$ls180.v:5863$1323 + attribute \src "ls180.v:5859.42-5859.98" + cell $and $and$ls180.v:5859$1322 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5863$1322_Y - connect \Y $and$ls180.v:5863$1323_Y + connect \B $not$ls180.v:5859$1321_Y + connect \Y $and$ls180.v:5859$1322_Y end - attribute \src "ls180.v:5863.41-5863.148" - cell $and $and$ls180.v:5863$1325 + attribute \src "ls180.v:5859.41-5859.148" + cell $and $and$ls180.v:5859$1324 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5863$1323_Y - connect \B $eq$ls180.v:5863$1324_Y - connect \Y $and$ls180.v:5863$1325_Y + connect \A $and$ls180.v:5859$1322_Y + connect \B $eq$ls180.v:5859$1323_Y + connect \Y $and$ls180.v:5859$1324_Y end - attribute \src "ls180.v:5865.42-5865.95" - cell $and $and$ls180.v:5865$1326 + attribute \src "ls180.v:5861.42-5861.95" + cell $and $and$ls180.v:5861$1325 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88461,43 +88457,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5865$1326_Y + connect \Y $and$ls180.v:5861$1325_Y end - attribute \src "ls180.v:5865.41-5865.145" - cell $and $and$ls180.v:5865$1328 + attribute \src "ls180.v:5861.41-5861.145" + cell $and $and$ls180.v:5861$1327 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5865$1326_Y - connect \B $eq$ls180.v:5865$1327_Y - connect \Y $and$ls180.v:5865$1328_Y + connect \A $and$ls180.v:5861$1325_Y + connect \B $eq$ls180.v:5861$1326_Y + connect \Y $and$ls180.v:5861$1327_Y end - attribute \src "ls180.v:5866.42-5866.98" - cell $and $and$ls180.v:5866$1330 + attribute \src "ls180.v:5862.42-5862.98" + cell $and $and$ls180.v:5862$1329 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5866$1329_Y - connect \Y $and$ls180.v:5866$1330_Y + connect \B $not$ls180.v:5862$1328_Y + connect \Y $and$ls180.v:5862$1329_Y end - attribute \src "ls180.v:5866.41-5866.148" - cell $and $and$ls180.v:5866$1332 + attribute \src "ls180.v:5862.41-5862.148" + cell $and $and$ls180.v:5862$1331 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5866$1330_Y - connect \B $eq$ls180.v:5866$1331_Y - connect \Y $and$ls180.v:5866$1332_Y + connect \A $and$ls180.v:5862$1329_Y + connect \B $eq$ls180.v:5862$1330_Y + connect \Y $and$ls180.v:5862$1331_Y end - attribute \src "ls180.v:5868.42-5868.95" - cell $and $and$ls180.v:5868$1333 + attribute \src "ls180.v:5864.42-5864.95" + cell $and $and$ls180.v:5864$1332 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88505,43 +88501,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5868$1333_Y + connect \Y $and$ls180.v:5864$1332_Y end - attribute \src "ls180.v:5868.41-5868.145" - cell $and $and$ls180.v:5868$1335 + attribute \src "ls180.v:5864.41-5864.145" + cell $and $and$ls180.v:5864$1334 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5868$1333_Y - connect \B $eq$ls180.v:5868$1334_Y - connect \Y $and$ls180.v:5868$1335_Y + connect \A $and$ls180.v:5864$1332_Y + connect \B $eq$ls180.v:5864$1333_Y + connect \Y $and$ls180.v:5864$1334_Y end - attribute \src "ls180.v:5869.42-5869.98" - cell $and $and$ls180.v:5869$1337 + attribute \src "ls180.v:5865.42-5865.98" + cell $and $and$ls180.v:5865$1336 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5869$1336_Y - connect \Y $and$ls180.v:5869$1337_Y + connect \B $not$ls180.v:5865$1335_Y + connect \Y $and$ls180.v:5865$1336_Y end - attribute \src "ls180.v:5869.41-5869.148" - cell $and $and$ls180.v:5869$1339 + attribute \src "ls180.v:5865.41-5865.148" + cell $and $and$ls180.v:5865$1338 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5869$1337_Y - connect \B $eq$ls180.v:5869$1338_Y - connect \Y $and$ls180.v:5869$1339_Y + connect \A $and$ls180.v:5865$1336_Y + connect \B $eq$ls180.v:5865$1337_Y + connect \Y $and$ls180.v:5865$1338_Y end - attribute \src "ls180.v:5871.42-5871.95" - cell $and $and$ls180.v:5871$1340 + attribute \src "ls180.v:5867.42-5867.95" + cell $and $and$ls180.v:5867$1339 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88549,43 +88545,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5871$1340_Y + connect \Y $and$ls180.v:5867$1339_Y end - attribute \src "ls180.v:5871.41-5871.145" - cell $and $and$ls180.v:5871$1342 + attribute \src "ls180.v:5867.41-5867.145" + cell $and $and$ls180.v:5867$1341 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5871$1340_Y - connect \B $eq$ls180.v:5871$1341_Y - connect \Y $and$ls180.v:5871$1342_Y + connect \A $and$ls180.v:5867$1339_Y + connect \B $eq$ls180.v:5867$1340_Y + connect \Y $and$ls180.v:5867$1341_Y end - attribute \src "ls180.v:5872.42-5872.98" - cell $and $and$ls180.v:5872$1344 + attribute \src "ls180.v:5868.42-5868.98" + cell $and $and$ls180.v:5868$1343 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5872$1343_Y - connect \Y $and$ls180.v:5872$1344_Y + connect \B $not$ls180.v:5868$1342_Y + connect \Y $and$ls180.v:5868$1343_Y end - attribute \src "ls180.v:5872.41-5872.148" - cell $and $and$ls180.v:5872$1346 + attribute \src "ls180.v:5868.41-5868.148" + cell $and $and$ls180.v:5868$1345 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5872$1344_Y - connect \B $eq$ls180.v:5872$1345_Y - connect \Y $and$ls180.v:5872$1346_Y + connect \A $and$ls180.v:5868$1343_Y + connect \B $eq$ls180.v:5868$1344_Y + connect \Y $and$ls180.v:5868$1345_Y end - attribute \src "ls180.v:5874.42-5874.95" - cell $and $and$ls180.v:5874$1347 + attribute \src "ls180.v:5870.42-5870.95" + cell $and $and$ls180.v:5870$1346 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88593,43 +88589,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5874$1347_Y + connect \Y $and$ls180.v:5870$1346_Y end - attribute \src "ls180.v:5874.41-5874.145" - cell $and $and$ls180.v:5874$1349 + attribute \src "ls180.v:5870.41-5870.145" + cell $and $and$ls180.v:5870$1348 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5874$1347_Y - connect \B $eq$ls180.v:5874$1348_Y - connect \Y $and$ls180.v:5874$1349_Y + connect \A $and$ls180.v:5870$1346_Y + connect \B $eq$ls180.v:5870$1347_Y + connect \Y $and$ls180.v:5870$1348_Y end - attribute \src "ls180.v:5875.42-5875.98" - cell $and $and$ls180.v:5875$1351 + attribute \src "ls180.v:5871.42-5871.98" + cell $and $and$ls180.v:5871$1350 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5875$1350_Y - connect \Y $and$ls180.v:5875$1351_Y + connect \B $not$ls180.v:5871$1349_Y + connect \Y $and$ls180.v:5871$1350_Y end - attribute \src "ls180.v:5875.41-5875.148" - cell $and $and$ls180.v:5875$1353 + attribute \src "ls180.v:5871.41-5871.148" + cell $and $and$ls180.v:5871$1352 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5875$1351_Y - connect \B $eq$ls180.v:5875$1352_Y - connect \Y $and$ls180.v:5875$1353_Y + connect \A $and$ls180.v:5871$1350_Y + connect \B $eq$ls180.v:5871$1351_Y + connect \Y $and$ls180.v:5871$1352_Y end - attribute \src "ls180.v:5877.42-5877.95" - cell $and $and$ls180.v:5877$1354 + attribute \src "ls180.v:5873.42-5873.95" + cell $and $and$ls180.v:5873$1353 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88637,43 +88633,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5877$1354_Y + connect \Y $and$ls180.v:5873$1353_Y end - attribute \src "ls180.v:5877.41-5877.145" - cell $and $and$ls180.v:5877$1356 + attribute \src "ls180.v:5873.41-5873.145" + cell $and $and$ls180.v:5873$1355 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5877$1354_Y - connect \B $eq$ls180.v:5877$1355_Y - connect \Y $and$ls180.v:5877$1356_Y + connect \A $and$ls180.v:5873$1353_Y + connect \B $eq$ls180.v:5873$1354_Y + connect \Y $and$ls180.v:5873$1355_Y end - attribute \src "ls180.v:5878.42-5878.98" - cell $and $and$ls180.v:5878$1358 + attribute \src "ls180.v:5874.42-5874.98" + cell $and $and$ls180.v:5874$1357 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5878$1357_Y - connect \Y $and$ls180.v:5878$1358_Y + connect \B $not$ls180.v:5874$1356_Y + connect \Y $and$ls180.v:5874$1357_Y end - attribute \src "ls180.v:5878.41-5878.148" - cell $and $and$ls180.v:5878$1360 + attribute \src "ls180.v:5874.41-5874.148" + cell $and $and$ls180.v:5874$1359 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5878$1358_Y - connect \B $eq$ls180.v:5878$1359_Y - connect \Y $and$ls180.v:5878$1360_Y + connect \A $and$ls180.v:5874$1357_Y + connect \B $eq$ls180.v:5874$1358_Y + connect \Y $and$ls180.v:5874$1359_Y end - attribute \src "ls180.v:5880.42-5880.95" - cell $and $and$ls180.v:5880$1361 + attribute \src "ls180.v:5876.42-5876.95" + cell $and $and$ls180.v:5876$1360 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88681,43 +88677,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5880$1361_Y + connect \Y $and$ls180.v:5876$1360_Y end - attribute \src "ls180.v:5880.41-5880.145" - cell $and $and$ls180.v:5880$1363 + attribute \src "ls180.v:5876.41-5876.145" + cell $and $and$ls180.v:5876$1362 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5880$1361_Y - connect \B $eq$ls180.v:5880$1362_Y - connect \Y $and$ls180.v:5880$1363_Y + connect \A $and$ls180.v:5876$1360_Y + connect \B $eq$ls180.v:5876$1361_Y + connect \Y $and$ls180.v:5876$1362_Y end - attribute \src "ls180.v:5881.42-5881.98" - cell $and $and$ls180.v:5881$1365 + attribute \src "ls180.v:5877.42-5877.98" + cell $and $and$ls180.v:5877$1364 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5881$1364_Y - connect \Y $and$ls180.v:5881$1365_Y + connect \B $not$ls180.v:5877$1363_Y + connect \Y $and$ls180.v:5877$1364_Y end - attribute \src "ls180.v:5881.41-5881.148" - cell $and $and$ls180.v:5881$1367 + attribute \src "ls180.v:5877.41-5877.148" + cell $and $and$ls180.v:5877$1366 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5881$1365_Y - connect \B $eq$ls180.v:5881$1366_Y - connect \Y $and$ls180.v:5881$1367_Y + connect \A $and$ls180.v:5877$1364_Y + connect \B $eq$ls180.v:5877$1365_Y + connect \Y $and$ls180.v:5877$1366_Y end - attribute \src "ls180.v:5883.42-5883.95" - cell $and $and$ls180.v:5883$1368 + attribute \src "ls180.v:5879.42-5879.95" + cell $and $and$ls180.v:5879$1367 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88725,43 +88721,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5883$1368_Y + connect \Y $and$ls180.v:5879$1367_Y end - attribute \src "ls180.v:5883.41-5883.145" - cell $and $and$ls180.v:5883$1370 + attribute \src "ls180.v:5879.41-5879.145" + cell $and $and$ls180.v:5879$1369 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5883$1368_Y - connect \B $eq$ls180.v:5883$1369_Y - connect \Y $and$ls180.v:5883$1370_Y + connect \A $and$ls180.v:5879$1367_Y + connect \B $eq$ls180.v:5879$1368_Y + connect \Y $and$ls180.v:5879$1369_Y end - attribute \src "ls180.v:5884.42-5884.98" - cell $and $and$ls180.v:5884$1372 + attribute \src "ls180.v:5880.42-5880.98" + cell $and $and$ls180.v:5880$1371 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5884$1371_Y - connect \Y $and$ls180.v:5884$1372_Y + connect \B $not$ls180.v:5880$1370_Y + connect \Y $and$ls180.v:5880$1371_Y end - attribute \src "ls180.v:5884.41-5884.148" - cell $and $and$ls180.v:5884$1374 + attribute \src "ls180.v:5880.41-5880.148" + cell $and $and$ls180.v:5880$1373 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5884$1372_Y - connect \B $eq$ls180.v:5884$1373_Y - connect \Y $and$ls180.v:5884$1374_Y + connect \A $and$ls180.v:5880$1371_Y + connect \B $eq$ls180.v:5880$1372_Y + connect \Y $and$ls180.v:5880$1373_Y end - attribute \src "ls180.v:5886.44-5886.97" - cell $and $and$ls180.v:5886$1375 + attribute \src "ls180.v:5882.44-5882.97" + cell $and $and$ls180.v:5882$1374 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88769,43 +88765,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5886$1375_Y + connect \Y $and$ls180.v:5882$1374_Y end - attribute \src "ls180.v:5886.43-5886.147" - cell $and $and$ls180.v:5886$1377 + attribute \src "ls180.v:5882.43-5882.147" + cell $and $and$ls180.v:5882$1376 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5886$1375_Y - connect \B $eq$ls180.v:5886$1376_Y - connect \Y $and$ls180.v:5886$1377_Y + connect \A $and$ls180.v:5882$1374_Y + connect \B $eq$ls180.v:5882$1375_Y + connect \Y $and$ls180.v:5882$1376_Y end - attribute \src "ls180.v:5887.44-5887.100" - cell $and $and$ls180.v:5887$1379 + attribute \src "ls180.v:5883.44-5883.100" + cell $and $and$ls180.v:5883$1378 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5887$1378_Y - connect \Y $and$ls180.v:5887$1379_Y + connect \B $not$ls180.v:5883$1377_Y + connect \Y $and$ls180.v:5883$1378_Y end - attribute \src "ls180.v:5887.43-5887.150" - cell $and $and$ls180.v:5887$1381 + attribute \src "ls180.v:5883.43-5883.150" + cell $and $and$ls180.v:5883$1380 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5887$1379_Y - connect \B $eq$ls180.v:5887$1380_Y - connect \Y $and$ls180.v:5887$1381_Y + connect \A $and$ls180.v:5883$1378_Y + connect \B $eq$ls180.v:5883$1379_Y + connect \Y $and$ls180.v:5883$1380_Y end - attribute \src "ls180.v:5889.44-5889.97" - cell $and $and$ls180.v:5889$1382 + attribute \src "ls180.v:5885.44-5885.97" + cell $and $and$ls180.v:5885$1381 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88813,43 +88809,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5889$1382_Y + connect \Y $and$ls180.v:5885$1381_Y end - attribute \src "ls180.v:5889.43-5889.147" - cell $and $and$ls180.v:5889$1384 + attribute \src "ls180.v:5885.43-5885.147" + cell $and $and$ls180.v:5885$1383 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5889$1382_Y - connect \B $eq$ls180.v:5889$1383_Y - connect \Y $and$ls180.v:5889$1384_Y + connect \A $and$ls180.v:5885$1381_Y + connect \B $eq$ls180.v:5885$1382_Y + connect \Y $and$ls180.v:5885$1383_Y end - attribute \src "ls180.v:5890.44-5890.100" - cell $and $and$ls180.v:5890$1386 + attribute \src "ls180.v:5886.44-5886.100" + cell $and $and$ls180.v:5886$1385 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5890$1385_Y - connect \Y $and$ls180.v:5890$1386_Y + connect \B $not$ls180.v:5886$1384_Y + connect \Y $and$ls180.v:5886$1385_Y end - attribute \src "ls180.v:5890.43-5890.150" - cell $and $and$ls180.v:5890$1388 + attribute \src "ls180.v:5886.43-5886.150" + cell $and $and$ls180.v:5886$1387 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5890$1386_Y - connect \B $eq$ls180.v:5890$1387_Y - connect \Y $and$ls180.v:5890$1388_Y + connect \A $and$ls180.v:5886$1385_Y + connect \B $eq$ls180.v:5886$1386_Y + connect \Y $and$ls180.v:5886$1387_Y end - attribute \src "ls180.v:5892.44-5892.97" - cell $and $and$ls180.v:5892$1389 + attribute \src "ls180.v:5888.44-5888.97" + cell $and $and$ls180.v:5888$1388 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88857,43 +88853,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5892$1389_Y + connect \Y $and$ls180.v:5888$1388_Y end - attribute \src "ls180.v:5892.43-5892.148" - cell $and $and$ls180.v:5892$1391 + attribute \src "ls180.v:5888.43-5888.148" + cell $and $and$ls180.v:5888$1390 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5892$1389_Y - connect \B $eq$ls180.v:5892$1390_Y - connect \Y $and$ls180.v:5892$1391_Y + connect \A $and$ls180.v:5888$1388_Y + connect \B $eq$ls180.v:5888$1389_Y + connect \Y $and$ls180.v:5888$1390_Y end - attribute \src "ls180.v:5893.44-5893.100" - cell $and $and$ls180.v:5893$1393 + attribute \src "ls180.v:5889.44-5889.100" + cell $and $and$ls180.v:5889$1392 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5893$1392_Y - connect \Y $and$ls180.v:5893$1393_Y + connect \B $not$ls180.v:5889$1391_Y + connect \Y $and$ls180.v:5889$1392_Y end - attribute \src "ls180.v:5893.43-5893.151" - cell $and $and$ls180.v:5893$1395 + attribute \src "ls180.v:5889.43-5889.151" + cell $and $and$ls180.v:5889$1394 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5893$1393_Y - connect \B $eq$ls180.v:5893$1394_Y - connect \Y $and$ls180.v:5893$1395_Y + connect \A $and$ls180.v:5889$1392_Y + connect \B $eq$ls180.v:5889$1393_Y + connect \Y $and$ls180.v:5889$1394_Y end - attribute \src "ls180.v:5895.44-5895.97" - cell $and $and$ls180.v:5895$1396 + attribute \src "ls180.v:5891.44-5891.97" + cell $and $and$ls180.v:5891$1395 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88901,43 +88897,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5895$1396_Y + connect \Y $and$ls180.v:5891$1395_Y end - attribute \src "ls180.v:5895.43-5895.148" - cell $and $and$ls180.v:5895$1398 + attribute \src "ls180.v:5891.43-5891.148" + cell $and $and$ls180.v:5891$1397 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5895$1396_Y - connect \B $eq$ls180.v:5895$1397_Y - connect \Y $and$ls180.v:5895$1398_Y + connect \A $and$ls180.v:5891$1395_Y + connect \B $eq$ls180.v:5891$1396_Y + connect \Y $and$ls180.v:5891$1397_Y end - attribute \src "ls180.v:5896.44-5896.100" - cell $and $and$ls180.v:5896$1400 + attribute \src "ls180.v:5892.44-5892.100" + cell $and $and$ls180.v:5892$1399 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5896$1399_Y - connect \Y $and$ls180.v:5896$1400_Y + connect \B $not$ls180.v:5892$1398_Y + connect \Y $and$ls180.v:5892$1399_Y end - attribute \src "ls180.v:5896.43-5896.151" - cell $and $and$ls180.v:5896$1402 + attribute \src "ls180.v:5892.43-5892.151" + cell $and $and$ls180.v:5892$1401 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5896$1400_Y - connect \B $eq$ls180.v:5896$1401_Y - connect \Y $and$ls180.v:5896$1402_Y + connect \A $and$ls180.v:5892$1399_Y + connect \B $eq$ls180.v:5892$1400_Y + connect \Y $and$ls180.v:5892$1401_Y end - attribute \src "ls180.v:5898.44-5898.97" - cell $and $and$ls180.v:5898$1403 + attribute \src "ls180.v:5894.44-5894.97" + cell $and $and$ls180.v:5894$1402 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88945,43 +88941,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5898$1403_Y + connect \Y $and$ls180.v:5894$1402_Y end - attribute \src "ls180.v:5898.43-5898.148" - cell $and $and$ls180.v:5898$1405 + attribute \src "ls180.v:5894.43-5894.148" + cell $and $and$ls180.v:5894$1404 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5898$1403_Y - connect \B $eq$ls180.v:5898$1404_Y - connect \Y $and$ls180.v:5898$1405_Y + connect \A $and$ls180.v:5894$1402_Y + connect \B $eq$ls180.v:5894$1403_Y + connect \Y $and$ls180.v:5894$1404_Y end - attribute \src "ls180.v:5899.44-5899.100" - cell $and $and$ls180.v:5899$1407 + attribute \src "ls180.v:5895.44-5895.100" + cell $and $and$ls180.v:5895$1406 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5899$1406_Y - connect \Y $and$ls180.v:5899$1407_Y + connect \B $not$ls180.v:5895$1405_Y + connect \Y $and$ls180.v:5895$1406_Y end - attribute \src "ls180.v:5899.43-5899.151" - cell $and $and$ls180.v:5899$1409 + attribute \src "ls180.v:5895.43-5895.151" + cell $and $and$ls180.v:5895$1408 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5899$1407_Y - connect \B $eq$ls180.v:5899$1408_Y - connect \Y $and$ls180.v:5899$1409_Y + connect \A $and$ls180.v:5895$1406_Y + connect \B $eq$ls180.v:5895$1407_Y + connect \Y $and$ls180.v:5895$1408_Y end - attribute \src "ls180.v:5901.41-5901.94" - cell $and $and$ls180.v:5901$1410 + attribute \src "ls180.v:5897.41-5897.94" + cell $and $and$ls180.v:5897$1409 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88989,43 +88985,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5901$1410_Y + connect \Y $and$ls180.v:5897$1409_Y end - attribute \src "ls180.v:5901.40-5901.145" - cell $and $and$ls180.v:5901$1412 + attribute \src "ls180.v:5897.40-5897.145" + cell $and $and$ls180.v:5897$1411 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5901$1410_Y - connect \B $eq$ls180.v:5901$1411_Y - connect \Y $and$ls180.v:5901$1412_Y + connect \A $and$ls180.v:5897$1409_Y + connect \B $eq$ls180.v:5897$1410_Y + connect \Y $and$ls180.v:5897$1411_Y end - attribute \src "ls180.v:5902.41-5902.97" - cell $and $and$ls180.v:5902$1414 + attribute \src "ls180.v:5898.41-5898.97" + cell $and $and$ls180.v:5898$1413 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5902$1413_Y - connect \Y $and$ls180.v:5902$1414_Y + connect \B $not$ls180.v:5898$1412_Y + connect \Y $and$ls180.v:5898$1413_Y end - attribute \src "ls180.v:5902.40-5902.148" - cell $and $and$ls180.v:5902$1416 + attribute \src "ls180.v:5898.40-5898.148" + cell $and $and$ls180.v:5898$1415 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5902$1414_Y - connect \B $eq$ls180.v:5902$1415_Y - connect \Y $and$ls180.v:5902$1416_Y + connect \A $and$ls180.v:5898$1413_Y + connect \B $eq$ls180.v:5898$1414_Y + connect \Y $and$ls180.v:5898$1415_Y end - attribute \src "ls180.v:5904.42-5904.95" - cell $and $and$ls180.v:5904$1417 + attribute \src "ls180.v:5900.42-5900.95" + cell $and $and$ls180.v:5900$1416 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -89033,43 +89029,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5904$1417_Y + connect \Y $and$ls180.v:5900$1416_Y end - attribute \src "ls180.v:5904.41-5904.146" - cell $and $and$ls180.v:5904$1419 + attribute \src "ls180.v:5900.41-5900.146" + cell $and $and$ls180.v:5900$1418 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5904$1417_Y - connect \B $eq$ls180.v:5904$1418_Y - connect \Y $and$ls180.v:5904$1419_Y + connect \A $and$ls180.v:5900$1416_Y + connect \B $eq$ls180.v:5900$1417_Y + connect \Y $and$ls180.v:5900$1418_Y end - attribute \src "ls180.v:5905.42-5905.98" - cell $and $and$ls180.v:5905$1421 + attribute \src "ls180.v:5901.42-5901.98" + cell $and $and$ls180.v:5901$1420 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5905$1420_Y - connect \Y $and$ls180.v:5905$1421_Y + connect \B $not$ls180.v:5901$1419_Y + connect \Y $and$ls180.v:5901$1420_Y end - attribute \src "ls180.v:5905.41-5905.149" - cell $and $and$ls180.v:5905$1423 + attribute \src "ls180.v:5901.41-5901.149" + cell $and $and$ls180.v:5901$1422 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5905$1421_Y - connect \B $eq$ls180.v:5905$1422_Y - connect \Y $and$ls180.v:5905$1423_Y + connect \A $and$ls180.v:5901$1420_Y + connect \B $eq$ls180.v:5901$1421_Y + connect \Y $and$ls180.v:5901$1422_Y end - attribute \src "ls180.v:5924.46-5924.99" - cell $and $and$ls180.v:5924$1425 + attribute \src "ls180.v:5920.46-5920.99" + cell $and $and$ls180.v:5920$1424 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -89077,43 +89073,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5924$1425_Y + connect \Y $and$ls180.v:5920$1424_Y end - attribute \src "ls180.v:5924.45-5924.149" - cell $and $and$ls180.v:5924$1427 + attribute \src "ls180.v:5920.45-5920.149" + cell $and $and$ls180.v:5920$1426 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5924$1425_Y - connect \B $eq$ls180.v:5924$1426_Y - connect \Y $and$ls180.v:5924$1427_Y + connect \A $and$ls180.v:5920$1424_Y + connect \B $eq$ls180.v:5920$1425_Y + connect \Y $and$ls180.v:5920$1426_Y end - attribute \src "ls180.v:5925.46-5925.102" - cell $and $and$ls180.v:5925$1429 + attribute \src "ls180.v:5921.46-5921.102" + cell $and $and$ls180.v:5921$1428 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5925$1428_Y - connect \Y $and$ls180.v:5925$1429_Y + connect \B $not$ls180.v:5921$1427_Y + connect \Y $and$ls180.v:5921$1428_Y end - attribute \src "ls180.v:5925.45-5925.152" - cell $and $and$ls180.v:5925$1431 + attribute \src "ls180.v:5921.45-5921.152" + cell $and $and$ls180.v:5921$1430 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5925$1429_Y - connect \B $eq$ls180.v:5925$1430_Y - connect \Y $and$ls180.v:5925$1431_Y + connect \A $and$ls180.v:5921$1428_Y + connect \B $eq$ls180.v:5921$1429_Y + connect \Y $and$ls180.v:5921$1430_Y end - attribute \src "ls180.v:5927.46-5927.99" - cell $and $and$ls180.v:5927$1432 + attribute \src "ls180.v:5923.46-5923.99" + cell $and $and$ls180.v:5923$1431 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -89121,43 +89117,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5927$1432_Y + connect \Y $and$ls180.v:5923$1431_Y end - attribute \src "ls180.v:5927.45-5927.149" - cell $and $and$ls180.v:5927$1434 + attribute \src "ls180.v:5923.45-5923.149" + cell $and $and$ls180.v:5923$1433 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5927$1432_Y - connect \B $eq$ls180.v:5927$1433_Y - connect \Y $and$ls180.v:5927$1434_Y + connect \A $and$ls180.v:5923$1431_Y + connect \B $eq$ls180.v:5923$1432_Y + connect \Y $and$ls180.v:5923$1433_Y end - attribute \src "ls180.v:5928.46-5928.102" - cell $and $and$ls180.v:5928$1436 + attribute \src "ls180.v:5924.46-5924.102" + cell $and $and$ls180.v:5924$1435 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5928$1435_Y - connect \Y $and$ls180.v:5928$1436_Y + connect \B $not$ls180.v:5924$1434_Y + connect \Y $and$ls180.v:5924$1435_Y end - attribute \src "ls180.v:5928.45-5928.152" - cell $and $and$ls180.v:5928$1438 + attribute \src "ls180.v:5924.45-5924.152" + cell $and $and$ls180.v:5924$1437 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5928$1436_Y - connect \B $eq$ls180.v:5928$1437_Y - connect \Y $and$ls180.v:5928$1438_Y + connect \A $and$ls180.v:5924$1435_Y + connect \B $eq$ls180.v:5924$1436_Y + connect \Y $and$ls180.v:5924$1437_Y end - attribute \src "ls180.v:5930.46-5930.99" - cell $and $and$ls180.v:5930$1439 + attribute \src "ls180.v:5926.46-5926.99" + cell $and $and$ls180.v:5926$1438 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -89165,43 +89161,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5930$1439_Y + connect \Y $and$ls180.v:5926$1438_Y end - attribute \src "ls180.v:5930.45-5930.149" - cell $and $and$ls180.v:5930$1441 + attribute \src "ls180.v:5926.45-5926.149" + cell $and $and$ls180.v:5926$1440 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5930$1439_Y - connect \B $eq$ls180.v:5930$1440_Y - connect \Y $and$ls180.v:5930$1441_Y + connect \A $and$ls180.v:5926$1438_Y + connect \B $eq$ls180.v:5926$1439_Y + connect \Y $and$ls180.v:5926$1440_Y end - attribute \src "ls180.v:5931.46-5931.102" - cell $and $and$ls180.v:5931$1443 + attribute \src "ls180.v:5927.46-5927.102" + cell $and $and$ls180.v:5927$1442 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5931$1442_Y - connect \Y $and$ls180.v:5931$1443_Y + connect \B $not$ls180.v:5927$1441_Y + connect \Y $and$ls180.v:5927$1442_Y end - attribute \src "ls180.v:5931.45-5931.152" - cell $and $and$ls180.v:5931$1445 + attribute \src "ls180.v:5927.45-5927.152" + cell $and $and$ls180.v:5927$1444 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5931$1443_Y - connect \B $eq$ls180.v:5931$1444_Y - connect \Y $and$ls180.v:5931$1445_Y + connect \A $and$ls180.v:5927$1442_Y + connect \B $eq$ls180.v:5927$1443_Y + connect \Y $and$ls180.v:5927$1444_Y end - attribute \src "ls180.v:5933.46-5933.99" - cell $and $and$ls180.v:5933$1446 + attribute \src "ls180.v:5929.46-5929.99" + cell $and $and$ls180.v:5929$1445 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -89209,43 +89205,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5933$1446_Y + connect \Y $and$ls180.v:5929$1445_Y end - attribute \src "ls180.v:5933.45-5933.149" - cell $and $and$ls180.v:5933$1448 + attribute \src "ls180.v:5929.45-5929.149" + cell $and $and$ls180.v:5929$1447 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5933$1446_Y - connect \B $eq$ls180.v:5933$1447_Y - connect \Y $and$ls180.v:5933$1448_Y + connect \A $and$ls180.v:5929$1445_Y + connect \B $eq$ls180.v:5929$1446_Y + connect \Y $and$ls180.v:5929$1447_Y end - attribute \src "ls180.v:5934.46-5934.102" - cell $and $and$ls180.v:5934$1450 + attribute \src "ls180.v:5930.46-5930.102" + cell $and $and$ls180.v:5930$1449 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5934$1449_Y - connect \Y $and$ls180.v:5934$1450_Y + connect \B $not$ls180.v:5930$1448_Y + connect \Y $and$ls180.v:5930$1449_Y end - attribute \src "ls180.v:5934.45-5934.152" - cell $and $and$ls180.v:5934$1452 + attribute \src "ls180.v:5930.45-5930.152" + cell $and $and$ls180.v:5930$1451 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5934$1450_Y - connect \B $eq$ls180.v:5934$1451_Y - connect \Y $and$ls180.v:5934$1452_Y + connect \A $and$ls180.v:5930$1449_Y + connect \B $eq$ls180.v:5930$1450_Y + connect \Y $and$ls180.v:5930$1451_Y end - attribute \src "ls180.v:5936.45-5936.98" - cell $and $and$ls180.v:5936$1453 + attribute \src "ls180.v:5932.45-5932.98" + cell $and $and$ls180.v:5932$1452 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -89253,43 +89249,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5936$1453_Y + connect \Y $and$ls180.v:5932$1452_Y end - attribute \src "ls180.v:5936.44-5936.148" - cell $and $and$ls180.v:5936$1455 + attribute \src "ls180.v:5932.44-5932.148" + cell $and $and$ls180.v:5932$1454 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5936$1453_Y - connect \B $eq$ls180.v:5936$1454_Y - connect \Y $and$ls180.v:5936$1455_Y + connect \A $and$ls180.v:5932$1452_Y + connect \B $eq$ls180.v:5932$1453_Y + connect \Y $and$ls180.v:5932$1454_Y end - attribute \src "ls180.v:5937.45-5937.101" - cell $and $and$ls180.v:5937$1457 + attribute \src "ls180.v:5933.45-5933.101" + cell $and $and$ls180.v:5933$1456 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5937$1456_Y - connect \Y $and$ls180.v:5937$1457_Y + connect \B $not$ls180.v:5933$1455_Y + connect \Y $and$ls180.v:5933$1456_Y end - attribute \src "ls180.v:5937.44-5937.151" - cell $and $and$ls180.v:5937$1459 + attribute \src "ls180.v:5933.44-5933.151" + cell $and $and$ls180.v:5933$1458 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5937$1457_Y - connect \B $eq$ls180.v:5937$1458_Y - connect \Y $and$ls180.v:5937$1459_Y + connect \A $and$ls180.v:5933$1456_Y + connect \B $eq$ls180.v:5933$1457_Y + connect \Y $and$ls180.v:5933$1458_Y end - attribute \src "ls180.v:5939.45-5939.98" - cell $and $and$ls180.v:5939$1460 + attribute \src "ls180.v:5935.45-5935.98" + cell $and $and$ls180.v:5935$1459 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -89297,43 +89293,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5939$1460_Y + connect \Y $and$ls180.v:5935$1459_Y end - attribute \src "ls180.v:5939.44-5939.148" - cell $and $and$ls180.v:5939$1462 + attribute \src "ls180.v:5935.44-5935.148" + cell $and $and$ls180.v:5935$1461 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5939$1460_Y - connect \B $eq$ls180.v:5939$1461_Y - connect \Y $and$ls180.v:5939$1462_Y + connect \A $and$ls180.v:5935$1459_Y + connect \B $eq$ls180.v:5935$1460_Y + connect \Y $and$ls180.v:5935$1461_Y end - attribute \src "ls180.v:5940.45-5940.101" - cell $and $and$ls180.v:5940$1464 + attribute \src "ls180.v:5936.45-5936.101" + cell $and $and$ls180.v:5936$1463 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5940$1463_Y - connect \Y $and$ls180.v:5940$1464_Y + connect \B $not$ls180.v:5936$1462_Y + connect \Y $and$ls180.v:5936$1463_Y end - attribute \src "ls180.v:5940.44-5940.151" - cell $and $and$ls180.v:5940$1466 + attribute \src "ls180.v:5936.44-5936.151" + cell $and $and$ls180.v:5936$1465 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5940$1464_Y - connect \B $eq$ls180.v:5940$1465_Y - connect \Y $and$ls180.v:5940$1466_Y + connect \A $and$ls180.v:5936$1463_Y + connect \B $eq$ls180.v:5936$1464_Y + connect \Y $and$ls180.v:5936$1465_Y end - attribute \src "ls180.v:5942.45-5942.98" - cell $and $and$ls180.v:5942$1467 + attribute \src "ls180.v:5938.45-5938.98" + cell $and $and$ls180.v:5938$1466 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -89341,43 +89337,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5942$1467_Y + connect \Y $and$ls180.v:5938$1466_Y end - attribute \src "ls180.v:5942.44-5942.148" - cell $and $and$ls180.v:5942$1469 + attribute \src "ls180.v:5938.44-5938.148" + cell $and $and$ls180.v:5938$1468 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5942$1467_Y - connect \B $eq$ls180.v:5942$1468_Y - connect \Y $and$ls180.v:5942$1469_Y + connect \A $and$ls180.v:5938$1466_Y + connect \B $eq$ls180.v:5938$1467_Y + connect \Y $and$ls180.v:5938$1468_Y end - attribute \src "ls180.v:5943.45-5943.101" - cell $and $and$ls180.v:5943$1471 + attribute \src "ls180.v:5939.45-5939.101" + cell $and $and$ls180.v:5939$1470 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5943$1470_Y - connect \Y $and$ls180.v:5943$1471_Y + connect \B $not$ls180.v:5939$1469_Y + connect \Y $and$ls180.v:5939$1470_Y end - attribute \src "ls180.v:5943.44-5943.151" - cell $and $and$ls180.v:5943$1473 + attribute \src "ls180.v:5939.44-5939.151" + cell $and $and$ls180.v:5939$1472 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5943$1471_Y - connect \B $eq$ls180.v:5943$1472_Y - connect \Y $and$ls180.v:5943$1473_Y + connect \A $and$ls180.v:5939$1470_Y + connect \B $eq$ls180.v:5939$1471_Y + connect \Y $and$ls180.v:5939$1472_Y end - attribute \src "ls180.v:5945.45-5945.98" - cell $and $and$ls180.v:5945$1474 + attribute \src "ls180.v:5941.45-5941.98" + cell $and $and$ls180.v:5941$1473 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -89385,43 +89381,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5945$1474_Y + connect \Y $and$ls180.v:5941$1473_Y end - attribute \src "ls180.v:5945.44-5945.148" - cell $and $and$ls180.v:5945$1476 + attribute \src "ls180.v:5941.44-5941.148" + cell $and $and$ls180.v:5941$1475 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5945$1474_Y - connect \B $eq$ls180.v:5945$1475_Y - connect \Y $and$ls180.v:5945$1476_Y + connect \A $and$ls180.v:5941$1473_Y + connect \B $eq$ls180.v:5941$1474_Y + connect \Y $and$ls180.v:5941$1475_Y end - attribute \src "ls180.v:5946.45-5946.101" - cell $and $and$ls180.v:5946$1478 + attribute \src "ls180.v:5942.45-5942.101" + cell $and $and$ls180.v:5942$1477 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5946$1477_Y - connect \Y $and$ls180.v:5946$1478_Y + connect \B $not$ls180.v:5942$1476_Y + connect \Y $and$ls180.v:5942$1477_Y end - attribute \src "ls180.v:5946.44-5946.151" - cell $and $and$ls180.v:5946$1480 + attribute \src "ls180.v:5942.44-5942.151" + cell $and $and$ls180.v:5942$1479 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5946$1478_Y - connect \B $eq$ls180.v:5946$1479_Y - connect \Y $and$ls180.v:5946$1480_Y + connect \A $and$ls180.v:5942$1477_Y + connect \B $eq$ls180.v:5942$1478_Y + connect \Y $and$ls180.v:5942$1479_Y end - attribute \src "ls180.v:5948.36-5948.89" - cell $and $and$ls180.v:5948$1481 + attribute \src "ls180.v:5944.36-5944.89" + cell $and $and$ls180.v:5944$1480 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -89429,43 +89425,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5948$1481_Y + connect \Y $and$ls180.v:5944$1480_Y end - attribute \src "ls180.v:5948.35-5948.139" - cell $and $and$ls180.v:5948$1483 + attribute \src "ls180.v:5944.35-5944.139" + cell $and $and$ls180.v:5944$1482 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5948$1481_Y - connect \B $eq$ls180.v:5948$1482_Y - connect \Y $and$ls180.v:5948$1483_Y + connect \A $and$ls180.v:5944$1480_Y + connect \B $eq$ls180.v:5944$1481_Y + connect \Y $and$ls180.v:5944$1482_Y end - attribute \src "ls180.v:5949.36-5949.92" - cell $and $and$ls180.v:5949$1485 + attribute \src "ls180.v:5945.36-5945.92" + cell $and $and$ls180.v:5945$1484 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5949$1484_Y - connect \Y $and$ls180.v:5949$1485_Y + connect \B $not$ls180.v:5945$1483_Y + connect \Y $and$ls180.v:5945$1484_Y end - attribute \src "ls180.v:5949.35-5949.142" - cell $and $and$ls180.v:5949$1487 + attribute \src "ls180.v:5945.35-5945.142" + cell $and $and$ls180.v:5945$1486 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5949$1485_Y - connect \B $eq$ls180.v:5949$1486_Y - connect \Y $and$ls180.v:5949$1487_Y + connect \A $and$ls180.v:5945$1484_Y + connect \B $eq$ls180.v:5945$1485_Y + connect \Y $and$ls180.v:5945$1486_Y end - attribute \src "ls180.v:5951.47-5951.100" - cell $and $and$ls180.v:5951$1488 + attribute \src "ls180.v:5947.47-5947.100" + cell $and $and$ls180.v:5947$1487 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -89473,43 +89469,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5951$1488_Y + connect \Y $and$ls180.v:5947$1487_Y end - attribute \src "ls180.v:5951.46-5951.150" - cell $and $and$ls180.v:5951$1490 + attribute \src "ls180.v:5947.46-5947.150" + cell $and $and$ls180.v:5947$1489 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5951$1488_Y - connect \B $eq$ls180.v:5951$1489_Y - connect \Y $and$ls180.v:5951$1490_Y + connect \A $and$ls180.v:5947$1487_Y + connect \B $eq$ls180.v:5947$1488_Y + connect \Y $and$ls180.v:5947$1489_Y end - attribute \src "ls180.v:5952.47-5952.103" - cell $and $and$ls180.v:5952$1492 + attribute \src "ls180.v:5948.47-5948.103" + cell $and $and$ls180.v:5948$1491 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5952$1491_Y - connect \Y $and$ls180.v:5952$1492_Y + connect \B $not$ls180.v:5948$1490_Y + connect \Y $and$ls180.v:5948$1491_Y end - attribute \src "ls180.v:5952.46-5952.153" - cell $and $and$ls180.v:5952$1494 + attribute \src "ls180.v:5948.46-5948.153" + cell $and $and$ls180.v:5948$1493 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5952$1492_Y - connect \B $eq$ls180.v:5952$1493_Y - connect \Y $and$ls180.v:5952$1494_Y + connect \A $and$ls180.v:5948$1491_Y + connect \B $eq$ls180.v:5948$1492_Y + connect \Y $and$ls180.v:5948$1493_Y end - attribute \src "ls180.v:5954.47-5954.100" - cell $and $and$ls180.v:5954$1495 + attribute \src "ls180.v:5950.47-5950.100" + cell $and $and$ls180.v:5950$1494 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -89517,43 +89513,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5954$1495_Y + connect \Y $and$ls180.v:5950$1494_Y end - attribute \src "ls180.v:5954.46-5954.151" - cell $and $and$ls180.v:5954$1497 + attribute \src "ls180.v:5950.46-5950.151" + cell $and $and$ls180.v:5950$1496 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5954$1495_Y - connect \B $eq$ls180.v:5954$1496_Y - connect \Y $and$ls180.v:5954$1497_Y + connect \A $and$ls180.v:5950$1494_Y + connect \B $eq$ls180.v:5950$1495_Y + connect \Y $and$ls180.v:5950$1496_Y end - attribute \src "ls180.v:5955.47-5955.103" - cell $and $and$ls180.v:5955$1499 + attribute \src "ls180.v:5951.47-5951.103" + cell $and $and$ls180.v:5951$1498 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5955$1498_Y - connect \Y $and$ls180.v:5955$1499_Y + connect \B $not$ls180.v:5951$1497_Y + connect \Y $and$ls180.v:5951$1498_Y end - attribute \src "ls180.v:5955.46-5955.154" - cell $and $and$ls180.v:5955$1501 + attribute \src "ls180.v:5951.46-5951.154" + cell $and $and$ls180.v:5951$1500 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5955$1499_Y - connect \B $eq$ls180.v:5955$1500_Y - connect \Y $and$ls180.v:5955$1501_Y + connect \A $and$ls180.v:5951$1498_Y + connect \B $eq$ls180.v:5951$1499_Y + connect \Y $and$ls180.v:5951$1500_Y end - attribute \src "ls180.v:5957.47-5957.100" - cell $and $and$ls180.v:5957$1502 + attribute \src "ls180.v:5953.47-5953.100" + cell $and $and$ls180.v:5953$1501 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -89561,43 +89557,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5957$1502_Y + connect \Y $and$ls180.v:5953$1501_Y end - attribute \src "ls180.v:5957.46-5957.151" - cell $and $and$ls180.v:5957$1504 + attribute \src "ls180.v:5953.46-5953.151" + cell $and $and$ls180.v:5953$1503 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5957$1502_Y - connect \B $eq$ls180.v:5957$1503_Y - connect \Y $and$ls180.v:5957$1504_Y + connect \A $and$ls180.v:5953$1501_Y + connect \B $eq$ls180.v:5953$1502_Y + connect \Y $and$ls180.v:5953$1503_Y end - attribute \src "ls180.v:5958.47-5958.103" - cell $and $and$ls180.v:5958$1506 + attribute \src "ls180.v:5954.47-5954.103" + cell $and $and$ls180.v:5954$1505 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5958$1505_Y - connect \Y $and$ls180.v:5958$1506_Y + connect \B $not$ls180.v:5954$1504_Y + connect \Y $and$ls180.v:5954$1505_Y end - attribute \src "ls180.v:5958.46-5958.154" - cell $and $and$ls180.v:5958$1508 + attribute \src "ls180.v:5954.46-5954.154" + cell $and $and$ls180.v:5954$1507 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5958$1506_Y - connect \B $eq$ls180.v:5958$1507_Y - connect \Y $and$ls180.v:5958$1508_Y + connect \A $and$ls180.v:5954$1505_Y + connect \B $eq$ls180.v:5954$1506_Y + connect \Y $and$ls180.v:5954$1507_Y end - attribute \src "ls180.v:5960.47-5960.100" - cell $and $and$ls180.v:5960$1509 + attribute \src "ls180.v:5956.47-5956.100" + cell $and $and$ls180.v:5956$1508 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -89605,43 +89601,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5960$1509_Y + connect \Y $and$ls180.v:5956$1508_Y end - attribute \src "ls180.v:5960.46-5960.151" - cell $and $and$ls180.v:5960$1511 + attribute \src "ls180.v:5956.46-5956.151" + cell $and $and$ls180.v:5956$1510 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5960$1509_Y - connect \B $eq$ls180.v:5960$1510_Y - connect \Y $and$ls180.v:5960$1511_Y + connect \A $and$ls180.v:5956$1508_Y + connect \B $eq$ls180.v:5956$1509_Y + connect \Y $and$ls180.v:5956$1510_Y end - attribute \src "ls180.v:5961.47-5961.103" - cell $and $and$ls180.v:5961$1513 + attribute \src "ls180.v:5957.47-5957.103" + cell $and $and$ls180.v:5957$1512 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5961$1512_Y - connect \Y $and$ls180.v:5961$1513_Y + connect \B $not$ls180.v:5957$1511_Y + connect \Y $and$ls180.v:5957$1512_Y end - attribute \src "ls180.v:5961.46-5961.154" - cell $and $and$ls180.v:5961$1515 + attribute \src "ls180.v:5957.46-5957.154" + cell $and $and$ls180.v:5957$1514 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5961$1513_Y - connect \B $eq$ls180.v:5961$1514_Y - connect \Y $and$ls180.v:5961$1515_Y + connect \A $and$ls180.v:5957$1512_Y + connect \B $eq$ls180.v:5957$1513_Y + connect \Y $and$ls180.v:5957$1514_Y end - attribute \src "ls180.v:5963.47-5963.100" - cell $and $and$ls180.v:5963$1516 + attribute \src "ls180.v:5959.47-5959.100" + cell $and $and$ls180.v:5959$1515 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -89649,43 +89645,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5963$1516_Y + connect \Y $and$ls180.v:5959$1515_Y end - attribute \src "ls180.v:5963.46-5963.151" - cell $and $and$ls180.v:5963$1518 + attribute \src "ls180.v:5959.46-5959.151" + cell $and $and$ls180.v:5959$1517 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5963$1516_Y - connect \B $eq$ls180.v:5963$1517_Y - connect \Y $and$ls180.v:5963$1518_Y + connect \A $and$ls180.v:5959$1515_Y + connect \B $eq$ls180.v:5959$1516_Y + connect \Y $and$ls180.v:5959$1517_Y end - attribute \src "ls180.v:5964.47-5964.103" - cell $and $and$ls180.v:5964$1520 + attribute \src "ls180.v:5960.47-5960.103" + cell $and $and$ls180.v:5960$1519 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5964$1519_Y - connect \Y $and$ls180.v:5964$1520_Y + connect \B $not$ls180.v:5960$1518_Y + connect \Y $and$ls180.v:5960$1519_Y end - attribute \src "ls180.v:5964.46-5964.154" - cell $and $and$ls180.v:5964$1522 + attribute \src "ls180.v:5960.46-5960.154" + cell $and $and$ls180.v:5960$1521 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5964$1520_Y - connect \B $eq$ls180.v:5964$1521_Y - connect \Y $and$ls180.v:5964$1522_Y + connect \A $and$ls180.v:5960$1519_Y + connect \B $eq$ls180.v:5960$1520_Y + connect \Y $and$ls180.v:5960$1521_Y end - attribute \src "ls180.v:5966.47-5966.100" - cell $and $and$ls180.v:5966$1523 + attribute \src "ls180.v:5962.47-5962.100" + cell $and $and$ls180.v:5962$1522 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -89693,43 +89689,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5966$1523_Y + connect \Y $and$ls180.v:5962$1522_Y end - attribute \src "ls180.v:5966.46-5966.151" - cell $and $and$ls180.v:5966$1525 + attribute \src "ls180.v:5962.46-5962.151" + cell $and $and$ls180.v:5962$1524 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5966$1523_Y - connect \B $eq$ls180.v:5966$1524_Y - connect \Y $and$ls180.v:5966$1525_Y + connect \A $and$ls180.v:5962$1522_Y + connect \B $eq$ls180.v:5962$1523_Y + connect \Y $and$ls180.v:5962$1524_Y end - attribute \src "ls180.v:5967.47-5967.103" - cell $and $and$ls180.v:5967$1527 + attribute \src "ls180.v:5963.47-5963.103" + cell $and $and$ls180.v:5963$1526 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5967$1526_Y - connect \Y $and$ls180.v:5967$1527_Y + connect \B $not$ls180.v:5963$1525_Y + connect \Y $and$ls180.v:5963$1526_Y end - attribute \src "ls180.v:5967.46-5967.154" - cell $and $and$ls180.v:5967$1529 + attribute \src "ls180.v:5963.46-5963.154" + cell $and $and$ls180.v:5963$1528 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5967$1527_Y - connect \B $eq$ls180.v:5967$1528_Y - connect \Y $and$ls180.v:5967$1529_Y + connect \A $and$ls180.v:5963$1526_Y + connect \B $eq$ls180.v:5963$1527_Y + connect \Y $and$ls180.v:5963$1528_Y end - attribute \src "ls180.v:5969.46-5969.99" - cell $and $and$ls180.v:5969$1530 + attribute \src "ls180.v:5965.46-5965.99" + cell $and $and$ls180.v:5965$1529 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -89737,43 +89733,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5969$1530_Y + connect \Y $and$ls180.v:5965$1529_Y end - attribute \src "ls180.v:5969.45-5969.150" - cell $and $and$ls180.v:5969$1532 + attribute \src "ls180.v:5965.45-5965.150" + cell $and $and$ls180.v:5965$1531 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5969$1530_Y - connect \B $eq$ls180.v:5969$1531_Y - connect \Y $and$ls180.v:5969$1532_Y + connect \A $and$ls180.v:5965$1529_Y + connect \B $eq$ls180.v:5965$1530_Y + connect \Y $and$ls180.v:5965$1531_Y end - attribute \src "ls180.v:5970.46-5970.102" - cell $and $and$ls180.v:5970$1534 + attribute \src "ls180.v:5966.46-5966.102" + cell $and $and$ls180.v:5966$1533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5970$1533_Y - connect \Y $and$ls180.v:5970$1534_Y + connect \B $not$ls180.v:5966$1532_Y + connect \Y $and$ls180.v:5966$1533_Y end - attribute \src "ls180.v:5970.45-5970.153" - cell $and $and$ls180.v:5970$1536 + attribute \src "ls180.v:5966.45-5966.153" + cell $and $and$ls180.v:5966$1535 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5970$1534_Y - connect \B $eq$ls180.v:5970$1535_Y - connect \Y $and$ls180.v:5970$1536_Y + connect \A $and$ls180.v:5966$1533_Y + connect \B $eq$ls180.v:5966$1534_Y + connect \Y $and$ls180.v:5966$1535_Y end - attribute \src "ls180.v:5972.46-5972.99" - cell $and $and$ls180.v:5972$1537 + attribute \src "ls180.v:5968.46-5968.99" + cell $and $and$ls180.v:5968$1536 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -89781,43 +89777,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5972$1537_Y + connect \Y $and$ls180.v:5968$1536_Y end - attribute \src "ls180.v:5972.45-5972.150" - cell $and $and$ls180.v:5972$1539 + attribute \src "ls180.v:5968.45-5968.150" + cell $and $and$ls180.v:5968$1538 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5972$1537_Y - connect \B $eq$ls180.v:5972$1538_Y - connect \Y $and$ls180.v:5972$1539_Y + connect \A $and$ls180.v:5968$1536_Y + connect \B $eq$ls180.v:5968$1537_Y + connect \Y $and$ls180.v:5968$1538_Y end - attribute \src "ls180.v:5973.46-5973.102" - cell $and $and$ls180.v:5973$1541 + attribute \src "ls180.v:5969.46-5969.102" + cell $and $and$ls180.v:5969$1540 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5973$1540_Y - connect \Y $and$ls180.v:5973$1541_Y + connect \B $not$ls180.v:5969$1539_Y + connect \Y $and$ls180.v:5969$1540_Y end - attribute \src "ls180.v:5973.45-5973.153" - cell $and $and$ls180.v:5973$1543 + attribute \src "ls180.v:5969.45-5969.153" + cell $and $and$ls180.v:5969$1542 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5973$1541_Y - connect \B $eq$ls180.v:5973$1542_Y - connect \Y $and$ls180.v:5973$1543_Y + connect \A $and$ls180.v:5969$1540_Y + connect \B $eq$ls180.v:5969$1541_Y + connect \Y $and$ls180.v:5969$1542_Y end - attribute \src "ls180.v:5975.46-5975.99" - cell $and $and$ls180.v:5975$1544 + attribute \src "ls180.v:5971.46-5971.99" + cell $and $and$ls180.v:5971$1543 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -89825,43 +89821,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5975$1544_Y + connect \Y $and$ls180.v:5971$1543_Y end - attribute \src "ls180.v:5975.45-5975.150" - cell $and $and$ls180.v:5975$1546 + attribute \src "ls180.v:5971.45-5971.150" + cell $and $and$ls180.v:5971$1545 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5975$1544_Y - connect \B $eq$ls180.v:5975$1545_Y - connect \Y $and$ls180.v:5975$1546_Y + connect \A $and$ls180.v:5971$1543_Y + connect \B $eq$ls180.v:5971$1544_Y + connect \Y $and$ls180.v:5971$1545_Y end - attribute \src "ls180.v:5976.46-5976.102" - cell $and $and$ls180.v:5976$1548 + attribute \src "ls180.v:5972.46-5972.102" + cell $and $and$ls180.v:5972$1547 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5976$1547_Y - connect \Y $and$ls180.v:5976$1548_Y + connect \B $not$ls180.v:5972$1546_Y + connect \Y $and$ls180.v:5972$1547_Y end - attribute \src "ls180.v:5976.45-5976.153" - cell $and $and$ls180.v:5976$1550 + attribute \src "ls180.v:5972.45-5972.153" + cell $and $and$ls180.v:5972$1549 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5976$1548_Y - connect \B $eq$ls180.v:5976$1549_Y - connect \Y $and$ls180.v:5976$1550_Y + connect \A $and$ls180.v:5972$1547_Y + connect \B $eq$ls180.v:5972$1548_Y + connect \Y $and$ls180.v:5972$1549_Y end - attribute \src "ls180.v:5978.46-5978.99" - cell $and $and$ls180.v:5978$1551 + attribute \src "ls180.v:5974.46-5974.99" + cell $and $and$ls180.v:5974$1550 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -89869,43 +89865,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5978$1551_Y + connect \Y $and$ls180.v:5974$1550_Y end - attribute \src "ls180.v:5978.45-5978.150" - cell $and $and$ls180.v:5978$1553 + attribute \src "ls180.v:5974.45-5974.150" + cell $and $and$ls180.v:5974$1552 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5978$1551_Y - connect \B $eq$ls180.v:5978$1552_Y - connect \Y $and$ls180.v:5978$1553_Y + connect \A $and$ls180.v:5974$1550_Y + connect \B $eq$ls180.v:5974$1551_Y + connect \Y $and$ls180.v:5974$1552_Y end - attribute \src "ls180.v:5979.46-5979.102" - cell $and $and$ls180.v:5979$1555 + attribute \src "ls180.v:5975.46-5975.102" + cell $and $and$ls180.v:5975$1554 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5979$1554_Y - connect \Y $and$ls180.v:5979$1555_Y + connect \B $not$ls180.v:5975$1553_Y + connect \Y $and$ls180.v:5975$1554_Y end - attribute \src "ls180.v:5979.45-5979.153" - cell $and $and$ls180.v:5979$1557 + attribute \src "ls180.v:5975.45-5975.153" + cell $and $and$ls180.v:5975$1556 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5979$1555_Y - connect \B $eq$ls180.v:5979$1556_Y - connect \Y $and$ls180.v:5979$1557_Y + connect \A $and$ls180.v:5975$1554_Y + connect \B $eq$ls180.v:5975$1555_Y + connect \Y $and$ls180.v:5975$1556_Y end - attribute \src "ls180.v:5981.46-5981.99" - cell $and $and$ls180.v:5981$1558 + attribute \src "ls180.v:5977.46-5977.99" + cell $and $and$ls180.v:5977$1557 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -89913,43 +89909,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5981$1558_Y + connect \Y $and$ls180.v:5977$1557_Y end - attribute \src "ls180.v:5981.45-5981.150" - cell $and $and$ls180.v:5981$1560 + attribute \src "ls180.v:5977.45-5977.150" + cell $and $and$ls180.v:5977$1559 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5981$1558_Y - connect \B $eq$ls180.v:5981$1559_Y - connect \Y $and$ls180.v:5981$1560_Y + connect \A $and$ls180.v:5977$1557_Y + connect \B $eq$ls180.v:5977$1558_Y + connect \Y $and$ls180.v:5977$1559_Y end - attribute \src "ls180.v:5982.46-5982.102" - cell $and $and$ls180.v:5982$1562 + attribute \src "ls180.v:5978.46-5978.102" + cell $and $and$ls180.v:5978$1561 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5982$1561_Y - connect \Y $and$ls180.v:5982$1562_Y + connect \B $not$ls180.v:5978$1560_Y + connect \Y $and$ls180.v:5978$1561_Y end - attribute \src "ls180.v:5982.45-5982.153" - cell $and $and$ls180.v:5982$1564 + attribute \src "ls180.v:5978.45-5978.153" + cell $and $and$ls180.v:5978$1563 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5982$1562_Y - connect \B $eq$ls180.v:5982$1563_Y - connect \Y $and$ls180.v:5982$1564_Y + connect \A $and$ls180.v:5978$1561_Y + connect \B $eq$ls180.v:5978$1562_Y + connect \Y $and$ls180.v:5978$1563_Y end - attribute \src "ls180.v:5984.46-5984.99" - cell $and $and$ls180.v:5984$1565 + attribute \src "ls180.v:5980.46-5980.99" + cell $and $and$ls180.v:5980$1564 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -89957,43 +89953,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5984$1565_Y + connect \Y $and$ls180.v:5980$1564_Y end - attribute \src "ls180.v:5984.45-5984.150" - cell $and $and$ls180.v:5984$1567 + attribute \src "ls180.v:5980.45-5980.150" + cell $and $and$ls180.v:5980$1566 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5984$1565_Y - connect \B $eq$ls180.v:5984$1566_Y - connect \Y $and$ls180.v:5984$1567_Y + connect \A $and$ls180.v:5980$1564_Y + connect \B $eq$ls180.v:5980$1565_Y + connect \Y $and$ls180.v:5980$1566_Y end - attribute \src "ls180.v:5985.46-5985.102" - cell $and $and$ls180.v:5985$1569 + attribute \src "ls180.v:5981.46-5981.102" + cell $and $and$ls180.v:5981$1568 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5985$1568_Y - connect \Y $and$ls180.v:5985$1569_Y + connect \B $not$ls180.v:5981$1567_Y + connect \Y $and$ls180.v:5981$1568_Y end - attribute \src "ls180.v:5985.45-5985.153" - cell $and $and$ls180.v:5985$1571 + attribute \src "ls180.v:5981.45-5981.153" + cell $and $and$ls180.v:5981$1570 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5985$1569_Y - connect \B $eq$ls180.v:5985$1570_Y - connect \Y $and$ls180.v:5985$1571_Y + connect \A $and$ls180.v:5981$1568_Y + connect \B $eq$ls180.v:5981$1569_Y + connect \Y $and$ls180.v:5981$1570_Y end - attribute \src "ls180.v:5987.46-5987.99" - cell $and $and$ls180.v:5987$1572 + attribute \src "ls180.v:5983.46-5983.99" + cell $and $and$ls180.v:5983$1571 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90001,43 +89997,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5987$1572_Y + connect \Y $and$ls180.v:5983$1571_Y end - attribute \src "ls180.v:5987.45-5987.150" - cell $and $and$ls180.v:5987$1574 + attribute \src "ls180.v:5983.45-5983.150" + cell $and $and$ls180.v:5983$1573 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5987$1572_Y - connect \B $eq$ls180.v:5987$1573_Y - connect \Y $and$ls180.v:5987$1574_Y + connect \A $and$ls180.v:5983$1571_Y + connect \B $eq$ls180.v:5983$1572_Y + connect \Y $and$ls180.v:5983$1573_Y end - attribute \src "ls180.v:5988.46-5988.102" - cell $and $and$ls180.v:5988$1576 + attribute \src "ls180.v:5984.46-5984.102" + cell $and $and$ls180.v:5984$1575 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5988$1575_Y - connect \Y $and$ls180.v:5988$1576_Y + connect \B $not$ls180.v:5984$1574_Y + connect \Y $and$ls180.v:5984$1575_Y end - attribute \src "ls180.v:5988.45-5988.153" - cell $and $and$ls180.v:5988$1578 + attribute \src "ls180.v:5984.45-5984.153" + cell $and $and$ls180.v:5984$1577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5988$1576_Y - connect \B $eq$ls180.v:5988$1577_Y - connect \Y $and$ls180.v:5988$1578_Y + connect \A $and$ls180.v:5984$1575_Y + connect \B $eq$ls180.v:5984$1576_Y + connect \Y $and$ls180.v:5984$1577_Y end - attribute \src "ls180.v:5990.46-5990.99" - cell $and $and$ls180.v:5990$1579 + attribute \src "ls180.v:5986.46-5986.99" + cell $and $and$ls180.v:5986$1578 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90045,43 +90041,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5990$1579_Y + connect \Y $and$ls180.v:5986$1578_Y end - attribute \src "ls180.v:5990.45-5990.150" - cell $and $and$ls180.v:5990$1581 + attribute \src "ls180.v:5986.45-5986.150" + cell $and $and$ls180.v:5986$1580 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5990$1579_Y - connect \B $eq$ls180.v:5990$1580_Y - connect \Y $and$ls180.v:5990$1581_Y + connect \A $and$ls180.v:5986$1578_Y + connect \B $eq$ls180.v:5986$1579_Y + connect \Y $and$ls180.v:5986$1580_Y end - attribute \src "ls180.v:5991.46-5991.102" - cell $and $and$ls180.v:5991$1583 + attribute \src "ls180.v:5987.46-5987.102" + cell $and $and$ls180.v:5987$1582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5991$1582_Y - connect \Y $and$ls180.v:5991$1583_Y + connect \B $not$ls180.v:5987$1581_Y + connect \Y $and$ls180.v:5987$1582_Y end - attribute \src "ls180.v:5991.45-5991.153" - cell $and $and$ls180.v:5991$1585 + attribute \src "ls180.v:5987.45-5987.153" + cell $and $and$ls180.v:5987$1584 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5991$1583_Y - connect \B $eq$ls180.v:5991$1584_Y - connect \Y $and$ls180.v:5991$1585_Y + connect \A $and$ls180.v:5987$1582_Y + connect \B $eq$ls180.v:5987$1583_Y + connect \Y $and$ls180.v:5987$1584_Y end - attribute \src "ls180.v:5993.46-5993.99" - cell $and $and$ls180.v:5993$1586 + attribute \src "ls180.v:5989.46-5989.99" + cell $and $and$ls180.v:5989$1585 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90089,43 +90085,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5993$1586_Y + connect \Y $and$ls180.v:5989$1585_Y end - attribute \src "ls180.v:5993.45-5993.150" - cell $and $and$ls180.v:5993$1588 + attribute \src "ls180.v:5989.45-5989.150" + cell $and $and$ls180.v:5989$1587 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5993$1586_Y - connect \B $eq$ls180.v:5993$1587_Y - connect \Y $and$ls180.v:5993$1588_Y + connect \A $and$ls180.v:5989$1585_Y + connect \B $eq$ls180.v:5989$1586_Y + connect \Y $and$ls180.v:5989$1587_Y end - attribute \src "ls180.v:5994.46-5994.102" - cell $and $and$ls180.v:5994$1590 + attribute \src "ls180.v:5990.46-5990.102" + cell $and $and$ls180.v:5990$1589 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5994$1589_Y - connect \Y $and$ls180.v:5994$1590_Y + connect \B $not$ls180.v:5990$1588_Y + connect \Y $and$ls180.v:5990$1589_Y end - attribute \src "ls180.v:5994.45-5994.153" - cell $and $and$ls180.v:5994$1592 + attribute \src "ls180.v:5990.45-5990.153" + cell $and $and$ls180.v:5990$1591 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5994$1590_Y - connect \B $eq$ls180.v:5994$1591_Y - connect \Y $and$ls180.v:5994$1592_Y + connect \A $and$ls180.v:5990$1589_Y + connect \B $eq$ls180.v:5990$1590_Y + connect \Y $and$ls180.v:5990$1591_Y end - attribute \src "ls180.v:5996.46-5996.99" - cell $and $and$ls180.v:5996$1593 + attribute \src "ls180.v:5992.46-5992.99" + cell $and $and$ls180.v:5992$1592 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90133,43 +90129,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5996$1593_Y + connect \Y $and$ls180.v:5992$1592_Y end - attribute \src "ls180.v:5996.45-5996.150" - cell $and $and$ls180.v:5996$1595 + attribute \src "ls180.v:5992.45-5992.150" + cell $and $and$ls180.v:5992$1594 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5996$1593_Y - connect \B $eq$ls180.v:5996$1594_Y - connect \Y $and$ls180.v:5996$1595_Y + connect \A $and$ls180.v:5992$1592_Y + connect \B $eq$ls180.v:5992$1593_Y + connect \Y $and$ls180.v:5992$1594_Y end - attribute \src "ls180.v:5997.46-5997.102" - cell $and $and$ls180.v:5997$1597 + attribute \src "ls180.v:5993.46-5993.102" + cell $and $and$ls180.v:5993$1596 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5997$1596_Y - connect \Y $and$ls180.v:5997$1597_Y + connect \B $not$ls180.v:5993$1595_Y + connect \Y $and$ls180.v:5993$1596_Y end - attribute \src "ls180.v:5997.45-5997.153" - cell $and $and$ls180.v:5997$1599 + attribute \src "ls180.v:5993.45-5993.153" + cell $and $and$ls180.v:5993$1598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5997$1597_Y - connect \B $eq$ls180.v:5997$1598_Y - connect \Y $and$ls180.v:5997$1599_Y + connect \A $and$ls180.v:5993$1596_Y + connect \B $eq$ls180.v:5993$1597_Y + connect \Y $and$ls180.v:5993$1598_Y end - attribute \src "ls180.v:5999.42-5999.95" - cell $and $and$ls180.v:5999$1600 + attribute \src "ls180.v:5995.42-5995.95" + cell $and $and$ls180.v:5995$1599 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90177,43 +90173,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5999$1600_Y + connect \Y $and$ls180.v:5995$1599_Y end - attribute \src "ls180.v:5999.41-5999.146" - cell $and $and$ls180.v:5999$1602 + attribute \src "ls180.v:5995.41-5995.146" + cell $and $and$ls180.v:5995$1601 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5999$1600_Y - connect \B $eq$ls180.v:5999$1601_Y - connect \Y $and$ls180.v:5999$1602_Y + connect \A $and$ls180.v:5995$1599_Y + connect \B $eq$ls180.v:5995$1600_Y + connect \Y $and$ls180.v:5995$1601_Y end - attribute \src "ls180.v:6000.42-6000.98" - cell $and $and$ls180.v:6000$1604 + attribute \src "ls180.v:5996.42-5996.98" + cell $and $and$ls180.v:5996$1603 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6000$1603_Y - connect \Y $and$ls180.v:6000$1604_Y + connect \B $not$ls180.v:5996$1602_Y + connect \Y $and$ls180.v:5996$1603_Y end - attribute \src "ls180.v:6000.41-6000.149" - cell $and $and$ls180.v:6000$1606 + attribute \src "ls180.v:5996.41-5996.149" + cell $and $and$ls180.v:5996$1605 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6000$1604_Y - connect \B $eq$ls180.v:6000$1605_Y - connect \Y $and$ls180.v:6000$1606_Y + connect \A $and$ls180.v:5996$1603_Y + connect \B $eq$ls180.v:5996$1604_Y + connect \Y $and$ls180.v:5996$1605_Y end - attribute \src "ls180.v:6002.43-6002.96" - cell $and $and$ls180.v:6002$1607 + attribute \src "ls180.v:5998.43-5998.96" + cell $and $and$ls180.v:5998$1606 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90221,43 +90217,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6002$1607_Y + connect \Y $and$ls180.v:5998$1606_Y end - attribute \src "ls180.v:6002.42-6002.147" - cell $and $and$ls180.v:6002$1609 + attribute \src "ls180.v:5998.42-5998.147" + cell $and $and$ls180.v:5998$1608 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6002$1607_Y - connect \B $eq$ls180.v:6002$1608_Y - connect \Y $and$ls180.v:6002$1609_Y + connect \A $and$ls180.v:5998$1606_Y + connect \B $eq$ls180.v:5998$1607_Y + connect \Y $and$ls180.v:5998$1608_Y end - attribute \src "ls180.v:6003.43-6003.99" - cell $and $and$ls180.v:6003$1611 + attribute \src "ls180.v:5999.43-5999.99" + cell $and $and$ls180.v:5999$1610 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6003$1610_Y - connect \Y $and$ls180.v:6003$1611_Y + connect \B $not$ls180.v:5999$1609_Y + connect \Y $and$ls180.v:5999$1610_Y end - attribute \src "ls180.v:6003.42-6003.150" - cell $and $and$ls180.v:6003$1613 + attribute \src "ls180.v:5999.42-5999.150" + cell $and $and$ls180.v:5999$1612 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6003$1611_Y - connect \B $eq$ls180.v:6003$1612_Y - connect \Y $and$ls180.v:6003$1613_Y + connect \A $and$ls180.v:5999$1610_Y + connect \B $eq$ls180.v:5999$1611_Y + connect \Y $and$ls180.v:5999$1612_Y end - attribute \src "ls180.v:6005.46-6005.99" - cell $and $and$ls180.v:6005$1614 + attribute \src "ls180.v:6001.46-6001.99" + cell $and $and$ls180.v:6001$1613 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90265,43 +90261,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6005$1614_Y + connect \Y $and$ls180.v:6001$1613_Y end - attribute \src "ls180.v:6005.45-6005.150" - cell $and $and$ls180.v:6005$1616 + attribute \src "ls180.v:6001.45-6001.150" + cell $and $and$ls180.v:6001$1615 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6005$1614_Y - connect \B $eq$ls180.v:6005$1615_Y - connect \Y $and$ls180.v:6005$1616_Y + connect \A $and$ls180.v:6001$1613_Y + connect \B $eq$ls180.v:6001$1614_Y + connect \Y $and$ls180.v:6001$1615_Y end - attribute \src "ls180.v:6006.46-6006.102" - cell $and $and$ls180.v:6006$1618 + attribute \src "ls180.v:6002.46-6002.102" + cell $and $and$ls180.v:6002$1617 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6006$1617_Y - connect \Y $and$ls180.v:6006$1618_Y + connect \B $not$ls180.v:6002$1616_Y + connect \Y $and$ls180.v:6002$1617_Y end - attribute \src "ls180.v:6006.45-6006.153" - cell $and $and$ls180.v:6006$1620 + attribute \src "ls180.v:6002.45-6002.153" + cell $and $and$ls180.v:6002$1619 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6006$1618_Y - connect \B $eq$ls180.v:6006$1619_Y - connect \Y $and$ls180.v:6006$1620_Y + connect \A $and$ls180.v:6002$1617_Y + connect \B $eq$ls180.v:6002$1618_Y + connect \Y $and$ls180.v:6002$1619_Y end - attribute \src "ls180.v:6008.46-6008.99" - cell $and $and$ls180.v:6008$1621 + attribute \src "ls180.v:6004.46-6004.99" + cell $and $and$ls180.v:6004$1620 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90309,43 +90305,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6008$1621_Y + connect \Y $and$ls180.v:6004$1620_Y end - attribute \src "ls180.v:6008.45-6008.150" - cell $and $and$ls180.v:6008$1623 + attribute \src "ls180.v:6004.45-6004.150" + cell $and $and$ls180.v:6004$1622 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6008$1621_Y - connect \B $eq$ls180.v:6008$1622_Y - connect \Y $and$ls180.v:6008$1623_Y + connect \A $and$ls180.v:6004$1620_Y + connect \B $eq$ls180.v:6004$1621_Y + connect \Y $and$ls180.v:6004$1622_Y end - attribute \src "ls180.v:6009.46-6009.102" - cell $and $and$ls180.v:6009$1625 + attribute \src "ls180.v:6005.46-6005.102" + cell $and $and$ls180.v:6005$1624 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6009$1624_Y - connect \Y $and$ls180.v:6009$1625_Y + connect \B $not$ls180.v:6005$1623_Y + connect \Y $and$ls180.v:6005$1624_Y end - attribute \src "ls180.v:6009.45-6009.153" - cell $and $and$ls180.v:6009$1627 + attribute \src "ls180.v:6005.45-6005.153" + cell $and $and$ls180.v:6005$1626 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6009$1625_Y - connect \B $eq$ls180.v:6009$1626_Y - connect \Y $and$ls180.v:6009$1627_Y + connect \A $and$ls180.v:6005$1624_Y + connect \B $eq$ls180.v:6005$1625_Y + connect \Y $and$ls180.v:6005$1626_Y end - attribute \src "ls180.v:6011.45-6011.98" - cell $and $and$ls180.v:6011$1628 + attribute \src "ls180.v:6007.45-6007.98" + cell $and $and$ls180.v:6007$1627 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90353,43 +90349,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6011$1628_Y + connect \Y $and$ls180.v:6007$1627_Y end - attribute \src "ls180.v:6011.44-6011.149" - cell $and $and$ls180.v:6011$1630 + attribute \src "ls180.v:6007.44-6007.149" + cell $and $and$ls180.v:6007$1629 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6011$1628_Y - connect \B $eq$ls180.v:6011$1629_Y - connect \Y $and$ls180.v:6011$1630_Y + connect \A $and$ls180.v:6007$1627_Y + connect \B $eq$ls180.v:6007$1628_Y + connect \Y $and$ls180.v:6007$1629_Y end - attribute \src "ls180.v:6012.45-6012.101" - cell $and $and$ls180.v:6012$1632 + attribute \src "ls180.v:6008.45-6008.101" + cell $and $and$ls180.v:6008$1631 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6012$1631_Y - connect \Y $and$ls180.v:6012$1632_Y + connect \B $not$ls180.v:6008$1630_Y + connect \Y $and$ls180.v:6008$1631_Y end - attribute \src "ls180.v:6012.44-6012.152" - cell $and $and$ls180.v:6012$1634 + attribute \src "ls180.v:6008.44-6008.152" + cell $and $and$ls180.v:6008$1633 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6012$1632_Y - connect \B $eq$ls180.v:6012$1633_Y - connect \Y $and$ls180.v:6012$1634_Y + connect \A $and$ls180.v:6008$1631_Y + connect \B $eq$ls180.v:6008$1632_Y + connect \Y $and$ls180.v:6008$1633_Y end - attribute \src "ls180.v:6014.45-6014.98" - cell $and $and$ls180.v:6014$1635 + attribute \src "ls180.v:6010.45-6010.98" + cell $and $and$ls180.v:6010$1634 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90397,43 +90393,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6014$1635_Y + connect \Y $and$ls180.v:6010$1634_Y end - attribute \src "ls180.v:6014.44-6014.149" - cell $and $and$ls180.v:6014$1637 + attribute \src "ls180.v:6010.44-6010.149" + cell $and $and$ls180.v:6010$1636 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6014$1635_Y - connect \B $eq$ls180.v:6014$1636_Y - connect \Y $and$ls180.v:6014$1637_Y + connect \A $and$ls180.v:6010$1634_Y + connect \B $eq$ls180.v:6010$1635_Y + connect \Y $and$ls180.v:6010$1636_Y end - attribute \src "ls180.v:6015.45-6015.101" - cell $and $and$ls180.v:6015$1639 + attribute \src "ls180.v:6011.45-6011.101" + cell $and $and$ls180.v:6011$1638 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6015$1638_Y - connect \Y $and$ls180.v:6015$1639_Y + connect \B $not$ls180.v:6011$1637_Y + connect \Y $and$ls180.v:6011$1638_Y end - attribute \src "ls180.v:6015.44-6015.152" - cell $and $and$ls180.v:6015$1641 + attribute \src "ls180.v:6011.44-6011.152" + cell $and $and$ls180.v:6011$1640 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6015$1639_Y - connect \B $eq$ls180.v:6015$1640_Y - connect \Y $and$ls180.v:6015$1641_Y + connect \A $and$ls180.v:6011$1638_Y + connect \B $eq$ls180.v:6011$1639_Y + connect \Y $and$ls180.v:6011$1640_Y end - attribute \src "ls180.v:6017.45-6017.98" - cell $and $and$ls180.v:6017$1642 + attribute \src "ls180.v:6013.45-6013.98" + cell $and $and$ls180.v:6013$1641 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90441,43 +90437,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6017$1642_Y + connect \Y $and$ls180.v:6013$1641_Y end - attribute \src "ls180.v:6017.44-6017.149" - cell $and $and$ls180.v:6017$1644 + attribute \src "ls180.v:6013.44-6013.149" + cell $and $and$ls180.v:6013$1643 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6017$1642_Y - connect \B $eq$ls180.v:6017$1643_Y - connect \Y $and$ls180.v:6017$1644_Y + connect \A $and$ls180.v:6013$1641_Y + connect \B $eq$ls180.v:6013$1642_Y + connect \Y $and$ls180.v:6013$1643_Y end - attribute \src "ls180.v:6018.45-6018.101" - cell $and $and$ls180.v:6018$1646 + attribute \src "ls180.v:6014.45-6014.101" + cell $and $and$ls180.v:6014$1645 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6018$1645_Y - connect \Y $and$ls180.v:6018$1646_Y + connect \B $not$ls180.v:6014$1644_Y + connect \Y $and$ls180.v:6014$1645_Y end - attribute \src "ls180.v:6018.44-6018.152" - cell $and $and$ls180.v:6018$1648 + attribute \src "ls180.v:6014.44-6014.152" + cell $and $and$ls180.v:6014$1647 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6018$1646_Y - connect \B $eq$ls180.v:6018$1647_Y - connect \Y $and$ls180.v:6018$1648_Y + connect \A $and$ls180.v:6014$1645_Y + connect \B $eq$ls180.v:6014$1646_Y + connect \Y $and$ls180.v:6014$1647_Y end - attribute \src "ls180.v:6020.45-6020.98" - cell $and $and$ls180.v:6020$1649 + attribute \src "ls180.v:6016.45-6016.98" + cell $and $and$ls180.v:6016$1648 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90485,43 +90481,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6020$1649_Y + connect \Y $and$ls180.v:6016$1648_Y end - attribute \src "ls180.v:6020.44-6020.149" - cell $and $and$ls180.v:6020$1651 + attribute \src "ls180.v:6016.44-6016.149" + cell $and $and$ls180.v:6016$1650 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6020$1649_Y - connect \B $eq$ls180.v:6020$1650_Y - connect \Y $and$ls180.v:6020$1651_Y + connect \A $and$ls180.v:6016$1648_Y + connect \B $eq$ls180.v:6016$1649_Y + connect \Y $and$ls180.v:6016$1650_Y end - attribute \src "ls180.v:6021.45-6021.101" - cell $and $and$ls180.v:6021$1653 + attribute \src "ls180.v:6017.45-6017.101" + cell $and $and$ls180.v:6017$1652 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6021$1652_Y - connect \Y $and$ls180.v:6021$1653_Y + connect \B $not$ls180.v:6017$1651_Y + connect \Y $and$ls180.v:6017$1652_Y end - attribute \src "ls180.v:6021.44-6021.152" - cell $and $and$ls180.v:6021$1655 + attribute \src "ls180.v:6017.44-6017.152" + cell $and $and$ls180.v:6017$1654 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6021$1653_Y - connect \B $eq$ls180.v:6021$1654_Y - connect \Y $and$ls180.v:6021$1655_Y + connect \A $and$ls180.v:6017$1652_Y + connect \B $eq$ls180.v:6017$1653_Y + connect \Y $and$ls180.v:6017$1654_Y end - attribute \src "ls180.v:6059.42-6059.95" - cell $and $and$ls180.v:6059$1657 + attribute \src "ls180.v:6055.42-6055.95" + cell $and $and$ls180.v:6055$1656 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90529,43 +90525,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6059$1657_Y + connect \Y $and$ls180.v:6055$1656_Y end - attribute \src "ls180.v:6059.41-6059.145" - cell $and $and$ls180.v:6059$1659 + attribute \src "ls180.v:6055.41-6055.145" + cell $and $and$ls180.v:6055$1658 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6059$1657_Y - connect \B $eq$ls180.v:6059$1658_Y - connect \Y $and$ls180.v:6059$1659_Y + connect \A $and$ls180.v:6055$1656_Y + connect \B $eq$ls180.v:6055$1657_Y + connect \Y $and$ls180.v:6055$1658_Y end - attribute \src "ls180.v:6060.42-6060.98" - cell $and $and$ls180.v:6060$1661 + attribute \src "ls180.v:6056.42-6056.98" + cell $and $and$ls180.v:6056$1660 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6060$1660_Y - connect \Y $and$ls180.v:6060$1661_Y + connect \B $not$ls180.v:6056$1659_Y + connect \Y $and$ls180.v:6056$1660_Y end - attribute \src "ls180.v:6060.41-6060.148" - cell $and $and$ls180.v:6060$1663 + attribute \src "ls180.v:6056.41-6056.148" + cell $and $and$ls180.v:6056$1662 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6060$1661_Y - connect \B $eq$ls180.v:6060$1662_Y - connect \Y $and$ls180.v:6060$1663_Y + connect \A $and$ls180.v:6056$1660_Y + connect \B $eq$ls180.v:6056$1661_Y + connect \Y $and$ls180.v:6056$1662_Y end - attribute \src "ls180.v:6062.42-6062.95" - cell $and $and$ls180.v:6062$1664 + attribute \src "ls180.v:6058.42-6058.95" + cell $and $and$ls180.v:6058$1663 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90573,43 +90569,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6062$1664_Y + connect \Y $and$ls180.v:6058$1663_Y end - attribute \src "ls180.v:6062.41-6062.145" - cell $and $and$ls180.v:6062$1666 + attribute \src "ls180.v:6058.41-6058.145" + cell $and $and$ls180.v:6058$1665 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6062$1664_Y - connect \B $eq$ls180.v:6062$1665_Y - connect \Y $and$ls180.v:6062$1666_Y + connect \A $and$ls180.v:6058$1663_Y + connect \B $eq$ls180.v:6058$1664_Y + connect \Y $and$ls180.v:6058$1665_Y end - attribute \src "ls180.v:6063.42-6063.98" - cell $and $and$ls180.v:6063$1668 + attribute \src "ls180.v:6059.42-6059.98" + cell $and $and$ls180.v:6059$1667 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6063$1667_Y - connect \Y $and$ls180.v:6063$1668_Y + connect \B $not$ls180.v:6059$1666_Y + connect \Y $and$ls180.v:6059$1667_Y end - attribute \src "ls180.v:6063.41-6063.148" - cell $and $and$ls180.v:6063$1670 + attribute \src "ls180.v:6059.41-6059.148" + cell $and $and$ls180.v:6059$1669 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6063$1668_Y - connect \B $eq$ls180.v:6063$1669_Y - connect \Y $and$ls180.v:6063$1670_Y + connect \A $and$ls180.v:6059$1667_Y + connect \B $eq$ls180.v:6059$1668_Y + connect \Y $and$ls180.v:6059$1669_Y end - attribute \src "ls180.v:6065.42-6065.95" - cell $and $and$ls180.v:6065$1671 + attribute \src "ls180.v:6061.42-6061.95" + cell $and $and$ls180.v:6061$1670 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90617,43 +90613,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6065$1671_Y + connect \Y $and$ls180.v:6061$1670_Y end - attribute \src "ls180.v:6065.41-6065.145" - cell $and $and$ls180.v:6065$1673 + attribute \src "ls180.v:6061.41-6061.145" + cell $and $and$ls180.v:6061$1672 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6065$1671_Y - connect \B $eq$ls180.v:6065$1672_Y - connect \Y $and$ls180.v:6065$1673_Y + connect \A $and$ls180.v:6061$1670_Y + connect \B $eq$ls180.v:6061$1671_Y + connect \Y $and$ls180.v:6061$1672_Y end - attribute \src "ls180.v:6066.42-6066.98" - cell $and $and$ls180.v:6066$1675 + attribute \src "ls180.v:6062.42-6062.98" + cell $and $and$ls180.v:6062$1674 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6066$1674_Y - connect \Y $and$ls180.v:6066$1675_Y + connect \B $not$ls180.v:6062$1673_Y + connect \Y $and$ls180.v:6062$1674_Y end - attribute \src "ls180.v:6066.41-6066.148" - cell $and $and$ls180.v:6066$1677 + attribute \src "ls180.v:6062.41-6062.148" + cell $and $and$ls180.v:6062$1676 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6066$1675_Y - connect \B $eq$ls180.v:6066$1676_Y - connect \Y $and$ls180.v:6066$1677_Y + connect \A $and$ls180.v:6062$1674_Y + connect \B $eq$ls180.v:6062$1675_Y + connect \Y $and$ls180.v:6062$1676_Y end - attribute \src "ls180.v:6068.42-6068.95" - cell $and $and$ls180.v:6068$1678 + attribute \src "ls180.v:6064.42-6064.95" + cell $and $and$ls180.v:6064$1677 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90661,43 +90657,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6068$1678_Y + connect \Y $and$ls180.v:6064$1677_Y end - attribute \src "ls180.v:6068.41-6068.145" - cell $and $and$ls180.v:6068$1680 + attribute \src "ls180.v:6064.41-6064.145" + cell $and $and$ls180.v:6064$1679 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6068$1678_Y - connect \B $eq$ls180.v:6068$1679_Y - connect \Y $and$ls180.v:6068$1680_Y + connect \A $and$ls180.v:6064$1677_Y + connect \B $eq$ls180.v:6064$1678_Y + connect \Y $and$ls180.v:6064$1679_Y end - attribute \src "ls180.v:6069.42-6069.98" - cell $and $and$ls180.v:6069$1682 + attribute \src "ls180.v:6065.42-6065.98" + cell $and $and$ls180.v:6065$1681 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6069$1681_Y - connect \Y $and$ls180.v:6069$1682_Y + connect \B $not$ls180.v:6065$1680_Y + connect \Y $and$ls180.v:6065$1681_Y end - attribute \src "ls180.v:6069.41-6069.148" - cell $and $and$ls180.v:6069$1684 + attribute \src "ls180.v:6065.41-6065.148" + cell $and $and$ls180.v:6065$1683 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6069$1682_Y - connect \B $eq$ls180.v:6069$1683_Y - connect \Y $and$ls180.v:6069$1684_Y + connect \A $and$ls180.v:6065$1681_Y + connect \B $eq$ls180.v:6065$1682_Y + connect \Y $and$ls180.v:6065$1683_Y end - attribute \src "ls180.v:6071.42-6071.95" - cell $and $and$ls180.v:6071$1685 + attribute \src "ls180.v:6067.42-6067.95" + cell $and $and$ls180.v:6067$1684 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90705,43 +90701,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6071$1685_Y + connect \Y $and$ls180.v:6067$1684_Y end - attribute \src "ls180.v:6071.41-6071.145" - cell $and $and$ls180.v:6071$1687 + attribute \src "ls180.v:6067.41-6067.145" + cell $and $and$ls180.v:6067$1686 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6071$1685_Y - connect \B $eq$ls180.v:6071$1686_Y - connect \Y $and$ls180.v:6071$1687_Y + connect \A $and$ls180.v:6067$1684_Y + connect \B $eq$ls180.v:6067$1685_Y + connect \Y $and$ls180.v:6067$1686_Y end - attribute \src "ls180.v:6072.42-6072.98" - cell $and $and$ls180.v:6072$1689 + attribute \src "ls180.v:6068.42-6068.98" + cell $and $and$ls180.v:6068$1688 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6072$1688_Y - connect \Y $and$ls180.v:6072$1689_Y + connect \B $not$ls180.v:6068$1687_Y + connect \Y $and$ls180.v:6068$1688_Y end - attribute \src "ls180.v:6072.41-6072.148" - cell $and $and$ls180.v:6072$1691 + attribute \src "ls180.v:6068.41-6068.148" + cell $and $and$ls180.v:6068$1690 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6072$1689_Y - connect \B $eq$ls180.v:6072$1690_Y - connect \Y $and$ls180.v:6072$1691_Y + connect \A $and$ls180.v:6068$1688_Y + connect \B $eq$ls180.v:6068$1689_Y + connect \Y $and$ls180.v:6068$1690_Y end - attribute \src "ls180.v:6074.42-6074.95" - cell $and $and$ls180.v:6074$1692 + attribute \src "ls180.v:6070.42-6070.95" + cell $and $and$ls180.v:6070$1691 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90749,43 +90745,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6074$1692_Y + connect \Y $and$ls180.v:6070$1691_Y end - attribute \src "ls180.v:6074.41-6074.145" - cell $and $and$ls180.v:6074$1694 + attribute \src "ls180.v:6070.41-6070.145" + cell $and $and$ls180.v:6070$1693 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6074$1692_Y - connect \B $eq$ls180.v:6074$1693_Y - connect \Y $and$ls180.v:6074$1694_Y + connect \A $and$ls180.v:6070$1691_Y + connect \B $eq$ls180.v:6070$1692_Y + connect \Y $and$ls180.v:6070$1693_Y end - attribute \src "ls180.v:6075.42-6075.98" - cell $and $and$ls180.v:6075$1696 + attribute \src "ls180.v:6071.42-6071.98" + cell $and $and$ls180.v:6071$1695 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6075$1695_Y - connect \Y $and$ls180.v:6075$1696_Y + connect \B $not$ls180.v:6071$1694_Y + connect \Y $and$ls180.v:6071$1695_Y end - attribute \src "ls180.v:6075.41-6075.148" - cell $and $and$ls180.v:6075$1698 + attribute \src "ls180.v:6071.41-6071.148" + cell $and $and$ls180.v:6071$1697 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6075$1696_Y - connect \B $eq$ls180.v:6075$1697_Y - connect \Y $and$ls180.v:6075$1698_Y + connect \A $and$ls180.v:6071$1695_Y + connect \B $eq$ls180.v:6071$1696_Y + connect \Y $and$ls180.v:6071$1697_Y end - attribute \src "ls180.v:6077.42-6077.95" - cell $and $and$ls180.v:6077$1699 + attribute \src "ls180.v:6073.42-6073.95" + cell $and $and$ls180.v:6073$1698 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90793,43 +90789,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6077$1699_Y + connect \Y $and$ls180.v:6073$1698_Y end - attribute \src "ls180.v:6077.41-6077.145" - cell $and $and$ls180.v:6077$1701 + attribute \src "ls180.v:6073.41-6073.145" + cell $and $and$ls180.v:6073$1700 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6077$1699_Y - connect \B $eq$ls180.v:6077$1700_Y - connect \Y $and$ls180.v:6077$1701_Y + connect \A $and$ls180.v:6073$1698_Y + connect \B $eq$ls180.v:6073$1699_Y + connect \Y $and$ls180.v:6073$1700_Y end - attribute \src "ls180.v:6078.42-6078.98" - cell $and $and$ls180.v:6078$1703 + attribute \src "ls180.v:6074.42-6074.98" + cell $and $and$ls180.v:6074$1702 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6078$1702_Y - connect \Y $and$ls180.v:6078$1703_Y + connect \B $not$ls180.v:6074$1701_Y + connect \Y $and$ls180.v:6074$1702_Y end - attribute \src "ls180.v:6078.41-6078.148" - cell $and $and$ls180.v:6078$1705 + attribute \src "ls180.v:6074.41-6074.148" + cell $and $and$ls180.v:6074$1704 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6078$1703_Y - connect \B $eq$ls180.v:6078$1704_Y - connect \Y $and$ls180.v:6078$1705_Y + connect \A $and$ls180.v:6074$1702_Y + connect \B $eq$ls180.v:6074$1703_Y + connect \Y $and$ls180.v:6074$1704_Y end - attribute \src "ls180.v:6080.42-6080.95" - cell $and $and$ls180.v:6080$1706 + attribute \src "ls180.v:6076.42-6076.95" + cell $and $and$ls180.v:6076$1705 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90837,43 +90833,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6080$1706_Y + connect \Y $and$ls180.v:6076$1705_Y end - attribute \src "ls180.v:6080.41-6080.145" - cell $and $and$ls180.v:6080$1708 + attribute \src "ls180.v:6076.41-6076.145" + cell $and $and$ls180.v:6076$1707 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6080$1706_Y - connect \B $eq$ls180.v:6080$1707_Y - connect \Y $and$ls180.v:6080$1708_Y + connect \A $and$ls180.v:6076$1705_Y + connect \B $eq$ls180.v:6076$1706_Y + connect \Y $and$ls180.v:6076$1707_Y end - attribute \src "ls180.v:6081.42-6081.98" - cell $and $and$ls180.v:6081$1710 + attribute \src "ls180.v:6077.42-6077.98" + cell $and $and$ls180.v:6077$1709 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6081$1709_Y - connect \Y $and$ls180.v:6081$1710_Y + connect \B $not$ls180.v:6077$1708_Y + connect \Y $and$ls180.v:6077$1709_Y end - attribute \src "ls180.v:6081.41-6081.148" - cell $and $and$ls180.v:6081$1712 + attribute \src "ls180.v:6077.41-6077.148" + cell $and $and$ls180.v:6077$1711 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6081$1710_Y - connect \B $eq$ls180.v:6081$1711_Y - connect \Y $and$ls180.v:6081$1712_Y + connect \A $and$ls180.v:6077$1709_Y + connect \B $eq$ls180.v:6077$1710_Y + connect \Y $and$ls180.v:6077$1711_Y end - attribute \src "ls180.v:6083.44-6083.97" - cell $and $and$ls180.v:6083$1713 + attribute \src "ls180.v:6079.44-6079.97" + cell $and $and$ls180.v:6079$1712 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90881,43 +90877,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6083$1713_Y + connect \Y $and$ls180.v:6079$1712_Y end - attribute \src "ls180.v:6083.43-6083.147" - cell $and $and$ls180.v:6083$1715 + attribute \src "ls180.v:6079.43-6079.147" + cell $and $and$ls180.v:6079$1714 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6083$1713_Y - connect \B $eq$ls180.v:6083$1714_Y - connect \Y $and$ls180.v:6083$1715_Y + connect \A $and$ls180.v:6079$1712_Y + connect \B $eq$ls180.v:6079$1713_Y + connect \Y $and$ls180.v:6079$1714_Y end - attribute \src "ls180.v:6084.44-6084.100" - cell $and $and$ls180.v:6084$1717 + attribute \src "ls180.v:6080.44-6080.100" + cell $and $and$ls180.v:6080$1716 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6084$1716_Y - connect \Y $and$ls180.v:6084$1717_Y + connect \B $not$ls180.v:6080$1715_Y + connect \Y $and$ls180.v:6080$1716_Y end - attribute \src "ls180.v:6084.43-6084.150" - cell $and $and$ls180.v:6084$1719 + attribute \src "ls180.v:6080.43-6080.150" + cell $and $and$ls180.v:6080$1718 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6084$1717_Y - connect \B $eq$ls180.v:6084$1718_Y - connect \Y $and$ls180.v:6084$1719_Y + connect \A $and$ls180.v:6080$1716_Y + connect \B $eq$ls180.v:6080$1717_Y + connect \Y $and$ls180.v:6080$1718_Y end - attribute \src "ls180.v:6086.44-6086.97" - cell $and $and$ls180.v:6086$1720 + attribute \src "ls180.v:6082.44-6082.97" + cell $and $and$ls180.v:6082$1719 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90925,43 +90921,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6086$1720_Y + connect \Y $and$ls180.v:6082$1719_Y end - attribute \src "ls180.v:6086.43-6086.147" - cell $and $and$ls180.v:6086$1722 + attribute \src "ls180.v:6082.43-6082.147" + cell $and $and$ls180.v:6082$1721 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6086$1720_Y - connect \B $eq$ls180.v:6086$1721_Y - connect \Y $and$ls180.v:6086$1722_Y + connect \A $and$ls180.v:6082$1719_Y + connect \B $eq$ls180.v:6082$1720_Y + connect \Y $and$ls180.v:6082$1721_Y end - attribute \src "ls180.v:6087.44-6087.100" - cell $and $and$ls180.v:6087$1724 + attribute \src "ls180.v:6083.44-6083.100" + cell $and $and$ls180.v:6083$1723 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6087$1723_Y - connect \Y $and$ls180.v:6087$1724_Y + connect \B $not$ls180.v:6083$1722_Y + connect \Y $and$ls180.v:6083$1723_Y end - attribute \src "ls180.v:6087.43-6087.150" - cell $and $and$ls180.v:6087$1726 + attribute \src "ls180.v:6083.43-6083.150" + cell $and $and$ls180.v:6083$1725 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6087$1724_Y - connect \B $eq$ls180.v:6087$1725_Y - connect \Y $and$ls180.v:6087$1726_Y + connect \A $and$ls180.v:6083$1723_Y + connect \B $eq$ls180.v:6083$1724_Y + connect \Y $and$ls180.v:6083$1725_Y end - attribute \src "ls180.v:6089.44-6089.97" - cell $and $and$ls180.v:6089$1727 + attribute \src "ls180.v:6085.44-6085.97" + cell $and $and$ls180.v:6085$1726 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90969,43 +90965,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6089$1727_Y + connect \Y $and$ls180.v:6085$1726_Y end - attribute \src "ls180.v:6089.43-6089.148" - cell $and $and$ls180.v:6089$1729 + attribute \src "ls180.v:6085.43-6085.148" + cell $and $and$ls180.v:6085$1728 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6089$1727_Y - connect \B $eq$ls180.v:6089$1728_Y - connect \Y $and$ls180.v:6089$1729_Y + connect \A $and$ls180.v:6085$1726_Y + connect \B $eq$ls180.v:6085$1727_Y + connect \Y $and$ls180.v:6085$1728_Y end - attribute \src "ls180.v:6090.44-6090.100" - cell $and $and$ls180.v:6090$1731 + attribute \src "ls180.v:6086.44-6086.100" + cell $and $and$ls180.v:6086$1730 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6090$1730_Y - connect \Y $and$ls180.v:6090$1731_Y + connect \B $not$ls180.v:6086$1729_Y + connect \Y $and$ls180.v:6086$1730_Y end - attribute \src "ls180.v:6090.43-6090.151" - cell $and $and$ls180.v:6090$1733 + attribute \src "ls180.v:6086.43-6086.151" + cell $and $and$ls180.v:6086$1732 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6090$1731_Y - connect \B $eq$ls180.v:6090$1732_Y - connect \Y $and$ls180.v:6090$1733_Y + connect \A $and$ls180.v:6086$1730_Y + connect \B $eq$ls180.v:6086$1731_Y + connect \Y $and$ls180.v:6086$1732_Y end - attribute \src "ls180.v:6092.44-6092.97" - cell $and $and$ls180.v:6092$1734 + attribute \src "ls180.v:6088.44-6088.97" + cell $and $and$ls180.v:6088$1733 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -91013,43 +91009,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6092$1734_Y + connect \Y $and$ls180.v:6088$1733_Y end - attribute \src "ls180.v:6092.43-6092.148" - cell $and $and$ls180.v:6092$1736 + attribute \src "ls180.v:6088.43-6088.148" + cell $and $and$ls180.v:6088$1735 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6092$1734_Y - connect \B $eq$ls180.v:6092$1735_Y - connect \Y $and$ls180.v:6092$1736_Y + connect \A $and$ls180.v:6088$1733_Y + connect \B $eq$ls180.v:6088$1734_Y + connect \Y $and$ls180.v:6088$1735_Y end - attribute \src "ls180.v:6093.44-6093.100" - cell $and $and$ls180.v:6093$1738 + attribute \src "ls180.v:6089.44-6089.100" + cell $and $and$ls180.v:6089$1737 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6093$1737_Y - connect \Y $and$ls180.v:6093$1738_Y + connect \B $not$ls180.v:6089$1736_Y + connect \Y $and$ls180.v:6089$1737_Y end - attribute \src "ls180.v:6093.43-6093.151" - cell $and $and$ls180.v:6093$1740 + attribute \src "ls180.v:6089.43-6089.151" + cell $and $and$ls180.v:6089$1739 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6093$1738_Y - connect \B $eq$ls180.v:6093$1739_Y - connect \Y $and$ls180.v:6093$1740_Y + connect \A $and$ls180.v:6089$1737_Y + connect \B $eq$ls180.v:6089$1738_Y + connect \Y $and$ls180.v:6089$1739_Y end - attribute \src "ls180.v:6095.44-6095.97" - cell $and $and$ls180.v:6095$1741 + attribute \src "ls180.v:6091.44-6091.97" + cell $and $and$ls180.v:6091$1740 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -91057,43 +91053,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6095$1741_Y + connect \Y $and$ls180.v:6091$1740_Y end - attribute \src "ls180.v:6095.43-6095.148" - cell $and $and$ls180.v:6095$1743 + attribute \src "ls180.v:6091.43-6091.148" + cell $and $and$ls180.v:6091$1742 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6095$1741_Y - connect \B $eq$ls180.v:6095$1742_Y - connect \Y $and$ls180.v:6095$1743_Y + connect \A $and$ls180.v:6091$1740_Y + connect \B $eq$ls180.v:6091$1741_Y + connect \Y $and$ls180.v:6091$1742_Y end - attribute \src "ls180.v:6096.44-6096.100" - cell $and $and$ls180.v:6096$1745 + attribute \src "ls180.v:6092.44-6092.100" + cell $and $and$ls180.v:6092$1744 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6096$1744_Y - connect \Y $and$ls180.v:6096$1745_Y + connect \B $not$ls180.v:6092$1743_Y + connect \Y $and$ls180.v:6092$1744_Y end - attribute \src "ls180.v:6096.43-6096.151" - cell $and $and$ls180.v:6096$1747 + attribute \src "ls180.v:6092.43-6092.151" + cell $and $and$ls180.v:6092$1746 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6096$1745_Y - connect \B $eq$ls180.v:6096$1746_Y - connect \Y $and$ls180.v:6096$1747_Y + connect \A $and$ls180.v:6092$1744_Y + connect \B $eq$ls180.v:6092$1745_Y + connect \Y $and$ls180.v:6092$1746_Y end - attribute \src "ls180.v:6098.41-6098.94" - cell $and $and$ls180.v:6098$1748 + attribute \src "ls180.v:6094.41-6094.94" + cell $and $and$ls180.v:6094$1747 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -91101,43 +91097,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6098$1748_Y + connect \Y $and$ls180.v:6094$1747_Y end - attribute \src "ls180.v:6098.40-6098.145" - cell $and $and$ls180.v:6098$1750 + attribute \src "ls180.v:6094.40-6094.145" + cell $and $and$ls180.v:6094$1749 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6098$1748_Y - connect \B $eq$ls180.v:6098$1749_Y - connect \Y $and$ls180.v:6098$1750_Y + connect \A $and$ls180.v:6094$1747_Y + connect \B $eq$ls180.v:6094$1748_Y + connect \Y $and$ls180.v:6094$1749_Y end - attribute \src "ls180.v:6099.41-6099.97" - cell $and $and$ls180.v:6099$1752 + attribute \src "ls180.v:6095.41-6095.97" + cell $and $and$ls180.v:6095$1751 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6099$1751_Y - connect \Y $and$ls180.v:6099$1752_Y + connect \B $not$ls180.v:6095$1750_Y + connect \Y $and$ls180.v:6095$1751_Y end - attribute \src "ls180.v:6099.40-6099.148" - cell $and $and$ls180.v:6099$1754 + attribute \src "ls180.v:6095.40-6095.148" + cell $and $and$ls180.v:6095$1753 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6099$1752_Y - connect \B $eq$ls180.v:6099$1753_Y - connect \Y $and$ls180.v:6099$1754_Y + connect \A $and$ls180.v:6095$1751_Y + connect \B $eq$ls180.v:6095$1752_Y + connect \Y $and$ls180.v:6095$1753_Y end - attribute \src "ls180.v:6101.42-6101.95" - cell $and $and$ls180.v:6101$1755 + attribute \src "ls180.v:6097.42-6097.95" + cell $and $and$ls180.v:6097$1754 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -91145,43 +91141,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6101$1755_Y + connect \Y $and$ls180.v:6097$1754_Y end - attribute \src "ls180.v:6101.41-6101.146" - cell $and $and$ls180.v:6101$1757 + attribute \src "ls180.v:6097.41-6097.146" + cell $and $and$ls180.v:6097$1756 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6101$1755_Y - connect \B $eq$ls180.v:6101$1756_Y - connect \Y $and$ls180.v:6101$1757_Y + connect \A $and$ls180.v:6097$1754_Y + connect \B $eq$ls180.v:6097$1755_Y + connect \Y $and$ls180.v:6097$1756_Y end - attribute \src "ls180.v:6102.42-6102.98" - cell $and $and$ls180.v:6102$1759 + attribute \src "ls180.v:6098.42-6098.98" + cell $and $and$ls180.v:6098$1758 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6102$1758_Y - connect \Y $and$ls180.v:6102$1759_Y + connect \B $not$ls180.v:6098$1757_Y + connect \Y $and$ls180.v:6098$1758_Y end - attribute \src "ls180.v:6102.41-6102.149" - cell $and $and$ls180.v:6102$1761 + attribute \src "ls180.v:6098.41-6098.149" + cell $and $and$ls180.v:6098$1760 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6102$1759_Y - connect \B $eq$ls180.v:6102$1760_Y - connect \Y $and$ls180.v:6102$1761_Y + connect \A $and$ls180.v:6098$1758_Y + connect \B $eq$ls180.v:6098$1759_Y + connect \Y $and$ls180.v:6098$1760_Y end - attribute \src "ls180.v:6104.44-6104.97" - cell $and $and$ls180.v:6104$1762 + attribute \src "ls180.v:6100.44-6100.97" + cell $and $and$ls180.v:6100$1761 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -91189,43 +91185,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6104$1762_Y + connect \Y $and$ls180.v:6100$1761_Y end - attribute \src "ls180.v:6104.43-6104.148" - cell $and $and$ls180.v:6104$1764 + attribute \src "ls180.v:6100.43-6100.148" + cell $and $and$ls180.v:6100$1763 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6104$1762_Y - connect \B $eq$ls180.v:6104$1763_Y - connect \Y $and$ls180.v:6104$1764_Y + connect \A $and$ls180.v:6100$1761_Y + connect \B $eq$ls180.v:6100$1762_Y + connect \Y $and$ls180.v:6100$1763_Y end - attribute \src "ls180.v:6105.44-6105.100" - cell $and $and$ls180.v:6105$1766 + attribute \src "ls180.v:6101.44-6101.100" + cell $and $and$ls180.v:6101$1765 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6105$1765_Y - connect \Y $and$ls180.v:6105$1766_Y + connect \B $not$ls180.v:6101$1764_Y + connect \Y $and$ls180.v:6101$1765_Y end - attribute \src "ls180.v:6105.43-6105.151" - cell $and $and$ls180.v:6105$1768 + attribute \src "ls180.v:6101.43-6101.151" + cell $and $and$ls180.v:6101$1767 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6105$1766_Y - connect \B $eq$ls180.v:6105$1767_Y - connect \Y $and$ls180.v:6105$1768_Y + connect \A $and$ls180.v:6101$1765_Y + connect \B $eq$ls180.v:6101$1766_Y + connect \Y $and$ls180.v:6101$1767_Y end - attribute \src "ls180.v:6107.44-6107.97" - cell $and $and$ls180.v:6107$1769 + attribute \src "ls180.v:6103.44-6103.97" + cell $and $and$ls180.v:6103$1768 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -91233,43 +91229,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6107$1769_Y + connect \Y $and$ls180.v:6103$1768_Y end - attribute \src "ls180.v:6107.43-6107.148" - cell $and $and$ls180.v:6107$1771 + attribute \src "ls180.v:6103.43-6103.148" + cell $and $and$ls180.v:6103$1770 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6107$1769_Y - connect \B $eq$ls180.v:6107$1770_Y - connect \Y $and$ls180.v:6107$1771_Y + connect \A $and$ls180.v:6103$1768_Y + connect \B $eq$ls180.v:6103$1769_Y + connect \Y $and$ls180.v:6103$1770_Y end - attribute \src "ls180.v:6108.44-6108.100" - cell $and $and$ls180.v:6108$1773 + attribute \src "ls180.v:6104.44-6104.100" + cell $and $and$ls180.v:6104$1772 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6108$1772_Y - connect \Y $and$ls180.v:6108$1773_Y + connect \B $not$ls180.v:6104$1771_Y + connect \Y $and$ls180.v:6104$1772_Y end - attribute \src "ls180.v:6108.43-6108.151" - cell $and $and$ls180.v:6108$1775 + attribute \src "ls180.v:6104.43-6104.151" + cell $and $and$ls180.v:6104$1774 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6108$1773_Y - connect \B $eq$ls180.v:6108$1774_Y - connect \Y $and$ls180.v:6108$1775_Y + connect \A $and$ls180.v:6104$1772_Y + connect \B $eq$ls180.v:6104$1773_Y + connect \Y $and$ls180.v:6104$1774_Y end - attribute \src "ls180.v:6110.44-6110.97" - cell $and $and$ls180.v:6110$1776 + attribute \src "ls180.v:6106.44-6106.97" + cell $and $and$ls180.v:6106$1775 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -91277,43 +91273,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6110$1776_Y + connect \Y $and$ls180.v:6106$1775_Y end - attribute \src "ls180.v:6110.43-6110.148" - cell $and $and$ls180.v:6110$1778 + attribute \src "ls180.v:6106.43-6106.148" + cell $and $and$ls180.v:6106$1777 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6110$1776_Y - connect \B $eq$ls180.v:6110$1777_Y - connect \Y $and$ls180.v:6110$1778_Y + connect \A $and$ls180.v:6106$1775_Y + connect \B $eq$ls180.v:6106$1776_Y + connect \Y $and$ls180.v:6106$1777_Y end - attribute \src "ls180.v:6111.44-6111.100" - cell $and $and$ls180.v:6111$1780 + attribute \src "ls180.v:6107.44-6107.100" + cell $and $and$ls180.v:6107$1779 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6111$1779_Y - connect \Y $and$ls180.v:6111$1780_Y + connect \B $not$ls180.v:6107$1778_Y + connect \Y $and$ls180.v:6107$1779_Y end - attribute \src "ls180.v:6111.43-6111.151" - cell $and $and$ls180.v:6111$1782 + attribute \src "ls180.v:6107.43-6107.151" + cell $and $and$ls180.v:6107$1781 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6111$1780_Y - connect \B $eq$ls180.v:6111$1781_Y - connect \Y $and$ls180.v:6111$1782_Y + connect \A $and$ls180.v:6107$1779_Y + connect \B $eq$ls180.v:6107$1780_Y + connect \Y $and$ls180.v:6107$1781_Y end - attribute \src "ls180.v:6113.44-6113.97" - cell $and $and$ls180.v:6113$1783 + attribute \src "ls180.v:6109.44-6109.97" + cell $and $and$ls180.v:6109$1782 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -91321,43 +91317,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6113$1783_Y + connect \Y $and$ls180.v:6109$1782_Y end - attribute \src "ls180.v:6113.43-6113.148" - cell $and $and$ls180.v:6113$1785 + attribute \src "ls180.v:6109.43-6109.148" + cell $and $and$ls180.v:6109$1784 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6113$1783_Y - connect \B $eq$ls180.v:6113$1784_Y - connect \Y $and$ls180.v:6113$1785_Y + connect \A $and$ls180.v:6109$1782_Y + connect \B $eq$ls180.v:6109$1783_Y + connect \Y $and$ls180.v:6109$1784_Y end - attribute \src "ls180.v:6114.44-6114.100" - cell $and $and$ls180.v:6114$1787 + attribute \src "ls180.v:6110.44-6110.100" + cell $and $and$ls180.v:6110$1786 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6114$1786_Y - connect \Y $and$ls180.v:6114$1787_Y + connect \B $not$ls180.v:6110$1785_Y + connect \Y $and$ls180.v:6110$1786_Y end - attribute \src "ls180.v:6114.43-6114.151" - cell $and $and$ls180.v:6114$1789 + attribute \src "ls180.v:6110.43-6110.151" + cell $and $and$ls180.v:6110$1788 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6114$1787_Y - connect \B $eq$ls180.v:6114$1788_Y - connect \Y $and$ls180.v:6114$1789_Y + connect \A $and$ls180.v:6110$1786_Y + connect \B $eq$ls180.v:6110$1787_Y + connect \Y $and$ls180.v:6110$1788_Y end - attribute \src "ls180.v:6138.44-6138.97" - cell $and $and$ls180.v:6138$1791 + attribute \src "ls180.v:6134.44-6134.97" + cell $and $and$ls180.v:6134$1790 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -91365,43 +91361,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6138$1791_Y + connect \Y $and$ls180.v:6134$1790_Y end - attribute \src "ls180.v:6138.43-6138.147" - cell $and $and$ls180.v:6138$1793 + attribute \src "ls180.v:6134.43-6134.147" + cell $and $and$ls180.v:6134$1792 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6138$1791_Y - connect \B $eq$ls180.v:6138$1792_Y - connect \Y $and$ls180.v:6138$1793_Y + connect \A $and$ls180.v:6134$1790_Y + connect \B $eq$ls180.v:6134$1791_Y + connect \Y $and$ls180.v:6134$1792_Y end - attribute \src "ls180.v:6139.44-6139.100" - cell $and $and$ls180.v:6139$1795 + attribute \src "ls180.v:6135.44-6135.100" + cell $and $and$ls180.v:6135$1794 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6139$1794_Y - connect \Y $and$ls180.v:6139$1795_Y + connect \B $not$ls180.v:6135$1793_Y + connect \Y $and$ls180.v:6135$1794_Y end - attribute \src "ls180.v:6139.43-6139.150" - cell $and $and$ls180.v:6139$1797 + attribute \src "ls180.v:6135.43-6135.150" + cell $and $and$ls180.v:6135$1796 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6139$1795_Y - connect \B $eq$ls180.v:6139$1796_Y - connect \Y $and$ls180.v:6139$1797_Y + connect \A $and$ls180.v:6135$1794_Y + connect \B $eq$ls180.v:6135$1795_Y + connect \Y $and$ls180.v:6135$1796_Y end - attribute \src "ls180.v:6141.49-6141.102" - cell $and $and$ls180.v:6141$1798 + attribute \src "ls180.v:6137.49-6137.102" + cell $and $and$ls180.v:6137$1797 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -91409,43 +91405,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6141$1798_Y + connect \Y $and$ls180.v:6137$1797_Y end - attribute \src "ls180.v:6141.48-6141.152" - cell $and $and$ls180.v:6141$1800 + attribute \src "ls180.v:6137.48-6137.152" + cell $and $and$ls180.v:6137$1799 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6141$1798_Y - connect \B $eq$ls180.v:6141$1799_Y - connect \Y $and$ls180.v:6141$1800_Y + connect \A $and$ls180.v:6137$1797_Y + connect \B $eq$ls180.v:6137$1798_Y + connect \Y $and$ls180.v:6137$1799_Y end - attribute \src "ls180.v:6142.49-6142.105" - cell $and $and$ls180.v:6142$1802 + attribute \src "ls180.v:6138.49-6138.105" + cell $and $and$ls180.v:6138$1801 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6142$1801_Y - connect \Y $and$ls180.v:6142$1802_Y + connect \B $not$ls180.v:6138$1800_Y + connect \Y $and$ls180.v:6138$1801_Y end - attribute \src "ls180.v:6142.48-6142.155" - cell $and $and$ls180.v:6142$1804 + attribute \src "ls180.v:6138.48-6138.155" + cell $and $and$ls180.v:6138$1803 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6142$1802_Y - connect \B $eq$ls180.v:6142$1803_Y - connect \Y $and$ls180.v:6142$1804_Y + connect \A $and$ls180.v:6138$1801_Y + connect \B $eq$ls180.v:6138$1802_Y + connect \Y $and$ls180.v:6138$1803_Y end - attribute \src "ls180.v:6144.49-6144.102" - cell $and $and$ls180.v:6144$1805 + attribute \src "ls180.v:6140.49-6140.102" + cell $and $and$ls180.v:6140$1804 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -91453,43 +91449,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6144$1805_Y + connect \Y $and$ls180.v:6140$1804_Y end - attribute \src "ls180.v:6144.48-6144.152" - cell $and $and$ls180.v:6144$1807 + attribute \src "ls180.v:6140.48-6140.152" + cell $and $and$ls180.v:6140$1806 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6144$1805_Y - connect \B $eq$ls180.v:6144$1806_Y - connect \Y $and$ls180.v:6144$1807_Y + connect \A $and$ls180.v:6140$1804_Y + connect \B $eq$ls180.v:6140$1805_Y + connect \Y $and$ls180.v:6140$1806_Y end - attribute \src "ls180.v:6145.49-6145.105" - cell $and $and$ls180.v:6145$1809 + attribute \src "ls180.v:6141.49-6141.105" + cell $and $and$ls180.v:6141$1808 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6145$1808_Y - connect \Y $and$ls180.v:6145$1809_Y + connect \B $not$ls180.v:6141$1807_Y + connect \Y $and$ls180.v:6141$1808_Y end - attribute \src "ls180.v:6145.48-6145.155" - cell $and $and$ls180.v:6145$1811 + attribute \src "ls180.v:6141.48-6141.155" + cell $and $and$ls180.v:6141$1810 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6145$1809_Y - connect \B $eq$ls180.v:6145$1810_Y - connect \Y $and$ls180.v:6145$1811_Y + connect \A $and$ls180.v:6141$1808_Y + connect \B $eq$ls180.v:6141$1809_Y + connect \Y $and$ls180.v:6141$1810_Y end - attribute \src "ls180.v:6147.42-6147.95" - cell $and $and$ls180.v:6147$1812 + attribute \src "ls180.v:6143.42-6143.95" + cell $and $and$ls180.v:6143$1811 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -91497,43 +91493,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6147$1812_Y + connect \Y $and$ls180.v:6143$1811_Y end - attribute \src "ls180.v:6147.41-6147.145" - cell $and $and$ls180.v:6147$1814 + attribute \src "ls180.v:6143.41-6143.145" + cell $and $and$ls180.v:6143$1813 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6147$1812_Y - connect \B $eq$ls180.v:6147$1813_Y - connect \Y $and$ls180.v:6147$1814_Y + connect \A $and$ls180.v:6143$1811_Y + connect \B $eq$ls180.v:6143$1812_Y + connect \Y $and$ls180.v:6143$1813_Y end - attribute \src "ls180.v:6148.42-6148.98" - cell $and $and$ls180.v:6148$1816 + attribute \src "ls180.v:6144.42-6144.98" + cell $and $and$ls180.v:6144$1815 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6148$1815_Y - connect \Y $and$ls180.v:6148$1816_Y + connect \B $not$ls180.v:6144$1814_Y + connect \Y $and$ls180.v:6144$1815_Y end - attribute \src "ls180.v:6148.41-6148.148" - cell $and $and$ls180.v:6148$1818 + attribute \src "ls180.v:6144.41-6144.148" + cell $and $and$ls180.v:6144$1817 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6148$1816_Y - connect \B $eq$ls180.v:6148$1817_Y - connect \Y $and$ls180.v:6148$1818_Y + connect \A $and$ls180.v:6144$1815_Y + connect \B $eq$ls180.v:6144$1816_Y + connect \Y $and$ls180.v:6144$1817_Y end - attribute \src "ls180.v:6155.46-6155.99" - cell $and $and$ls180.v:6155$1820 + attribute \src "ls180.v:6151.46-6151.99" + cell $and $and$ls180.v:6151$1819 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -91541,43 +91537,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:6155$1820_Y + connect \Y $and$ls180.v:6151$1819_Y end - attribute \src "ls180.v:6155.45-6155.149" - cell $and $and$ls180.v:6155$1822 + attribute \src "ls180.v:6151.45-6151.149" + cell $and $and$ls180.v:6151$1821 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6155$1820_Y - connect \B $eq$ls180.v:6155$1821_Y - connect \Y $and$ls180.v:6155$1822_Y + connect \A $and$ls180.v:6151$1819_Y + connect \B $eq$ls180.v:6151$1820_Y + connect \Y $and$ls180.v:6151$1821_Y end - attribute \src "ls180.v:6156.46-6156.102" - cell $and $and$ls180.v:6156$1824 + attribute \src "ls180.v:6152.46-6152.102" + cell $and $and$ls180.v:6152$1823 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:6156$1823_Y - connect \Y $and$ls180.v:6156$1824_Y + connect \B $not$ls180.v:6152$1822_Y + connect \Y $and$ls180.v:6152$1823_Y end - attribute \src "ls180.v:6156.45-6156.152" - cell $and $and$ls180.v:6156$1826 + attribute \src "ls180.v:6152.45-6152.152" + cell $and $and$ls180.v:6152$1825 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6156$1824_Y - connect \B $eq$ls180.v:6156$1825_Y - connect \Y $and$ls180.v:6156$1826_Y + connect \A $and$ls180.v:6152$1823_Y + connect \B $eq$ls180.v:6152$1824_Y + connect \Y $and$ls180.v:6152$1825_Y end - attribute \src "ls180.v:6158.50-6158.103" - cell $and $and$ls180.v:6158$1827 + attribute \src "ls180.v:6154.50-6154.103" + cell $and $and$ls180.v:6154$1826 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -91585,43 +91581,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:6158$1827_Y + connect \Y $and$ls180.v:6154$1826_Y end - attribute \src "ls180.v:6158.49-6158.153" - cell $and $and$ls180.v:6158$1829 + attribute \src "ls180.v:6154.49-6154.153" + cell $and $and$ls180.v:6154$1828 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6158$1827_Y - connect \B $eq$ls180.v:6158$1828_Y - connect \Y $and$ls180.v:6158$1829_Y + connect \A $and$ls180.v:6154$1826_Y + connect \B $eq$ls180.v:6154$1827_Y + connect \Y $and$ls180.v:6154$1828_Y end - attribute \src "ls180.v:6159.50-6159.106" - cell $and $and$ls180.v:6159$1831 + attribute \src "ls180.v:6155.50-6155.106" + cell $and $and$ls180.v:6155$1830 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:6159$1830_Y - connect \Y $and$ls180.v:6159$1831_Y + connect \B $not$ls180.v:6155$1829_Y + connect \Y $and$ls180.v:6155$1830_Y end - attribute \src "ls180.v:6159.49-6159.156" - cell $and $and$ls180.v:6159$1833 + attribute \src "ls180.v:6155.49-6155.156" + cell $and $and$ls180.v:6155$1832 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6159$1831_Y - connect \B $eq$ls180.v:6159$1832_Y - connect \Y $and$ls180.v:6159$1833_Y + connect \A $and$ls180.v:6155$1830_Y + connect \B $eq$ls180.v:6155$1831_Y + connect \Y $and$ls180.v:6155$1832_Y end - attribute \src "ls180.v:6161.40-6161.93" - cell $and $and$ls180.v:6161$1834 + attribute \src "ls180.v:6157.40-6157.93" + cell $and $and$ls180.v:6157$1833 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -91629,43 +91625,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:6161$1834_Y + connect \Y $and$ls180.v:6157$1833_Y end - attribute \src "ls180.v:6161.39-6161.143" - cell $and $and$ls180.v:6161$1836 + attribute \src "ls180.v:6157.39-6157.143" + cell $and $and$ls180.v:6157$1835 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6161$1834_Y - connect \B $eq$ls180.v:6161$1835_Y - connect \Y $and$ls180.v:6161$1836_Y + connect \A $and$ls180.v:6157$1833_Y + connect \B $eq$ls180.v:6157$1834_Y + connect \Y $and$ls180.v:6157$1835_Y end - attribute \src "ls180.v:6162.40-6162.96" - cell $and $and$ls180.v:6162$1838 + attribute \src "ls180.v:6158.40-6158.96" + cell $and $and$ls180.v:6158$1837 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:6162$1837_Y - connect \Y $and$ls180.v:6162$1838_Y + connect \B $not$ls180.v:6158$1836_Y + connect \Y $and$ls180.v:6158$1837_Y end - attribute \src "ls180.v:6162.39-6162.146" - cell $and $and$ls180.v:6162$1840 + attribute \src "ls180.v:6158.39-6158.146" + cell $and $and$ls180.v:6158$1839 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6162$1838_Y - connect \B $eq$ls180.v:6162$1839_Y - connect \Y $and$ls180.v:6162$1840_Y + connect \A $and$ls180.v:6158$1837_Y + connect \B $eq$ls180.v:6158$1838_Y + connect \Y $and$ls180.v:6158$1839_Y end - attribute \src "ls180.v:6164.50-6164.103" - cell $and $and$ls180.v:6164$1841 + attribute \src "ls180.v:6160.50-6160.103" + cell $and $and$ls180.v:6160$1840 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -91673,43 +91669,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:6164$1841_Y + connect \Y $and$ls180.v:6160$1840_Y end - attribute \src "ls180.v:6164.49-6164.153" - cell $and $and$ls180.v:6164$1843 + attribute \src "ls180.v:6160.49-6160.153" + cell $and $and$ls180.v:6160$1842 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6164$1841_Y - connect \B $eq$ls180.v:6164$1842_Y - connect \Y $and$ls180.v:6164$1843_Y + connect \A $and$ls180.v:6160$1840_Y + connect \B $eq$ls180.v:6160$1841_Y + connect \Y $and$ls180.v:6160$1842_Y end - attribute \src "ls180.v:6165.50-6165.106" - cell $and $and$ls180.v:6165$1845 + attribute \src "ls180.v:6161.50-6161.106" + cell $and $and$ls180.v:6161$1844 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:6165$1844_Y - connect \Y $and$ls180.v:6165$1845_Y + connect \B $not$ls180.v:6161$1843_Y + connect \Y $and$ls180.v:6161$1844_Y end - attribute \src "ls180.v:6165.49-6165.156" - cell $and $and$ls180.v:6165$1847 + attribute \src "ls180.v:6161.49-6161.156" + cell $and $and$ls180.v:6161$1846 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6165$1845_Y - connect \B $eq$ls180.v:6165$1846_Y - connect \Y $and$ls180.v:6165$1847_Y + connect \A $and$ls180.v:6161$1844_Y + connect \B $eq$ls180.v:6161$1845_Y + connect \Y $and$ls180.v:6161$1846_Y end - attribute \src "ls180.v:6167.50-6167.103" - cell $and $and$ls180.v:6167$1848 + attribute \src "ls180.v:6163.50-6163.103" + cell $and $and$ls180.v:6163$1847 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -91717,43 +91713,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:6167$1848_Y + connect \Y $and$ls180.v:6163$1847_Y end - attribute \src "ls180.v:6167.49-6167.153" - cell $and $and$ls180.v:6167$1850 + attribute \src "ls180.v:6163.49-6163.153" + cell $and $and$ls180.v:6163$1849 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6167$1848_Y - connect \B $eq$ls180.v:6167$1849_Y - connect \Y $and$ls180.v:6167$1850_Y + connect \A $and$ls180.v:6163$1847_Y + connect \B $eq$ls180.v:6163$1848_Y + connect \Y $and$ls180.v:6163$1849_Y end - attribute \src "ls180.v:6168.50-6168.106" - cell $and $and$ls180.v:6168$1852 + attribute \src "ls180.v:6164.50-6164.106" + cell $and $and$ls180.v:6164$1851 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:6168$1851_Y - connect \Y $and$ls180.v:6168$1852_Y + connect \B $not$ls180.v:6164$1850_Y + connect \Y $and$ls180.v:6164$1851_Y end - attribute \src "ls180.v:6168.49-6168.156" - cell $and $and$ls180.v:6168$1854 + attribute \src "ls180.v:6164.49-6164.156" + cell $and $and$ls180.v:6164$1853 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6168$1852_Y - connect \B $eq$ls180.v:6168$1853_Y - connect \Y $and$ls180.v:6168$1854_Y + connect \A $and$ls180.v:6164$1851_Y + connect \B $eq$ls180.v:6164$1852_Y + connect \Y $and$ls180.v:6164$1853_Y end - attribute \src "ls180.v:6170.51-6170.104" - cell $and $and$ls180.v:6170$1855 + attribute \src "ls180.v:6166.51-6166.104" + cell $and $and$ls180.v:6166$1854 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -91761,43 +91757,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:6170$1855_Y + connect \Y $and$ls180.v:6166$1854_Y end - attribute \src "ls180.v:6170.50-6170.154" - cell $and $and$ls180.v:6170$1857 + attribute \src "ls180.v:6166.50-6166.154" + cell $and $and$ls180.v:6166$1856 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6170$1855_Y - connect \B $eq$ls180.v:6170$1856_Y - connect \Y $and$ls180.v:6170$1857_Y + connect \A $and$ls180.v:6166$1854_Y + connect \B $eq$ls180.v:6166$1855_Y + connect \Y $and$ls180.v:6166$1856_Y end - attribute \src "ls180.v:6171.51-6171.107" - cell $and $and$ls180.v:6171$1859 + attribute \src "ls180.v:6167.51-6167.107" + cell $and $and$ls180.v:6167$1858 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:6171$1858_Y - connect \Y $and$ls180.v:6171$1859_Y + connect \B $not$ls180.v:6167$1857_Y + connect \Y $and$ls180.v:6167$1858_Y end - attribute \src "ls180.v:6171.50-6171.157" - cell $and $and$ls180.v:6171$1861 + attribute \src "ls180.v:6167.50-6167.157" + cell $and $and$ls180.v:6167$1860 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6171$1859_Y - connect \B $eq$ls180.v:6171$1860_Y - connect \Y $and$ls180.v:6171$1861_Y + connect \A $and$ls180.v:6167$1858_Y + connect \B $eq$ls180.v:6167$1859_Y + connect \Y $and$ls180.v:6167$1860_Y end - attribute \src "ls180.v:6173.49-6173.102" - cell $and $and$ls180.v:6173$1862 + attribute \src "ls180.v:6169.49-6169.102" + cell $and $and$ls180.v:6169$1861 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -91805,43 +91801,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:6173$1862_Y + connect \Y $and$ls180.v:6169$1861_Y end - attribute \src "ls180.v:6173.48-6173.152" - cell $and $and$ls180.v:6173$1864 + attribute \src "ls180.v:6169.48-6169.152" + cell $and $and$ls180.v:6169$1863 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6173$1862_Y - connect \B $eq$ls180.v:6173$1863_Y - connect \Y $and$ls180.v:6173$1864_Y + connect \A $and$ls180.v:6169$1861_Y + connect \B $eq$ls180.v:6169$1862_Y + connect \Y $and$ls180.v:6169$1863_Y end - attribute \src "ls180.v:6174.49-6174.105" - cell $and $and$ls180.v:6174$1866 + attribute \src "ls180.v:6170.49-6170.105" + cell $and $and$ls180.v:6170$1865 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:6174$1865_Y - connect \Y $and$ls180.v:6174$1866_Y + connect \B $not$ls180.v:6170$1864_Y + connect \Y $and$ls180.v:6170$1865_Y end - attribute \src "ls180.v:6174.48-6174.155" - cell $and $and$ls180.v:6174$1868 + attribute \src "ls180.v:6170.48-6170.155" + cell $and $and$ls180.v:6170$1867 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6174$1866_Y - connect \B $eq$ls180.v:6174$1867_Y - connect \Y $and$ls180.v:6174$1868_Y + connect \A $and$ls180.v:6170$1865_Y + connect \B $eq$ls180.v:6170$1866_Y + connect \Y $and$ls180.v:6170$1867_Y end - attribute \src "ls180.v:6176.49-6176.102" - cell $and $and$ls180.v:6176$1869 + attribute \src "ls180.v:6172.49-6172.102" + cell $and $and$ls180.v:6172$1868 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -91849,43 +91845,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:6176$1869_Y + connect \Y $and$ls180.v:6172$1868_Y end - attribute \src "ls180.v:6176.48-6176.152" - cell $and $and$ls180.v:6176$1871 + attribute \src "ls180.v:6172.48-6172.152" + cell $and $and$ls180.v:6172$1870 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6176$1869_Y - connect \B $eq$ls180.v:6176$1870_Y - connect \Y $and$ls180.v:6176$1871_Y + connect \A $and$ls180.v:6172$1868_Y + connect \B $eq$ls180.v:6172$1869_Y + connect \Y $and$ls180.v:6172$1870_Y end - attribute \src "ls180.v:6177.49-6177.105" - cell $and $and$ls180.v:6177$1873 + attribute \src "ls180.v:6173.49-6173.105" + cell $and $and$ls180.v:6173$1872 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:6177$1872_Y - connect \Y $and$ls180.v:6177$1873_Y + connect \B $not$ls180.v:6173$1871_Y + connect \Y $and$ls180.v:6173$1872_Y end - attribute \src "ls180.v:6177.48-6177.155" - cell $and $and$ls180.v:6177$1875 + attribute \src "ls180.v:6173.48-6173.155" + cell $and $and$ls180.v:6173$1874 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6177$1873_Y - connect \B $eq$ls180.v:6177$1874_Y - connect \Y $and$ls180.v:6177$1875_Y + connect \A $and$ls180.v:6173$1872_Y + connect \B $eq$ls180.v:6173$1873_Y + connect \Y $and$ls180.v:6173$1874_Y end - attribute \src "ls180.v:6179.49-6179.102" - cell $and $and$ls180.v:6179$1876 + attribute \src "ls180.v:6175.49-6175.102" + cell $and $and$ls180.v:6175$1875 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -91893,43 +91889,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:6179$1876_Y + connect \Y $and$ls180.v:6175$1875_Y end - attribute \src "ls180.v:6179.48-6179.152" - cell $and $and$ls180.v:6179$1878 + attribute \src "ls180.v:6175.48-6175.152" + cell $and $and$ls180.v:6175$1877 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6179$1876_Y - connect \B $eq$ls180.v:6179$1877_Y - connect \Y $and$ls180.v:6179$1878_Y + connect \A $and$ls180.v:6175$1875_Y + connect \B $eq$ls180.v:6175$1876_Y + connect \Y $and$ls180.v:6175$1877_Y end - attribute \src "ls180.v:6180.49-6180.105" - cell $and $and$ls180.v:6180$1880 + attribute \src "ls180.v:6176.49-6176.105" + cell $and $and$ls180.v:6176$1879 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:6180$1879_Y - connect \Y $and$ls180.v:6180$1880_Y + connect \B $not$ls180.v:6176$1878_Y + connect \Y $and$ls180.v:6176$1879_Y end - attribute \src "ls180.v:6180.48-6180.155" - cell $and $and$ls180.v:6180$1882 + attribute \src "ls180.v:6176.48-6176.155" + cell $and $and$ls180.v:6176$1881 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6180$1880_Y - connect \B $eq$ls180.v:6180$1881_Y - connect \Y $and$ls180.v:6180$1882_Y + connect \A $and$ls180.v:6176$1879_Y + connect \B $eq$ls180.v:6176$1880_Y + connect \Y $and$ls180.v:6176$1881_Y end - attribute \src "ls180.v:6182.49-6182.102" - cell $and $and$ls180.v:6182$1883 + attribute \src "ls180.v:6178.49-6178.102" + cell $and $and$ls180.v:6178$1882 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -91937,43 +91933,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:6182$1883_Y + connect \Y $and$ls180.v:6178$1882_Y end - attribute \src "ls180.v:6182.48-6182.152" - cell $and $and$ls180.v:6182$1885 + attribute \src "ls180.v:6178.48-6178.152" + cell $and $and$ls180.v:6178$1884 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6182$1883_Y - connect \B $eq$ls180.v:6182$1884_Y - connect \Y $and$ls180.v:6182$1885_Y + connect \A $and$ls180.v:6178$1882_Y + connect \B $eq$ls180.v:6178$1883_Y + connect \Y $and$ls180.v:6178$1884_Y end - attribute \src "ls180.v:6183.49-6183.105" - cell $and $and$ls180.v:6183$1887 + attribute \src "ls180.v:6179.49-6179.105" + cell $and $and$ls180.v:6179$1886 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:6183$1886_Y - connect \Y $and$ls180.v:6183$1887_Y + connect \B $not$ls180.v:6179$1885_Y + connect \Y $and$ls180.v:6179$1886_Y end - attribute \src "ls180.v:6183.48-6183.155" - cell $and $and$ls180.v:6183$1889 + attribute \src "ls180.v:6179.48-6179.155" + cell $and $and$ls180.v:6179$1888 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6183$1887_Y - connect \B $eq$ls180.v:6183$1888_Y - connect \Y $and$ls180.v:6183$1889_Y + connect \A $and$ls180.v:6179$1886_Y + connect \B $eq$ls180.v:6179$1887_Y + connect \Y $and$ls180.v:6179$1888_Y end - attribute \src "ls180.v:6200.41-6200.94" - cell $and $and$ls180.v:6200$1891 + attribute \src "ls180.v:6196.41-6196.94" + cell $and $and$ls180.v:6196$1890 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -91981,43 +91977,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6200$1891_Y + connect \Y $and$ls180.v:6196$1890_Y end - attribute \src "ls180.v:6200.40-6200.144" - cell $and $and$ls180.v:6200$1893 + attribute \src "ls180.v:6196.40-6196.144" + cell $and $and$ls180.v:6196$1892 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6200$1891_Y - connect \B $eq$ls180.v:6200$1892_Y - connect \Y $and$ls180.v:6200$1893_Y + connect \A $and$ls180.v:6196$1890_Y + connect \B $eq$ls180.v:6196$1891_Y + connect \Y $and$ls180.v:6196$1892_Y end - attribute \src "ls180.v:6201.41-6201.97" - cell $and $and$ls180.v:6201$1895 + attribute \src "ls180.v:6197.41-6197.97" + cell $and $and$ls180.v:6197$1894 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6201$1894_Y - connect \Y $and$ls180.v:6201$1895_Y + connect \B $not$ls180.v:6197$1893_Y + connect \Y $and$ls180.v:6197$1894_Y end - attribute \src "ls180.v:6201.40-6201.147" - cell $and $and$ls180.v:6201$1897 + attribute \src "ls180.v:6197.40-6197.147" + cell $and $and$ls180.v:6197$1896 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6201$1895_Y - connect \B $eq$ls180.v:6201$1896_Y - connect \Y $and$ls180.v:6201$1897_Y + connect \A $and$ls180.v:6197$1894_Y + connect \B $eq$ls180.v:6197$1895_Y + connect \Y $and$ls180.v:6197$1896_Y end - attribute \src "ls180.v:6203.41-6203.94" - cell $and $and$ls180.v:6203$1898 + attribute \src "ls180.v:6199.41-6199.94" + cell $and $and$ls180.v:6199$1897 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -92025,43 +92021,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6203$1898_Y + connect \Y $and$ls180.v:6199$1897_Y end - attribute \src "ls180.v:6203.40-6203.144" - cell $and $and$ls180.v:6203$1900 + attribute \src "ls180.v:6199.40-6199.144" + cell $and $and$ls180.v:6199$1899 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6203$1898_Y - connect \B $eq$ls180.v:6203$1899_Y - connect \Y $and$ls180.v:6203$1900_Y + connect \A $and$ls180.v:6199$1897_Y + connect \B $eq$ls180.v:6199$1898_Y + connect \Y $and$ls180.v:6199$1899_Y end - attribute \src "ls180.v:6204.41-6204.97" - cell $and $and$ls180.v:6204$1902 + attribute \src "ls180.v:6200.41-6200.97" + cell $and $and$ls180.v:6200$1901 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6204$1901_Y - connect \Y $and$ls180.v:6204$1902_Y + connect \B $not$ls180.v:6200$1900_Y + connect \Y $and$ls180.v:6200$1901_Y end - attribute \src "ls180.v:6204.40-6204.147" - cell $and $and$ls180.v:6204$1904 + attribute \src "ls180.v:6200.40-6200.147" + cell $and $and$ls180.v:6200$1903 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6204$1902_Y - connect \B $eq$ls180.v:6204$1903_Y - connect \Y $and$ls180.v:6204$1904_Y + connect \A $and$ls180.v:6200$1901_Y + connect \B $eq$ls180.v:6200$1902_Y + connect \Y $and$ls180.v:6200$1903_Y end - attribute \src "ls180.v:6206.39-6206.92" - cell $and $and$ls180.v:6206$1905 + attribute \src "ls180.v:6202.39-6202.92" + cell $and $and$ls180.v:6202$1904 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -92069,43 +92065,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6206$1905_Y + connect \Y $and$ls180.v:6202$1904_Y end - attribute \src "ls180.v:6206.38-6206.142" - cell $and $and$ls180.v:6206$1907 + attribute \src "ls180.v:6202.38-6202.142" + cell $and $and$ls180.v:6202$1906 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6206$1905_Y - connect \B $eq$ls180.v:6206$1906_Y - connect \Y $and$ls180.v:6206$1907_Y + connect \A $and$ls180.v:6202$1904_Y + connect \B $eq$ls180.v:6202$1905_Y + connect \Y $and$ls180.v:6202$1906_Y end - attribute \src "ls180.v:6207.39-6207.95" - cell $and $and$ls180.v:6207$1909 + attribute \src "ls180.v:6203.39-6203.95" + cell $and $and$ls180.v:6203$1908 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6207$1908_Y - connect \Y $and$ls180.v:6207$1909_Y + connect \B $not$ls180.v:6203$1907_Y + connect \Y $and$ls180.v:6203$1908_Y end - attribute \src "ls180.v:6207.38-6207.145" - cell $and $and$ls180.v:6207$1911 + attribute \src "ls180.v:6203.38-6203.145" + cell $and $and$ls180.v:6203$1910 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6207$1909_Y - connect \B $eq$ls180.v:6207$1910_Y - connect \Y $and$ls180.v:6207$1911_Y + connect \A $and$ls180.v:6203$1908_Y + connect \B $eq$ls180.v:6203$1909_Y + connect \Y $and$ls180.v:6203$1910_Y end - attribute \src "ls180.v:6209.38-6209.91" - cell $and $and$ls180.v:6209$1912 + attribute \src "ls180.v:6205.38-6205.91" + cell $and $and$ls180.v:6205$1911 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -92113,43 +92109,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6209$1912_Y + connect \Y $and$ls180.v:6205$1911_Y end - attribute \src "ls180.v:6209.37-6209.141" - cell $and $and$ls180.v:6209$1914 + attribute \src "ls180.v:6205.37-6205.141" + cell $and $and$ls180.v:6205$1913 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6209$1912_Y - connect \B $eq$ls180.v:6209$1913_Y - connect \Y $and$ls180.v:6209$1914_Y + connect \A $and$ls180.v:6205$1911_Y + connect \B $eq$ls180.v:6205$1912_Y + connect \Y $and$ls180.v:6205$1913_Y end - attribute \src "ls180.v:6210.38-6210.94" - cell $and $and$ls180.v:6210$1916 + attribute \src "ls180.v:6206.38-6206.94" + cell $and $and$ls180.v:6206$1915 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6210$1915_Y - connect \Y $and$ls180.v:6210$1916_Y + connect \B $not$ls180.v:6206$1914_Y + connect \Y $and$ls180.v:6206$1915_Y end - attribute \src "ls180.v:6210.37-6210.144" - cell $and $and$ls180.v:6210$1918 + attribute \src "ls180.v:6206.37-6206.144" + cell $and $and$ls180.v:6206$1917 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6210$1916_Y - connect \B $eq$ls180.v:6210$1917_Y - connect \Y $and$ls180.v:6210$1918_Y + connect \A $and$ls180.v:6206$1915_Y + connect \B $eq$ls180.v:6206$1916_Y + connect \Y $and$ls180.v:6206$1917_Y end - attribute \src "ls180.v:6212.37-6212.90" - cell $and $and$ls180.v:6212$1919 + attribute \src "ls180.v:6208.37-6208.90" + cell $and $and$ls180.v:6208$1918 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -92157,43 +92153,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6212$1919_Y + connect \Y $and$ls180.v:6208$1918_Y end - attribute \src "ls180.v:6212.36-6212.140" - cell $and $and$ls180.v:6212$1921 + attribute \src "ls180.v:6208.36-6208.140" + cell $and $and$ls180.v:6208$1920 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6212$1919_Y - connect \B $eq$ls180.v:6212$1920_Y - connect \Y $and$ls180.v:6212$1921_Y + connect \A $and$ls180.v:6208$1918_Y + connect \B $eq$ls180.v:6208$1919_Y + connect \Y $and$ls180.v:6208$1920_Y end - attribute \src "ls180.v:6213.37-6213.93" - cell $and $and$ls180.v:6213$1923 + attribute \src "ls180.v:6209.37-6209.93" + cell $and $and$ls180.v:6209$1922 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6213$1922_Y - connect \Y $and$ls180.v:6213$1923_Y + connect \B $not$ls180.v:6209$1921_Y + connect \Y $and$ls180.v:6209$1922_Y end - attribute \src "ls180.v:6213.36-6213.143" - cell $and $and$ls180.v:6213$1925 + attribute \src "ls180.v:6209.36-6209.143" + cell $and $and$ls180.v:6209$1924 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6213$1923_Y - connect \B $eq$ls180.v:6213$1924_Y - connect \Y $and$ls180.v:6213$1925_Y + connect \A $and$ls180.v:6209$1922_Y + connect \B $eq$ls180.v:6209$1923_Y + connect \Y $and$ls180.v:6209$1924_Y end - attribute \src "ls180.v:6215.36-6215.89" - cell $and $and$ls180.v:6215$1926 + attribute \src "ls180.v:6211.36-6211.89" + cell $and $and$ls180.v:6211$1925 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -92201,43 +92197,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6215$1926_Y + connect \Y $and$ls180.v:6211$1925_Y end - attribute \src "ls180.v:6215.35-6215.139" - cell $and $and$ls180.v:6215$1928 + attribute \src "ls180.v:6211.35-6211.139" + cell $and $and$ls180.v:6211$1927 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6215$1926_Y - connect \B $eq$ls180.v:6215$1927_Y - connect \Y $and$ls180.v:6215$1928_Y + connect \A $and$ls180.v:6211$1925_Y + connect \B $eq$ls180.v:6211$1926_Y + connect \Y $and$ls180.v:6211$1927_Y end - attribute \src "ls180.v:6216.36-6216.92" - cell $and $and$ls180.v:6216$1930 + attribute \src "ls180.v:6212.36-6212.92" + cell $and $and$ls180.v:6212$1929 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6216$1929_Y - connect \Y $and$ls180.v:6216$1930_Y + connect \B $not$ls180.v:6212$1928_Y + connect \Y $and$ls180.v:6212$1929_Y end - attribute \src "ls180.v:6216.35-6216.142" - cell $and $and$ls180.v:6216$1932 + attribute \src "ls180.v:6212.35-6212.142" + cell $and $and$ls180.v:6212$1931 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6216$1930_Y - connect \B $eq$ls180.v:6216$1931_Y - connect \Y $and$ls180.v:6216$1932_Y + connect \A $and$ls180.v:6212$1929_Y + connect \B $eq$ls180.v:6212$1930_Y + connect \Y $and$ls180.v:6212$1931_Y end - attribute \src "ls180.v:6218.42-6218.95" - cell $and $and$ls180.v:6218$1933 + attribute \src "ls180.v:6214.42-6214.95" + cell $and $and$ls180.v:6214$1932 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -92245,43 +92241,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6218$1933_Y + connect \Y $and$ls180.v:6214$1932_Y end - attribute \src "ls180.v:6218.41-6218.145" - cell $and $and$ls180.v:6218$1935 + attribute \src "ls180.v:6214.41-6214.145" + cell $and $and$ls180.v:6214$1934 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6218$1933_Y - connect \B $eq$ls180.v:6218$1934_Y - connect \Y $and$ls180.v:6218$1935_Y + connect \A $and$ls180.v:6214$1932_Y + connect \B $eq$ls180.v:6214$1933_Y + connect \Y $and$ls180.v:6214$1934_Y end - attribute \src "ls180.v:6219.42-6219.98" - cell $and $and$ls180.v:6219$1937 + attribute \src "ls180.v:6215.42-6215.98" + cell $and $and$ls180.v:6215$1936 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6219$1936_Y - connect \Y $and$ls180.v:6219$1937_Y + connect \B $not$ls180.v:6215$1935_Y + connect \Y $and$ls180.v:6215$1936_Y end - attribute \src "ls180.v:6219.41-6219.148" - cell $and $and$ls180.v:6219$1939 + attribute \src "ls180.v:6215.41-6215.148" + cell $and $and$ls180.v:6215$1938 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6219$1937_Y - connect \B $eq$ls180.v:6219$1938_Y - connect \Y $and$ls180.v:6219$1939_Y + connect \A $and$ls180.v:6215$1936_Y + connect \B $eq$ls180.v:6215$1937_Y + connect \Y $and$ls180.v:6215$1938_Y end - attribute \src "ls180.v:6240.42-6240.97" - cell $and $and$ls180.v:6240$1942 + attribute \src "ls180.v:6236.42-6236.97" + cell $and $and$ls180.v:6236$1941 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -92289,43 +92285,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6240$1942_Y + connect \Y $and$ls180.v:6236$1941_Y end - attribute \src "ls180.v:6240.41-6240.148" - cell $and $and$ls180.v:6240$1944 + attribute \src "ls180.v:6236.41-6236.148" + cell $and $and$ls180.v:6236$1943 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6240$1942_Y - connect \B $eq$ls180.v:6240$1943_Y - connect \Y $and$ls180.v:6240$1944_Y + connect \A $and$ls180.v:6236$1941_Y + connect \B $eq$ls180.v:6236$1942_Y + connect \Y $and$ls180.v:6236$1943_Y end - attribute \src "ls180.v:6241.42-6241.100" - cell $and $and$ls180.v:6241$1946 + attribute \src "ls180.v:6237.42-6237.100" + cell $and $and$ls180.v:6237$1945 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6241$1945_Y - connect \Y $and$ls180.v:6241$1946_Y + connect \B $not$ls180.v:6237$1944_Y + connect \Y $and$ls180.v:6237$1945_Y end - attribute \src "ls180.v:6241.41-6241.151" - cell $and $and$ls180.v:6241$1948 + attribute \src "ls180.v:6237.41-6237.151" + cell $and $and$ls180.v:6237$1947 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6241$1946_Y - connect \B $eq$ls180.v:6241$1947_Y - connect \Y $and$ls180.v:6241$1948_Y + connect \A $and$ls180.v:6237$1945_Y + connect \B $eq$ls180.v:6237$1946_Y + connect \Y $and$ls180.v:6237$1947_Y end - attribute \src "ls180.v:6243.42-6243.97" - cell $and $and$ls180.v:6243$1949 + attribute \src "ls180.v:6239.42-6239.97" + cell $and $and$ls180.v:6239$1948 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -92333,43 +92329,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6243$1949_Y + connect \Y $and$ls180.v:6239$1948_Y end - attribute \src "ls180.v:6243.41-6243.148" - cell $and $and$ls180.v:6243$1951 + attribute \src "ls180.v:6239.41-6239.148" + cell $and $and$ls180.v:6239$1950 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6243$1949_Y - connect \B $eq$ls180.v:6243$1950_Y - connect \Y $and$ls180.v:6243$1951_Y + connect \A $and$ls180.v:6239$1948_Y + connect \B $eq$ls180.v:6239$1949_Y + connect \Y $and$ls180.v:6239$1950_Y end - attribute \src "ls180.v:6244.42-6244.100" - cell $and $and$ls180.v:6244$1953 + attribute \src "ls180.v:6240.42-6240.100" + cell $and $and$ls180.v:6240$1952 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6244$1952_Y - connect \Y $and$ls180.v:6244$1953_Y + connect \B $not$ls180.v:6240$1951_Y + connect \Y $and$ls180.v:6240$1952_Y end - attribute \src "ls180.v:6244.41-6244.151" - cell $and $and$ls180.v:6244$1955 + attribute \src "ls180.v:6240.41-6240.151" + cell $and $and$ls180.v:6240$1954 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6244$1953_Y - connect \B $eq$ls180.v:6244$1954_Y - connect \Y $and$ls180.v:6244$1955_Y + connect \A $and$ls180.v:6240$1952_Y + connect \B $eq$ls180.v:6240$1953_Y + connect \Y $and$ls180.v:6240$1954_Y end - attribute \src "ls180.v:6246.40-6246.95" - cell $and $and$ls180.v:6246$1956 + attribute \src "ls180.v:6242.40-6242.95" + cell $and $and$ls180.v:6242$1955 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -92377,43 +92373,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6246$1956_Y + connect \Y $and$ls180.v:6242$1955_Y end - attribute \src "ls180.v:6246.39-6246.146" - cell $and $and$ls180.v:6246$1958 + attribute \src "ls180.v:6242.39-6242.146" + cell $and $and$ls180.v:6242$1957 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6246$1956_Y - connect \B $eq$ls180.v:6246$1957_Y - connect \Y $and$ls180.v:6246$1958_Y + connect \A $and$ls180.v:6242$1955_Y + connect \B $eq$ls180.v:6242$1956_Y + connect \Y $and$ls180.v:6242$1957_Y end - attribute \src "ls180.v:6247.40-6247.98" - cell $and $and$ls180.v:6247$1960 + attribute \src "ls180.v:6243.40-6243.98" + cell $and $and$ls180.v:6243$1959 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6247$1959_Y - connect \Y $and$ls180.v:6247$1960_Y + connect \B $not$ls180.v:6243$1958_Y + connect \Y $and$ls180.v:6243$1959_Y end - attribute \src "ls180.v:6247.39-6247.149" - cell $and $and$ls180.v:6247$1962 + attribute \src "ls180.v:6243.39-6243.149" + cell $and $and$ls180.v:6243$1961 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6247$1960_Y - connect \B $eq$ls180.v:6247$1961_Y - connect \Y $and$ls180.v:6247$1962_Y + connect \A $and$ls180.v:6243$1959_Y + connect \B $eq$ls180.v:6243$1960_Y + connect \Y $and$ls180.v:6243$1961_Y end - attribute \src "ls180.v:6249.39-6249.94" - cell $and $and$ls180.v:6249$1963 + attribute \src "ls180.v:6245.39-6245.94" + cell $and $and$ls180.v:6245$1962 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -92421,43 +92417,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6249$1963_Y + connect \Y $and$ls180.v:6245$1962_Y end - attribute \src "ls180.v:6249.38-6249.145" - cell $and $and$ls180.v:6249$1965 + attribute \src "ls180.v:6245.38-6245.145" + cell $and $and$ls180.v:6245$1964 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6249$1963_Y - connect \B $eq$ls180.v:6249$1964_Y - connect \Y $and$ls180.v:6249$1965_Y + connect \A $and$ls180.v:6245$1962_Y + connect \B $eq$ls180.v:6245$1963_Y + connect \Y $and$ls180.v:6245$1964_Y end - attribute \src "ls180.v:6250.39-6250.97" - cell $and $and$ls180.v:6250$1967 + attribute \src "ls180.v:6246.39-6246.97" + cell $and $and$ls180.v:6246$1966 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6250$1966_Y - connect \Y $and$ls180.v:6250$1967_Y + connect \B $not$ls180.v:6246$1965_Y + connect \Y $and$ls180.v:6246$1966_Y end - attribute \src "ls180.v:6250.38-6250.148" - cell $and $and$ls180.v:6250$1969 + attribute \src "ls180.v:6246.38-6246.148" + cell $and $and$ls180.v:6246$1968 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6250$1967_Y - connect \B $eq$ls180.v:6250$1968_Y - connect \Y $and$ls180.v:6250$1969_Y + connect \A $and$ls180.v:6246$1966_Y + connect \B $eq$ls180.v:6246$1967_Y + connect \Y $and$ls180.v:6246$1968_Y end - attribute \src "ls180.v:6252.38-6252.93" - cell $and $and$ls180.v:6252$1970 + attribute \src "ls180.v:6248.38-6248.93" + cell $and $and$ls180.v:6248$1969 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -92465,43 +92461,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6252$1970_Y + connect \Y $and$ls180.v:6248$1969_Y end - attribute \src "ls180.v:6252.37-6252.144" - cell $and $and$ls180.v:6252$1972 + attribute \src "ls180.v:6248.37-6248.144" + cell $and $and$ls180.v:6248$1971 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6252$1970_Y - connect \B $eq$ls180.v:6252$1971_Y - connect \Y $and$ls180.v:6252$1972_Y + connect \A $and$ls180.v:6248$1969_Y + connect \B $eq$ls180.v:6248$1970_Y + connect \Y $and$ls180.v:6248$1971_Y end - attribute \src "ls180.v:6253.38-6253.96" - cell $and $and$ls180.v:6253$1974 + attribute \src "ls180.v:6249.38-6249.96" + cell $and $and$ls180.v:6249$1973 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6253$1973_Y - connect \Y $and$ls180.v:6253$1974_Y + connect \B $not$ls180.v:6249$1972_Y + connect \Y $and$ls180.v:6249$1973_Y end - attribute \src "ls180.v:6253.37-6253.147" - cell $and $and$ls180.v:6253$1976 + attribute \src "ls180.v:6249.37-6249.147" + cell $and $and$ls180.v:6249$1975 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6253$1974_Y - connect \B $eq$ls180.v:6253$1975_Y - connect \Y $and$ls180.v:6253$1976_Y + connect \A $and$ls180.v:6249$1973_Y + connect \B $eq$ls180.v:6249$1974_Y + connect \Y $and$ls180.v:6249$1975_Y end - attribute \src "ls180.v:6255.37-6255.92" - cell $and $and$ls180.v:6255$1977 + attribute \src "ls180.v:6251.37-6251.92" + cell $and $and$ls180.v:6251$1976 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -92509,43 +92505,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6255$1977_Y + connect \Y $and$ls180.v:6251$1976_Y end - attribute \src "ls180.v:6255.36-6255.143" - cell $and $and$ls180.v:6255$1979 + attribute \src "ls180.v:6251.36-6251.143" + cell $and $and$ls180.v:6251$1978 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6255$1977_Y - connect \B $eq$ls180.v:6255$1978_Y - connect \Y $and$ls180.v:6255$1979_Y + connect \A $and$ls180.v:6251$1976_Y + connect \B $eq$ls180.v:6251$1977_Y + connect \Y $and$ls180.v:6251$1978_Y end - attribute \src "ls180.v:6256.37-6256.95" - cell $and $and$ls180.v:6256$1981 + attribute \src "ls180.v:6252.37-6252.95" + cell $and $and$ls180.v:6252$1980 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6256$1980_Y - connect \Y $and$ls180.v:6256$1981_Y + connect \B $not$ls180.v:6252$1979_Y + connect \Y $and$ls180.v:6252$1980_Y end - attribute \src "ls180.v:6256.36-6256.146" - cell $and $and$ls180.v:6256$1983 + attribute \src "ls180.v:6252.36-6252.146" + cell $and $and$ls180.v:6252$1982 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6256$1981_Y - connect \B $eq$ls180.v:6256$1982_Y - connect \Y $and$ls180.v:6256$1983_Y + connect \A $and$ls180.v:6252$1980_Y + connect \B $eq$ls180.v:6252$1981_Y + connect \Y $and$ls180.v:6252$1982_Y end - attribute \src "ls180.v:6258.43-6258.98" - cell $and $and$ls180.v:6258$1984 + attribute \src "ls180.v:6254.43-6254.98" + cell $and $and$ls180.v:6254$1983 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -92553,43 +92549,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6258$1984_Y + connect \Y $and$ls180.v:6254$1983_Y end - attribute \src "ls180.v:6258.42-6258.149" - cell $and $and$ls180.v:6258$1986 + attribute \src "ls180.v:6254.42-6254.149" + cell $and $and$ls180.v:6254$1985 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6258$1984_Y - connect \B $eq$ls180.v:6258$1985_Y - connect \Y $and$ls180.v:6258$1986_Y + connect \A $and$ls180.v:6254$1983_Y + connect \B $eq$ls180.v:6254$1984_Y + connect \Y $and$ls180.v:6254$1985_Y end - attribute \src "ls180.v:6259.43-6259.101" - cell $and $and$ls180.v:6259$1988 + attribute \src "ls180.v:6255.43-6255.101" + cell $and $and$ls180.v:6255$1987 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6259$1987_Y - connect \Y $and$ls180.v:6259$1988_Y + connect \B $not$ls180.v:6255$1986_Y + connect \Y $and$ls180.v:6255$1987_Y end - attribute \src "ls180.v:6259.42-6259.152" - cell $and $and$ls180.v:6259$1990 + attribute \src "ls180.v:6255.42-6255.152" + cell $and $and$ls180.v:6255$1989 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6259$1988_Y - connect \B $eq$ls180.v:6259$1989_Y - connect \Y $and$ls180.v:6259$1990_Y + connect \A $and$ls180.v:6255$1987_Y + connect \B $eq$ls180.v:6255$1988_Y + connect \Y $and$ls180.v:6255$1989_Y end - attribute \src "ls180.v:6261.46-6261.101" - cell $and $and$ls180.v:6261$1991 + attribute \src "ls180.v:6257.46-6257.101" + cell $and $and$ls180.v:6257$1990 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -92597,43 +92593,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6261$1991_Y + connect \Y $and$ls180.v:6257$1990_Y end - attribute \src "ls180.v:6261.45-6261.152" - cell $and $and$ls180.v:6261$1993 + attribute \src "ls180.v:6257.45-6257.152" + cell $and $and$ls180.v:6257$1992 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6261$1991_Y - connect \B $eq$ls180.v:6261$1992_Y - connect \Y $and$ls180.v:6261$1993_Y + connect \A $and$ls180.v:6257$1990_Y + connect \B $eq$ls180.v:6257$1991_Y + connect \Y $and$ls180.v:6257$1992_Y end - attribute \src "ls180.v:6262.46-6262.104" - cell $and $and$ls180.v:6262$1995 + attribute \src "ls180.v:6258.46-6258.104" + cell $and $and$ls180.v:6258$1994 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6262$1994_Y - connect \Y $and$ls180.v:6262$1995_Y + connect \B $not$ls180.v:6258$1993_Y + connect \Y $and$ls180.v:6258$1994_Y end - attribute \src "ls180.v:6262.45-6262.155" - cell $and $and$ls180.v:6262$1997 + attribute \src "ls180.v:6258.45-6258.155" + cell $and $and$ls180.v:6258$1996 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6262$1995_Y - connect \B $eq$ls180.v:6262$1996_Y - connect \Y $and$ls180.v:6262$1997_Y + connect \A $and$ls180.v:6258$1994_Y + connect \B $eq$ls180.v:6258$1995_Y + connect \Y $and$ls180.v:6258$1996_Y end - attribute \src "ls180.v:6264.46-6264.101" - cell $and $and$ls180.v:6264$1998 + attribute \src "ls180.v:6260.46-6260.101" + cell $and $and$ls180.v:6260$1997 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -92641,43 +92637,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6264$1998_Y + connect \Y $and$ls180.v:6260$1997_Y end - attribute \src "ls180.v:6264.45-6264.152" - cell $and $and$ls180.v:6264$2000 + attribute \src "ls180.v:6260.45-6260.152" + cell $and $and$ls180.v:6260$1999 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6264$1998_Y - connect \B $eq$ls180.v:6264$1999_Y - connect \Y $and$ls180.v:6264$2000_Y + connect \A $and$ls180.v:6260$1997_Y + connect \B $eq$ls180.v:6260$1998_Y + connect \Y $and$ls180.v:6260$1999_Y end - attribute \src "ls180.v:6265.46-6265.104" - cell $and $and$ls180.v:6265$2002 + attribute \src "ls180.v:6261.46-6261.104" + cell $and $and$ls180.v:6261$2001 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6265$2001_Y - connect \Y $and$ls180.v:6265$2002_Y + connect \B $not$ls180.v:6261$2000_Y + connect \Y $and$ls180.v:6261$2001_Y end - attribute \src "ls180.v:6265.45-6265.155" - cell $and $and$ls180.v:6265$2004 + attribute \src "ls180.v:6261.45-6261.155" + cell $and $and$ls180.v:6261$2003 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6265$2002_Y - connect \B $eq$ls180.v:6265$2003_Y - connect \Y $and$ls180.v:6265$2004_Y + connect \A $and$ls180.v:6261$2001_Y + connect \B $eq$ls180.v:6261$2002_Y + connect \Y $and$ls180.v:6261$2003_Y end - attribute \src "ls180.v:6288.39-6288.94" - cell $and $and$ls180.v:6288$2007 + attribute \src "ls180.v:6284.39-6284.94" + cell $and $and$ls180.v:6284$2006 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -92685,43 +92681,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6288$2007_Y + connect \Y $and$ls180.v:6284$2006_Y end - attribute \src "ls180.v:6288.38-6288.145" - cell $and $and$ls180.v:6288$2009 + attribute \src "ls180.v:6284.38-6284.145" + cell $and $and$ls180.v:6284$2008 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6288$2007_Y - connect \B $eq$ls180.v:6288$2008_Y - connect \Y $and$ls180.v:6288$2009_Y + connect \A $and$ls180.v:6284$2006_Y + connect \B $eq$ls180.v:6284$2007_Y + connect \Y $and$ls180.v:6284$2008_Y end - attribute \src "ls180.v:6289.39-6289.97" - cell $and $and$ls180.v:6289$2011 + attribute \src "ls180.v:6285.39-6285.97" + cell $and $and$ls180.v:6285$2010 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6289$2010_Y - connect \Y $and$ls180.v:6289$2011_Y + connect \B $not$ls180.v:6285$2009_Y + connect \Y $and$ls180.v:6285$2010_Y end - attribute \src "ls180.v:6289.38-6289.148" - cell $and $and$ls180.v:6289$2013 + attribute \src "ls180.v:6285.38-6285.148" + cell $and $and$ls180.v:6285$2012 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6289$2011_Y - connect \B $eq$ls180.v:6289$2012_Y - connect \Y $and$ls180.v:6289$2013_Y + connect \A $and$ls180.v:6285$2010_Y + connect \B $eq$ls180.v:6285$2011_Y + connect \Y $and$ls180.v:6285$2012_Y end - attribute \src "ls180.v:6291.39-6291.94" - cell $and $and$ls180.v:6291$2014 + attribute \src "ls180.v:6287.39-6287.94" + cell $and $and$ls180.v:6287$2013 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -92729,43 +92725,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6291$2014_Y + connect \Y $and$ls180.v:6287$2013_Y end - attribute \src "ls180.v:6291.38-6291.145" - cell $and $and$ls180.v:6291$2016 + attribute \src "ls180.v:6287.38-6287.145" + cell $and $and$ls180.v:6287$2015 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6291$2014_Y - connect \B $eq$ls180.v:6291$2015_Y - connect \Y $and$ls180.v:6291$2016_Y + connect \A $and$ls180.v:6287$2013_Y + connect \B $eq$ls180.v:6287$2014_Y + connect \Y $and$ls180.v:6287$2015_Y end - attribute \src "ls180.v:6292.39-6292.97" - cell $and $and$ls180.v:6292$2018 + attribute \src "ls180.v:6288.39-6288.97" + cell $and $and$ls180.v:6288$2017 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6292$2017_Y - connect \Y $and$ls180.v:6292$2018_Y + connect \B $not$ls180.v:6288$2016_Y + connect \Y $and$ls180.v:6288$2017_Y end - attribute \src "ls180.v:6292.38-6292.148" - cell $and $and$ls180.v:6292$2020 + attribute \src "ls180.v:6288.38-6288.148" + cell $and $and$ls180.v:6288$2019 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6292$2018_Y - connect \B $eq$ls180.v:6292$2019_Y - connect \Y $and$ls180.v:6292$2020_Y + connect \A $and$ls180.v:6288$2017_Y + connect \B $eq$ls180.v:6288$2018_Y + connect \Y $and$ls180.v:6288$2019_Y end - attribute \src "ls180.v:6294.39-6294.94" - cell $and $and$ls180.v:6294$2021 + attribute \src "ls180.v:6290.39-6290.94" + cell $and $and$ls180.v:6290$2020 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -92773,43 +92769,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6294$2021_Y + connect \Y $and$ls180.v:6290$2020_Y end - attribute \src "ls180.v:6294.38-6294.145" - cell $and $and$ls180.v:6294$2023 + attribute \src "ls180.v:6290.38-6290.145" + cell $and $and$ls180.v:6290$2022 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6294$2021_Y - connect \B $eq$ls180.v:6294$2022_Y - connect \Y $and$ls180.v:6294$2023_Y + connect \A $and$ls180.v:6290$2020_Y + connect \B $eq$ls180.v:6290$2021_Y + connect \Y $and$ls180.v:6290$2022_Y end - attribute \src "ls180.v:6295.39-6295.97" - cell $and $and$ls180.v:6295$2025 + attribute \src "ls180.v:6291.39-6291.97" + cell $and $and$ls180.v:6291$2024 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6295$2024_Y - connect \Y $and$ls180.v:6295$2025_Y + connect \B $not$ls180.v:6291$2023_Y + connect \Y $and$ls180.v:6291$2024_Y end - attribute \src "ls180.v:6295.38-6295.148" - cell $and $and$ls180.v:6295$2027 + attribute \src "ls180.v:6291.38-6291.148" + cell $and $and$ls180.v:6291$2026 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6295$2025_Y - connect \B $eq$ls180.v:6295$2026_Y - connect \Y $and$ls180.v:6295$2027_Y + connect \A $and$ls180.v:6291$2024_Y + connect \B $eq$ls180.v:6291$2025_Y + connect \Y $and$ls180.v:6291$2026_Y end - attribute \src "ls180.v:6297.39-6297.94" - cell $and $and$ls180.v:6297$2028 + attribute \src "ls180.v:6293.39-6293.94" + cell $and $and$ls180.v:6293$2027 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -92817,43 +92813,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6297$2028_Y + connect \Y $and$ls180.v:6293$2027_Y end - attribute \src "ls180.v:6297.38-6297.145" - cell $and $and$ls180.v:6297$2030 + attribute \src "ls180.v:6293.38-6293.145" + cell $and $and$ls180.v:6293$2029 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6297$2028_Y - connect \B $eq$ls180.v:6297$2029_Y - connect \Y $and$ls180.v:6297$2030_Y + connect \A $and$ls180.v:6293$2027_Y + connect \B $eq$ls180.v:6293$2028_Y + connect \Y $and$ls180.v:6293$2029_Y end - attribute \src "ls180.v:6298.39-6298.97" - cell $and $and$ls180.v:6298$2032 + attribute \src "ls180.v:6294.39-6294.97" + cell $and $and$ls180.v:6294$2031 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6298$2031_Y - connect \Y $and$ls180.v:6298$2032_Y + connect \B $not$ls180.v:6294$2030_Y + connect \Y $and$ls180.v:6294$2031_Y end - attribute \src "ls180.v:6298.38-6298.148" - cell $and $and$ls180.v:6298$2034 + attribute \src "ls180.v:6294.38-6294.148" + cell $and $and$ls180.v:6294$2033 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6298$2032_Y - connect \B $eq$ls180.v:6298$2033_Y - connect \Y $and$ls180.v:6298$2034_Y + connect \A $and$ls180.v:6294$2031_Y + connect \B $eq$ls180.v:6294$2032_Y + connect \Y $and$ls180.v:6294$2033_Y end - attribute \src "ls180.v:6300.41-6300.96" - cell $and $and$ls180.v:6300$2035 + attribute \src "ls180.v:6296.41-6296.96" + cell $and $and$ls180.v:6296$2034 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -92861,43 +92857,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6300$2035_Y + connect \Y $and$ls180.v:6296$2034_Y end - attribute \src "ls180.v:6300.40-6300.147" - cell $and $and$ls180.v:6300$2037 + attribute \src "ls180.v:6296.40-6296.147" + cell $and $and$ls180.v:6296$2036 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6300$2035_Y - connect \B $eq$ls180.v:6300$2036_Y - connect \Y $and$ls180.v:6300$2037_Y + connect \A $and$ls180.v:6296$2034_Y + connect \B $eq$ls180.v:6296$2035_Y + connect \Y $and$ls180.v:6296$2036_Y end - attribute \src "ls180.v:6301.41-6301.99" - cell $and $and$ls180.v:6301$2039 + attribute \src "ls180.v:6297.41-6297.99" + cell $and $and$ls180.v:6297$2038 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6301$2038_Y - connect \Y $and$ls180.v:6301$2039_Y + connect \B $not$ls180.v:6297$2037_Y + connect \Y $and$ls180.v:6297$2038_Y end - attribute \src "ls180.v:6301.40-6301.150" - cell $and $and$ls180.v:6301$2041 + attribute \src "ls180.v:6297.40-6297.150" + cell $and $and$ls180.v:6297$2040 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6301$2039_Y - connect \B $eq$ls180.v:6301$2040_Y - connect \Y $and$ls180.v:6301$2041_Y + connect \A $and$ls180.v:6297$2038_Y + connect \B $eq$ls180.v:6297$2039_Y + connect \Y $and$ls180.v:6297$2040_Y end - attribute \src "ls180.v:6303.41-6303.96" - cell $and $and$ls180.v:6303$2042 + attribute \src "ls180.v:6299.41-6299.96" + cell $and $and$ls180.v:6299$2041 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -92905,43 +92901,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6303$2042_Y + connect \Y $and$ls180.v:6299$2041_Y end - attribute \src "ls180.v:6303.40-6303.147" - cell $and $and$ls180.v:6303$2044 + attribute \src "ls180.v:6299.40-6299.147" + cell $and $and$ls180.v:6299$2043 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6303$2042_Y - connect \B $eq$ls180.v:6303$2043_Y - connect \Y $and$ls180.v:6303$2044_Y + connect \A $and$ls180.v:6299$2041_Y + connect \B $eq$ls180.v:6299$2042_Y + connect \Y $and$ls180.v:6299$2043_Y end - attribute \src "ls180.v:6304.41-6304.99" - cell $and $and$ls180.v:6304$2046 + attribute \src "ls180.v:6300.41-6300.99" + cell $and $and$ls180.v:6300$2045 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6304$2045_Y - connect \Y $and$ls180.v:6304$2046_Y + connect \B $not$ls180.v:6300$2044_Y + connect \Y $and$ls180.v:6300$2045_Y end - attribute \src "ls180.v:6304.40-6304.150" - cell $and $and$ls180.v:6304$2048 + attribute \src "ls180.v:6300.40-6300.150" + cell $and $and$ls180.v:6300$2047 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6304$2046_Y - connect \B $eq$ls180.v:6304$2047_Y - connect \Y $and$ls180.v:6304$2048_Y + connect \A $and$ls180.v:6300$2045_Y + connect \B $eq$ls180.v:6300$2046_Y + connect \Y $and$ls180.v:6300$2047_Y end - attribute \src "ls180.v:6306.41-6306.96" - cell $and $and$ls180.v:6306$2049 + attribute \src "ls180.v:6302.41-6302.96" + cell $and $and$ls180.v:6302$2048 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -92949,43 +92945,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6306$2049_Y + connect \Y $and$ls180.v:6302$2048_Y end - attribute \src "ls180.v:6306.40-6306.147" - cell $and $and$ls180.v:6306$2051 + attribute \src "ls180.v:6302.40-6302.147" + cell $and $and$ls180.v:6302$2050 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6306$2049_Y - connect \B $eq$ls180.v:6306$2050_Y - connect \Y $and$ls180.v:6306$2051_Y + connect \A $and$ls180.v:6302$2048_Y + connect \B $eq$ls180.v:6302$2049_Y + connect \Y $and$ls180.v:6302$2050_Y end - attribute \src "ls180.v:6307.41-6307.99" - cell $and $and$ls180.v:6307$2053 + attribute \src "ls180.v:6303.41-6303.99" + cell $and $and$ls180.v:6303$2052 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6307$2052_Y - connect \Y $and$ls180.v:6307$2053_Y + connect \B $not$ls180.v:6303$2051_Y + connect \Y $and$ls180.v:6303$2052_Y end - attribute \src "ls180.v:6307.40-6307.150" - cell $and $and$ls180.v:6307$2055 + attribute \src "ls180.v:6303.40-6303.150" + cell $and $and$ls180.v:6303$2054 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6307$2053_Y - connect \B $eq$ls180.v:6307$2054_Y - connect \Y $and$ls180.v:6307$2055_Y + connect \A $and$ls180.v:6303$2052_Y + connect \B $eq$ls180.v:6303$2053_Y + connect \Y $and$ls180.v:6303$2054_Y end - attribute \src "ls180.v:6309.41-6309.96" - cell $and $and$ls180.v:6309$2056 + attribute \src "ls180.v:6305.41-6305.96" + cell $and $and$ls180.v:6305$2055 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -92993,43 +92989,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6309$2056_Y + connect \Y $and$ls180.v:6305$2055_Y end - attribute \src "ls180.v:6309.40-6309.147" - cell $and $and$ls180.v:6309$2058 + attribute \src "ls180.v:6305.40-6305.147" + cell $and $and$ls180.v:6305$2057 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6309$2056_Y - connect \B $eq$ls180.v:6309$2057_Y - connect \Y $and$ls180.v:6309$2058_Y + connect \A $and$ls180.v:6305$2055_Y + connect \B $eq$ls180.v:6305$2056_Y + connect \Y $and$ls180.v:6305$2057_Y end - attribute \src "ls180.v:6310.41-6310.99" - cell $and $and$ls180.v:6310$2060 + attribute \src "ls180.v:6306.41-6306.99" + cell $and $and$ls180.v:6306$2059 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6310$2059_Y - connect \Y $and$ls180.v:6310$2060_Y + connect \B $not$ls180.v:6306$2058_Y + connect \Y $and$ls180.v:6306$2059_Y end - attribute \src "ls180.v:6310.40-6310.150" - cell $and $and$ls180.v:6310$2062 + attribute \src "ls180.v:6306.40-6306.150" + cell $and $and$ls180.v:6306$2061 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6310$2060_Y - connect \B $eq$ls180.v:6310$2061_Y - connect \Y $and$ls180.v:6310$2062_Y + connect \A $and$ls180.v:6306$2059_Y + connect \B $eq$ls180.v:6306$2060_Y + connect \Y $and$ls180.v:6306$2061_Y end - attribute \src "ls180.v:6312.37-6312.92" - cell $and $and$ls180.v:6312$2063 + attribute \src "ls180.v:6308.37-6308.92" + cell $and $and$ls180.v:6308$2062 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -93037,43 +93033,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6312$2063_Y + connect \Y $and$ls180.v:6308$2062_Y end - attribute \src "ls180.v:6312.36-6312.143" - cell $and $and$ls180.v:6312$2065 + attribute \src "ls180.v:6308.36-6308.143" + cell $and $and$ls180.v:6308$2064 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6312$2063_Y - connect \B $eq$ls180.v:6312$2064_Y - connect \Y $and$ls180.v:6312$2065_Y + connect \A $and$ls180.v:6308$2062_Y + connect \B $eq$ls180.v:6308$2063_Y + connect \Y $and$ls180.v:6308$2064_Y end - attribute \src "ls180.v:6313.37-6313.95" - cell $and $and$ls180.v:6313$2067 + attribute \src "ls180.v:6309.37-6309.95" + cell $and $and$ls180.v:6309$2066 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6313$2066_Y - connect \Y $and$ls180.v:6313$2067_Y + connect \B $not$ls180.v:6309$2065_Y + connect \Y $and$ls180.v:6309$2066_Y end - attribute \src "ls180.v:6313.36-6313.146" - cell $and $and$ls180.v:6313$2069 + attribute \src "ls180.v:6309.36-6309.146" + cell $and $and$ls180.v:6309$2068 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6313$2067_Y - connect \B $eq$ls180.v:6313$2068_Y - connect \Y $and$ls180.v:6313$2069_Y + connect \A $and$ls180.v:6309$2066_Y + connect \B $eq$ls180.v:6309$2067_Y + connect \Y $and$ls180.v:6309$2068_Y end - attribute \src "ls180.v:6315.47-6315.102" - cell $and $and$ls180.v:6315$2070 + attribute \src "ls180.v:6311.47-6311.102" + cell $and $and$ls180.v:6311$2069 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -93081,43 +93077,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6315$2070_Y + connect \Y $and$ls180.v:6311$2069_Y end - attribute \src "ls180.v:6315.46-6315.153" - cell $and $and$ls180.v:6315$2072 + attribute \src "ls180.v:6311.46-6311.153" + cell $and $and$ls180.v:6311$2071 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6315$2070_Y - connect \B $eq$ls180.v:6315$2071_Y - connect \Y $and$ls180.v:6315$2072_Y + connect \A $and$ls180.v:6311$2069_Y + connect \B $eq$ls180.v:6311$2070_Y + connect \Y $and$ls180.v:6311$2071_Y end - attribute \src "ls180.v:6316.47-6316.105" - cell $and $and$ls180.v:6316$2074 + attribute \src "ls180.v:6312.47-6312.105" + cell $and $and$ls180.v:6312$2073 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6316$2073_Y - connect \Y $and$ls180.v:6316$2074_Y + connect \B $not$ls180.v:6312$2072_Y + connect \Y $and$ls180.v:6312$2073_Y end - attribute \src "ls180.v:6316.46-6316.156" - cell $and $and$ls180.v:6316$2076 + attribute \src "ls180.v:6312.46-6312.156" + cell $and $and$ls180.v:6312$2075 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6316$2074_Y - connect \B $eq$ls180.v:6316$2075_Y - connect \Y $and$ls180.v:6316$2076_Y + connect \A $and$ls180.v:6312$2073_Y + connect \B $eq$ls180.v:6312$2074_Y + connect \Y $and$ls180.v:6312$2075_Y end - attribute \src "ls180.v:6318.40-6318.95" - cell $and $and$ls180.v:6318$2077 + attribute \src "ls180.v:6314.40-6314.95" + cell $and $and$ls180.v:6314$2076 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -93125,43 +93121,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6318$2077_Y + connect \Y $and$ls180.v:6314$2076_Y end - attribute \src "ls180.v:6318.39-6318.147" - cell $and $and$ls180.v:6318$2079 + attribute \src "ls180.v:6314.39-6314.147" + cell $and $and$ls180.v:6314$2078 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6318$2077_Y - connect \B $eq$ls180.v:6318$2078_Y - connect \Y $and$ls180.v:6318$2079_Y + connect \A $and$ls180.v:6314$2076_Y + connect \B $eq$ls180.v:6314$2077_Y + connect \Y $and$ls180.v:6314$2078_Y end - attribute \src "ls180.v:6319.40-6319.98" - cell $and $and$ls180.v:6319$2081 + attribute \src "ls180.v:6315.40-6315.98" + cell $and $and$ls180.v:6315$2080 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6319$2080_Y - connect \Y $and$ls180.v:6319$2081_Y + connect \B $not$ls180.v:6315$2079_Y + connect \Y $and$ls180.v:6315$2080_Y end - attribute \src "ls180.v:6319.39-6319.150" - cell $and $and$ls180.v:6319$2083 + attribute \src "ls180.v:6315.39-6315.150" + cell $and $and$ls180.v:6315$2082 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6319$2081_Y - connect \B $eq$ls180.v:6319$2082_Y - connect \Y $and$ls180.v:6319$2083_Y + connect \A $and$ls180.v:6315$2080_Y + connect \B $eq$ls180.v:6315$2081_Y + connect \Y $and$ls180.v:6315$2082_Y end - attribute \src "ls180.v:6321.40-6321.95" - cell $and $and$ls180.v:6321$2084 + attribute \src "ls180.v:6317.40-6317.95" + cell $and $and$ls180.v:6317$2083 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -93169,43 +93165,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6321$2084_Y + connect \Y $and$ls180.v:6317$2083_Y end - attribute \src "ls180.v:6321.39-6321.147" - cell $and $and$ls180.v:6321$2086 + attribute \src "ls180.v:6317.39-6317.147" + cell $and $and$ls180.v:6317$2085 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6321$2084_Y - connect \B $eq$ls180.v:6321$2085_Y - connect \Y $and$ls180.v:6321$2086_Y + connect \A $and$ls180.v:6317$2083_Y + connect \B $eq$ls180.v:6317$2084_Y + connect \Y $and$ls180.v:6317$2085_Y end - attribute \src "ls180.v:6322.40-6322.98" - cell $and $and$ls180.v:6322$2088 + attribute \src "ls180.v:6318.40-6318.98" + cell $and $and$ls180.v:6318$2087 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6322$2087_Y - connect \Y $and$ls180.v:6322$2088_Y + connect \B $not$ls180.v:6318$2086_Y + connect \Y $and$ls180.v:6318$2087_Y end - attribute \src "ls180.v:6322.39-6322.150" - cell $and $and$ls180.v:6322$2090 + attribute \src "ls180.v:6318.39-6318.150" + cell $and $and$ls180.v:6318$2089 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6322$2088_Y - connect \B $eq$ls180.v:6322$2089_Y - connect \Y $and$ls180.v:6322$2090_Y + connect \A $and$ls180.v:6318$2087_Y + connect \B $eq$ls180.v:6318$2088_Y + connect \Y $and$ls180.v:6318$2089_Y end - attribute \src "ls180.v:6324.40-6324.95" - cell $and $and$ls180.v:6324$2091 + attribute \src "ls180.v:6320.40-6320.95" + cell $and $and$ls180.v:6320$2090 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -93213,43 +93209,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6324$2091_Y + connect \Y $and$ls180.v:6320$2090_Y end - attribute \src "ls180.v:6324.39-6324.147" - cell $and $and$ls180.v:6324$2093 + attribute \src "ls180.v:6320.39-6320.147" + cell $and $and$ls180.v:6320$2092 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6324$2091_Y - connect \B $eq$ls180.v:6324$2092_Y - connect \Y $and$ls180.v:6324$2093_Y + connect \A $and$ls180.v:6320$2090_Y + connect \B $eq$ls180.v:6320$2091_Y + connect \Y $and$ls180.v:6320$2092_Y end - attribute \src "ls180.v:6325.40-6325.98" - cell $and $and$ls180.v:6325$2095 + attribute \src "ls180.v:6321.40-6321.98" + cell $and $and$ls180.v:6321$2094 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6325$2094_Y - connect \Y $and$ls180.v:6325$2095_Y + connect \B $not$ls180.v:6321$2093_Y + connect \Y $and$ls180.v:6321$2094_Y end - attribute \src "ls180.v:6325.39-6325.150" - cell $and $and$ls180.v:6325$2097 + attribute \src "ls180.v:6321.39-6321.150" + cell $and $and$ls180.v:6321$2096 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6325$2095_Y - connect \B $eq$ls180.v:6325$2096_Y - connect \Y $and$ls180.v:6325$2097_Y + connect \A $and$ls180.v:6321$2094_Y + connect \B $eq$ls180.v:6321$2095_Y + connect \Y $and$ls180.v:6321$2096_Y end - attribute \src "ls180.v:6327.40-6327.95" - cell $and $and$ls180.v:6327$2098 + attribute \src "ls180.v:6323.40-6323.95" + cell $and $and$ls180.v:6323$2097 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -93257,43 +93253,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6327$2098_Y + connect \Y $and$ls180.v:6323$2097_Y end - attribute \src "ls180.v:6327.39-6327.147" - cell $and $and$ls180.v:6327$2100 + attribute \src "ls180.v:6323.39-6323.147" + cell $and $and$ls180.v:6323$2099 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6327$2098_Y - connect \B $eq$ls180.v:6327$2099_Y - connect \Y $and$ls180.v:6327$2100_Y + connect \A $and$ls180.v:6323$2097_Y + connect \B $eq$ls180.v:6323$2098_Y + connect \Y $and$ls180.v:6323$2099_Y end - attribute \src "ls180.v:6328.40-6328.98" - cell $and $and$ls180.v:6328$2102 + attribute \src "ls180.v:6324.40-6324.98" + cell $and $and$ls180.v:6324$2101 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6328$2101_Y - connect \Y $and$ls180.v:6328$2102_Y + connect \B $not$ls180.v:6324$2100_Y + connect \Y $and$ls180.v:6324$2101_Y end - attribute \src "ls180.v:6328.39-6328.150" - cell $and $and$ls180.v:6328$2104 + attribute \src "ls180.v:6324.39-6324.150" + cell $and $and$ls180.v:6324$2103 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6328$2102_Y - connect \B $eq$ls180.v:6328$2103_Y - connect \Y $and$ls180.v:6328$2104_Y + connect \A $and$ls180.v:6324$2101_Y + connect \B $eq$ls180.v:6324$2102_Y + connect \Y $and$ls180.v:6324$2103_Y end - attribute \src "ls180.v:6330.52-6330.107" - cell $and $and$ls180.v:6330$2105 + attribute \src "ls180.v:6326.52-6326.107" + cell $and $and$ls180.v:6326$2104 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -93301,43 +93297,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6330$2105_Y + connect \Y $and$ls180.v:6326$2104_Y end - attribute \src "ls180.v:6330.51-6330.159" - cell $and $and$ls180.v:6330$2107 + attribute \src "ls180.v:6326.51-6326.159" + cell $and $and$ls180.v:6326$2106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6330$2105_Y - connect \B $eq$ls180.v:6330$2106_Y - connect \Y $and$ls180.v:6330$2107_Y + connect \A $and$ls180.v:6326$2104_Y + connect \B $eq$ls180.v:6326$2105_Y + connect \Y $and$ls180.v:6326$2106_Y end - attribute \src "ls180.v:6331.52-6331.110" - cell $and $and$ls180.v:6331$2109 + attribute \src "ls180.v:6327.52-6327.110" + cell $and $and$ls180.v:6327$2108 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6331$2108_Y - connect \Y $and$ls180.v:6331$2109_Y + connect \B $not$ls180.v:6327$2107_Y + connect \Y $and$ls180.v:6327$2108_Y end - attribute \src "ls180.v:6331.51-6331.162" - cell $and $and$ls180.v:6331$2111 + attribute \src "ls180.v:6327.51-6327.162" + cell $and $and$ls180.v:6327$2110 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6331$2109_Y - connect \B $eq$ls180.v:6331$2110_Y - connect \Y $and$ls180.v:6331$2111_Y + connect \A $and$ls180.v:6327$2108_Y + connect \B $eq$ls180.v:6327$2109_Y + connect \Y $and$ls180.v:6327$2110_Y end - attribute \src "ls180.v:6333.53-6333.108" - cell $and $and$ls180.v:6333$2112 + attribute \src "ls180.v:6329.53-6329.108" + cell $and $and$ls180.v:6329$2111 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -93345,43 +93341,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6333$2112_Y + connect \Y $and$ls180.v:6329$2111_Y end - attribute \src "ls180.v:6333.52-6333.160" - cell $and $and$ls180.v:6333$2114 + attribute \src "ls180.v:6329.52-6329.160" + cell $and $and$ls180.v:6329$2113 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6333$2112_Y - connect \B $eq$ls180.v:6333$2113_Y - connect \Y $and$ls180.v:6333$2114_Y + connect \A $and$ls180.v:6329$2111_Y + connect \B $eq$ls180.v:6329$2112_Y + connect \Y $and$ls180.v:6329$2113_Y end - attribute \src "ls180.v:6334.53-6334.111" - cell $and $and$ls180.v:6334$2116 + attribute \src "ls180.v:6330.53-6330.111" + cell $and $and$ls180.v:6330$2115 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6334$2115_Y - connect \Y $and$ls180.v:6334$2116_Y + connect \B $not$ls180.v:6330$2114_Y + connect \Y $and$ls180.v:6330$2115_Y end - attribute \src "ls180.v:6334.52-6334.163" - cell $and $and$ls180.v:6334$2118 + attribute \src "ls180.v:6330.52-6330.163" + cell $and $and$ls180.v:6330$2117 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6334$2116_Y - connect \B $eq$ls180.v:6334$2117_Y - connect \Y $and$ls180.v:6334$2118_Y + connect \A $and$ls180.v:6330$2115_Y + connect \B $eq$ls180.v:6330$2116_Y + connect \Y $and$ls180.v:6330$2117_Y end - attribute \src "ls180.v:6336.44-6336.99" - cell $and $and$ls180.v:6336$2119 + attribute \src "ls180.v:6332.44-6332.99" + cell $and $and$ls180.v:6332$2118 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -93389,43 +93385,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6336$2119_Y + connect \Y $and$ls180.v:6332$2118_Y end - attribute \src "ls180.v:6336.43-6336.151" - cell $and $and$ls180.v:6336$2121 + attribute \src "ls180.v:6332.43-6332.151" + cell $and $and$ls180.v:6332$2120 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6336$2119_Y - connect \B $eq$ls180.v:6336$2120_Y - connect \Y $and$ls180.v:6336$2121_Y + connect \A $and$ls180.v:6332$2118_Y + connect \B $eq$ls180.v:6332$2119_Y + connect \Y $and$ls180.v:6332$2120_Y end - attribute \src "ls180.v:6337.44-6337.102" - cell $and $and$ls180.v:6337$2123 + attribute \src "ls180.v:6333.44-6333.102" + cell $and $and$ls180.v:6333$2122 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6337$2122_Y - connect \Y $and$ls180.v:6337$2123_Y + connect \B $not$ls180.v:6333$2121_Y + connect \Y $and$ls180.v:6333$2122_Y end - attribute \src "ls180.v:6337.43-6337.154" - cell $and $and$ls180.v:6337$2125 + attribute \src "ls180.v:6333.43-6333.154" + cell $and $and$ls180.v:6333$2124 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6337$2123_Y - connect \B $eq$ls180.v:6337$2124_Y - connect \Y $and$ls180.v:6337$2125_Y + connect \A $and$ls180.v:6333$2122_Y + connect \B $eq$ls180.v:6333$2123_Y + connect \Y $and$ls180.v:6333$2124_Y end - attribute \src "ls180.v:6356.30-6356.85" - cell $and $and$ls180.v:6356$2127 + attribute \src "ls180.v:6352.30-6352.85" + cell $and $and$ls180.v:6352$2126 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -93433,43 +93429,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6356$2127_Y + connect \Y $and$ls180.v:6352$2126_Y end - attribute \src "ls180.v:6356.29-6356.136" - cell $and $and$ls180.v:6356$2129 + attribute \src "ls180.v:6352.29-6352.136" + cell $and $and$ls180.v:6352$2128 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6356$2127_Y - connect \B $eq$ls180.v:6356$2128_Y - connect \Y $and$ls180.v:6356$2129_Y + connect \A $and$ls180.v:6352$2126_Y + connect \B $eq$ls180.v:6352$2127_Y + connect \Y $and$ls180.v:6352$2128_Y end - attribute \src "ls180.v:6357.30-6357.88" - cell $and $and$ls180.v:6357$2131 + attribute \src "ls180.v:6353.30-6353.88" + cell $and $and$ls180.v:6353$2130 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6357$2130_Y - connect \Y $and$ls180.v:6357$2131_Y + connect \B $not$ls180.v:6353$2129_Y + connect \Y $and$ls180.v:6353$2130_Y end - attribute \src "ls180.v:6357.29-6357.139" - cell $and $and$ls180.v:6357$2133 + attribute \src "ls180.v:6353.29-6353.139" + cell $and $and$ls180.v:6353$2132 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6357$2131_Y - connect \B $eq$ls180.v:6357$2132_Y - connect \Y $and$ls180.v:6357$2133_Y + connect \A $and$ls180.v:6353$2130_Y + connect \B $eq$ls180.v:6353$2131_Y + connect \Y $and$ls180.v:6353$2132_Y end - attribute \src "ls180.v:6359.40-6359.95" - cell $and $and$ls180.v:6359$2134 + attribute \src "ls180.v:6355.40-6355.95" + cell $and $and$ls180.v:6355$2133 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -93477,43 +93473,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6359$2134_Y + connect \Y $and$ls180.v:6355$2133_Y end - attribute \src "ls180.v:6359.39-6359.146" - cell $and $and$ls180.v:6359$2136 + attribute \src "ls180.v:6355.39-6355.146" + cell $and $and$ls180.v:6355$2135 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6359$2134_Y - connect \B $eq$ls180.v:6359$2135_Y - connect \Y $and$ls180.v:6359$2136_Y + connect \A $and$ls180.v:6355$2133_Y + connect \B $eq$ls180.v:6355$2134_Y + connect \Y $and$ls180.v:6355$2135_Y end - attribute \src "ls180.v:6360.40-6360.98" - cell $and $and$ls180.v:6360$2138 + attribute \src "ls180.v:6356.40-6356.98" + cell $and $and$ls180.v:6356$2137 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6360$2137_Y - connect \Y $and$ls180.v:6360$2138_Y + connect \B $not$ls180.v:6356$2136_Y + connect \Y $and$ls180.v:6356$2137_Y end - attribute \src "ls180.v:6360.39-6360.149" - cell $and $and$ls180.v:6360$2140 + attribute \src "ls180.v:6356.39-6356.149" + cell $and $and$ls180.v:6356$2139 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6360$2138_Y - connect \B $eq$ls180.v:6360$2139_Y - connect \Y $and$ls180.v:6360$2140_Y + connect \A $and$ls180.v:6356$2137_Y + connect \B $eq$ls180.v:6356$2138_Y + connect \Y $and$ls180.v:6356$2139_Y end - attribute \src "ls180.v:6362.41-6362.96" - cell $and $and$ls180.v:6362$2141 + attribute \src "ls180.v:6358.41-6358.96" + cell $and $and$ls180.v:6358$2140 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -93521,43 +93517,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6362$2141_Y + connect \Y $and$ls180.v:6358$2140_Y end - attribute \src "ls180.v:6362.40-6362.147" - cell $and $and$ls180.v:6362$2143 + attribute \src "ls180.v:6358.40-6358.147" + cell $and $and$ls180.v:6358$2142 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6362$2141_Y - connect \B $eq$ls180.v:6362$2142_Y - connect \Y $and$ls180.v:6362$2143_Y + connect \A $and$ls180.v:6358$2140_Y + connect \B $eq$ls180.v:6358$2141_Y + connect \Y $and$ls180.v:6358$2142_Y end - attribute \src "ls180.v:6363.41-6363.99" - cell $and $and$ls180.v:6363$2145 + attribute \src "ls180.v:6359.41-6359.99" + cell $and $and$ls180.v:6359$2144 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6363$2144_Y - connect \Y $and$ls180.v:6363$2145_Y + connect \B $not$ls180.v:6359$2143_Y + connect \Y $and$ls180.v:6359$2144_Y end - attribute \src "ls180.v:6363.40-6363.150" - cell $and $and$ls180.v:6363$2147 + attribute \src "ls180.v:6359.40-6359.150" + cell $and $and$ls180.v:6359$2146 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6363$2145_Y - connect \B $eq$ls180.v:6363$2146_Y - connect \Y $and$ls180.v:6363$2147_Y + connect \A $and$ls180.v:6359$2144_Y + connect \B $eq$ls180.v:6359$2145_Y + connect \Y $and$ls180.v:6359$2146_Y end - attribute \src "ls180.v:6365.45-6365.100" - cell $and $and$ls180.v:6365$2148 + attribute \src "ls180.v:6361.45-6361.100" + cell $and $and$ls180.v:6361$2147 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -93565,43 +93561,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6365$2148_Y + connect \Y $and$ls180.v:6361$2147_Y end - attribute \src "ls180.v:6365.44-6365.151" - cell $and $and$ls180.v:6365$2150 + attribute \src "ls180.v:6361.44-6361.151" + cell $and $and$ls180.v:6361$2149 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6365$2148_Y - connect \B $eq$ls180.v:6365$2149_Y - connect \Y $and$ls180.v:6365$2150_Y + connect \A $and$ls180.v:6361$2147_Y + connect \B $eq$ls180.v:6361$2148_Y + connect \Y $and$ls180.v:6361$2149_Y end - attribute \src "ls180.v:6366.45-6366.103" - cell $and $and$ls180.v:6366$2152 + attribute \src "ls180.v:6362.45-6362.103" + cell $and $and$ls180.v:6362$2151 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6366$2151_Y - connect \Y $and$ls180.v:6366$2152_Y + connect \B $not$ls180.v:6362$2150_Y + connect \Y $and$ls180.v:6362$2151_Y end - attribute \src "ls180.v:6366.44-6366.154" - cell $and $and$ls180.v:6366$2154 + attribute \src "ls180.v:6362.44-6362.154" + cell $and $and$ls180.v:6362$2153 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6366$2152_Y - connect \B $eq$ls180.v:6366$2153_Y - connect \Y $and$ls180.v:6366$2154_Y + connect \A $and$ls180.v:6362$2151_Y + connect \B $eq$ls180.v:6362$2152_Y + connect \Y $and$ls180.v:6362$2153_Y end - attribute \src "ls180.v:6368.46-6368.101" - cell $and $and$ls180.v:6368$2155 + attribute \src "ls180.v:6364.46-6364.101" + cell $and $and$ls180.v:6364$2154 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -93609,43 +93605,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6368$2155_Y + connect \Y $and$ls180.v:6364$2154_Y end - attribute \src "ls180.v:6368.45-6368.152" - cell $and $and$ls180.v:6368$2157 + attribute \src "ls180.v:6364.45-6364.152" + cell $and $and$ls180.v:6364$2156 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6368$2155_Y - connect \B $eq$ls180.v:6368$2156_Y - connect \Y $and$ls180.v:6368$2157_Y + connect \A $and$ls180.v:6364$2154_Y + connect \B $eq$ls180.v:6364$2155_Y + connect \Y $and$ls180.v:6364$2156_Y end - attribute \src "ls180.v:6369.46-6369.104" - cell $and $and$ls180.v:6369$2159 + attribute \src "ls180.v:6365.46-6365.104" + cell $and $and$ls180.v:6365$2158 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6369$2158_Y - connect \Y $and$ls180.v:6369$2159_Y + connect \B $not$ls180.v:6365$2157_Y + connect \Y $and$ls180.v:6365$2158_Y end - attribute \src "ls180.v:6369.45-6369.155" - cell $and $and$ls180.v:6369$2161 + attribute \src "ls180.v:6365.45-6365.155" + cell $and $and$ls180.v:6365$2160 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6369$2159_Y - connect \B $eq$ls180.v:6369$2160_Y - connect \Y $and$ls180.v:6369$2161_Y + connect \A $and$ls180.v:6365$2158_Y + connect \B $eq$ls180.v:6365$2159_Y + connect \Y $and$ls180.v:6365$2160_Y end - attribute \src "ls180.v:6371.44-6371.99" - cell $and $and$ls180.v:6371$2162 + attribute \src "ls180.v:6367.44-6367.99" + cell $and $and$ls180.v:6367$2161 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -93653,43 +93649,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6371$2162_Y + connect \Y $and$ls180.v:6367$2161_Y end - attribute \src "ls180.v:6371.43-6371.150" - cell $and $and$ls180.v:6371$2164 + attribute \src "ls180.v:6367.43-6367.150" + cell $and $and$ls180.v:6367$2163 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6371$2162_Y - connect \B $eq$ls180.v:6371$2163_Y - connect \Y $and$ls180.v:6371$2164_Y + connect \A $and$ls180.v:6367$2161_Y + connect \B $eq$ls180.v:6367$2162_Y + connect \Y $and$ls180.v:6367$2163_Y end - attribute \src "ls180.v:6372.44-6372.102" - cell $and $and$ls180.v:6372$2166 + attribute \src "ls180.v:6368.44-6368.102" + cell $and $and$ls180.v:6368$2165 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6372$2165_Y - connect \Y $and$ls180.v:6372$2166_Y + connect \B $not$ls180.v:6368$2164_Y + connect \Y $and$ls180.v:6368$2165_Y end - attribute \src "ls180.v:6372.43-6372.153" - cell $and $and$ls180.v:6372$2168 + attribute \src "ls180.v:6368.43-6368.153" + cell $and $and$ls180.v:6368$2167 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6372$2166_Y - connect \B $eq$ls180.v:6372$2167_Y - connect \Y $and$ls180.v:6372$2168_Y + connect \A $and$ls180.v:6368$2165_Y + connect \B $eq$ls180.v:6368$2166_Y + connect \Y $and$ls180.v:6368$2167_Y end - attribute \src "ls180.v:6374.41-6374.96" - cell $and $and$ls180.v:6374$2169 + attribute \src "ls180.v:6370.41-6370.96" + cell $and $and$ls180.v:6370$2168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -93697,43 +93693,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6374$2169_Y + connect \Y $and$ls180.v:6370$2168_Y end - attribute \src "ls180.v:6374.40-6374.147" - cell $and $and$ls180.v:6374$2171 + attribute \src "ls180.v:6370.40-6370.147" + cell $and $and$ls180.v:6370$2170 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6374$2169_Y - connect \B $eq$ls180.v:6374$2170_Y - connect \Y $and$ls180.v:6374$2171_Y + connect \A $and$ls180.v:6370$2168_Y + connect \B $eq$ls180.v:6370$2169_Y + connect \Y $and$ls180.v:6370$2170_Y end - attribute \src "ls180.v:6375.41-6375.99" - cell $and $and$ls180.v:6375$2173 + attribute \src "ls180.v:6371.41-6371.99" + cell $and $and$ls180.v:6371$2172 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6375$2172_Y - connect \Y $and$ls180.v:6375$2173_Y + connect \B $not$ls180.v:6371$2171_Y + connect \Y $and$ls180.v:6371$2172_Y end - attribute \src "ls180.v:6375.40-6375.150" - cell $and $and$ls180.v:6375$2175 + attribute \src "ls180.v:6371.40-6371.150" + cell $and $and$ls180.v:6371$2174 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6375$2173_Y - connect \B $eq$ls180.v:6375$2174_Y - connect \Y $and$ls180.v:6375$2175_Y + connect \A $and$ls180.v:6371$2172_Y + connect \B $eq$ls180.v:6371$2173_Y + connect \Y $and$ls180.v:6371$2174_Y end - attribute \src "ls180.v:6377.40-6377.95" - cell $and $and$ls180.v:6377$2176 + attribute \src "ls180.v:6373.40-6373.95" + cell $and $and$ls180.v:6373$2175 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -93741,43 +93737,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6377$2176_Y + connect \Y $and$ls180.v:6373$2175_Y end - attribute \src "ls180.v:6377.39-6377.146" - cell $and $and$ls180.v:6377$2178 + attribute \src "ls180.v:6373.39-6373.146" + cell $and $and$ls180.v:6373$2177 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6377$2176_Y - connect \B $eq$ls180.v:6377$2177_Y - connect \Y $and$ls180.v:6377$2178_Y + connect \A $and$ls180.v:6373$2175_Y + connect \B $eq$ls180.v:6373$2176_Y + connect \Y $and$ls180.v:6373$2177_Y end - attribute \src "ls180.v:6378.40-6378.98" - cell $and $and$ls180.v:6378$2180 + attribute \src "ls180.v:6374.40-6374.98" + cell $and $and$ls180.v:6374$2179 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6378$2179_Y - connect \Y $and$ls180.v:6378$2180_Y + connect \B $not$ls180.v:6374$2178_Y + connect \Y $and$ls180.v:6374$2179_Y end - attribute \src "ls180.v:6378.39-6378.149" - cell $and $and$ls180.v:6378$2182 + attribute \src "ls180.v:6374.39-6374.149" + cell $and $and$ls180.v:6374$2181 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6378$2180_Y - connect \B $eq$ls180.v:6378$2181_Y - connect \Y $and$ls180.v:6378$2182_Y + connect \A $and$ls180.v:6374$2179_Y + connect \B $eq$ls180.v:6374$2180_Y + connect \Y $and$ls180.v:6374$2181_Y end - attribute \src "ls180.v:6390.46-6390.101" - cell $and $and$ls180.v:6390$2184 + attribute \src "ls180.v:6386.46-6386.101" + cell $and $and$ls180.v:6386$2183 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -93785,43 +93781,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6390$2184_Y + connect \Y $and$ls180.v:6386$2183_Y end - attribute \src "ls180.v:6390.45-6390.152" - cell $and $and$ls180.v:6390$2186 + attribute \src "ls180.v:6386.45-6386.152" + cell $and $and$ls180.v:6386$2185 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6390$2184_Y - connect \B $eq$ls180.v:6390$2185_Y - connect \Y $and$ls180.v:6390$2186_Y + connect \A $and$ls180.v:6386$2183_Y + connect \B $eq$ls180.v:6386$2184_Y + connect \Y $and$ls180.v:6386$2185_Y end - attribute \src "ls180.v:6391.46-6391.104" - cell $and $and$ls180.v:6391$2188 + attribute \src "ls180.v:6387.46-6387.104" + cell $and $and$ls180.v:6387$2187 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6391$2187_Y - connect \Y $and$ls180.v:6391$2188_Y + connect \B $not$ls180.v:6387$2186_Y + connect \Y $and$ls180.v:6387$2187_Y end - attribute \src "ls180.v:6391.45-6391.155" - cell $and $and$ls180.v:6391$2190 + attribute \src "ls180.v:6387.45-6387.155" + cell $and $and$ls180.v:6387$2189 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6391$2188_Y - connect \B $eq$ls180.v:6391$2189_Y - connect \Y $and$ls180.v:6391$2190_Y + connect \A $and$ls180.v:6387$2187_Y + connect \B $eq$ls180.v:6387$2188_Y + connect \Y $and$ls180.v:6387$2189_Y end - attribute \src "ls180.v:6393.46-6393.101" - cell $and $and$ls180.v:6393$2191 + attribute \src "ls180.v:6389.46-6389.101" + cell $and $and$ls180.v:6389$2190 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -93829,43 +93825,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6393$2191_Y + connect \Y $and$ls180.v:6389$2190_Y end - attribute \src "ls180.v:6393.45-6393.152" - cell $and $and$ls180.v:6393$2193 + attribute \src "ls180.v:6389.45-6389.152" + cell $and $and$ls180.v:6389$2192 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6393$2191_Y - connect \B $eq$ls180.v:6393$2192_Y - connect \Y $and$ls180.v:6393$2193_Y + connect \A $and$ls180.v:6389$2190_Y + connect \B $eq$ls180.v:6389$2191_Y + connect \Y $and$ls180.v:6389$2192_Y end - attribute \src "ls180.v:6394.46-6394.104" - cell $and $and$ls180.v:6394$2195 + attribute \src "ls180.v:6390.46-6390.104" + cell $and $and$ls180.v:6390$2194 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6394$2194_Y - connect \Y $and$ls180.v:6394$2195_Y + connect \B $not$ls180.v:6390$2193_Y + connect \Y $and$ls180.v:6390$2194_Y end - attribute \src "ls180.v:6394.45-6394.155" - cell $and $and$ls180.v:6394$2197 + attribute \src "ls180.v:6390.45-6390.155" + cell $and $and$ls180.v:6390$2196 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6394$2195_Y - connect \B $eq$ls180.v:6394$2196_Y - connect \Y $and$ls180.v:6394$2197_Y + connect \A $and$ls180.v:6390$2194_Y + connect \B $eq$ls180.v:6390$2195_Y + connect \Y $and$ls180.v:6390$2196_Y end - attribute \src "ls180.v:6396.46-6396.101" - cell $and $and$ls180.v:6396$2198 + attribute \src "ls180.v:6392.46-6392.101" + cell $and $and$ls180.v:6392$2197 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -93873,43 +93869,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6396$2198_Y + connect \Y $and$ls180.v:6392$2197_Y end - attribute \src "ls180.v:6396.45-6396.152" - cell $and $and$ls180.v:6396$2200 + attribute \src "ls180.v:6392.45-6392.152" + cell $and $and$ls180.v:6392$2199 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6396$2198_Y - connect \B $eq$ls180.v:6396$2199_Y - connect \Y $and$ls180.v:6396$2200_Y + connect \A $and$ls180.v:6392$2197_Y + connect \B $eq$ls180.v:6392$2198_Y + connect \Y $and$ls180.v:6392$2199_Y end - attribute \src "ls180.v:6397.46-6397.104" - cell $and $and$ls180.v:6397$2202 + attribute \src "ls180.v:6393.46-6393.104" + cell $and $and$ls180.v:6393$2201 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6397$2201_Y - connect \Y $and$ls180.v:6397$2202_Y + connect \B $not$ls180.v:6393$2200_Y + connect \Y $and$ls180.v:6393$2201_Y end - attribute \src "ls180.v:6397.45-6397.155" - cell $and $and$ls180.v:6397$2204 + attribute \src "ls180.v:6393.45-6393.155" + cell $and $and$ls180.v:6393$2203 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6397$2202_Y - connect \B $eq$ls180.v:6397$2203_Y - connect \Y $and$ls180.v:6397$2204_Y + connect \A $and$ls180.v:6393$2201_Y + connect \B $eq$ls180.v:6393$2202_Y + connect \Y $and$ls180.v:6393$2203_Y end - attribute \src "ls180.v:6399.46-6399.101" - cell $and $and$ls180.v:6399$2205 + attribute \src "ls180.v:6395.46-6395.101" + cell $and $and$ls180.v:6395$2204 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -93917,263 +93913,263 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6399$2205_Y + connect \Y $and$ls180.v:6395$2204_Y end - attribute \src "ls180.v:6399.45-6399.152" - cell $and $and$ls180.v:6399$2207 + attribute \src "ls180.v:6395.45-6395.152" + cell $and $and$ls180.v:6395$2206 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6399$2205_Y - connect \B $eq$ls180.v:6399$2206_Y - connect \Y $and$ls180.v:6399$2207_Y + connect \A $and$ls180.v:6395$2204_Y + connect \B $eq$ls180.v:6395$2205_Y + connect \Y $and$ls180.v:6395$2206_Y end - attribute \src "ls180.v:6400.46-6400.104" - cell $and $and$ls180.v:6400$2209 + attribute \src "ls180.v:6396.46-6396.104" + cell $and $and$ls180.v:6396$2208 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6400$2208_Y - connect \Y $and$ls180.v:6400$2209_Y + connect \B $not$ls180.v:6396$2207_Y + connect \Y $and$ls180.v:6396$2208_Y end - attribute \src "ls180.v:6400.45-6400.155" - cell $and $and$ls180.v:6400$2211 + attribute \src "ls180.v:6396.45-6396.155" + cell $and $and$ls180.v:6396$2210 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6400$2209_Y - connect \B $eq$ls180.v:6400$2210_Y - connect \Y $and$ls180.v:6400$2211_Y + connect \A $and$ls180.v:6396$2208_Y + connect \B $eq$ls180.v:6396$2209_Y + connect \Y $and$ls180.v:6396$2210_Y end - attribute \src "ls180.v:6778.109-6778.178" - cell $and $and$ls180.v:6778$2248 + attribute \src "ls180.v:6774.109-6774.178" + cell $and $and$ls180.v:6774$2247 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:6778$2247_Y - connect \Y $and$ls180.v:6778$2248_Y + connect \B $eq$ls180.v:6774$2246_Y + connect \Y $and$ls180.v:6774$2247_Y end - attribute \src "ls180.v:6778.184-6778.253" - cell $and $and$ls180.v:6778$2251 + attribute \src "ls180.v:6774.184-6774.253" + cell $and $and$ls180.v:6774$2250 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:6778$2250_Y - connect \Y $and$ls180.v:6778$2251_Y + connect \B $eq$ls180.v:6774$2249_Y + connect \Y $and$ls180.v:6774$2250_Y end - attribute \src "ls180.v:6778.259-6778.328" - cell $and $and$ls180.v:6778$2254 + attribute \src "ls180.v:6774.259-6774.328" + cell $and $and$ls180.v:6774$2253 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:6778$2253_Y - connect \Y $and$ls180.v:6778$2254_Y + connect \B $eq$ls180.v:6774$2252_Y + connect \Y $and$ls180.v:6774$2253_Y end - attribute \src "ls180.v:6778.40-6778.331" - cell $and $and$ls180.v:6778$2257 + attribute \src "ls180.v:6774.40-6774.331" + cell $and $and$ls180.v:6774$2256 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:6778$2246_Y - connect \B $not$ls180.v:6778$2256_Y - connect \Y $and$ls180.v:6778$2257_Y + connect \A $eq$ls180.v:6774$2245_Y + connect \B $not$ls180.v:6774$2255_Y + connect \Y $and$ls180.v:6774$2256_Y end - attribute \src "ls180.v:6778.39-6778.354" - cell $and $and$ls180.v:6778$2258 + attribute \src "ls180.v:6774.39-6774.354" + cell $and $and$ls180.v:6774$2257 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6778$2257_Y + connect \A $and$ls180.v:6774$2256_Y connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:6778$2258_Y + connect \Y $and$ls180.v:6774$2257_Y end - attribute \src "ls180.v:6802.109-6802.178" - cell $and $and$ls180.v:6802$2264 + attribute \src "ls180.v:6798.109-6798.178" + cell $and $and$ls180.v:6798$2263 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:6802$2263_Y - connect \Y $and$ls180.v:6802$2264_Y + connect \B $eq$ls180.v:6798$2262_Y + connect \Y $and$ls180.v:6798$2263_Y end - attribute \src "ls180.v:6802.184-6802.253" - cell $and $and$ls180.v:6802$2267 + attribute \src "ls180.v:6798.184-6798.253" + cell $and $and$ls180.v:6798$2266 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:6802$2266_Y - connect \Y $and$ls180.v:6802$2267_Y + connect \B $eq$ls180.v:6798$2265_Y + connect \Y $and$ls180.v:6798$2266_Y end - attribute \src "ls180.v:6802.259-6802.328" - cell $and $and$ls180.v:6802$2270 + attribute \src "ls180.v:6798.259-6798.328" + cell $and $and$ls180.v:6798$2269 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:6802$2269_Y - connect \Y $and$ls180.v:6802$2270_Y + connect \B $eq$ls180.v:6798$2268_Y + connect \Y $and$ls180.v:6798$2269_Y end - attribute \src "ls180.v:6802.40-6802.331" - cell $and $and$ls180.v:6802$2273 + attribute \src "ls180.v:6798.40-6798.331" + cell $and $and$ls180.v:6798$2272 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:6802$2262_Y - connect \B $not$ls180.v:6802$2272_Y - connect \Y $and$ls180.v:6802$2273_Y + connect \A $eq$ls180.v:6798$2261_Y + connect \B $not$ls180.v:6798$2271_Y + connect \Y $and$ls180.v:6798$2272_Y end - attribute \src "ls180.v:6802.39-6802.354" - cell $and $and$ls180.v:6802$2274 + attribute \src "ls180.v:6798.39-6798.354" + cell $and $and$ls180.v:6798$2273 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6802$2273_Y + connect \A $and$ls180.v:6798$2272_Y connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:6802$2274_Y + connect \Y $and$ls180.v:6798$2273_Y end - attribute \src "ls180.v:6826.109-6826.178" - cell $and $and$ls180.v:6826$2280 + attribute \src "ls180.v:6822.109-6822.178" + cell $and $and$ls180.v:6822$2279 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:6826$2279_Y - connect \Y $and$ls180.v:6826$2280_Y + connect \B $eq$ls180.v:6822$2278_Y + connect \Y $and$ls180.v:6822$2279_Y end - attribute \src "ls180.v:6826.184-6826.253" - cell $and $and$ls180.v:6826$2283 + attribute \src "ls180.v:6822.184-6822.253" + cell $and $and$ls180.v:6822$2282 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:6826$2282_Y - connect \Y $and$ls180.v:6826$2283_Y + connect \B $eq$ls180.v:6822$2281_Y + connect \Y $and$ls180.v:6822$2282_Y end - attribute \src "ls180.v:6826.259-6826.328" - cell $and $and$ls180.v:6826$2286 + attribute \src "ls180.v:6822.259-6822.328" + cell $and $and$ls180.v:6822$2285 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:6826$2285_Y - connect \Y $and$ls180.v:6826$2286_Y + connect \B $eq$ls180.v:6822$2284_Y + connect \Y $and$ls180.v:6822$2285_Y end - attribute \src "ls180.v:6826.40-6826.331" - cell $and $and$ls180.v:6826$2289 + attribute \src "ls180.v:6822.40-6822.331" + cell $and $and$ls180.v:6822$2288 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:6826$2278_Y - connect \B $not$ls180.v:6826$2288_Y - connect \Y $and$ls180.v:6826$2289_Y + connect \A $eq$ls180.v:6822$2277_Y + connect \B $not$ls180.v:6822$2287_Y + connect \Y $and$ls180.v:6822$2288_Y end - attribute \src "ls180.v:6826.39-6826.354" - cell $and $and$ls180.v:6826$2290 + attribute \src "ls180.v:6822.39-6822.354" + cell $and $and$ls180.v:6822$2289 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6826$2289_Y + connect \A $and$ls180.v:6822$2288_Y connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:6826$2290_Y + connect \Y $and$ls180.v:6822$2289_Y end - attribute \src "ls180.v:6850.109-6850.178" - cell $and $and$ls180.v:6850$2296 + attribute \src "ls180.v:6846.109-6846.178" + cell $and $and$ls180.v:6846$2295 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:6850$2295_Y - connect \Y $and$ls180.v:6850$2296_Y + connect \B $eq$ls180.v:6846$2294_Y + connect \Y $and$ls180.v:6846$2295_Y end - attribute \src "ls180.v:6850.184-6850.253" - cell $and $and$ls180.v:6850$2299 + attribute \src "ls180.v:6846.184-6846.253" + cell $and $and$ls180.v:6846$2298 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:6850$2298_Y - connect \Y $and$ls180.v:6850$2299_Y + connect \B $eq$ls180.v:6846$2297_Y + connect \Y $and$ls180.v:6846$2298_Y end - attribute \src "ls180.v:6850.259-6850.328" - cell $and $and$ls180.v:6850$2302 + attribute \src "ls180.v:6846.259-6846.328" + cell $and $and$ls180.v:6846$2301 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:6850$2301_Y - connect \Y $and$ls180.v:6850$2302_Y + connect \B $eq$ls180.v:6846$2300_Y + connect \Y $and$ls180.v:6846$2301_Y end - attribute \src "ls180.v:6850.40-6850.331" - cell $and $and$ls180.v:6850$2305 + attribute \src "ls180.v:6846.40-6846.331" + cell $and $and$ls180.v:6846$2304 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:6850$2294_Y - connect \B $not$ls180.v:6850$2304_Y - connect \Y $and$ls180.v:6850$2305_Y + connect \A $eq$ls180.v:6846$2293_Y + connect \B $not$ls180.v:6846$2303_Y + connect \Y $and$ls180.v:6846$2304_Y end - attribute \src "ls180.v:6850.39-6850.354" - cell $and $and$ls180.v:6850$2306 + attribute \src "ls180.v:6846.39-6846.354" + cell $and $and$ls180.v:6846$2305 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6850$2305_Y + connect \A $and$ls180.v:6846$2304_Y connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:6850$2306_Y + connect \Y $and$ls180.v:6846$2305_Y end - attribute \src "ls180.v:7055.39-7055.104" - cell $and $and$ls180.v:7055$2318 + attribute \src "ls180.v:7051.39-7051.104" + cell $and $and$ls180.v:7051$2317 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -94181,21 +94177,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7055$2318_Y + connect \Y $and$ls180.v:7051$2317_Y end - attribute \src "ls180.v:7055.38-7055.145" - cell $and $and$ls180.v:7055$2319 + attribute \src "ls180.v:7051.38-7051.145" + cell $and $and$ls180.v:7051$2318 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7055$2318_Y + connect \A $and$ls180.v:7051$2317_Y connect \B \main_sdram_choose_req_cmd_payload_cas - connect \Y $and$ls180.v:7055$2319_Y + connect \Y $and$ls180.v:7051$2318_Y end - attribute \src "ls180.v:7058.39-7058.104" - cell $and $and$ls180.v:7058$2320 + attribute \src "ls180.v:7054.39-7054.104" + cell $and $and$ls180.v:7054$2319 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -94203,21 +94199,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7058$2320_Y + connect \Y $and$ls180.v:7054$2319_Y end - attribute \src "ls180.v:7058.38-7058.145" - cell $and $and$ls180.v:7058$2321 + attribute \src "ls180.v:7054.38-7054.145" + cell $and $and$ls180.v:7054$2320 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7058$2320_Y + connect \A $and$ls180.v:7054$2319_Y connect \B \main_sdram_choose_req_cmd_payload_cas - connect \Y $and$ls180.v:7058$2321_Y + connect \Y $and$ls180.v:7054$2320_Y end - attribute \src "ls180.v:7061.39-7061.82" - cell $and $and$ls180.v:7061$2322 + attribute \src "ls180.v:7057.39-7057.82" + cell $and $and$ls180.v:7057$2321 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -94225,21 +94221,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_cmd_valid connect \B \main_sdram_cmd_ready - connect \Y $and$ls180.v:7061$2322_Y + connect \Y $and$ls180.v:7057$2321_Y end - attribute \src "ls180.v:7061.38-7061.112" - cell $and $and$ls180.v:7061$2323 + attribute \src "ls180.v:7057.38-7057.112" + cell $and $and$ls180.v:7057$2322 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7061$2322_Y + connect \A $and$ls180.v:7057$2321_Y connect \B \main_sdram_cmd_payload_cas - connect \Y $and$ls180.v:7061$2323_Y + connect \Y $and$ls180.v:7057$2322_Y end - attribute \src "ls180.v:7072.39-7072.104" - cell $and $and$ls180.v:7072$2325 + attribute \src "ls180.v:7068.39-7068.104" + cell $and $and$ls180.v:7068$2324 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -94247,21 +94243,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7072$2325_Y + connect \Y $and$ls180.v:7068$2324_Y end - attribute \src "ls180.v:7072.38-7072.145" - cell $and $and$ls180.v:7072$2326 + attribute \src "ls180.v:7068.38-7068.145" + cell $and $and$ls180.v:7068$2325 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7072$2325_Y + connect \A $and$ls180.v:7068$2324_Y connect \B \main_sdram_choose_req_cmd_payload_ras - connect \Y $and$ls180.v:7072$2326_Y + connect \Y $and$ls180.v:7068$2325_Y end - attribute \src "ls180.v:7075.39-7075.104" - cell $and $and$ls180.v:7075$2327 + attribute \src "ls180.v:7071.39-7071.104" + cell $and $and$ls180.v:7071$2326 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -94269,21 +94265,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7075$2327_Y + connect \Y $and$ls180.v:7071$2326_Y end - attribute \src "ls180.v:7075.38-7075.145" - cell $and $and$ls180.v:7075$2328 + attribute \src "ls180.v:7071.38-7071.145" + cell $and $and$ls180.v:7071$2327 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7075$2327_Y + connect \A $and$ls180.v:7071$2326_Y connect \B \main_sdram_choose_req_cmd_payload_ras - connect \Y $and$ls180.v:7075$2328_Y + connect \Y $and$ls180.v:7071$2327_Y end - attribute \src "ls180.v:7078.39-7078.82" - cell $and $and$ls180.v:7078$2329 + attribute \src "ls180.v:7074.39-7074.82" + cell $and $and$ls180.v:7074$2328 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -94291,21 +94287,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_cmd_valid connect \B \main_sdram_cmd_ready - connect \Y $and$ls180.v:7078$2329_Y + connect \Y $and$ls180.v:7074$2328_Y end - attribute \src "ls180.v:7078.38-7078.112" - cell $and $and$ls180.v:7078$2330 + attribute \src "ls180.v:7074.38-7074.112" + cell $and $and$ls180.v:7074$2329 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7078$2329_Y + connect \A $and$ls180.v:7074$2328_Y connect \B \main_sdram_cmd_payload_ras - connect \Y $and$ls180.v:7078$2330_Y + connect \Y $and$ls180.v:7074$2329_Y end - attribute \src "ls180.v:7089.39-7089.104" - cell $and $and$ls180.v:7089$2332 + attribute \src "ls180.v:7085.39-7085.104" + cell $and $and$ls180.v:7085$2331 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -94313,21 +94309,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7089$2332_Y + connect \Y $and$ls180.v:7085$2331_Y end - attribute \src "ls180.v:7089.38-7089.144" - cell $and $and$ls180.v:7089$2333 + attribute \src "ls180.v:7085.38-7085.144" + cell $and $and$ls180.v:7085$2332 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7089$2332_Y + connect \A $and$ls180.v:7085$2331_Y connect \B \main_sdram_choose_req_cmd_payload_we - connect \Y $and$ls180.v:7089$2333_Y + connect \Y $and$ls180.v:7085$2332_Y end - attribute \src "ls180.v:7092.39-7092.104" - cell $and $and$ls180.v:7092$2334 + attribute \src "ls180.v:7088.39-7088.104" + cell $and $and$ls180.v:7088$2333 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -94335,21 +94331,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7092$2334_Y + connect \Y $and$ls180.v:7088$2333_Y end - attribute \src "ls180.v:7092.38-7092.144" - cell $and $and$ls180.v:7092$2335 + attribute \src "ls180.v:7088.38-7088.144" + cell $and $and$ls180.v:7088$2334 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7092$2334_Y + connect \A $and$ls180.v:7088$2333_Y connect \B \main_sdram_choose_req_cmd_payload_we - connect \Y $and$ls180.v:7092$2335_Y + connect \Y $and$ls180.v:7088$2334_Y end - attribute \src "ls180.v:7095.39-7095.82" - cell $and $and$ls180.v:7095$2336 + attribute \src "ls180.v:7091.39-7091.82" + cell $and $and$ls180.v:7091$2335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -94357,21 +94353,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_cmd_valid connect \B \main_sdram_cmd_ready - connect \Y $and$ls180.v:7095$2336_Y + connect \Y $and$ls180.v:7091$2335_Y end - attribute \src "ls180.v:7095.38-7095.111" - cell $and $and$ls180.v:7095$2337 + attribute \src "ls180.v:7091.38-7091.111" + cell $and $and$ls180.v:7091$2336 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7095$2336_Y + connect \A $and$ls180.v:7091$2335_Y connect \B \main_sdram_cmd_payload_we - connect \Y $and$ls180.v:7095$2337_Y + connect \Y $and$ls180.v:7091$2336_Y end - attribute \src "ls180.v:7106.39-7106.104" - cell $and $and$ls180.v:7106$2339 + attribute \src "ls180.v:7102.39-7102.104" + cell $and $and$ls180.v:7102$2338 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -94379,21 +94375,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7106$2339_Y + connect \Y $and$ls180.v:7102$2338_Y end - attribute \src "ls180.v:7106.38-7106.149" - cell $and $and$ls180.v:7106$2340 + attribute \src "ls180.v:7102.38-7102.149" + cell $and $and$ls180.v:7102$2339 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7106$2339_Y + connect \A $and$ls180.v:7102$2338_Y connect \B \main_sdram_choose_req_cmd_payload_is_read - connect \Y $and$ls180.v:7106$2340_Y + connect \Y $and$ls180.v:7102$2339_Y end - attribute \src "ls180.v:7109.39-7109.104" - cell $and $and$ls180.v:7109$2341 + attribute \src "ls180.v:7105.39-7105.104" + cell $and $and$ls180.v:7105$2340 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -94401,21 +94397,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7109$2341_Y + connect \Y $and$ls180.v:7105$2340_Y end - attribute \src "ls180.v:7109.38-7109.149" - cell $and $and$ls180.v:7109$2342 + attribute \src "ls180.v:7105.38-7105.149" + cell $and $and$ls180.v:7105$2341 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7109$2341_Y + connect \A $and$ls180.v:7105$2340_Y connect \B \main_sdram_choose_req_cmd_payload_is_read - connect \Y $and$ls180.v:7109$2342_Y + connect \Y $and$ls180.v:7105$2341_Y end - attribute \src "ls180.v:7112.39-7112.82" - cell $and $and$ls180.v:7112$2343 + attribute \src "ls180.v:7108.39-7108.82" + cell $and $and$ls180.v:7108$2342 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -94423,21 +94419,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_cmd_valid connect \B \main_sdram_cmd_ready - connect \Y $and$ls180.v:7112$2343_Y + connect \Y $and$ls180.v:7108$2342_Y end - attribute \src "ls180.v:7112.38-7112.116" - cell $and $and$ls180.v:7112$2344 + attribute \src "ls180.v:7108.38-7108.116" + cell $and $and$ls180.v:7108$2343 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7112$2343_Y + connect \A $and$ls180.v:7108$2342_Y connect \B \main_sdram_cmd_payload_is_read - connect \Y $and$ls180.v:7112$2344_Y + connect \Y $and$ls180.v:7108$2343_Y end - attribute \src "ls180.v:7123.39-7123.104" - cell $and $and$ls180.v:7123$2346 + attribute \src "ls180.v:7119.39-7119.104" + cell $and $and$ls180.v:7119$2345 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -94445,21 +94441,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7123$2346_Y + connect \Y $and$ls180.v:7119$2345_Y end - attribute \src "ls180.v:7123.38-7123.150" - cell $and $and$ls180.v:7123$2347 + attribute \src "ls180.v:7119.38-7119.150" + cell $and $and$ls180.v:7119$2346 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7123$2346_Y + connect \A $and$ls180.v:7119$2345_Y connect \B \main_sdram_choose_req_cmd_payload_is_write - connect \Y $and$ls180.v:7123$2347_Y + connect \Y $and$ls180.v:7119$2346_Y end - attribute \src "ls180.v:7126.39-7126.104" - cell $and $and$ls180.v:7126$2348 + attribute \src "ls180.v:7122.39-7122.104" + cell $and $and$ls180.v:7122$2347 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -94467,21 +94463,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7126$2348_Y + connect \Y $and$ls180.v:7122$2347_Y end - attribute \src "ls180.v:7126.38-7126.150" - cell $and $and$ls180.v:7126$2349 + attribute \src "ls180.v:7122.38-7122.150" + cell $and $and$ls180.v:7122$2348 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7126$2348_Y + connect \A $and$ls180.v:7122$2347_Y connect \B \main_sdram_choose_req_cmd_payload_is_write - connect \Y $and$ls180.v:7126$2349_Y + connect \Y $and$ls180.v:7122$2348_Y end - attribute \src "ls180.v:7129.39-7129.82" - cell $and $and$ls180.v:7129$2350 + attribute \src "ls180.v:7125.39-7125.82" + cell $and $and$ls180.v:7125$2349 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -94489,32 +94485,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_cmd_valid connect \B \main_sdram_cmd_ready - connect \Y $and$ls180.v:7129$2350_Y + connect \Y $and$ls180.v:7125$2349_Y end - attribute \src "ls180.v:7129.38-7129.117" - cell $and $and$ls180.v:7129$2351 + attribute \src "ls180.v:7125.38-7125.117" + cell $and $and$ls180.v:7125$2350 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7129$2350_Y + connect \A $and$ls180.v:7125$2349_Y connect \B \main_sdram_cmd_payload_is_write - connect \Y $and$ls180.v:7129$2351_Y + connect \Y $and$ls180.v:7125$2350_Y end attribute \src "ls180.v:7344.17-7344.67" - cell $and $and$ls180.v:7344$2358 + cell $and $and$ls180.v:7344$2357 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7344$2357_Y + connect \A $not$ls180.v:7344$2356_Y connect \B \main_sdphy_sdpads_clk - connect \Y $and$ls180.v:7344$2358_Y + connect \Y $and$ls180.v:7344$2357_Y end - attribute \src "ls180.v:7442.8-7442.67" - cell $and $and$ls180.v:7442$2408 + attribute \src "ls180.v:7441.8-7441.67" + cell $and $and$ls180.v:7441$2406 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -94522,54 +94518,54 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_cyc connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:7442$2408_Y + connect \Y $and$ls180.v:7441$2406_Y end - attribute \src "ls180.v:7442.7-7442.102" - cell $and $and$ls180.v:7442$2410 + attribute \src "ls180.v:7441.7-7441.102" + cell $and $and$ls180.v:7441$2408 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7442$2408_Y - connect \B $not$ls180.v:7442$2409_Y - connect \Y $and$ls180.v:7442$2410_Y + connect \A $and$ls180.v:7441$2406_Y + connect \B $not$ls180.v:7441$2407_Y + connect \Y $and$ls180.v:7441$2408_Y end - attribute \src "ls180.v:7461.7-7461.75" - cell $and $and$ls180.v:7461$2414 + attribute \src "ls180.v:7460.7-7460.75" + cell $and $and$ls180.v:7460$2412 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7461$2413_Y + connect \A $not$ls180.v:7460$2411_Y connect \B \main_libresocsim_zero_old_trigger - connect \Y $and$ls180.v:7461$2414_Y + connect \Y $and$ls180.v:7460$2412_Y end - attribute \src "ls180.v:7471.7-7471.56" - cell $and $and$ls180.v:7471$2416 + attribute \src "ls180.v:7468.7-7468.56" + cell $and $and$ls180.v:7468$2414 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_timer_wait - connect \B $not$ls180.v:7471$2415_Y - connect \Y $and$ls180.v:7471$2416_Y + connect \B $not$ls180.v:7468$2413_Y + connect \Y $and$ls180.v:7468$2414_Y end - attribute \src "ls180.v:7499.7-7499.75" - cell $and $and$ls180.v:7499$2423 + attribute \src "ls180.v:7496.7-7496.75" + cell $and $and$ls180.v:7496$2421 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_start1 - connect \B $eq$ls180.v:7499$2422_Y - connect \Y $and$ls180.v:7499$2423_Y + connect \B $eq$ls180.v:7496$2420_Y + connect \Y $and$ls180.v:7496$2421_Y end - attribute \src "ls180.v:7541.8-7541.131" - cell $and $and$ls180.v:7541$2429 + attribute \src "ls180.v:7538.8-7538.131" + cell $and $and$ls180.v:7538$2427 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -94577,21 +94573,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable - connect \Y $and$ls180.v:7541$2429_Y + connect \Y $and$ls180.v:7538$2427_Y end - attribute \src "ls180.v:7541.7-7541.190" - cell $and $and$ls180.v:7541$2431 + attribute \src "ls180.v:7538.7-7538.190" + cell $and $and$ls180.v:7538$2429 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7541$2429_Y - connect \B $not$ls180.v:7541$2430_Y - connect \Y $and$ls180.v:7541$2431_Y + connect \A $and$ls180.v:7538$2427_Y + connect \B $not$ls180.v:7538$2428_Y + connect \Y $and$ls180.v:7538$2429_Y end - attribute \src "ls180.v:7547.8-7547.131" - cell $and $and$ls180.v:7547$2434 + attribute \src "ls180.v:7544.8-7544.131" + cell $and $and$ls180.v:7544$2432 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -94599,21 +94595,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable - connect \Y $and$ls180.v:7547$2434_Y + connect \Y $and$ls180.v:7544$2432_Y end - attribute \src "ls180.v:7547.7-7547.190" - cell $and $and$ls180.v:7547$2436 + attribute \src "ls180.v:7544.7-7544.190" + cell $and $and$ls180.v:7544$2434 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7547$2434_Y - connect \B $not$ls180.v:7547$2435_Y - connect \Y $and$ls180.v:7547$2436_Y + connect \A $and$ls180.v:7544$2432_Y + connect \B $not$ls180.v:7544$2433_Y + connect \Y $and$ls180.v:7544$2434_Y end - attribute \src "ls180.v:7587.8-7587.131" - cell $and $and$ls180.v:7587$2445 + attribute \src "ls180.v:7584.8-7584.131" + cell $and $and$ls180.v:7584$2443 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -94621,21 +94617,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable - connect \Y $and$ls180.v:7587$2445_Y + connect \Y $and$ls180.v:7584$2443_Y end - attribute \src "ls180.v:7587.7-7587.190" - cell $and $and$ls180.v:7587$2447 + attribute \src "ls180.v:7584.7-7584.190" + cell $and $and$ls180.v:7584$2445 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7587$2445_Y - connect \B $not$ls180.v:7587$2446_Y - connect \Y $and$ls180.v:7587$2447_Y + connect \A $and$ls180.v:7584$2443_Y + connect \B $not$ls180.v:7584$2444_Y + connect \Y $and$ls180.v:7584$2445_Y end - attribute \src "ls180.v:7593.8-7593.131" - cell $and $and$ls180.v:7593$2450 + attribute \src "ls180.v:7590.8-7590.131" + cell $and $and$ls180.v:7590$2448 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -94643,21 +94639,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable - connect \Y $and$ls180.v:7593$2450_Y + connect \Y $and$ls180.v:7590$2448_Y end - attribute \src "ls180.v:7593.7-7593.190" - cell $and $and$ls180.v:7593$2452 + attribute \src "ls180.v:7590.7-7590.190" + cell $and $and$ls180.v:7590$2450 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7593$2450_Y - connect \B $not$ls180.v:7593$2451_Y - connect \Y $and$ls180.v:7593$2452_Y + connect \A $and$ls180.v:7590$2448_Y + connect \B $not$ls180.v:7590$2449_Y + connect \Y $and$ls180.v:7590$2450_Y end - attribute \src "ls180.v:7633.8-7633.131" - cell $and $and$ls180.v:7633$2461 + attribute \src "ls180.v:7630.8-7630.131" + cell $and $and$ls180.v:7630$2459 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -94665,21 +94661,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable - connect \Y $and$ls180.v:7633$2461_Y + connect \Y $and$ls180.v:7630$2459_Y end - attribute \src "ls180.v:7633.7-7633.190" - cell $and $and$ls180.v:7633$2463 + attribute \src "ls180.v:7630.7-7630.190" + cell $and $and$ls180.v:7630$2461 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7633$2461_Y - connect \B $not$ls180.v:7633$2462_Y - connect \Y $and$ls180.v:7633$2463_Y + connect \A $and$ls180.v:7630$2459_Y + connect \B $not$ls180.v:7630$2460_Y + connect \Y $and$ls180.v:7630$2461_Y end - attribute \src "ls180.v:7639.8-7639.131" - cell $and $and$ls180.v:7639$2466 + attribute \src "ls180.v:7636.8-7636.131" + cell $and $and$ls180.v:7636$2464 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -94687,21 +94683,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable - connect \Y $and$ls180.v:7639$2466_Y + connect \Y $and$ls180.v:7636$2464_Y end - attribute \src "ls180.v:7639.7-7639.190" - cell $and $and$ls180.v:7639$2468 + attribute \src "ls180.v:7636.7-7636.190" + cell $and $and$ls180.v:7636$2466 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7639$2466_Y - connect \B $not$ls180.v:7639$2467_Y - connect \Y $and$ls180.v:7639$2468_Y + connect \A $and$ls180.v:7636$2464_Y + connect \B $not$ls180.v:7636$2465_Y + connect \Y $and$ls180.v:7636$2466_Y end - attribute \src "ls180.v:7679.8-7679.131" - cell $and $and$ls180.v:7679$2477 + attribute \src "ls180.v:7676.8-7676.131" + cell $and $and$ls180.v:7676$2475 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -94709,21 +94705,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable - connect \Y $and$ls180.v:7679$2477_Y + connect \Y $and$ls180.v:7676$2475_Y end - attribute \src "ls180.v:7679.7-7679.190" - cell $and $and$ls180.v:7679$2479 + attribute \src "ls180.v:7676.7-7676.190" + cell $and $and$ls180.v:7676$2477 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7679$2477_Y - connect \B $not$ls180.v:7679$2478_Y - connect \Y $and$ls180.v:7679$2479_Y + connect \A $and$ls180.v:7676$2475_Y + connect \B $not$ls180.v:7676$2476_Y + connect \Y $and$ls180.v:7676$2477_Y end - attribute \src "ls180.v:7685.8-7685.131" - cell $and $and$ls180.v:7685$2482 + attribute \src "ls180.v:7682.8-7682.131" + cell $and $and$ls180.v:7682$2480 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -94731,109 +94727,109 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable - connect \Y $and$ls180.v:7685$2482_Y + connect \Y $and$ls180.v:7682$2480_Y end - attribute \src "ls180.v:7685.7-7685.190" - cell $and $and$ls180.v:7685$2484 + attribute \src "ls180.v:7682.7-7682.190" + cell $and $and$ls180.v:7682$2482 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7685$2482_Y - connect \B $not$ls180.v:7685$2483_Y - connect \Y $and$ls180.v:7685$2484_Y + connect \A $and$ls180.v:7682$2480_Y + connect \B $not$ls180.v:7682$2481_Y + connect \Y $and$ls180.v:7682$2482_Y end - attribute \src "ls180.v:7882.48-7882.124" - cell $and $and$ls180.v:7882$2509 + attribute \src "ls180.v:7879.48-7879.124" + cell $and $and$ls180.v:7879$2507 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7882$2508_Y + connect \A $eq$ls180.v:7879$2506_Y connect \B \main_sdram_interface_bank0_wdata_ready - connect \Y $and$ls180.v:7882$2509_Y + connect \Y $and$ls180.v:7879$2507_Y end - attribute \src "ls180.v:7882.130-7882.206" - cell $and $and$ls180.v:7882$2512 + attribute \src "ls180.v:7879.130-7879.206" + cell $and $and$ls180.v:7879$2510 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7882$2511_Y + connect \A $eq$ls180.v:7879$2509_Y connect \B \main_sdram_interface_bank1_wdata_ready - connect \Y $and$ls180.v:7882$2512_Y + connect \Y $and$ls180.v:7879$2510_Y end - attribute \src "ls180.v:7882.212-7882.288" - cell $and $and$ls180.v:7882$2515 + attribute \src "ls180.v:7879.212-7879.288" + cell $and $and$ls180.v:7879$2513 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7882$2514_Y + connect \A $eq$ls180.v:7879$2512_Y connect \B \main_sdram_interface_bank2_wdata_ready - connect \Y $and$ls180.v:7882$2515_Y + connect \Y $and$ls180.v:7879$2513_Y end - attribute \src "ls180.v:7882.294-7882.370" - cell $and $and$ls180.v:7882$2518 + attribute \src "ls180.v:7879.294-7879.370" + cell $and $and$ls180.v:7879$2516 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7882$2517_Y + connect \A $eq$ls180.v:7879$2515_Y connect \B \main_sdram_interface_bank3_wdata_ready - connect \Y $and$ls180.v:7882$2518_Y + connect \Y $and$ls180.v:7879$2516_Y end - attribute \src "ls180.v:7883.49-7883.125" - cell $and $and$ls180.v:7883$2521 + attribute \src "ls180.v:7880.49-7880.125" + cell $and $and$ls180.v:7880$2519 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7883$2520_Y + connect \A $eq$ls180.v:7880$2518_Y connect \B \main_sdram_interface_bank0_rdata_valid - connect \Y $and$ls180.v:7883$2521_Y + connect \Y $and$ls180.v:7880$2519_Y end - attribute \src "ls180.v:7883.131-7883.207" - cell $and $and$ls180.v:7883$2524 + attribute \src "ls180.v:7880.131-7880.207" + cell $and $and$ls180.v:7880$2522 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7883$2523_Y + connect \A $eq$ls180.v:7880$2521_Y connect \B \main_sdram_interface_bank1_rdata_valid - connect \Y $and$ls180.v:7883$2524_Y + connect \Y $and$ls180.v:7880$2522_Y end - attribute \src "ls180.v:7883.213-7883.289" - cell $and $and$ls180.v:7883$2527 + attribute \src "ls180.v:7880.213-7880.289" + cell $and $and$ls180.v:7880$2525 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7883$2526_Y + connect \A $eq$ls180.v:7880$2524_Y connect \B \main_sdram_interface_bank2_rdata_valid - connect \Y $and$ls180.v:7883$2527_Y + connect \Y $and$ls180.v:7880$2525_Y end - attribute \src "ls180.v:7883.295-7883.371" - cell $and $and$ls180.v:7883$2530 + attribute \src "ls180.v:7880.295-7880.371" + cell $and $and$ls180.v:7880$2528 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7883$2529_Y + connect \A $eq$ls180.v:7880$2527_Y connect \B \main_sdram_interface_bank3_rdata_valid - connect \Y $and$ls180.v:7883$2530_Y + connect \Y $and$ls180.v:7880$2528_Y end - attribute \src "ls180.v:7902.8-7902.49" - cell $and $and$ls180.v:7902$2533 + attribute \src "ls180.v:7899.8-7899.49" + cell $and $and$ls180.v:7899$2531 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -94841,10 +94837,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_valid connect \B \main_port_cmd_ready - connect \Y $and$ls180.v:7902$2533_Y + connect \Y $and$ls180.v:7899$2531_Y end - attribute \src "ls180.v:7905.8-7905.53" - cell $and $and$ls180.v:7905$2534 + attribute \src "ls180.v:7902.8-7902.53" + cell $and $and$ls180.v:7902$2532 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -94852,32 +94848,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_wdata_valid connect \B \main_port_wdata_ready - connect \Y $and$ls180.v:7905$2534_Y + connect \Y $and$ls180.v:7902$2532_Y end - attribute \src "ls180.v:7910.8-7910.41" - cell $and $and$ls180.v:7910$2536 + attribute \src "ls180.v:7907.8-7907.41" + cell $and $and$ls180.v:7907$2534 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sink_valid - connect \B $not$ls180.v:7910$2535_Y - connect \Y $and$ls180.v:7910$2536_Y + connect \B $not$ls180.v:7907$2533_Y + connect \Y $and$ls180.v:7907$2534_Y end - attribute \src "ls180.v:7910.7-7910.63" - cell $and $and$ls180.v:7910$2538 + attribute \src "ls180.v:7907.7-7907.63" + cell $and $and$ls180.v:7907$2536 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7910$2536_Y - connect \B $not$ls180.v:7910$2537_Y - connect \Y $and$ls180.v:7910$2538_Y + connect \A $and$ls180.v:7907$2534_Y + connect \B $not$ls180.v:7907$2535_Y + connect \Y $and$ls180.v:7907$2536_Y end - attribute \src "ls180.v:7916.8-7916.41" - cell $and $and$ls180.v:7916$2539 + attribute \src "ls180.v:7913.8-7913.41" + cell $and $and$ls180.v:7913$2537 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -94885,43 +94881,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_clk_txen connect \B \main_tx_busy - connect \Y $and$ls180.v:7916$2539_Y + connect \Y $and$ls180.v:7913$2537_Y end - attribute \src "ls180.v:7940.8-7940.30" - cell $and $and$ls180.v:7940$2546 + attribute \src "ls180.v:7937.8-7937.30" + cell $and $and$ls180.v:7937$2544 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7940$2545_Y + connect \A $not$ls180.v:7937$2543_Y connect \B \main_rx_r - connect \Y $and$ls180.v:7940$2546_Y + connect \Y $and$ls180.v:7937$2544_Y end - attribute \src "ls180.v:7973.7-7973.57" - cell $and $and$ls180.v:7973$2552 + attribute \src "ls180.v:7970.7-7970.57" + cell $and $and$ls180.v:7970$2550 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7973$2551_Y + connect \A $not$ls180.v:7970$2549_Y connect \B \main_uart_tx_old_trigger - connect \Y $and$ls180.v:7973$2552_Y + connect \Y $and$ls180.v:7970$2550_Y end - attribute \src "ls180.v:7980.7-7980.57" - cell $and $and$ls180.v:7980$2554 + attribute \src "ls180.v:7977.7-7977.57" + cell $and $and$ls180.v:7977$2552 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7980$2553_Y + connect \A $not$ls180.v:7977$2551_Y connect \B \main_uart_rx_old_trigger - connect \Y $and$ls180.v:7980$2554_Y + connect \Y $and$ls180.v:7977$2552_Y end - attribute \src "ls180.v:7990.8-7990.75" - cell $and $and$ls180.v:7990$2555 + attribute \src "ls180.v:7987.8-7987.75" + cell $and $and$ls180.v:7987$2553 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -94929,21 +94925,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_syncfifo_we connect \B \main_uart_tx_fifo_syncfifo_writable - connect \Y $and$ls180.v:7990$2555_Y + connect \Y $and$ls180.v:7987$2553_Y end - attribute \src "ls180.v:7990.7-7990.107" - cell $and $and$ls180.v:7990$2557 + attribute \src "ls180.v:7987.7-7987.107" + cell $and $and$ls180.v:7987$2555 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7990$2555_Y - connect \B $not$ls180.v:7990$2556_Y - connect \Y $and$ls180.v:7990$2557_Y + connect \A $and$ls180.v:7987$2553_Y + connect \B $not$ls180.v:7987$2554_Y + connect \Y $and$ls180.v:7987$2555_Y end - attribute \src "ls180.v:7996.8-7996.75" - cell $and $and$ls180.v:7996$2560 + attribute \src "ls180.v:7993.8-7993.75" + cell $and $and$ls180.v:7993$2558 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -94951,21 +94947,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_syncfifo_we connect \B \main_uart_tx_fifo_syncfifo_writable - connect \Y $and$ls180.v:7996$2560_Y + connect \Y $and$ls180.v:7993$2558_Y end - attribute \src "ls180.v:7996.7-7996.107" - cell $and $and$ls180.v:7996$2562 + attribute \src "ls180.v:7993.7-7993.107" + cell $and $and$ls180.v:7993$2560 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7996$2560_Y - connect \B $not$ls180.v:7996$2561_Y - connect \Y $and$ls180.v:7996$2562_Y + connect \A $and$ls180.v:7993$2558_Y + connect \B $not$ls180.v:7993$2559_Y + connect \Y $and$ls180.v:7993$2560_Y end - attribute \src "ls180.v:8012.8-8012.75" - cell $and $and$ls180.v:8012$2566 + attribute \src "ls180.v:8009.8-8009.75" + cell $and $and$ls180.v:8009$2564 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -94973,21 +94969,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_syncfifo_we connect \B \main_uart_rx_fifo_syncfifo_writable - connect \Y $and$ls180.v:8012$2566_Y + connect \Y $and$ls180.v:8009$2564_Y end - attribute \src "ls180.v:8012.7-8012.107" - cell $and $and$ls180.v:8012$2568 + attribute \src "ls180.v:8009.7-8009.107" + cell $and $and$ls180.v:8009$2566 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8012$2566_Y - connect \B $not$ls180.v:8012$2567_Y - connect \Y $and$ls180.v:8012$2568_Y + connect \A $and$ls180.v:8009$2564_Y + connect \B $not$ls180.v:8009$2565_Y + connect \Y $and$ls180.v:8009$2566_Y end - attribute \src "ls180.v:8018.8-8018.75" - cell $and $and$ls180.v:8018$2571 + attribute \src "ls180.v:8015.8-8015.75" + cell $and $and$ls180.v:8015$2569 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -94995,21 +94991,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_syncfifo_we connect \B \main_uart_rx_fifo_syncfifo_writable - connect \Y $and$ls180.v:8018$2571_Y + connect \Y $and$ls180.v:8015$2569_Y end - attribute \src "ls180.v:8018.7-8018.107" - cell $and $and$ls180.v:8018$2573 + attribute \src "ls180.v:8015.7-8015.107" + cell $and $and$ls180.v:8015$2571 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8018$2571_Y - connect \B $not$ls180.v:8018$2572_Y - connect \Y $and$ls180.v:8018$2573_Y + connect \A $and$ls180.v:8015$2569_Y + connect \B $not$ls180.v:8015$2570_Y + connect \Y $and$ls180.v:8015$2571_Y end - attribute \src "ls180.v:8131.7-8131.96" - cell $and $and$ls180.v:8131$2596 + attribute \src "ls180.v:8128.7-8128.96" + cell $and $and$ls180.v:8128$2594 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -95017,10 +95013,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_source_valid connect \B \main_sdphy_cmdr_cmdr_converter_source_ready - connect \Y $and$ls180.v:8131$2596_Y + connect \Y $and$ls180.v:8128$2594_Y end - attribute \src "ls180.v:8132.8-8132.93" - cell $and $and$ls180.v:8132$2597 + attribute \src "ls180.v:8129.8-8129.93" + cell $and $and$ls180.v:8129$2595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -95028,10 +95024,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready - connect \Y $and$ls180.v:8132$2597_Y + connect \Y $and$ls180.v:8129$2595_Y end - attribute \src "ls180.v:8140.8-8140.93" - cell $and $and$ls180.v:8140$2598 + attribute \src "ls180.v:8137.8-8137.93" + cell $and $and$ls180.v:8137$2596 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -95039,10 +95035,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready - connect \Y $and$ls180.v:8140$2598_Y + connect \Y $and$ls180.v:8137$2596_Y end - attribute \src "ls180.v:8212.7-8212.98" - cell $and $and$ls180.v:8212$2608 + attribute \src "ls180.v:8209.7-8209.98" + cell $and $and$ls180.v:8209$2606 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -95050,10 +95046,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_source_valid connect \B \main_sdphy_dataw_crcr_converter_source_ready - connect \Y $and$ls180.v:8212$2608_Y + connect \Y $and$ls180.v:8209$2606_Y end - attribute \src "ls180.v:8213.8-8213.95" - cell $and $and$ls180.v:8213$2609 + attribute \src "ls180.v:8210.8-8210.95" + cell $and $and$ls180.v:8210$2607 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -95061,10 +95057,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_sink_valid connect \B \main_sdphy_dataw_crcr_converter_sink_ready - connect \Y $and$ls180.v:8213$2609_Y + connect \Y $and$ls180.v:8210$2607_Y end - attribute \src "ls180.v:8221.8-8221.95" - cell $and $and$ls180.v:8221$2610 + attribute \src "ls180.v:8218.8-8218.95" + cell $and $and$ls180.v:8218$2608 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -95072,10 +95068,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_sink_valid connect \B \main_sdphy_dataw_crcr_converter_sink_ready - connect \Y $and$ls180.v:8221$2610_Y + connect \Y $and$ls180.v:8218$2608_Y end - attribute \src "ls180.v:8291.7-8291.100" - cell $and $and$ls180.v:8291$2620 + attribute \src "ls180.v:8288.7-8288.100" + cell $and $and$ls180.v:8288$2618 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -95083,10 +95079,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_source_valid connect \B \main_sdphy_datar_datar_converter_source_ready - connect \Y $and$ls180.v:8291$2620_Y + connect \Y $and$ls180.v:8288$2618_Y end - attribute \src "ls180.v:8292.8-8292.97" - cell $and $and$ls180.v:8292$2621 + attribute \src "ls180.v:8289.8-8289.97" + cell $and $and$ls180.v:8289$2619 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -95094,10 +95090,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_sink_valid connect \B \main_sdphy_datar_datar_converter_sink_ready - connect \Y $and$ls180.v:8292$2621_Y + connect \Y $and$ls180.v:8289$2619_Y end - attribute \src "ls180.v:8300.8-8300.97" - cell $and $and$ls180.v:8300$2622 + attribute \src "ls180.v:8297.8-8297.97" + cell $and $and$ls180.v:8297$2620 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -95105,10 +95101,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_sink_valid connect \B \main_sdphy_datar_datar_converter_sink_ready - connect \Y $and$ls180.v:8300$2622_Y + connect \Y $and$ls180.v:8297$2620_Y end - attribute \src "ls180.v:8391.7-8391.82" - cell $and $and$ls180.v:8391$2628 + attribute \src "ls180.v:8388.7-8388.82" + cell $and $and$ls180.v:8388$2626 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -95116,10 +95112,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_ready connect \B \main_sdcore_crc16_checker_sink_valid - connect \Y $and$ls180.v:8391$2628_Y + connect \Y $and$ls180.v:8388$2626_Y end - attribute \src "ls180.v:8394.7-8394.82" - cell $and $and$ls180.v:8394$2629 + attribute \src "ls180.v:8391.7-8391.82" + cell $and $and$ls180.v:8391$2627 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -95127,10 +95123,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_ready connect \B \main_sdcore_crc16_checker_sink_valid - connect \Y $and$ls180.v:8394$2629_Y + connect \Y $and$ls180.v:8391$2627_Y end - attribute \src "ls180.v:8397.7-8397.82" - cell $and $and$ls180.v:8397$2630 + attribute \src "ls180.v:8394.7-8394.82" + cell $and $and$ls180.v:8394$2628 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -95138,10 +95134,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_ready connect \B \main_sdcore_crc16_checker_sink_valid - connect \Y $and$ls180.v:8397$2630_Y + connect \Y $and$ls180.v:8394$2628_Y end - attribute \src "ls180.v:8400.7-8400.82" - cell $and $and$ls180.v:8400$2631 + attribute \src "ls180.v:8397.7-8397.82" + cell $and $and$ls180.v:8397$2629 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -95149,10 +95145,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_ready connect \B \main_sdcore_crc16_checker_sink_valid - connect \Y $and$ls180.v:8400$2631_Y + connect \Y $and$ls180.v:8397$2629_Y end - attribute \src "ls180.v:8403.7-8403.82" - cell $and $and$ls180.v:8403$2632 + attribute \src "ls180.v:8400.7-8400.82" + cell $and $and$ls180.v:8400$2630 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -95160,10 +95156,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8403$2632_Y + connect \Y $and$ls180.v:8400$2630_Y end - attribute \src "ls180.v:8408.7-8408.82" - cell $and $and$ls180.v:8408$2633 + attribute \src "ls180.v:8405.7-8405.82" + cell $and $and$ls180.v:8405$2631 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -95171,10 +95167,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8408$2633_Y + connect \Y $and$ls180.v:8405$2631_Y end - attribute \src "ls180.v:8413.7-8413.82" - cell $and $and$ls180.v:8413$2634 + attribute \src "ls180.v:8410.7-8410.82" + cell $and $and$ls180.v:8410$2632 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -95182,10 +95178,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8413$2634_Y + connect \Y $and$ls180.v:8410$2632_Y end - attribute \src "ls180.v:8418.7-8418.82" - cell $and $and$ls180.v:8418$2635 + attribute \src "ls180.v:8415.7-8415.82" + cell $and $and$ls180.v:8415$2633 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -95193,10 +95189,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8418$2635_Y + connect \Y $and$ls180.v:8415$2633_Y end - attribute \src "ls180.v:8423.7-8423.82" - cell $and $and$ls180.v:8423$2636 + attribute \src "ls180.v:8420.7-8420.82" + cell $and $and$ls180.v:8420$2634 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -95204,10 +95200,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8423$2636_Y + connect \Y $and$ls180.v:8420$2634_Y end - attribute \src "ls180.v:8488.8-8488.83" - cell $and $and$ls180.v:8488$2639 + attribute \src "ls180.v:8485.8-8485.83" + cell $and $and$ls180.v:8485$2637 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -95215,21 +95211,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_syncfifo_we connect \B \main_sdblock2mem_fifo_syncfifo_writable - connect \Y $and$ls180.v:8488$2639_Y + connect \Y $and$ls180.v:8485$2637_Y end - attribute \src "ls180.v:8488.7-8488.119" - cell $and $and$ls180.v:8488$2641 + attribute \src "ls180.v:8485.7-8485.119" + cell $and $and$ls180.v:8485$2639 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8488$2639_Y - connect \B $not$ls180.v:8488$2640_Y - connect \Y $and$ls180.v:8488$2641_Y + connect \A $and$ls180.v:8485$2637_Y + connect \B $not$ls180.v:8485$2638_Y + connect \Y $and$ls180.v:8485$2639_Y end - attribute \src "ls180.v:8494.8-8494.83" - cell $and $and$ls180.v:8494$2644 + attribute \src "ls180.v:8491.8-8491.83" + cell $and $and$ls180.v:8491$2642 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -95237,21 +95233,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_syncfifo_we connect \B \main_sdblock2mem_fifo_syncfifo_writable - connect \Y $and$ls180.v:8494$2644_Y + connect \Y $and$ls180.v:8491$2642_Y end - attribute \src "ls180.v:8494.7-8494.119" - cell $and $and$ls180.v:8494$2646 + attribute \src "ls180.v:8491.7-8491.119" + cell $and $and$ls180.v:8491$2644 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8494$2644_Y - connect \B $not$ls180.v:8494$2645_Y - connect \Y $and$ls180.v:8494$2646_Y + connect \A $and$ls180.v:8491$2642_Y + connect \B $not$ls180.v:8491$2643_Y + connect \Y $and$ls180.v:8491$2644_Y end - attribute \src "ls180.v:8514.7-8514.88" - cell $and $and$ls180.v:8514$2653 + attribute \src "ls180.v:8511.7-8511.88" + cell $and $and$ls180.v:8511$2651 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -95259,10 +95255,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_source_valid connect \B \main_sdblock2mem_converter_source_ready - connect \Y $and$ls180.v:8514$2653_Y + connect \Y $and$ls180.v:8511$2651_Y end - attribute \src "ls180.v:8515.8-8515.85" - cell $and $and$ls180.v:8515$2654 + attribute \src "ls180.v:8512.8-8512.85" + cell $and $and$ls180.v:8512$2652 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -95270,10 +95266,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_sink_valid connect \B \main_sdblock2mem_converter_sink_ready - connect \Y $and$ls180.v:8515$2654_Y + connect \Y $and$ls180.v:8512$2652_Y end - attribute \src "ls180.v:8523.8-8523.85" - cell $and $and$ls180.v:8523$2655 + attribute \src "ls180.v:8520.8-8520.85" + cell $and $and$ls180.v:8520$2653 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -95281,10 +95277,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_sink_valid connect \B \main_sdblock2mem_converter_sink_ready - connect \Y $and$ls180.v:8523$2655_Y + connect \Y $and$ls180.v:8520$2653_Y end - attribute \src "ls180.v:8567.7-8567.88" - cell $and $and$ls180.v:8567$2659 + attribute \src "ls180.v:8564.7-8564.88" + cell $and $and$ls180.v:8564$2657 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -95292,10 +95288,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_converter_source_valid connect \B \main_sdmem2block_converter_source_ready - connect \Y $and$ls180.v:8567$2659_Y + connect \Y $and$ls180.v:8564$2657_Y end - attribute \src "ls180.v:8574.8-8574.83" - cell $and $and$ls180.v:8574$2661 + attribute \src "ls180.v:8571.8-8571.83" + cell $and $and$ls180.v:8571$2659 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -95303,21 +95299,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_syncfifo_we connect \B \main_sdmem2block_fifo_syncfifo_writable - connect \Y $and$ls180.v:8574$2661_Y + connect \Y $and$ls180.v:8571$2659_Y end - attribute \src "ls180.v:8574.7-8574.119" - cell $and $and$ls180.v:8574$2663 + attribute \src "ls180.v:8571.7-8571.119" + cell $and $and$ls180.v:8571$2661 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8574$2661_Y - connect \B $not$ls180.v:8574$2662_Y - connect \Y $and$ls180.v:8574$2663_Y + connect \A $and$ls180.v:8571$2659_Y + connect \B $not$ls180.v:8571$2660_Y + connect \Y $and$ls180.v:8571$2661_Y end - attribute \src "ls180.v:8580.8-8580.83" - cell $and $and$ls180.v:8580$2666 + attribute \src "ls180.v:8577.8-8577.83" + cell $and $and$ls180.v:8577$2664 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -95325,21 +95321,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_syncfifo_we connect \B \main_sdmem2block_fifo_syncfifo_writable - connect \Y $and$ls180.v:8580$2666_Y + connect \Y $and$ls180.v:8577$2664_Y end - attribute \src "ls180.v:8580.7-8580.119" - cell $and $and$ls180.v:8580$2668 + attribute \src "ls180.v:8577.7-8577.119" + cell $and $and$ls180.v:8577$2666 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8580$2666_Y - connect \B $not$ls180.v:8580$2667_Y - connect \Y $and$ls180.v:8580$2668_Y + connect \A $and$ls180.v:8577$2664_Y + connect \B $not$ls180.v:8577$2665_Y + connect \Y $and$ls180.v:8577$2666_Y end - attribute \src "ls180.v:2762.42-2762.101" - cell $eq $eq$ls180.v:2762$18 + attribute \src "ls180.v:2763.42-2763.101" + cell $eq $eq$ls180.v:2763$18 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -95347,10 +95343,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_interface0_converted_interface_sel connect \B 1'0 - connect \Y $eq$ls180.v:2762$18_Y + connect \Y $eq$ls180.v:2763$18_Y end - attribute \src "ls180.v:2769.11-2769.54" - cell $eq $eq$ls180.v:2769$23 + attribute \src "ls180.v:2770.11-2770.54" + cell $eq $eq$ls180.v:2770$23 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -95358,10 +95354,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_converter0_counter connect \B 1'1 - connect \Y $eq$ls180.v:2769$23_Y + connect \Y $eq$ls180.v:2770$23_Y end - attribute \src "ls180.v:2822.42-2822.101" - cell $eq $eq$ls180.v:2822$29 + attribute \src "ls180.v:2823.42-2823.101" + cell $eq $eq$ls180.v:2823$29 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -95369,10 +95365,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_interface1_converted_interface_sel connect \B 1'0 - connect \Y $eq$ls180.v:2822$29_Y + connect \Y $eq$ls180.v:2823$29_Y end - attribute \src "ls180.v:2829.11-2829.54" - cell $eq $eq$ls180.v:2829$34 + attribute \src "ls180.v:2830.11-2830.54" + cell $eq $eq$ls180.v:2830$34 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -95380,10 +95376,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_converter1_counter connect \B 1'1 - connect \Y $eq$ls180.v:2829$34_Y + connect \Y $eq$ls180.v:2830$34_Y end - attribute \src "ls180.v:2882.42-2882.101" - cell $eq $eq$ls180.v:2882$40 + attribute \src "ls180.v:2883.42-2883.101" + cell $eq $eq$ls180.v:2883$40 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -95391,10 +95387,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_interface2_converted_interface_sel connect \B 1'0 - connect \Y $eq$ls180.v:2882$40_Y + connect \Y $eq$ls180.v:2883$40_Y end - attribute \src "ls180.v:2889.11-2889.54" - cell $eq $eq$ls180.v:2889$45 + attribute \src "ls180.v:2890.11-2890.54" + cell $eq $eq$ls180.v:2890$45 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -95402,10 +95398,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_converter2_counter connect \B 1'1 - connect \Y $eq$ls180.v:2889$45_Y + connect \Y $eq$ls180.v:2890$45_Y end - attribute \src "ls180.v:3080.34-3080.65" - cell $eq $eq$ls180.v:3080$74 + attribute \src "ls180.v:3076.34-3076.65" + cell $eq $eq$ls180.v:3076$73 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -95413,10 +95409,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_timer_count1 connect \B 1'0 - connect \Y $eq$ls180.v:3080$74_Y + connect \Y $eq$ls180.v:3076$73_Y end - attribute \src "ls180.v:3084.68-3084.102" - cell $eq $eq$ls180.v:3084$77 + attribute \src "ls180.v:3080.68-3080.102" + cell $eq $eq$ls180.v:3080$76 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -95424,10 +95420,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_count connect \B 1'0 - connect \Y $eq$ls180.v:3084$77_Y + connect \Y $eq$ls180.v:3080$76_Y end - attribute \src "ls180.v:3128.43-3128.134" - cell $eq $eq$ls180.v:3128$82 + attribute \src "ls180.v:3124.43-3124.134" + cell $eq $eq$ls180.v:3124$81 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -95435,10 +95431,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_row connect \B \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] - connect \Y $eq$ls180.v:3128$82_Y + connect \Y $eq$ls180.v:3124$81_Y end - attribute \src "ls180.v:3145.47-3145.88" - cell $eq $eq$ls180.v:3145$95 + attribute \src "ls180.v:3141.47-3141.88" + cell $eq $eq$ls180.v:3141$94 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -95446,10 +95442,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_row_close connect \B 1'0 - connect \Y $eq$ls180.v:3145$95_Y + connect \Y $eq$ls180.v:3141$94_Y end - attribute \src "ls180.v:3285.43-3285.134" - cell $eq $eq$ls180.v:3285$112 + attribute \src "ls180.v:3281.43-3281.134" + cell $eq $eq$ls180.v:3281$111 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -95457,10 +95453,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_row connect \B \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] - connect \Y $eq$ls180.v:3285$112_Y + connect \Y $eq$ls180.v:3281$111_Y end - attribute \src "ls180.v:3302.47-3302.88" - cell $eq $eq$ls180.v:3302$125 + attribute \src "ls180.v:3298.47-3298.88" + cell $eq $eq$ls180.v:3298$124 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -95468,10 +95464,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_row_close connect \B 1'0 - connect \Y $eq$ls180.v:3302$125_Y + connect \Y $eq$ls180.v:3298$124_Y end - attribute \src "ls180.v:3442.43-3442.134" - cell $eq $eq$ls180.v:3442$142 + attribute \src "ls180.v:3438.43-3438.134" + cell $eq $eq$ls180.v:3438$141 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -95479,10 +95475,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_row connect \B \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] - connect \Y $eq$ls180.v:3442$142_Y + connect \Y $eq$ls180.v:3438$141_Y end - attribute \src "ls180.v:3459.47-3459.88" - cell $eq $eq$ls180.v:3459$155 + attribute \src "ls180.v:3455.47-3455.88" + cell $eq $eq$ls180.v:3455$154 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -95490,10 +95486,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_row_close connect \B 1'0 - connect \Y $eq$ls180.v:3459$155_Y + connect \Y $eq$ls180.v:3455$154_Y end - attribute \src "ls180.v:3599.43-3599.134" - cell $eq $eq$ls180.v:3599$172 + attribute \src "ls180.v:3595.43-3595.134" + cell $eq $eq$ls180.v:3595$171 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -95501,10 +95497,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_row connect \B \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] - connect \Y $eq$ls180.v:3599$172_Y + connect \Y $eq$ls180.v:3595$171_Y end - attribute \src "ls180.v:3616.47-3616.88" - cell $eq $eq$ls180.v:3616$185 + attribute \src "ls180.v:3612.47-3612.88" + cell $eq $eq$ls180.v:3612$184 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -95512,10 +95508,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_row_close connect \B 1'0 - connect \Y $eq$ls180.v:3616$185_Y + connect \Y $eq$ls180.v:3612$184_Y end - attribute \src "ls180.v:3753.32-3753.56" - cell $eq $eq$ls180.v:3753$232 + attribute \src "ls180.v:3749.32-3749.56" + cell $eq $eq$ls180.v:3749$231 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -95523,10 +95519,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_time0 connect \B 1'0 - connect \Y $eq$ls180.v:3753$232_Y + connect \Y $eq$ls180.v:3749$231_Y end - attribute \src "ls180.v:3754.32-3754.56" - cell $eq $eq$ls180.v:3754$233 + attribute \src "ls180.v:3750.32-3750.56" + cell $eq $eq$ls180.v:3750$232 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -95534,10 +95530,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_time1 connect \B 1'0 - connect \Y $eq$ls180.v:3754$233_Y + connect \Y $eq$ls180.v:3750$232_Y end - attribute \src "ls180.v:3765.339-3765.418" - cell $eq $eq$ls180.v:3765$247 + attribute \src "ls180.v:3761.339-3761.418" + cell $eq $eq$ls180.v:3761$246 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -95545,10 +95541,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_is_read connect \B \main_sdram_choose_cmd_want_reads - connect \Y $eq$ls180.v:3765$247_Y + connect \Y $eq$ls180.v:3761$246_Y end - attribute \src "ls180.v:3765.423-3765.504" - cell $eq $eq$ls180.v:3765$248 + attribute \src "ls180.v:3761.423-3761.504" + cell $eq $eq$ls180.v:3761$247 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -95556,10 +95552,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_is_write connect \B \main_sdram_choose_cmd_want_writes - connect \Y $eq$ls180.v:3765$248_Y + connect \Y $eq$ls180.v:3761$247_Y end - attribute \src "ls180.v:3766.339-3766.418" - cell $eq $eq$ls180.v:3766$260 + attribute \src "ls180.v:3762.339-3762.418" + cell $eq $eq$ls180.v:3762$259 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -95567,10 +95563,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_is_read connect \B \main_sdram_choose_cmd_want_reads - connect \Y $eq$ls180.v:3766$260_Y + connect \Y $eq$ls180.v:3762$259_Y end - attribute \src "ls180.v:3766.423-3766.504" - cell $eq $eq$ls180.v:3766$261 + attribute \src "ls180.v:3762.423-3762.504" + cell $eq $eq$ls180.v:3762$260 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -95578,10 +95574,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_is_write connect \B \main_sdram_choose_cmd_want_writes - connect \Y $eq$ls180.v:3766$261_Y + connect \Y $eq$ls180.v:3762$260_Y end - attribute \src "ls180.v:3767.339-3767.418" - cell $eq $eq$ls180.v:3767$273 + attribute \src "ls180.v:3763.339-3763.418" + cell $eq $eq$ls180.v:3763$272 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -95589,10 +95585,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_is_read connect \B \main_sdram_choose_cmd_want_reads - connect \Y $eq$ls180.v:3767$273_Y + connect \Y $eq$ls180.v:3763$272_Y end - attribute \src "ls180.v:3767.423-3767.504" - cell $eq $eq$ls180.v:3767$274 + attribute \src "ls180.v:3763.423-3763.504" + cell $eq $eq$ls180.v:3763$273 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -95600,10 +95596,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_is_write connect \B \main_sdram_choose_cmd_want_writes - connect \Y $eq$ls180.v:3767$274_Y + connect \Y $eq$ls180.v:3763$273_Y end - attribute \src "ls180.v:3768.339-3768.418" - cell $eq $eq$ls180.v:3768$286 + attribute \src "ls180.v:3764.339-3764.418" + cell $eq $eq$ls180.v:3764$285 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -95611,10 +95607,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_is_read connect \B \main_sdram_choose_cmd_want_reads - connect \Y $eq$ls180.v:3768$286_Y + connect \Y $eq$ls180.v:3764$285_Y end - attribute \src "ls180.v:3768.423-3768.504" - cell $eq $eq$ls180.v:3768$287 + attribute \src "ls180.v:3764.423-3764.504" + cell $eq $eq$ls180.v:3764$286 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -95622,10 +95618,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_is_write connect \B \main_sdram_choose_cmd_want_writes - connect \Y $eq$ls180.v:3768$287_Y + connect \Y $eq$ls180.v:3764$286_Y end - attribute \src "ls180.v:3798.339-3798.418" - cell $eq $eq$ls180.v:3798$305 + attribute \src "ls180.v:3794.339-3794.418" + cell $eq $eq$ls180.v:3794$304 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -95633,10 +95629,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_is_read connect \B \main_sdram_choose_req_want_reads - connect \Y $eq$ls180.v:3798$305_Y + connect \Y $eq$ls180.v:3794$304_Y end - attribute \src "ls180.v:3798.423-3798.504" - cell $eq $eq$ls180.v:3798$306 + attribute \src "ls180.v:3794.423-3794.504" + cell $eq $eq$ls180.v:3794$305 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -95644,10 +95640,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_is_write connect \B \main_sdram_choose_req_want_writes - connect \Y $eq$ls180.v:3798$306_Y + connect \Y $eq$ls180.v:3794$305_Y end - attribute \src "ls180.v:3799.339-3799.418" - cell $eq $eq$ls180.v:3799$318 + attribute \src "ls180.v:3795.339-3795.418" + cell $eq $eq$ls180.v:3795$317 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -95655,10 +95651,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_is_read connect \B \main_sdram_choose_req_want_reads - connect \Y $eq$ls180.v:3799$318_Y + connect \Y $eq$ls180.v:3795$317_Y end - attribute \src "ls180.v:3799.423-3799.504" - cell $eq $eq$ls180.v:3799$319 + attribute \src "ls180.v:3795.423-3795.504" + cell $eq $eq$ls180.v:3795$318 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -95666,10 +95662,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_is_write connect \B \main_sdram_choose_req_want_writes - connect \Y $eq$ls180.v:3799$319_Y + connect \Y $eq$ls180.v:3795$318_Y end - attribute \src "ls180.v:3800.339-3800.418" - cell $eq $eq$ls180.v:3800$331 + attribute \src "ls180.v:3796.339-3796.418" + cell $eq $eq$ls180.v:3796$330 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -95677,10 +95673,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_is_read connect \B \main_sdram_choose_req_want_reads - connect \Y $eq$ls180.v:3800$331_Y + connect \Y $eq$ls180.v:3796$330_Y end - attribute \src "ls180.v:3800.423-3800.504" - cell $eq $eq$ls180.v:3800$332 + attribute \src "ls180.v:3796.423-3796.504" + cell $eq $eq$ls180.v:3796$331 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -95688,10 +95684,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_is_write connect \B \main_sdram_choose_req_want_writes - connect \Y $eq$ls180.v:3800$332_Y + connect \Y $eq$ls180.v:3796$331_Y end - attribute \src "ls180.v:3801.339-3801.418" - cell $eq $eq$ls180.v:3801$344 + attribute \src "ls180.v:3797.339-3797.418" + cell $eq $eq$ls180.v:3797$343 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -95699,10 +95695,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_is_read connect \B \main_sdram_choose_req_want_reads - connect \Y $eq$ls180.v:3801$344_Y + connect \Y $eq$ls180.v:3797$343_Y end - attribute \src "ls180.v:3801.423-3801.504" - cell $eq $eq$ls180.v:3801$345 + attribute \src "ls180.v:3797.423-3797.504" + cell $eq $eq$ls180.v:3797$344 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -95710,10 +95706,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_is_write connect \B \main_sdram_choose_req_want_writes - connect \Y $eq$ls180.v:3801$345_Y + connect \Y $eq$ls180.v:3797$344_Y end - attribute \src "ls180.v:3830.78-3830.113" - cell $eq $eq$ls180.v:3830$354 + attribute \src "ls180.v:3826.78-3826.113" + cell $eq $eq$ls180.v:3826$353 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -95721,10 +95717,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_grant connect \B 1'0 - connect \Y $eq$ls180.v:3830$354_Y + connect \Y $eq$ls180.v:3826$353_Y end - attribute \src "ls180.v:3833.78-3833.113" - cell $eq $eq$ls180.v:3833$357 + attribute \src "ls180.v:3829.78-3829.113" + cell $eq $eq$ls180.v:3829$356 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -95732,10 +95728,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_grant connect \B 1'0 - connect \Y $eq$ls180.v:3833$357_Y + connect \Y $eq$ls180.v:3829$356_Y end - attribute \src "ls180.v:3839.78-3839.113" - cell $eq $eq$ls180.v:3839$361 + attribute \src "ls180.v:3835.78-3835.113" + cell $eq $eq$ls180.v:3835$360 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -95743,10 +95739,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_grant connect \B 1'1 - connect \Y $eq$ls180.v:3839$361_Y + connect \Y $eq$ls180.v:3835$360_Y end - attribute \src "ls180.v:3842.78-3842.113" - cell $eq $eq$ls180.v:3842$364 + attribute \src "ls180.v:3838.78-3838.113" + cell $eq $eq$ls180.v:3838$363 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -95754,10 +95750,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_grant connect \B 1'1 - connect \Y $eq$ls180.v:3842$364_Y + connect \Y $eq$ls180.v:3838$363_Y end - attribute \src "ls180.v:3848.78-3848.113" - cell $eq $eq$ls180.v:3848$368 + attribute \src "ls180.v:3844.78-3844.113" + cell $eq $eq$ls180.v:3844$367 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -95765,10 +95761,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_grant connect \B 2'10 - connect \Y $eq$ls180.v:3848$368_Y + connect \Y $eq$ls180.v:3844$367_Y end - attribute \src "ls180.v:3851.78-3851.113" - cell $eq $eq$ls180.v:3851$371 + attribute \src "ls180.v:3847.78-3847.113" + cell $eq $eq$ls180.v:3847$370 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -95776,10 +95772,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_grant connect \B 2'10 - connect \Y $eq$ls180.v:3851$371_Y + connect \Y $eq$ls180.v:3847$370_Y end - attribute \src "ls180.v:3857.78-3857.113" - cell $eq $eq$ls180.v:3857$375 + attribute \src "ls180.v:3853.78-3853.113" + cell $eq $eq$ls180.v:3853$374 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -95787,10 +95783,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_grant connect \B 2'11 - connect \Y $eq$ls180.v:3857$375_Y + connect \Y $eq$ls180.v:3853$374_Y end - attribute \src "ls180.v:3860.78-3860.113" - cell $eq $eq$ls180.v:3860$378 + attribute \src "ls180.v:3856.78-3856.113" + cell $eq $eq$ls180.v:3856$377 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -95798,10 +95794,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_grant connect \B 2'11 - connect \Y $eq$ls180.v:3860$378_Y + connect \Y $eq$ls180.v:3856$377_Y end - attribute \src "ls180.v:3941.42-3941.82" - cell $eq $eq$ls180.v:3941$401 + attribute \src "ls180.v:3937.42-3937.82" + cell $eq $eq$ls180.v:3937$400 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -95809,10 +95805,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 1'0 - connect \Y $eq$ls180.v:3941$401_Y + connect \Y $eq$ls180.v:3937$400_Y end - attribute \src "ls180.v:3941.145-3941.178" - cell $eq $eq$ls180.v:3941$402 + attribute \src "ls180.v:3937.145-3937.178" + cell $eq $eq$ls180.v:3937$401 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -95820,10 +95816,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:3941$402_Y + connect \Y $eq$ls180.v:3937$401_Y end - attribute \src "ls180.v:3941.220-3941.253" - cell $eq $eq$ls180.v:3941$405 + attribute \src "ls180.v:3937.220-3937.253" + cell $eq $eq$ls180.v:3937$404 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -95831,10 +95827,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:3941$405_Y + connect \Y $eq$ls180.v:3937$404_Y end - attribute \src "ls180.v:3941.295-3941.328" - cell $eq $eq$ls180.v:3941$408 + attribute \src "ls180.v:3937.295-3937.328" + cell $eq $eq$ls180.v:3937$407 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -95842,10 +95838,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:3941$408_Y + connect \Y $eq$ls180.v:3937$407_Y end - attribute \src "ls180.v:3946.42-3946.82" - cell $eq $eq$ls180.v:3946$417 + attribute \src "ls180.v:3942.42-3942.82" + cell $eq $eq$ls180.v:3942$416 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -95853,10 +95849,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 1'1 - connect \Y $eq$ls180.v:3946$417_Y + connect \Y $eq$ls180.v:3942$416_Y end - attribute \src "ls180.v:3946.145-3946.178" - cell $eq $eq$ls180.v:3946$418 + attribute \src "ls180.v:3942.145-3942.178" + cell $eq $eq$ls180.v:3942$417 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -95864,10 +95860,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:3946$418_Y + connect \Y $eq$ls180.v:3942$417_Y end - attribute \src "ls180.v:3946.220-3946.253" - cell $eq $eq$ls180.v:3946$421 + attribute \src "ls180.v:3942.220-3942.253" + cell $eq $eq$ls180.v:3942$420 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -95875,10 +95871,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:3946$421_Y + connect \Y $eq$ls180.v:3942$420_Y end - attribute \src "ls180.v:3946.295-3946.328" - cell $eq $eq$ls180.v:3946$424 + attribute \src "ls180.v:3942.295-3942.328" + cell $eq $eq$ls180.v:3942$423 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -95886,10 +95882,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:3946$424_Y + connect \Y $eq$ls180.v:3942$423_Y end - attribute \src "ls180.v:3951.42-3951.82" - cell $eq $eq$ls180.v:3951$433 + attribute \src "ls180.v:3947.42-3947.82" + cell $eq $eq$ls180.v:3947$432 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -95897,10 +95893,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 2'10 - connect \Y $eq$ls180.v:3951$433_Y + connect \Y $eq$ls180.v:3947$432_Y end - attribute \src "ls180.v:3951.145-3951.178" - cell $eq $eq$ls180.v:3951$434 + attribute \src "ls180.v:3947.145-3947.178" + cell $eq $eq$ls180.v:3947$433 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -95908,10 +95904,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:3951$434_Y + connect \Y $eq$ls180.v:3947$433_Y end - attribute \src "ls180.v:3951.220-3951.253" - cell $eq $eq$ls180.v:3951$437 + attribute \src "ls180.v:3947.220-3947.253" + cell $eq $eq$ls180.v:3947$436 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -95919,10 +95915,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:3951$437_Y + connect \Y $eq$ls180.v:3947$436_Y end - attribute \src "ls180.v:3951.295-3951.328" - cell $eq $eq$ls180.v:3951$440 + attribute \src "ls180.v:3947.295-3947.328" + cell $eq $eq$ls180.v:3947$439 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -95930,10 +95926,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:3951$440_Y + connect \Y $eq$ls180.v:3947$439_Y end - attribute \src "ls180.v:3956.42-3956.82" - cell $eq $eq$ls180.v:3956$449 + attribute \src "ls180.v:3952.42-3952.82" + cell $eq $eq$ls180.v:3952$448 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -95941,10 +95937,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 2'11 - connect \Y $eq$ls180.v:3956$449_Y + connect \Y $eq$ls180.v:3952$448_Y end - attribute \src "ls180.v:3956.145-3956.178" - cell $eq $eq$ls180.v:3956$450 + attribute \src "ls180.v:3952.145-3952.178" + cell $eq $eq$ls180.v:3952$449 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -95952,10 +95948,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:3956$450_Y + connect \Y $eq$ls180.v:3952$449_Y end - attribute \src "ls180.v:3956.220-3956.253" - cell $eq $eq$ls180.v:3956$453 + attribute \src "ls180.v:3952.220-3952.253" + cell $eq $eq$ls180.v:3952$452 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -95963,10 +95959,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:3956$453_Y + connect \Y $eq$ls180.v:3952$452_Y end - attribute \src "ls180.v:3956.295-3956.328" - cell $eq $eq$ls180.v:3956$456 + attribute \src "ls180.v:3952.295-3952.328" + cell $eq $eq$ls180.v:3952$455 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -95974,10 +95970,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:3956$456_Y + connect \Y $eq$ls180.v:3952$455_Y end - attribute \src "ls180.v:3961.44-3961.77" - cell $eq $eq$ls180.v:3961$465 + attribute \src "ls180.v:3957.44-3957.77" + cell $eq $eq$ls180.v:3957$464 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -95985,10 +95981,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:3961$465_Y + connect \Y $eq$ls180.v:3957$464_Y end - attribute \src "ls180.v:3961.83-3961.123" - cell $eq $eq$ls180.v:3961$466 + attribute \src "ls180.v:3957.83-3957.123" + cell $eq $eq$ls180.v:3957$465 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -95996,10 +95992,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 1'0 - connect \Y $eq$ls180.v:3961$466_Y + connect \Y $eq$ls180.v:3957$465_Y end - attribute \src "ls180.v:3961.186-3961.219" - cell $eq $eq$ls180.v:3961$467 + attribute \src "ls180.v:3957.186-3957.219" + cell $eq $eq$ls180.v:3957$466 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -96007,10 +96003,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:3961$467_Y + connect \Y $eq$ls180.v:3957$466_Y end - attribute \src "ls180.v:3961.261-3961.294" - cell $eq $eq$ls180.v:3961$470 + attribute \src "ls180.v:3957.261-3957.294" + cell $eq $eq$ls180.v:3957$469 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -96018,10 +96014,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:3961$470_Y + connect \Y $eq$ls180.v:3957$469_Y end - attribute \src "ls180.v:3961.336-3961.369" - cell $eq $eq$ls180.v:3961$473 + attribute \src "ls180.v:3957.336-3957.369" + cell $eq $eq$ls180.v:3957$472 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -96029,10 +96025,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:3961$473_Y + connect \Y $eq$ls180.v:3957$472_Y end - attribute \src "ls180.v:3961.418-3961.451" - cell $eq $eq$ls180.v:3961$481 + attribute \src "ls180.v:3957.418-3957.451" + cell $eq $eq$ls180.v:3957$480 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -96040,10 +96036,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:3961$481_Y + connect \Y $eq$ls180.v:3957$480_Y end - attribute \src "ls180.v:3961.457-3961.497" - cell $eq $eq$ls180.v:3961$482 + attribute \src "ls180.v:3957.457-3957.497" + cell $eq $eq$ls180.v:3957$481 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -96051,10 +96047,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 1'1 - connect \Y $eq$ls180.v:3961$482_Y + connect \Y $eq$ls180.v:3957$481_Y end - attribute \src "ls180.v:3961.560-3961.593" - cell $eq $eq$ls180.v:3961$483 + attribute \src "ls180.v:3957.560-3957.593" + cell $eq $eq$ls180.v:3957$482 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -96062,10 +96058,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:3961$483_Y + connect \Y $eq$ls180.v:3957$482_Y end - attribute \src "ls180.v:3961.635-3961.668" - cell $eq $eq$ls180.v:3961$486 + attribute \src "ls180.v:3957.635-3957.668" + cell $eq $eq$ls180.v:3957$485 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -96073,10 +96069,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:3961$486_Y + connect \Y $eq$ls180.v:3957$485_Y end - attribute \src "ls180.v:3961.710-3961.743" - cell $eq $eq$ls180.v:3961$489 + attribute \src "ls180.v:3957.710-3957.743" + cell $eq $eq$ls180.v:3957$488 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -96084,10 +96080,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:3961$489_Y + connect \Y $eq$ls180.v:3957$488_Y end - attribute \src "ls180.v:3961.792-3961.825" - cell $eq $eq$ls180.v:3961$497 + attribute \src "ls180.v:3957.792-3957.825" + cell $eq $eq$ls180.v:3957$496 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -96095,10 +96091,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:3961$497_Y + connect \Y $eq$ls180.v:3957$496_Y end - attribute \src "ls180.v:3961.831-3961.871" - cell $eq $eq$ls180.v:3961$498 + attribute \src "ls180.v:3957.831-3957.871" + cell $eq $eq$ls180.v:3957$497 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -96106,10 +96102,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 2'10 - connect \Y $eq$ls180.v:3961$498_Y + connect \Y $eq$ls180.v:3957$497_Y end - attribute \src "ls180.v:3961.934-3961.967" - cell $eq $eq$ls180.v:3961$499 + attribute \src "ls180.v:3957.934-3957.967" + cell $eq $eq$ls180.v:3957$498 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -96117,10 +96113,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:3961$499_Y + connect \Y $eq$ls180.v:3957$498_Y end - attribute \src "ls180.v:3961.1009-3961.1042" - cell $eq $eq$ls180.v:3961$502 + attribute \src "ls180.v:3957.1009-3957.1042" + cell $eq $eq$ls180.v:3957$501 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -96128,10 +96124,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:3961$502_Y + connect \Y $eq$ls180.v:3957$501_Y end - attribute \src "ls180.v:3961.1084-3961.1117" - cell $eq $eq$ls180.v:3961$505 + attribute \src "ls180.v:3957.1084-3957.1117" + cell $eq $eq$ls180.v:3957$504 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -96139,10 +96135,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:3961$505_Y + connect \Y $eq$ls180.v:3957$504_Y end - attribute \src "ls180.v:3961.1166-3961.1199" - cell $eq $eq$ls180.v:3961$513 + attribute \src "ls180.v:3957.1166-3957.1199" + cell $eq $eq$ls180.v:3957$512 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -96150,10 +96146,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:3961$513_Y + connect \Y $eq$ls180.v:3957$512_Y end - attribute \src "ls180.v:3961.1205-3961.1245" - cell $eq $eq$ls180.v:3961$514 + attribute \src "ls180.v:3957.1205-3957.1245" + cell $eq $eq$ls180.v:3957$513 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -96161,10 +96157,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 2'11 - connect \Y $eq$ls180.v:3961$514_Y + connect \Y $eq$ls180.v:3957$513_Y end - attribute \src "ls180.v:3961.1308-3961.1341" - cell $eq $eq$ls180.v:3961$515 + attribute \src "ls180.v:3957.1308-3957.1341" + cell $eq $eq$ls180.v:3957$514 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -96172,10 +96168,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:3961$515_Y + connect \Y $eq$ls180.v:3957$514_Y end - attribute \src "ls180.v:3961.1383-3961.1416" - cell $eq $eq$ls180.v:3961$518 + attribute \src "ls180.v:3957.1383-3957.1416" + cell $eq $eq$ls180.v:3957$517 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -96183,10 +96179,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:3961$518_Y + connect \Y $eq$ls180.v:3957$517_Y end - attribute \src "ls180.v:3961.1458-3961.1491" - cell $eq $eq$ls180.v:3961$521 + attribute \src "ls180.v:3957.1458-3957.1491" + cell $eq $eq$ls180.v:3957$520 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -96194,10 +96190,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:3961$521_Y + connect \Y $eq$ls180.v:3957$520_Y end - attribute \src "ls180.v:4020.29-4020.57" - cell $eq $eq$ls180.v:4020$534 + attribute \src "ls180.v:4016.29-4016.57" + cell $eq $eq$ls180.v:4016$533 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -96205,10 +96201,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_litedram_wb_sel connect \B 1'0 - connect \Y $eq$ls180.v:4020$534_Y + connect \Y $eq$ls180.v:4016$533_Y end - attribute \src "ls180.v:4027.11-4027.41" - cell $eq $eq$ls180.v:4027$539 + attribute \src "ls180.v:4023.11-4023.41" + cell $eq $eq$ls180.v:4023$538 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -96216,43 +96212,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_converter_counter connect \B 1'1 - connect \Y $eq$ls180.v:4027$539_Y + connect \Y $eq$ls180.v:4023$538_Y end - attribute \src "ls180.v:4184.36-4184.111" - cell $eq $eq$ls180.v:4184$604 + attribute \src "ls180.v:4180.36-4180.111" + cell $eq $eq$ls180.v:4180$603 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 parameter \B_WIDTH 16 parameter \Y_WIDTH 1 connect \A \main_spi_master_clk_divider1 - connect \B $sub$ls180.v:4184$603_Y - connect \Y $eq$ls180.v:4184$604_Y + connect \B $sub$ls180.v:4180$602_Y + connect \Y $eq$ls180.v:4180$603_Y end - attribute \src "ls180.v:4185.36-4185.105" - cell $eq $eq$ls180.v:4185$606 + attribute \src "ls180.v:4181.36-4181.105" + cell $eq $eq$ls180.v:4181$605 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 parameter \B_WIDTH 16 parameter \Y_WIDTH 1 connect \A \main_spi_master_clk_divider1 - connect \B $sub$ls180.v:4185$605_Y - connect \Y $eq$ls180.v:4185$606_Y + connect \B $sub$ls180.v:4181$604_Y + connect \Y $eq$ls180.v:4181$605_Y end - attribute \src "ls180.v:4212.10-4212.67" - cell $eq $eq$ls180.v:4212$610 + attribute \src "ls180.v:4208.10-4208.67" + cell $eq $eq$ls180.v:4208$609 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \main_spi_master_count - connect \B $sub$ls180.v:4212$609_Y - connect \Y $eq$ls180.v:4212$610_Y + connect \B $sub$ls180.v:4208$608_Y + connect \Y $eq$ls180.v:4208$609_Y end - attribute \src "ls180.v:4312.10-4312.40" - cell $eq $eq$ls180.v:4312$637 + attribute \src "ls180.v:4308.10-4308.40" + cell $eq $eq$ls180.v:4308$636 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -96260,10 +96256,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_init_count connect \B 7'1001111 - connect \Y $eq$ls180.v:4312$637_Y + connect \Y $eq$ls180.v:4308$636_Y end - attribute \src "ls180.v:4369.10-4369.39" - cell $eq $eq$ls180.v:4369$640 + attribute \src "ls180.v:4365.10-4365.39" + cell $eq $eq$ls180.v:4365$639 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -96271,10 +96267,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdw_count connect \B 3'111 - connect \Y $eq$ls180.v:4369$640_Y + connect \Y $eq$ls180.v:4365$639_Y end - attribute \src "ls180.v:4386.10-4386.39" - cell $eq $eq$ls180.v:4386$642 + attribute \src "ls180.v:4382.10-4382.39" + cell $eq $eq$ls180.v:4382$641 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -96282,10 +96278,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdw_count connect \B 3'111 - connect \Y $eq$ls180.v:4386$642_Y + connect \Y $eq$ls180.v:4382$641_Y end - attribute \src "ls180.v:4414.38-4414.88" - cell $eq $eq$ls180.v:4414$644 + attribute \src "ls180.v:4410.38-4410.88" + cell $eq $eq$ls180.v:4410$643 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -96293,10 +96289,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i connect \B 1'0 - connect \Y $eq$ls180.v:4414$644_Y + connect \Y $eq$ls180.v:4410$643_Y end - attribute \src "ls180.v:4464.9-4464.40" - cell $eq $eq$ls180.v:4464$654 + attribute \src "ls180.v:4460.9-4460.40" + cell $eq $eq$ls180.v:4460$653 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -96304,21 +96300,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_timeout connect \B 1'0 - connect \Y $eq$ls180.v:4464$654_Y + connect \Y $eq$ls180.v:4460$653_Y end - attribute \src "ls180.v:4473.36-4473.105" - cell $eq $eq$ls180.v:4473$656 + attribute \src "ls180.v:4469.36-4469.105" + cell $eq $eq$ls180.v:4469$655 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_count - connect \B $sub$ls180.v:4473$655_Y - connect \Y $eq$ls180.v:4473$656_Y + connect \B $sub$ls180.v:4469$654_Y + connect \Y $eq$ls180.v:4469$655_Y end - attribute \src "ls180.v:4492.9-4492.40" - cell $eq $eq$ls180.v:4492$660 + attribute \src "ls180.v:4488.9-4488.40" + cell $eq $eq$ls180.v:4488$659 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -96326,10 +96322,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_timeout connect \B 1'0 - connect \Y $eq$ls180.v:4492$660_Y + connect \Y $eq$ls180.v:4488$659_Y end - attribute \src "ls180.v:4504.10-4504.39" - cell $eq $eq$ls180.v:4504$662 + attribute \src "ls180.v:4500.10-4500.39" + cell $eq $eq$ls180.v:4500$661 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -96337,10 +96333,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_count connect \B 3'111 - connect \Y $eq$ls180.v:4504$662_Y + connect \Y $eq$ls180.v:4500$661_Y end - attribute \src "ls180.v:4541.39-4541.94" - cell $eq $eq$ls180.v:4541$666 + attribute \src "ls180.v:4537.39-4537.94" + cell $eq $eq$ls180.v:4537$665 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -96348,10 +96344,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_pads_in_payload_data_i [0] connect \B 1'0 - connect \Y $eq$ls180.v:4541$666_Y + connect \Y $eq$ls180.v:4537$665_Y end - attribute \src "ls180.v:4578.32-4578.89" - cell $eq $eq$ls180.v:4578$675 + attribute \src "ls180.v:4574.32-4574.89" + cell $eq $eq$ls180.v:4574$674 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -96359,10 +96355,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_source_source_payload_data0 connect \B 3'101 - connect \Y $eq$ls180.v:4578$675_Y + connect \Y $eq$ls180.v:4574$674_Y end - attribute \src "ls180.v:4626.10-4626.40" - cell $eq $eq$ls180.v:4626$679 + attribute \src "ls180.v:4622.10-4622.40" + cell $eq $eq$ls180.v:4622$678 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -96370,10 +96366,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_count connect \B 1'1 - connect \Y $eq$ls180.v:4626$679_Y + connect \Y $eq$ls180.v:4622$678_Y end - attribute \src "ls180.v:4675.40-4675.98" - cell $eq $eq$ls180.v:4675$681 + attribute \src "ls180.v:4671.40-4671.98" + cell $eq $eq$ls180.v:4671$680 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -96381,10 +96377,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_pads_in_payload_data_i connect \B 1'0 - connect \Y $eq$ls180.v:4675$681_Y + connect \Y $eq$ls180.v:4671$680_Y end - attribute \src "ls180.v:4726.9-4726.41" - cell $eq $eq$ls180.v:4726$691 + attribute \src "ls180.v:4722.9-4722.41" + cell $eq $eq$ls180.v:4722$690 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -96392,21 +96388,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_timeout connect \B 1'0 - connect \Y $eq$ls180.v:4726$691_Y + connect \Y $eq$ls180.v:4722$690_Y end - attribute \src "ls180.v:4735.37-4735.123" - cell $eq $eq$ls180.v:4735$694 + attribute \src "ls180.v:4731.37-4731.123" + cell $eq $eq$ls180.v:4731$693 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 10 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_count - connect \B $sub$ls180.v:4735$693_Y - connect \Y $eq$ls180.v:4735$694_Y + connect \B $sub$ls180.v:4731$692_Y + connect \Y $eq$ls180.v:4731$693_Y end - attribute \src "ls180.v:4758.9-4758.41" - cell $eq $eq$ls180.v:4758$697 + attribute \src "ls180.v:4754.9-4754.41" + cell $eq $eq$ls180.v:4754$696 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -96414,10 +96410,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_timeout connect \B 1'0 - connect \Y $eq$ls180.v:4758$697_Y + connect \Y $eq$ls180.v:4754$696_Y end - attribute \src "ls180.v:4768.10-4768.41" - cell $eq $eq$ls180.v:4768$699 + attribute \src "ls180.v:4764.10-4764.41" + cell $eq $eq$ls180.v:4764$698 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -96425,10 +96421,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_count connect \B 6'100111 - connect \Y $eq$ls180.v:4768$699_Y + connect \Y $eq$ls180.v:4764$698_Y end - attribute \src "ls180.v:4937.9-4937.47" - cell $eq $eq$ls180.v:4937$881 + attribute \src "ls180.v:4933.9-4933.47" + cell $eq $eq$ls180.v:4933$880 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -96436,10 +96432,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_cnt connect \B 3'111 - connect \Y $eq$ls180.v:4937$881_Y + connect \Y $eq$ls180.v:4933$880_Y end - attribute \src "ls180.v:4967.10-4967.48" - cell $eq $eq$ls180.v:4967$882 + attribute \src "ls180.v:4963.10-4963.48" + cell $eq $eq$ls180.v:4963$881 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -96447,10 +96443,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_cnt connect \B 3'111 - connect \Y $eq$ls180.v:4967$882_Y + connect \Y $eq$ls180.v:4963$881_Y end - attribute \src "ls180.v:4998.10-4998.78" - cell $eq $eq$ls180.v:4998$887 + attribute \src "ls180.v:4994.10-4994.78" + cell $eq $eq$ls180.v:4994$886 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -96458,10 +96454,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_fifo0 connect \B \main_sdcore_crc16_checker_crctmp0 - connect \Y $eq$ls180.v:4998$887_Y + connect \Y $eq$ls180.v:4994$886_Y end - attribute \src "ls180.v:4998.83-4998.151" - cell $eq $eq$ls180.v:4998$888 + attribute \src "ls180.v:4994.83-4994.151" + cell $eq $eq$ls180.v:4994$887 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -96469,10 +96465,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_fifo1 connect \B \main_sdcore_crc16_checker_crctmp1 - connect \Y $eq$ls180.v:4998$888_Y + connect \Y $eq$ls180.v:4994$887_Y end - attribute \src "ls180.v:4998.157-4998.225" - cell $eq $eq$ls180.v:4998$890 + attribute \src "ls180.v:4994.157-4994.225" + cell $eq $eq$ls180.v:4994$889 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -96480,10 +96476,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_fifo2 connect \B \main_sdcore_crc16_checker_crctmp2 - connect \Y $eq$ls180.v:4998$890_Y + connect \Y $eq$ls180.v:4994$889_Y end - attribute \src "ls180.v:4998.231-4998.299" - cell $eq $eq$ls180.v:4998$892 + attribute \src "ls180.v:4994.231-4994.299" + cell $eq $eq$ls180.v:4994$891 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -96491,10 +96487,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_fifo3 connect \B \main_sdcore_crc16_checker_crctmp3 - connect \Y $eq$ls180.v:4998$892_Y + connect \Y $eq$ls180.v:4994$891_Y end - attribute \src "ls180.v:5006.7-5006.44" - cell $eq $eq$ls180.v:5006$896 + attribute \src "ls180.v:5002.7-5002.44" + cell $eq $eq$ls180.v:5002$895 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -96502,10 +96498,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_cnt connect \B 3'111 - connect \Y $eq$ls180.v:5006$896_Y + connect \Y $eq$ls180.v:5002$895_Y end - attribute \src "ls180.v:5016.7-5016.44" - cell $eq $eq$ls180.v:5016$899 + attribute \src "ls180.v:5012.7-5012.44" + cell $eq $eq$ls180.v:5012$898 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -96513,10 +96509,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_cnt connect \B 3'111 - connect \Y $eq$ls180.v:5016$899_Y + connect \Y $eq$ls180.v:5012$898_Y end - attribute \src "ls180.v:5026.7-5026.44" - cell $eq $eq$ls180.v:5026$902 + attribute \src "ls180.v:5022.7-5022.44" + cell $eq $eq$ls180.v:5022$901 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -96524,10 +96520,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_cnt connect \B 3'111 - connect \Y $eq$ls180.v:5026$902_Y + connect \Y $eq$ls180.v:5022$901_Y end - attribute \src "ls180.v:5036.7-5036.44" - cell $eq $eq$ls180.v:5036$905 + attribute \src "ls180.v:5032.7-5032.44" + cell $eq $eq$ls180.v:5032$904 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -96535,10 +96531,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_cnt connect \B 3'111 - connect \Y $eq$ls180.v:5036$905_Y + connect \Y $eq$ls180.v:5032$904_Y end - attribute \src "ls180.v:5160.36-5160.64" - cell $eq $eq$ls180.v:5160$956 + attribute \src "ls180.v:5156.36-5156.64" + cell $eq $eq$ls180.v:5156$955 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -96546,10 +96542,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_cmd_type connect \B 1'0 - connect \Y $eq$ls180.v:5160$956_Y + connect \Y $eq$ls180.v:5156$955_Y end - attribute \src "ls180.v:5166.10-5166.39" - cell $eq $eq$ls180.v:5166$959 + attribute \src "ls180.v:5162.10-5162.39" + cell $eq $eq$ls180.v:5162$958 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -96557,10 +96553,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_cmd_count connect \B 3'101 - connect \Y $eq$ls180.v:5166$959_Y + connect \Y $eq$ls180.v:5162$958_Y end - attribute \src "ls180.v:5167.11-5167.39" - cell $eq $eq$ls180.v:5167$960 + attribute \src "ls180.v:5163.11-5163.39" + cell $eq $eq$ls180.v:5163$959 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -96568,10 +96564,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_cmd_type connect \B 1'0 - connect \Y $eq$ls180.v:5167$960_Y + connect \Y $eq$ls180.v:5163$959_Y end - attribute \src "ls180.v:5179.34-5179.63" - cell $eq $eq$ls180.v:5179$961 + attribute \src "ls180.v:5175.34-5175.63" + cell $eq $eq$ls180.v:5175$960 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -96579,10 +96575,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_data_type connect \B 1'0 - connect \Y $eq$ls180.v:5179$961_Y + connect \Y $eq$ls180.v:5175$960_Y end - attribute \src "ls180.v:5180.9-5180.37" - cell $eq $eq$ls180.v:5180$962 + attribute \src "ls180.v:5176.9-5176.37" + cell $eq $eq$ls180.v:5176$961 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -96590,10 +96586,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_cmd_type connect \B 2'10 - connect \Y $eq$ls180.v:5180$962_Y + connect \Y $eq$ls180.v:5176$961_Y end - attribute \src "ls180.v:5187.10-5187.55" - cell $eq $eq$ls180.v:5187$963 + attribute \src "ls180.v:5183.10-5183.55" + cell $eq $eq$ls180.v:5183$962 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -96601,10 +96597,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_source_payload_status connect \B 1'1 - connect \Y $eq$ls180.v:5187$963_Y + connect \Y $eq$ls180.v:5183$962_Y end - attribute \src "ls180.v:5193.12-5193.41" - cell $eq $eq$ls180.v:5193$964 + attribute \src "ls180.v:5189.12-5189.41" + cell $eq $eq$ls180.v:5189$963 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -96612,10 +96608,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_data_type connect \B 2'10 - connect \Y $eq$ls180.v:5193$964_Y + connect \Y $eq$ls180.v:5189$963_Y end - attribute \src "ls180.v:5196.13-5196.42" - cell $eq $eq$ls180.v:5196$965 + attribute \src "ls180.v:5192.13-5192.42" + cell $eq $eq$ls180.v:5192$964 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -96623,32 +96619,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_data_type connect \B 1'1 - connect \Y $eq$ls180.v:5196$965_Y + connect \Y $eq$ls180.v:5192$964_Y end - attribute \src "ls180.v:5218.10-5218.76" - cell $eq $eq$ls180.v:5218$970 + attribute \src "ls180.v:5214.10-5214.76" + cell $eq $eq$ls180.v:5214$969 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 1 connect \A \main_sdcore_data_count - connect \B $sub$ls180.v:5218$969_Y - connect \Y $eq$ls180.v:5218$970_Y + connect \B $sub$ls180.v:5214$968_Y + connect \Y $eq$ls180.v:5214$969_Y end - attribute \src "ls180.v:5233.35-5233.101" - cell $eq $eq$ls180.v:5233$973 + attribute \src "ls180.v:5229.35-5229.101" + cell $eq $eq$ls180.v:5229$972 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 1 connect \A \main_sdcore_data_count - connect \B $sub$ls180.v:5233$972_Y - connect \Y $eq$ls180.v:5233$973_Y + connect \B $sub$ls180.v:5229$971_Y + connect \Y $eq$ls180.v:5229$972_Y end - attribute \src "ls180.v:5235.10-5235.56" - cell $eq $eq$ls180.v:5235$974 + attribute \src "ls180.v:5231.10-5231.56" + cell $eq $eq$ls180.v:5231$973 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -96656,21 +96652,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_source_payload_status connect \B 1'0 - connect \Y $eq$ls180.v:5235$974_Y + connect \Y $eq$ls180.v:5231$973_Y end - attribute \src "ls180.v:5244.12-5244.78" - cell $eq $eq$ls180.v:5244$978 + attribute \src "ls180.v:5240.12-5240.78" + cell $eq $eq$ls180.v:5240$977 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 1 connect \A \main_sdcore_data_count - connect \B $sub$ls180.v:5244$977_Y - connect \Y $eq$ls180.v:5244$978_Y + connect \B $sub$ls180.v:5240$976_Y + connect \Y $eq$ls180.v:5240$977_Y end - attribute \src "ls180.v:5251.11-5251.57" - cell $eq $eq$ls180.v:5251$979 + attribute \src "ls180.v:5247.11-5247.57" + cell $eq $eq$ls180.v:5247$978 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -96678,32 +96674,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_source_payload_status connect \B 1'1 - connect \Y $eq$ls180.v:5251$979_Y + connect \Y $eq$ls180.v:5247$978_Y end - attribute \src "ls180.v:5368.10-5368.105" - cell $eq $eq$ls180.v:5368$996 + attribute \src "ls180.v:5364.10-5364.105" + cell $eq $eq$ls180.v:5364$995 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_wishbonedmawriter_offset - connect \B $sub$ls180.v:5368$995_Y - connect \Y $eq$ls180.v:5368$996_Y + connect \B $sub$ls180.v:5364$994_Y + connect \Y $eq$ls180.v:5364$995_Y end - attribute \src "ls180.v:5458.39-5458.106" - cell $eq $eq$ls180.v:5458$1002 + attribute \src "ls180.v:5454.39-5454.106" + cell $eq $eq$ls180.v:5454$1001 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_dma_offset - connect \B $sub$ls180.v:5458$1001_Y - connect \Y $eq$ls180.v:5458$1002_Y + connect \B $sub$ls180.v:5454$1000_Y + connect \Y $eq$ls180.v:5454$1001_Y end - attribute \src "ls180.v:5488.44-5488.82" - cell $eq $eq$ls180.v:5488$1005 + attribute \src "ls180.v:5484.44-5484.82" + cell $eq $eq$ls180.v:5484$1004 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -96711,10 +96707,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_converter_mux connect \B 1'0 - connect \Y $eq$ls180.v:5488$1005_Y + connect \Y $eq$ls180.v:5484$1004_Y end - attribute \src "ls180.v:5489.43-5489.81" - cell $eq $eq$ls180.v:5489$1006 + attribute \src "ls180.v:5485.43-5485.81" + cell $eq $eq$ls180.v:5485$1005 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -96722,43 +96718,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_converter_mux connect \B 2'11 - connect \Y $eq$ls180.v:5489$1006_Y + connect \Y $eq$ls180.v:5485$1005_Y end - attribute \src "ls180.v:5546.32-5546.99" - cell $eq $eq$ls180.v:5546$1019 + attribute \src "ls180.v:5542.32-5542.99" + cell $eq $eq$ls180.v:5542$1018 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 parameter \B_WIDTH 16 parameter \Y_WIDTH 1 connect \A \libresocsim_clk_divider1 - connect \B $sub$ls180.v:5546$1018_Y - connect \Y $eq$ls180.v:5546$1019_Y + connect \B $sub$ls180.v:5542$1017_Y + connect \Y $eq$ls180.v:5542$1018_Y end - attribute \src "ls180.v:5547.32-5547.93" - cell $eq $eq$ls180.v:5547$1021 + attribute \src "ls180.v:5543.32-5543.93" + cell $eq $eq$ls180.v:5543$1020 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 parameter \B_WIDTH 16 parameter \Y_WIDTH 1 connect \A \libresocsim_clk_divider1 - connect \B $sub$ls180.v:5547$1020_Y - connect \Y $eq$ls180.v:5547$1021_Y + connect \B $sub$ls180.v:5543$1019_Y + connect \Y $eq$ls180.v:5543$1020_Y end - attribute \src "ls180.v:5575.10-5575.59" - cell $eq $eq$ls180.v:5575$1025 + attribute \src "ls180.v:5571.10-5571.59" + cell $eq $eq$ls180.v:5571$1024 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \libresocsim_count - connect \B $sub$ls180.v:5575$1024_Y - connect \Y $eq$ls180.v:5575$1025_Y + connect \B $sub$ls180.v:5571$1023_Y + connect \Y $eq$ls180.v:5571$1024_Y end - attribute \src "ls180.v:5648.85-5648.106" - cell $eq $eq$ls180.v:5648$1030 + attribute \src "ls180.v:5644.85-5644.106" + cell $eq $eq$ls180.v:5644$1029 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -96766,10 +96762,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 1'0 - connect \Y $eq$ls180.v:5648$1030_Y + connect \Y $eq$ls180.v:5644$1029_Y end - attribute \src "ls180.v:5649.85-5649.106" - cell $eq $eq$ls180.v:5649$1032 + attribute \src "ls180.v:5645.85-5645.106" + cell $eq $eq$ls180.v:5645$1031 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -96777,10 +96773,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 1'1 - connect \Y $eq$ls180.v:5649$1032_Y + connect \Y $eq$ls180.v:5645$1031_Y end - attribute \src "ls180.v:5650.85-5650.106" - cell $eq $eq$ls180.v:5650$1034 + attribute \src "ls180.v:5646.85-5646.106" + cell $eq $eq$ls180.v:5646$1033 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -96788,10 +96784,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 2'10 - connect \Y $eq$ls180.v:5650$1034_Y + connect \Y $eq$ls180.v:5646$1033_Y end - attribute \src "ls180.v:5651.57-5651.78" - cell $eq $eq$ls180.v:5651$1036 + attribute \src "ls180.v:5647.57-5647.78" + cell $eq $eq$ls180.v:5647$1035 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -96799,10 +96795,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 2'11 - connect \Y $eq$ls180.v:5651$1036_Y + connect \Y $eq$ls180.v:5647$1035_Y end - attribute \src "ls180.v:5652.57-5652.78" - cell $eq $eq$ls180.v:5652$1038 + attribute \src "ls180.v:5648.57-5648.78" + cell $eq $eq$ls180.v:5648$1037 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -96810,10 +96806,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 3'100 - connect \Y $eq$ls180.v:5652$1038_Y + connect \Y $eq$ls180.v:5648$1037_Y end - attribute \src "ls180.v:5653.85-5653.106" - cell $eq $eq$ls180.v:5653$1040 + attribute \src "ls180.v:5649.85-5649.106" + cell $eq $eq$ls180.v:5649$1039 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -96821,10 +96817,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 1'0 - connect \Y $eq$ls180.v:5653$1040_Y + connect \Y $eq$ls180.v:5649$1039_Y end - attribute \src "ls180.v:5654.85-5654.106" - cell $eq $eq$ls180.v:5654$1042 + attribute \src "ls180.v:5650.85-5650.106" + cell $eq $eq$ls180.v:5650$1041 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -96832,10 +96828,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 1'1 - connect \Y $eq$ls180.v:5654$1042_Y + connect \Y $eq$ls180.v:5650$1041_Y end - attribute \src "ls180.v:5655.85-5655.106" - cell $eq $eq$ls180.v:5655$1044 + attribute \src "ls180.v:5651.85-5651.106" + cell $eq $eq$ls180.v:5651$1043 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -96843,10 +96839,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 2'10 - connect \Y $eq$ls180.v:5655$1044_Y + connect \Y $eq$ls180.v:5651$1043_Y end - attribute \src "ls180.v:5656.57-5656.78" - cell $eq $eq$ls180.v:5656$1046 + attribute \src "ls180.v:5652.57-5652.78" + cell $eq $eq$ls180.v:5652$1045 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -96854,10 +96850,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 2'11 - connect \Y $eq$ls180.v:5656$1046_Y + connect \Y $eq$ls180.v:5652$1045_Y end - attribute \src "ls180.v:5657.57-5657.78" - cell $eq $eq$ls180.v:5657$1048 + attribute \src "ls180.v:5653.57-5653.78" + cell $eq $eq$ls180.v:5653$1047 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -96865,10 +96861,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 3'100 - connect \Y $eq$ls180.v:5657$1048_Y + connect \Y $eq$ls180.v:5653$1047_Y end - attribute \src "ls180.v:5661.27-5661.59" - cell $eq $eq$ls180.v:5661$1051 + attribute \src "ls180.v:5657.27-5657.59" + cell $eq $eq$ls180.v:5657$1050 parameter \A_SIGNED 0 parameter \A_WIDTH 23 parameter \B_SIGNED 0 @@ -96876,10 +96872,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_adr [29:7] connect \B 1'0 - connect \Y $eq$ls180.v:5661$1051_Y + connect \Y $eq$ls180.v:5657$1050_Y end - attribute \src "ls180.v:5662.27-5662.68" - cell $eq $eq$ls180.v:5662$1052 + attribute \src "ls180.v:5658.27-5658.68" + cell $eq $eq$ls180.v:5658$1051 parameter \A_SIGNED 0 parameter \A_WIDTH 27 parameter \B_SIGNED 0 @@ -96887,10 +96883,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_adr [29:3] connect \B 27'110000000000000100000000000 - connect \Y $eq$ls180.v:5662$1052_Y + connect \Y $eq$ls180.v:5658$1051_Y end - attribute \src "ls180.v:5663.27-5663.66" - cell $eq $eq$ls180.v:5663$1053 + attribute \src "ls180.v:5659.27-5659.66" + cell $eq $eq$ls180.v:5659$1052 parameter \A_SIGNED 0 parameter \A_WIDTH 20 parameter \B_SIGNED 0 @@ -96898,10 +96894,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_adr [29:10] connect \B 20'11000000000000010001 - connect \Y $eq$ls180.v:5663$1053_Y + connect \Y $eq$ls180.v:5659$1052_Y end - attribute \src "ls180.v:5664.27-5664.61" - cell $eq $eq$ls180.v:5664$1054 + attribute \src "ls180.v:5660.27-5660.61" + cell $eq $eq$ls180.v:5660$1053 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -96909,10 +96905,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_adr [29:23] connect \B 7'1001000 - connect \Y $eq$ls180.v:5664$1054_Y + connect \Y $eq$ls180.v:5660$1053_Y end - attribute \src "ls180.v:5665.27-5665.65" - cell $eq $eq$ls180.v:5665$1055 + attribute \src "ls180.v:5661.27-5661.65" + cell $eq $eq$ls180.v:5661$1054 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -96920,10 +96916,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_adr [29:14] connect \B 16'1100000000000000 - connect \Y $eq$ls180.v:5665$1055_Y + connect \Y $eq$ls180.v:5661$1054_Y end - attribute \src "ls180.v:5721.24-5721.45" - cell $eq $eq$ls180.v:5721$1082 + attribute \src "ls180.v:5717.24-5717.45" + cell $eq $eq$ls180.v:5717$1081 parameter \A_SIGNED 0 parameter \A_WIDTH 20 parameter \B_SIGNED 0 @@ -96931,10 +96927,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_count connect \B 1'0 - connect \Y $eq$ls180.v:5721$1082_Y + connect \Y $eq$ls180.v:5717$1081_Y end - attribute \src "ls180.v:5722.32-5722.77" - cell $eq $eq$ls180.v:5722$1083 + attribute \src "ls180.v:5718.32-5718.77" + cell $eq $eq$ls180.v:5718$1082 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -96942,10 +96938,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [13:9] connect \B 1'0 - connect \Y $eq$ls180.v:5722$1083_Y + connect \Y $eq$ls180.v:5718$1082_Y end - attribute \src "ls180.v:5724.97-5724.141" - cell $eq $eq$ls180.v:5724$1085 + attribute \src "ls180.v:5720.97-5720.141" + cell $eq $eq$ls180.v:5720$1084 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -96953,10 +96949,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:5724$1085_Y + connect \Y $eq$ls180.v:5720$1084_Y end - attribute \src "ls180.v:5725.100-5725.144" - cell $eq $eq$ls180.v:5725$1089 + attribute \src "ls180.v:5721.100-5721.144" + cell $eq $eq$ls180.v:5721$1088 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -96964,10 +96960,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:5725$1089_Y + connect \Y $eq$ls180.v:5721$1088_Y end - attribute \src "ls180.v:5727.99-5727.143" - cell $eq $eq$ls180.v:5727$1092 + attribute \src "ls180.v:5723.99-5723.143" + cell $eq $eq$ls180.v:5723$1091 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -96975,10 +96971,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:5727$1092_Y + connect \Y $eq$ls180.v:5723$1091_Y end - attribute \src "ls180.v:5728.102-5728.146" - cell $eq $eq$ls180.v:5728$1096 + attribute \src "ls180.v:5724.102-5724.146" + cell $eq $eq$ls180.v:5724$1095 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -96986,10 +96982,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:5728$1096_Y + connect \Y $eq$ls180.v:5724$1095_Y end - attribute \src "ls180.v:5730.99-5730.143" - cell $eq $eq$ls180.v:5730$1099 + attribute \src "ls180.v:5726.99-5726.143" + cell $eq $eq$ls180.v:5726$1098 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -96997,10 +96993,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:5730$1099_Y + connect \Y $eq$ls180.v:5726$1098_Y end - attribute \src "ls180.v:5731.102-5731.146" - cell $eq $eq$ls180.v:5731$1103 + attribute \src "ls180.v:5727.102-5727.146" + cell $eq $eq$ls180.v:5727$1102 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97008,10 +97004,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:5731$1103_Y + connect \Y $eq$ls180.v:5727$1102_Y end - attribute \src "ls180.v:5733.99-5733.143" - cell $eq $eq$ls180.v:5733$1106 + attribute \src "ls180.v:5729.99-5729.143" + cell $eq $eq$ls180.v:5729$1105 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97019,10 +97015,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:5733$1106_Y + connect \Y $eq$ls180.v:5729$1105_Y end - attribute \src "ls180.v:5734.102-5734.146" - cell $eq $eq$ls180.v:5734$1110 + attribute \src "ls180.v:5730.102-5730.146" + cell $eq $eq$ls180.v:5730$1109 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97030,10 +97026,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:5734$1110_Y + connect \Y $eq$ls180.v:5730$1109_Y end - attribute \src "ls180.v:5736.99-5736.143" - cell $eq $eq$ls180.v:5736$1113 + attribute \src "ls180.v:5732.99-5732.143" + cell $eq $eq$ls180.v:5732$1112 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97041,10 +97037,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:5736$1113_Y + connect \Y $eq$ls180.v:5732$1112_Y end - attribute \src "ls180.v:5737.102-5737.146" - cell $eq $eq$ls180.v:5737$1117 + attribute \src "ls180.v:5733.102-5733.146" + cell $eq $eq$ls180.v:5733$1116 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97052,10 +97048,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:5737$1117_Y + connect \Y $eq$ls180.v:5733$1116_Y end - attribute \src "ls180.v:5739.102-5739.146" - cell $eq $eq$ls180.v:5739$1120 + attribute \src "ls180.v:5735.102-5735.146" + cell $eq $eq$ls180.v:5735$1119 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97063,10 +97059,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:5739$1120_Y + connect \Y $eq$ls180.v:5735$1119_Y end - attribute \src "ls180.v:5740.105-5740.149" - cell $eq $eq$ls180.v:5740$1124 + attribute \src "ls180.v:5736.105-5736.149" + cell $eq $eq$ls180.v:5736$1123 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97074,10 +97070,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:5740$1124_Y + connect \Y $eq$ls180.v:5736$1123_Y end - attribute \src "ls180.v:5742.102-5742.146" - cell $eq $eq$ls180.v:5742$1127 + attribute \src "ls180.v:5738.102-5738.146" + cell $eq $eq$ls180.v:5738$1126 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97085,10 +97081,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:5742$1127_Y + connect \Y $eq$ls180.v:5738$1126_Y end - attribute \src "ls180.v:5743.105-5743.149" - cell $eq $eq$ls180.v:5743$1131 + attribute \src "ls180.v:5739.105-5739.149" + cell $eq $eq$ls180.v:5739$1130 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97096,10 +97092,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:5743$1131_Y + connect \Y $eq$ls180.v:5739$1130_Y end - attribute \src "ls180.v:5745.102-5745.146" - cell $eq $eq$ls180.v:5745$1134 + attribute \src "ls180.v:5741.102-5741.146" + cell $eq $eq$ls180.v:5741$1133 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97107,10 +97103,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:5745$1134_Y + connect \Y $eq$ls180.v:5741$1133_Y end - attribute \src "ls180.v:5746.105-5746.149" - cell $eq $eq$ls180.v:5746$1138 + attribute \src "ls180.v:5742.105-5742.149" + cell $eq $eq$ls180.v:5742$1137 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97118,10 +97114,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:5746$1138_Y + connect \Y $eq$ls180.v:5742$1137_Y end - attribute \src "ls180.v:5748.102-5748.146" - cell $eq $eq$ls180.v:5748$1141 + attribute \src "ls180.v:5744.102-5744.146" + cell $eq $eq$ls180.v:5744$1140 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97129,10 +97125,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:5748$1141_Y + connect \Y $eq$ls180.v:5744$1140_Y end - attribute \src "ls180.v:5749.105-5749.149" - cell $eq $eq$ls180.v:5749$1145 + attribute \src "ls180.v:5745.105-5745.149" + cell $eq $eq$ls180.v:5745$1144 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97140,10 +97136,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:5749$1145_Y + connect \Y $eq$ls180.v:5745$1144_Y end - attribute \src "ls180.v:5760.32-5760.77" - cell $eq $eq$ls180.v:5760$1147 + attribute \src "ls180.v:5756.32-5756.77" + cell $eq $eq$ls180.v:5756$1146 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -97151,10 +97147,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [13:9] connect \B 3'110 - connect \Y $eq$ls180.v:5760$1147_Y + connect \Y $eq$ls180.v:5756$1146_Y end - attribute \src "ls180.v:5762.94-5762.138" - cell $eq $eq$ls180.v:5762$1149 + attribute \src "ls180.v:5758.94-5758.138" + cell $eq $eq$ls180.v:5758$1148 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -97162,10 +97158,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 1'0 - connect \Y $eq$ls180.v:5762$1149_Y + connect \Y $eq$ls180.v:5758$1148_Y end - attribute \src "ls180.v:5763.97-5763.141" - cell $eq $eq$ls180.v:5763$1153 + attribute \src "ls180.v:5759.97-5759.141" + cell $eq $eq$ls180.v:5759$1152 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -97173,10 +97169,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 1'0 - connect \Y $eq$ls180.v:5763$1153_Y + connect \Y $eq$ls180.v:5759$1152_Y end - attribute \src "ls180.v:5765.94-5765.138" - cell $eq $eq$ls180.v:5765$1156 + attribute \src "ls180.v:5761.94-5761.138" + cell $eq $eq$ls180.v:5761$1155 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -97184,10 +97180,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 1'1 - connect \Y $eq$ls180.v:5765$1156_Y + connect \Y $eq$ls180.v:5761$1155_Y end - attribute \src "ls180.v:5766.97-5766.141" - cell $eq $eq$ls180.v:5766$1160 + attribute \src "ls180.v:5762.97-5762.141" + cell $eq $eq$ls180.v:5762$1159 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -97195,10 +97191,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 1'1 - connect \Y $eq$ls180.v:5766$1160_Y + connect \Y $eq$ls180.v:5762$1159_Y end - attribute \src "ls180.v:5768.94-5768.138" - cell $eq $eq$ls180.v:5768$1163 + attribute \src "ls180.v:5764.94-5764.138" + cell $eq $eq$ls180.v:5764$1162 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -97206,10 +97202,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 2'10 - connect \Y $eq$ls180.v:5768$1163_Y + connect \Y $eq$ls180.v:5764$1162_Y end - attribute \src "ls180.v:5769.97-5769.141" - cell $eq $eq$ls180.v:5769$1167 + attribute \src "ls180.v:5765.97-5765.141" + cell $eq $eq$ls180.v:5765$1166 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -97217,10 +97213,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 2'10 - connect \Y $eq$ls180.v:5769$1167_Y + connect \Y $eq$ls180.v:5765$1166_Y end - attribute \src "ls180.v:5771.94-5771.138" - cell $eq $eq$ls180.v:5771$1170 + attribute \src "ls180.v:5767.94-5767.138" + cell $eq $eq$ls180.v:5767$1169 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -97228,10 +97224,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 2'11 - connect \Y $eq$ls180.v:5771$1170_Y + connect \Y $eq$ls180.v:5767$1169_Y end - attribute \src "ls180.v:5772.97-5772.141" - cell $eq $eq$ls180.v:5772$1174 + attribute \src "ls180.v:5768.97-5768.141" + cell $eq $eq$ls180.v:5768$1173 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -97239,10 +97235,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 2'11 - connect \Y $eq$ls180.v:5772$1174_Y + connect \Y $eq$ls180.v:5768$1173_Y end - attribute \src "ls180.v:5774.95-5774.139" - cell $eq $eq$ls180.v:5774$1177 + attribute \src "ls180.v:5770.95-5770.139" + cell $eq $eq$ls180.v:5770$1176 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -97250,10 +97246,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 3'100 - connect \Y $eq$ls180.v:5774$1177_Y + connect \Y $eq$ls180.v:5770$1176_Y end - attribute \src "ls180.v:5775.98-5775.142" - cell $eq $eq$ls180.v:5775$1181 + attribute \src "ls180.v:5771.98-5771.142" + cell $eq $eq$ls180.v:5771$1180 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -97261,10 +97257,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 3'100 - connect \Y $eq$ls180.v:5775$1181_Y + connect \Y $eq$ls180.v:5771$1180_Y end - attribute \src "ls180.v:5777.95-5777.139" - cell $eq $eq$ls180.v:5777$1184 + attribute \src "ls180.v:5773.95-5773.139" + cell $eq $eq$ls180.v:5773$1183 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -97272,10 +97268,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 3'101 - connect \Y $eq$ls180.v:5777$1184_Y + connect \Y $eq$ls180.v:5773$1183_Y end - attribute \src "ls180.v:5778.98-5778.142" - cell $eq $eq$ls180.v:5778$1188 + attribute \src "ls180.v:5774.98-5774.142" + cell $eq $eq$ls180.v:5774$1187 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -97283,10 +97279,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 3'101 - connect \Y $eq$ls180.v:5778$1188_Y + connect \Y $eq$ls180.v:5774$1187_Y end - attribute \src "ls180.v:5786.32-5786.77" - cell $eq $eq$ls180.v:5786$1190 + attribute \src "ls180.v:5782.32-5782.77" + cell $eq $eq$ls180.v:5782$1189 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -97294,10 +97290,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface2_bank_bus_adr [13:9] connect \B 4'1000 - connect \Y $eq$ls180.v:5786$1190_Y + connect \Y $eq$ls180.v:5782$1189_Y end - attribute \src "ls180.v:5788.98-5788.142" - cell $eq $eq$ls180.v:5788$1192 + attribute \src "ls180.v:5784.98-5784.142" + cell $eq $eq$ls180.v:5784$1191 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97305,10 +97301,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface2_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:5788$1192_Y + connect \Y $eq$ls180.v:5784$1191_Y end - attribute \src "ls180.v:5789.101-5789.145" - cell $eq $eq$ls180.v:5789$1196 + attribute \src "ls180.v:5785.101-5785.145" + cell $eq $eq$ls180.v:5785$1195 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97316,10 +97312,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface2_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:5789$1196_Y + connect \Y $eq$ls180.v:5785$1195_Y end - attribute \src "ls180.v:5791.97-5791.141" - cell $eq $eq$ls180.v:5791$1199 + attribute \src "ls180.v:5787.97-5787.141" + cell $eq $eq$ls180.v:5787$1198 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97327,10 +97323,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface2_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:5791$1199_Y + connect \Y $eq$ls180.v:5787$1198_Y end - attribute \src "ls180.v:5792.100-5792.144" - cell $eq $eq$ls180.v:5792$1203 + attribute \src "ls180.v:5788.100-5788.144" + cell $eq $eq$ls180.v:5788$1202 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97338,10 +97334,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface2_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:5792$1203_Y + connect \Y $eq$ls180.v:5788$1202_Y end - attribute \src "ls180.v:5794.97-5794.141" - cell $eq $eq$ls180.v:5794$1206 + attribute \src "ls180.v:5790.97-5790.141" + cell $eq $eq$ls180.v:5790$1205 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97349,10 +97345,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface2_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:5794$1206_Y + connect \Y $eq$ls180.v:5790$1205_Y end - attribute \src "ls180.v:5795.100-5795.144" - cell $eq $eq$ls180.v:5795$1210 + attribute \src "ls180.v:5791.100-5791.144" + cell $eq $eq$ls180.v:5791$1209 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97360,10 +97356,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface2_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:5795$1210_Y + connect \Y $eq$ls180.v:5791$1209_Y end - attribute \src "ls180.v:5797.97-5797.141" - cell $eq $eq$ls180.v:5797$1213 + attribute \src "ls180.v:5793.97-5793.141" + cell $eq $eq$ls180.v:5793$1212 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97371,10 +97367,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface2_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:5797$1213_Y + connect \Y $eq$ls180.v:5793$1212_Y end - attribute \src "ls180.v:5798.100-5798.144" - cell $eq $eq$ls180.v:5798$1217 + attribute \src "ls180.v:5794.100-5794.144" + cell $eq $eq$ls180.v:5794$1216 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97382,10 +97378,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface2_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:5798$1217_Y + connect \Y $eq$ls180.v:5794$1216_Y end - attribute \src "ls180.v:5800.97-5800.141" - cell $eq $eq$ls180.v:5800$1220 + attribute \src "ls180.v:5796.97-5796.141" + cell $eq $eq$ls180.v:5796$1219 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97393,10 +97389,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface2_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:5800$1220_Y + connect \Y $eq$ls180.v:5796$1219_Y end - attribute \src "ls180.v:5801.100-5801.144" - cell $eq $eq$ls180.v:5801$1224 + attribute \src "ls180.v:5797.100-5797.144" + cell $eq $eq$ls180.v:5797$1223 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97404,10 +97400,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface2_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:5801$1224_Y + connect \Y $eq$ls180.v:5797$1223_Y end - attribute \src "ls180.v:5803.98-5803.142" - cell $eq $eq$ls180.v:5803$1227 + attribute \src "ls180.v:5799.98-5799.142" + cell $eq $eq$ls180.v:5799$1226 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97415,10 +97411,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface2_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:5803$1227_Y + connect \Y $eq$ls180.v:5799$1226_Y end - attribute \src "ls180.v:5804.101-5804.145" - cell $eq $eq$ls180.v:5804$1231 + attribute \src "ls180.v:5800.101-5800.145" + cell $eq $eq$ls180.v:5800$1230 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97426,10 +97422,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface2_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:5804$1231_Y + connect \Y $eq$ls180.v:5800$1230_Y end - attribute \src "ls180.v:5806.98-5806.142" - cell $eq $eq$ls180.v:5806$1234 + attribute \src "ls180.v:5802.98-5802.142" + cell $eq $eq$ls180.v:5802$1233 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97437,10 +97433,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface2_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:5806$1234_Y + connect \Y $eq$ls180.v:5802$1233_Y end - attribute \src "ls180.v:5807.101-5807.145" - cell $eq $eq$ls180.v:5807$1238 + attribute \src "ls180.v:5803.101-5803.145" + cell $eq $eq$ls180.v:5803$1237 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97448,10 +97444,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface2_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:5807$1238_Y + connect \Y $eq$ls180.v:5803$1237_Y end - attribute \src "ls180.v:5809.98-5809.142" - cell $eq $eq$ls180.v:5809$1241 + attribute \src "ls180.v:5805.98-5805.142" + cell $eq $eq$ls180.v:5805$1240 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97459,10 +97455,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface2_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:5809$1241_Y + connect \Y $eq$ls180.v:5805$1240_Y end - attribute \src "ls180.v:5810.101-5810.145" - cell $eq $eq$ls180.v:5810$1245 + attribute \src "ls180.v:5806.101-5806.145" + cell $eq $eq$ls180.v:5806$1244 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97470,10 +97466,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface2_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:5810$1245_Y + connect \Y $eq$ls180.v:5806$1244_Y end - attribute \src "ls180.v:5812.98-5812.142" - cell $eq $eq$ls180.v:5812$1248 + attribute \src "ls180.v:5808.98-5808.142" + cell $eq $eq$ls180.v:5808$1247 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97481,10 +97477,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface2_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:5812$1248_Y + connect \Y $eq$ls180.v:5808$1247_Y end - attribute \src "ls180.v:5813.101-5813.145" - cell $eq $eq$ls180.v:5813$1252 + attribute \src "ls180.v:5809.101-5809.145" + cell $eq $eq$ls180.v:5809$1251 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97492,10 +97488,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface2_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:5813$1252_Y + connect \Y $eq$ls180.v:5809$1251_Y end - attribute \src "ls180.v:5823.32-5823.77" - cell $eq $eq$ls180.v:5823$1254 + attribute \src "ls180.v:5819.32-5819.77" + cell $eq $eq$ls180.v:5819$1253 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -97503,10 +97499,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [13:9] connect \B 4'1001 - connect \Y $eq$ls180.v:5823$1254_Y + connect \Y $eq$ls180.v:5819$1253_Y end - attribute \src "ls180.v:5825.98-5825.142" - cell $eq $eq$ls180.v:5825$1256 + attribute \src "ls180.v:5821.98-5821.142" + cell $eq $eq$ls180.v:5821$1255 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97514,10 +97510,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:5825$1256_Y + connect \Y $eq$ls180.v:5821$1255_Y end - attribute \src "ls180.v:5826.101-5826.145" - cell $eq $eq$ls180.v:5826$1260 + attribute \src "ls180.v:5822.101-5822.145" + cell $eq $eq$ls180.v:5822$1259 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97525,10 +97521,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:5826$1260_Y + connect \Y $eq$ls180.v:5822$1259_Y end - attribute \src "ls180.v:5828.97-5828.141" - cell $eq $eq$ls180.v:5828$1263 + attribute \src "ls180.v:5824.97-5824.141" + cell $eq $eq$ls180.v:5824$1262 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97536,10 +97532,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:5828$1263_Y + connect \Y $eq$ls180.v:5824$1262_Y end - attribute \src "ls180.v:5829.100-5829.144" - cell $eq $eq$ls180.v:5829$1267 + attribute \src "ls180.v:5825.100-5825.144" + cell $eq $eq$ls180.v:5825$1266 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97547,10 +97543,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:5829$1267_Y + connect \Y $eq$ls180.v:5825$1266_Y end - attribute \src "ls180.v:5831.97-5831.141" - cell $eq $eq$ls180.v:5831$1270 + attribute \src "ls180.v:5827.97-5827.141" + cell $eq $eq$ls180.v:5827$1269 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97558,10 +97554,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:5831$1270_Y + connect \Y $eq$ls180.v:5827$1269_Y end - attribute \src "ls180.v:5832.100-5832.144" - cell $eq $eq$ls180.v:5832$1274 + attribute \src "ls180.v:5828.100-5828.144" + cell $eq $eq$ls180.v:5828$1273 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97569,10 +97565,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:5832$1274_Y + connect \Y $eq$ls180.v:5828$1273_Y end - attribute \src "ls180.v:5834.97-5834.141" - cell $eq $eq$ls180.v:5834$1277 + attribute \src "ls180.v:5830.97-5830.141" + cell $eq $eq$ls180.v:5830$1276 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97580,10 +97576,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:5834$1277_Y + connect \Y $eq$ls180.v:5830$1276_Y end - attribute \src "ls180.v:5835.100-5835.144" - cell $eq $eq$ls180.v:5835$1281 + attribute \src "ls180.v:5831.100-5831.144" + cell $eq $eq$ls180.v:5831$1280 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97591,10 +97587,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:5835$1281_Y + connect \Y $eq$ls180.v:5831$1280_Y end - attribute \src "ls180.v:5837.97-5837.141" - cell $eq $eq$ls180.v:5837$1284 + attribute \src "ls180.v:5833.97-5833.141" + cell $eq $eq$ls180.v:5833$1283 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97602,10 +97598,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:5837$1284_Y + connect \Y $eq$ls180.v:5833$1283_Y end - attribute \src "ls180.v:5838.100-5838.144" - cell $eq $eq$ls180.v:5838$1288 + attribute \src "ls180.v:5834.100-5834.144" + cell $eq $eq$ls180.v:5834$1287 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97613,10 +97609,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:5838$1288_Y + connect \Y $eq$ls180.v:5834$1287_Y end - attribute \src "ls180.v:5840.98-5840.142" - cell $eq $eq$ls180.v:5840$1291 + attribute \src "ls180.v:5836.98-5836.142" + cell $eq $eq$ls180.v:5836$1290 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97624,10 +97620,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:5840$1291_Y + connect \Y $eq$ls180.v:5836$1290_Y end - attribute \src "ls180.v:5841.101-5841.145" - cell $eq $eq$ls180.v:5841$1295 + attribute \src "ls180.v:5837.101-5837.145" + cell $eq $eq$ls180.v:5837$1294 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97635,10 +97631,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:5841$1295_Y + connect \Y $eq$ls180.v:5837$1294_Y end - attribute \src "ls180.v:5843.98-5843.142" - cell $eq $eq$ls180.v:5843$1298 + attribute \src "ls180.v:5839.98-5839.142" + cell $eq $eq$ls180.v:5839$1297 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97646,10 +97642,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:5843$1298_Y + connect \Y $eq$ls180.v:5839$1297_Y end - attribute \src "ls180.v:5844.101-5844.145" - cell $eq $eq$ls180.v:5844$1302 + attribute \src "ls180.v:5840.101-5840.145" + cell $eq $eq$ls180.v:5840$1301 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97657,10 +97653,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:5844$1302_Y + connect \Y $eq$ls180.v:5840$1301_Y end - attribute \src "ls180.v:5846.98-5846.142" - cell $eq $eq$ls180.v:5846$1305 + attribute \src "ls180.v:5842.98-5842.142" + cell $eq $eq$ls180.v:5842$1304 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97668,10 +97664,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:5846$1305_Y + connect \Y $eq$ls180.v:5842$1304_Y end - attribute \src "ls180.v:5847.101-5847.145" - cell $eq $eq$ls180.v:5847$1309 + attribute \src "ls180.v:5843.101-5843.145" + cell $eq $eq$ls180.v:5843$1308 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97679,10 +97675,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:5847$1309_Y + connect \Y $eq$ls180.v:5843$1308_Y end - attribute \src "ls180.v:5849.98-5849.142" - cell $eq $eq$ls180.v:5849$1312 + attribute \src "ls180.v:5845.98-5845.142" + cell $eq $eq$ls180.v:5845$1311 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97690,10 +97686,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:5849$1312_Y + connect \Y $eq$ls180.v:5845$1311_Y end - attribute \src "ls180.v:5850.101-5850.145" - cell $eq $eq$ls180.v:5850$1316 + attribute \src "ls180.v:5846.101-5846.145" + cell $eq $eq$ls180.v:5846$1315 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97701,10 +97697,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:5850$1316_Y + connect \Y $eq$ls180.v:5846$1315_Y end - attribute \src "ls180.v:5860.32-5860.78" - cell $eq $eq$ls180.v:5860$1318 + attribute \src "ls180.v:5856.32-5856.78" + cell $eq $eq$ls180.v:5856$1317 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -97712,10 +97708,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [13:9] connect \B 4'1100 - connect \Y $eq$ls180.v:5860$1318_Y + connect \Y $eq$ls180.v:5856$1317_Y end - attribute \src "ls180.v:5862.100-5862.144" - cell $eq $eq$ls180.v:5862$1320 + attribute \src "ls180.v:5858.100-5858.144" + cell $eq $eq$ls180.v:5858$1319 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97723,10 +97719,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:5862$1320_Y + connect \Y $eq$ls180.v:5858$1319_Y end - attribute \src "ls180.v:5863.103-5863.147" - cell $eq $eq$ls180.v:5863$1324 + attribute \src "ls180.v:5859.103-5859.147" + cell $eq $eq$ls180.v:5859$1323 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97734,10 +97730,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:5863$1324_Y + connect \Y $eq$ls180.v:5859$1323_Y end - attribute \src "ls180.v:5865.100-5865.144" - cell $eq $eq$ls180.v:5865$1327 + attribute \src "ls180.v:5861.100-5861.144" + cell $eq $eq$ls180.v:5861$1326 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97745,10 +97741,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:5865$1327_Y + connect \Y $eq$ls180.v:5861$1326_Y end - attribute \src "ls180.v:5866.103-5866.147" - cell $eq $eq$ls180.v:5866$1331 + attribute \src "ls180.v:5862.103-5862.147" + cell $eq $eq$ls180.v:5862$1330 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97756,10 +97752,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:5866$1331_Y + connect \Y $eq$ls180.v:5862$1330_Y end - attribute \src "ls180.v:5868.100-5868.144" - cell $eq $eq$ls180.v:5868$1334 + attribute \src "ls180.v:5864.100-5864.144" + cell $eq $eq$ls180.v:5864$1333 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97767,10 +97763,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:5868$1334_Y + connect \Y $eq$ls180.v:5864$1333_Y end - attribute \src "ls180.v:5869.103-5869.147" - cell $eq $eq$ls180.v:5869$1338 + attribute \src "ls180.v:5865.103-5865.147" + cell $eq $eq$ls180.v:5865$1337 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97778,10 +97774,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:5869$1338_Y + connect \Y $eq$ls180.v:5865$1337_Y end - attribute \src "ls180.v:5871.100-5871.144" - cell $eq $eq$ls180.v:5871$1341 + attribute \src "ls180.v:5867.100-5867.144" + cell $eq $eq$ls180.v:5867$1340 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97789,10 +97785,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:5871$1341_Y + connect \Y $eq$ls180.v:5867$1340_Y end - attribute \src "ls180.v:5872.103-5872.147" - cell $eq $eq$ls180.v:5872$1345 + attribute \src "ls180.v:5868.103-5868.147" + cell $eq $eq$ls180.v:5868$1344 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97800,10 +97796,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:5872$1345_Y + connect \Y $eq$ls180.v:5868$1344_Y end - attribute \src "ls180.v:5874.100-5874.144" - cell $eq $eq$ls180.v:5874$1348 + attribute \src "ls180.v:5870.100-5870.144" + cell $eq $eq$ls180.v:5870$1347 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97811,10 +97807,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:5874$1348_Y + connect \Y $eq$ls180.v:5870$1347_Y end - attribute \src "ls180.v:5875.103-5875.147" - cell $eq $eq$ls180.v:5875$1352 + attribute \src "ls180.v:5871.103-5871.147" + cell $eq $eq$ls180.v:5871$1351 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97822,10 +97818,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:5875$1352_Y + connect \Y $eq$ls180.v:5871$1351_Y end - attribute \src "ls180.v:5877.100-5877.144" - cell $eq $eq$ls180.v:5877$1355 + attribute \src "ls180.v:5873.100-5873.144" + cell $eq $eq$ls180.v:5873$1354 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97833,10 +97829,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:5877$1355_Y + connect \Y $eq$ls180.v:5873$1354_Y end - attribute \src "ls180.v:5878.103-5878.147" - cell $eq $eq$ls180.v:5878$1359 + attribute \src "ls180.v:5874.103-5874.147" + cell $eq $eq$ls180.v:5874$1358 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97844,10 +97840,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:5878$1359_Y + connect \Y $eq$ls180.v:5874$1358_Y end - attribute \src "ls180.v:5880.100-5880.144" - cell $eq $eq$ls180.v:5880$1362 + attribute \src "ls180.v:5876.100-5876.144" + cell $eq $eq$ls180.v:5876$1361 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97855,10 +97851,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:5880$1362_Y + connect \Y $eq$ls180.v:5876$1361_Y end - attribute \src "ls180.v:5881.103-5881.147" - cell $eq $eq$ls180.v:5881$1366 + attribute \src "ls180.v:5877.103-5877.147" + cell $eq $eq$ls180.v:5877$1365 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97866,10 +97862,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:5881$1366_Y + connect \Y $eq$ls180.v:5877$1365_Y end - attribute \src "ls180.v:5883.100-5883.144" - cell $eq $eq$ls180.v:5883$1369 + attribute \src "ls180.v:5879.100-5879.144" + cell $eq $eq$ls180.v:5879$1368 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97877,10 +97873,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:5883$1369_Y + connect \Y $eq$ls180.v:5879$1368_Y end - attribute \src "ls180.v:5884.103-5884.147" - cell $eq $eq$ls180.v:5884$1373 + attribute \src "ls180.v:5880.103-5880.147" + cell $eq $eq$ls180.v:5880$1372 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97888,10 +97884,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:5884$1373_Y + connect \Y $eq$ls180.v:5880$1372_Y end - attribute \src "ls180.v:5886.102-5886.146" - cell $eq $eq$ls180.v:5886$1376 + attribute \src "ls180.v:5882.102-5882.146" + cell $eq $eq$ls180.v:5882$1375 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97899,10 +97895,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:5886$1376_Y + connect \Y $eq$ls180.v:5882$1375_Y end - attribute \src "ls180.v:5887.105-5887.149" - cell $eq $eq$ls180.v:5887$1380 + attribute \src "ls180.v:5883.105-5883.149" + cell $eq $eq$ls180.v:5883$1379 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97910,10 +97906,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:5887$1380_Y + connect \Y $eq$ls180.v:5883$1379_Y end - attribute \src "ls180.v:5889.102-5889.146" - cell $eq $eq$ls180.v:5889$1383 + attribute \src "ls180.v:5885.102-5885.146" + cell $eq $eq$ls180.v:5885$1382 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97921,10 +97917,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 4'1001 - connect \Y $eq$ls180.v:5889$1383_Y + connect \Y $eq$ls180.v:5885$1382_Y end - attribute \src "ls180.v:5890.105-5890.149" - cell $eq $eq$ls180.v:5890$1387 + attribute \src "ls180.v:5886.105-5886.149" + cell $eq $eq$ls180.v:5886$1386 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97932,10 +97928,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 4'1001 - connect \Y $eq$ls180.v:5890$1387_Y + connect \Y $eq$ls180.v:5886$1386_Y end - attribute \src "ls180.v:5892.102-5892.147" - cell $eq $eq$ls180.v:5892$1390 + attribute \src "ls180.v:5888.102-5888.147" + cell $eq $eq$ls180.v:5888$1389 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97943,10 +97939,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 4'1010 - connect \Y $eq$ls180.v:5892$1390_Y + connect \Y $eq$ls180.v:5888$1389_Y end - attribute \src "ls180.v:5893.105-5893.150" - cell $eq $eq$ls180.v:5893$1394 + attribute \src "ls180.v:5889.105-5889.150" + cell $eq $eq$ls180.v:5889$1393 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97954,10 +97950,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 4'1010 - connect \Y $eq$ls180.v:5893$1394_Y + connect \Y $eq$ls180.v:5889$1393_Y end - attribute \src "ls180.v:5895.102-5895.147" - cell $eq $eq$ls180.v:5895$1397 + attribute \src "ls180.v:5891.102-5891.147" + cell $eq $eq$ls180.v:5891$1396 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97965,10 +97961,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 4'1011 - connect \Y $eq$ls180.v:5895$1397_Y + connect \Y $eq$ls180.v:5891$1396_Y end - attribute \src "ls180.v:5896.105-5896.150" - cell $eq $eq$ls180.v:5896$1401 + attribute \src "ls180.v:5892.105-5892.150" + cell $eq $eq$ls180.v:5892$1400 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97976,10 +97972,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 4'1011 - connect \Y $eq$ls180.v:5896$1401_Y + connect \Y $eq$ls180.v:5892$1400_Y end - attribute \src "ls180.v:5898.102-5898.147" - cell $eq $eq$ls180.v:5898$1404 + attribute \src "ls180.v:5894.102-5894.147" + cell $eq $eq$ls180.v:5894$1403 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97987,10 +97983,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 4'1100 - connect \Y $eq$ls180.v:5898$1404_Y + connect \Y $eq$ls180.v:5894$1403_Y end - attribute \src "ls180.v:5899.105-5899.150" - cell $eq $eq$ls180.v:5899$1408 + attribute \src "ls180.v:5895.105-5895.150" + cell $eq $eq$ls180.v:5895$1407 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -97998,10 +97994,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 4'1100 - connect \Y $eq$ls180.v:5899$1408_Y + connect \Y $eq$ls180.v:5895$1407_Y end - attribute \src "ls180.v:5901.99-5901.144" - cell $eq $eq$ls180.v:5901$1411 + attribute \src "ls180.v:5897.99-5897.144" + cell $eq $eq$ls180.v:5897$1410 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -98009,10 +98005,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 4'1101 - connect \Y $eq$ls180.v:5901$1411_Y + connect \Y $eq$ls180.v:5897$1410_Y end - attribute \src "ls180.v:5902.102-5902.147" - cell $eq $eq$ls180.v:5902$1415 + attribute \src "ls180.v:5898.102-5898.147" + cell $eq $eq$ls180.v:5898$1414 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -98020,10 +98016,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 4'1101 - connect \Y $eq$ls180.v:5902$1415_Y + connect \Y $eq$ls180.v:5898$1414_Y end - attribute \src "ls180.v:5904.100-5904.145" - cell $eq $eq$ls180.v:5904$1418 + attribute \src "ls180.v:5900.100-5900.145" + cell $eq $eq$ls180.v:5900$1417 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -98031,10 +98027,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 4'1110 - connect \Y $eq$ls180.v:5904$1418_Y + connect \Y $eq$ls180.v:5900$1417_Y end - attribute \src "ls180.v:5905.103-5905.148" - cell $eq $eq$ls180.v:5905$1422 + attribute \src "ls180.v:5901.103-5901.148" + cell $eq $eq$ls180.v:5901$1421 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -98042,10 +98038,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 4'1110 - connect \Y $eq$ls180.v:5905$1422_Y + connect \Y $eq$ls180.v:5901$1421_Y end - attribute \src "ls180.v:5922.32-5922.78" - cell $eq $eq$ls180.v:5922$1424 + attribute \src "ls180.v:5918.32-5918.78" + cell $eq $eq$ls180.v:5918$1423 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -98053,10 +98049,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [13:9] connect \B 4'1011 - connect \Y $eq$ls180.v:5922$1424_Y + connect \Y $eq$ls180.v:5918$1423_Y end - attribute \src "ls180.v:5924.104-5924.148" - cell $eq $eq$ls180.v:5924$1426 + attribute \src "ls180.v:5920.104-5920.148" + cell $eq $eq$ls180.v:5920$1425 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98064,10 +98060,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 1'0 - connect \Y $eq$ls180.v:5924$1426_Y + connect \Y $eq$ls180.v:5920$1425_Y end - attribute \src "ls180.v:5925.107-5925.151" - cell $eq $eq$ls180.v:5925$1430 + attribute \src "ls180.v:5921.107-5921.151" + cell $eq $eq$ls180.v:5921$1429 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98075,10 +98071,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 1'0 - connect \Y $eq$ls180.v:5925$1430_Y + connect \Y $eq$ls180.v:5921$1429_Y end - attribute \src "ls180.v:5927.104-5927.148" - cell $eq $eq$ls180.v:5927$1433 + attribute \src "ls180.v:5923.104-5923.148" + cell $eq $eq$ls180.v:5923$1432 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98086,10 +98082,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 1'1 - connect \Y $eq$ls180.v:5927$1433_Y + connect \Y $eq$ls180.v:5923$1432_Y end - attribute \src "ls180.v:5928.107-5928.151" - cell $eq $eq$ls180.v:5928$1437 + attribute \src "ls180.v:5924.107-5924.151" + cell $eq $eq$ls180.v:5924$1436 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98097,10 +98093,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 1'1 - connect \Y $eq$ls180.v:5928$1437_Y + connect \Y $eq$ls180.v:5924$1436_Y end - attribute \src "ls180.v:5930.104-5930.148" - cell $eq $eq$ls180.v:5930$1440 + attribute \src "ls180.v:5926.104-5926.148" + cell $eq $eq$ls180.v:5926$1439 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98108,10 +98104,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 2'10 - connect \Y $eq$ls180.v:5930$1440_Y + connect \Y $eq$ls180.v:5926$1439_Y end - attribute \src "ls180.v:5931.107-5931.151" - cell $eq $eq$ls180.v:5931$1444 + attribute \src "ls180.v:5927.107-5927.151" + cell $eq $eq$ls180.v:5927$1443 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98119,10 +98115,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 2'10 - connect \Y $eq$ls180.v:5931$1444_Y + connect \Y $eq$ls180.v:5927$1443_Y end - attribute \src "ls180.v:5933.104-5933.148" - cell $eq $eq$ls180.v:5933$1447 + attribute \src "ls180.v:5929.104-5929.148" + cell $eq $eq$ls180.v:5929$1446 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98130,10 +98126,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 2'11 - connect \Y $eq$ls180.v:5933$1447_Y + connect \Y $eq$ls180.v:5929$1446_Y end - attribute \src "ls180.v:5934.107-5934.151" - cell $eq $eq$ls180.v:5934$1451 + attribute \src "ls180.v:5930.107-5930.151" + cell $eq $eq$ls180.v:5930$1450 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98141,10 +98137,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 2'11 - connect \Y $eq$ls180.v:5934$1451_Y + connect \Y $eq$ls180.v:5930$1450_Y end - attribute \src "ls180.v:5936.103-5936.147" - cell $eq $eq$ls180.v:5936$1454 + attribute \src "ls180.v:5932.103-5932.147" + cell $eq $eq$ls180.v:5932$1453 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98152,10 +98148,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 3'100 - connect \Y $eq$ls180.v:5936$1454_Y + connect \Y $eq$ls180.v:5932$1453_Y end - attribute \src "ls180.v:5937.106-5937.150" - cell $eq $eq$ls180.v:5937$1458 + attribute \src "ls180.v:5933.106-5933.150" + cell $eq $eq$ls180.v:5933$1457 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98163,10 +98159,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 3'100 - connect \Y $eq$ls180.v:5937$1458_Y + connect \Y $eq$ls180.v:5933$1457_Y end - attribute \src "ls180.v:5939.103-5939.147" - cell $eq $eq$ls180.v:5939$1461 + attribute \src "ls180.v:5935.103-5935.147" + cell $eq $eq$ls180.v:5935$1460 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98174,10 +98170,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 3'101 - connect \Y $eq$ls180.v:5939$1461_Y + connect \Y $eq$ls180.v:5935$1460_Y end - attribute \src "ls180.v:5940.106-5940.150" - cell $eq $eq$ls180.v:5940$1465 + attribute \src "ls180.v:5936.106-5936.150" + cell $eq $eq$ls180.v:5936$1464 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98185,10 +98181,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 3'101 - connect \Y $eq$ls180.v:5940$1465_Y + connect \Y $eq$ls180.v:5936$1464_Y end - attribute \src "ls180.v:5942.103-5942.147" - cell $eq $eq$ls180.v:5942$1468 + attribute \src "ls180.v:5938.103-5938.147" + cell $eq $eq$ls180.v:5938$1467 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98196,10 +98192,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 3'110 - connect \Y $eq$ls180.v:5942$1468_Y + connect \Y $eq$ls180.v:5938$1467_Y end - attribute \src "ls180.v:5943.106-5943.150" - cell $eq $eq$ls180.v:5943$1472 + attribute \src "ls180.v:5939.106-5939.150" + cell $eq $eq$ls180.v:5939$1471 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98207,10 +98203,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 3'110 - connect \Y $eq$ls180.v:5943$1472_Y + connect \Y $eq$ls180.v:5939$1471_Y end - attribute \src "ls180.v:5945.103-5945.147" - cell $eq $eq$ls180.v:5945$1475 + attribute \src "ls180.v:5941.103-5941.147" + cell $eq $eq$ls180.v:5941$1474 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98218,10 +98214,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 3'111 - connect \Y $eq$ls180.v:5945$1475_Y + connect \Y $eq$ls180.v:5941$1474_Y end - attribute \src "ls180.v:5946.106-5946.150" - cell $eq $eq$ls180.v:5946$1479 + attribute \src "ls180.v:5942.106-5942.150" + cell $eq $eq$ls180.v:5942$1478 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98229,10 +98225,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 3'111 - connect \Y $eq$ls180.v:5946$1479_Y + connect \Y $eq$ls180.v:5942$1478_Y end - attribute \src "ls180.v:5948.94-5948.138" - cell $eq $eq$ls180.v:5948$1482 + attribute \src "ls180.v:5944.94-5944.138" + cell $eq $eq$ls180.v:5944$1481 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98240,10 +98236,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 4'1000 - connect \Y $eq$ls180.v:5948$1482_Y + connect \Y $eq$ls180.v:5944$1481_Y end - attribute \src "ls180.v:5949.97-5949.141" - cell $eq $eq$ls180.v:5949$1486 + attribute \src "ls180.v:5945.97-5945.141" + cell $eq $eq$ls180.v:5945$1485 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98251,10 +98247,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 4'1000 - connect \Y $eq$ls180.v:5949$1486_Y + connect \Y $eq$ls180.v:5945$1485_Y end - attribute \src "ls180.v:5951.105-5951.149" - cell $eq $eq$ls180.v:5951$1489 + attribute \src "ls180.v:5947.105-5947.149" + cell $eq $eq$ls180.v:5947$1488 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98262,10 +98258,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 4'1001 - connect \Y $eq$ls180.v:5951$1489_Y + connect \Y $eq$ls180.v:5947$1488_Y end - attribute \src "ls180.v:5952.108-5952.152" - cell $eq $eq$ls180.v:5952$1493 + attribute \src "ls180.v:5948.108-5948.152" + cell $eq $eq$ls180.v:5948$1492 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98273,10 +98269,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 4'1001 - connect \Y $eq$ls180.v:5952$1493_Y + connect \Y $eq$ls180.v:5948$1492_Y end - attribute \src "ls180.v:5954.105-5954.150" - cell $eq $eq$ls180.v:5954$1496 + attribute \src "ls180.v:5950.105-5950.150" + cell $eq $eq$ls180.v:5950$1495 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98284,10 +98280,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 4'1010 - connect \Y $eq$ls180.v:5954$1496_Y + connect \Y $eq$ls180.v:5950$1495_Y end - attribute \src "ls180.v:5955.108-5955.153" - cell $eq $eq$ls180.v:5955$1500 + attribute \src "ls180.v:5951.108-5951.153" + cell $eq $eq$ls180.v:5951$1499 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98295,10 +98291,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 4'1010 - connect \Y $eq$ls180.v:5955$1500_Y + connect \Y $eq$ls180.v:5951$1499_Y end - attribute \src "ls180.v:5957.105-5957.150" - cell $eq $eq$ls180.v:5957$1503 + attribute \src "ls180.v:5953.105-5953.150" + cell $eq $eq$ls180.v:5953$1502 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98306,10 +98302,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 4'1011 - connect \Y $eq$ls180.v:5957$1503_Y + connect \Y $eq$ls180.v:5953$1502_Y end - attribute \src "ls180.v:5958.108-5958.153" - cell $eq $eq$ls180.v:5958$1507 + attribute \src "ls180.v:5954.108-5954.153" + cell $eq $eq$ls180.v:5954$1506 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98317,10 +98313,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 4'1011 - connect \Y $eq$ls180.v:5958$1507_Y + connect \Y $eq$ls180.v:5954$1506_Y end - attribute \src "ls180.v:5960.105-5960.150" - cell $eq $eq$ls180.v:5960$1510 + attribute \src "ls180.v:5956.105-5956.150" + cell $eq $eq$ls180.v:5956$1509 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98328,10 +98324,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 4'1100 - connect \Y $eq$ls180.v:5960$1510_Y + connect \Y $eq$ls180.v:5956$1509_Y end - attribute \src "ls180.v:5961.108-5961.153" - cell $eq $eq$ls180.v:5961$1514 + attribute \src "ls180.v:5957.108-5957.153" + cell $eq $eq$ls180.v:5957$1513 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98339,10 +98335,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 4'1100 - connect \Y $eq$ls180.v:5961$1514_Y + connect \Y $eq$ls180.v:5957$1513_Y end - attribute \src "ls180.v:5963.105-5963.150" - cell $eq $eq$ls180.v:5963$1517 + attribute \src "ls180.v:5959.105-5959.150" + cell $eq $eq$ls180.v:5959$1516 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98350,10 +98346,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 4'1101 - connect \Y $eq$ls180.v:5963$1517_Y + connect \Y $eq$ls180.v:5959$1516_Y end - attribute \src "ls180.v:5964.108-5964.153" - cell $eq $eq$ls180.v:5964$1521 + attribute \src "ls180.v:5960.108-5960.153" + cell $eq $eq$ls180.v:5960$1520 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98361,10 +98357,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 4'1101 - connect \Y $eq$ls180.v:5964$1521_Y + connect \Y $eq$ls180.v:5960$1520_Y end - attribute \src "ls180.v:5966.105-5966.150" - cell $eq $eq$ls180.v:5966$1524 + attribute \src "ls180.v:5962.105-5962.150" + cell $eq $eq$ls180.v:5962$1523 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98372,10 +98368,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 4'1110 - connect \Y $eq$ls180.v:5966$1524_Y + connect \Y $eq$ls180.v:5962$1523_Y end - attribute \src "ls180.v:5967.108-5967.153" - cell $eq $eq$ls180.v:5967$1528 + attribute \src "ls180.v:5963.108-5963.153" + cell $eq $eq$ls180.v:5963$1527 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98383,10 +98379,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 4'1110 - connect \Y $eq$ls180.v:5967$1528_Y + connect \Y $eq$ls180.v:5963$1527_Y end - attribute \src "ls180.v:5969.104-5969.149" - cell $eq $eq$ls180.v:5969$1531 + attribute \src "ls180.v:5965.104-5965.149" + cell $eq $eq$ls180.v:5965$1530 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98394,10 +98390,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 4'1111 - connect \Y $eq$ls180.v:5969$1531_Y + connect \Y $eq$ls180.v:5965$1530_Y end - attribute \src "ls180.v:5970.107-5970.152" - cell $eq $eq$ls180.v:5970$1535 + attribute \src "ls180.v:5966.107-5966.152" + cell $eq $eq$ls180.v:5966$1534 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98405,10 +98401,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 4'1111 - connect \Y $eq$ls180.v:5970$1535_Y + connect \Y $eq$ls180.v:5966$1534_Y end - attribute \src "ls180.v:5972.104-5972.149" - cell $eq $eq$ls180.v:5972$1538 + attribute \src "ls180.v:5968.104-5968.149" + cell $eq $eq$ls180.v:5968$1537 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98416,10 +98412,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 5'10000 - connect \Y $eq$ls180.v:5972$1538_Y + connect \Y $eq$ls180.v:5968$1537_Y end - attribute \src "ls180.v:5973.107-5973.152" - cell $eq $eq$ls180.v:5973$1542 + attribute \src "ls180.v:5969.107-5969.152" + cell $eq $eq$ls180.v:5969$1541 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98427,10 +98423,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 5'10000 - connect \Y $eq$ls180.v:5973$1542_Y + connect \Y $eq$ls180.v:5969$1541_Y end - attribute \src "ls180.v:5975.104-5975.149" - cell $eq $eq$ls180.v:5975$1545 + attribute \src "ls180.v:5971.104-5971.149" + cell $eq $eq$ls180.v:5971$1544 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98438,10 +98434,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 5'10001 - connect \Y $eq$ls180.v:5975$1545_Y + connect \Y $eq$ls180.v:5971$1544_Y end - attribute \src "ls180.v:5976.107-5976.152" - cell $eq $eq$ls180.v:5976$1549 + attribute \src "ls180.v:5972.107-5972.152" + cell $eq $eq$ls180.v:5972$1548 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98449,10 +98445,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 5'10001 - connect \Y $eq$ls180.v:5976$1549_Y + connect \Y $eq$ls180.v:5972$1548_Y end - attribute \src "ls180.v:5978.104-5978.149" - cell $eq $eq$ls180.v:5978$1552 + attribute \src "ls180.v:5974.104-5974.149" + cell $eq $eq$ls180.v:5974$1551 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98460,10 +98456,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 5'10010 - connect \Y $eq$ls180.v:5978$1552_Y + connect \Y $eq$ls180.v:5974$1551_Y end - attribute \src "ls180.v:5979.107-5979.152" - cell $eq $eq$ls180.v:5979$1556 + attribute \src "ls180.v:5975.107-5975.152" + cell $eq $eq$ls180.v:5975$1555 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98471,10 +98467,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 5'10010 - connect \Y $eq$ls180.v:5979$1556_Y + connect \Y $eq$ls180.v:5975$1555_Y end - attribute \src "ls180.v:5981.104-5981.149" - cell $eq $eq$ls180.v:5981$1559 + attribute \src "ls180.v:5977.104-5977.149" + cell $eq $eq$ls180.v:5977$1558 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98482,10 +98478,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 5'10011 - connect \Y $eq$ls180.v:5981$1559_Y + connect \Y $eq$ls180.v:5977$1558_Y end - attribute \src "ls180.v:5982.107-5982.152" - cell $eq $eq$ls180.v:5982$1563 + attribute \src "ls180.v:5978.107-5978.152" + cell $eq $eq$ls180.v:5978$1562 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98493,10 +98489,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 5'10011 - connect \Y $eq$ls180.v:5982$1563_Y + connect \Y $eq$ls180.v:5978$1562_Y end - attribute \src "ls180.v:5984.104-5984.149" - cell $eq $eq$ls180.v:5984$1566 + attribute \src "ls180.v:5980.104-5980.149" + cell $eq $eq$ls180.v:5980$1565 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98504,10 +98500,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 5'10100 - connect \Y $eq$ls180.v:5984$1566_Y + connect \Y $eq$ls180.v:5980$1565_Y end - attribute \src "ls180.v:5985.107-5985.152" - cell $eq $eq$ls180.v:5985$1570 + attribute \src "ls180.v:5981.107-5981.152" + cell $eq $eq$ls180.v:5981$1569 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98515,10 +98511,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 5'10100 - connect \Y $eq$ls180.v:5985$1570_Y + connect \Y $eq$ls180.v:5981$1569_Y end - attribute \src "ls180.v:5987.104-5987.149" - cell $eq $eq$ls180.v:5987$1573 + attribute \src "ls180.v:5983.104-5983.149" + cell $eq $eq$ls180.v:5983$1572 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98526,10 +98522,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 5'10101 - connect \Y $eq$ls180.v:5987$1573_Y + connect \Y $eq$ls180.v:5983$1572_Y end - attribute \src "ls180.v:5988.107-5988.152" - cell $eq $eq$ls180.v:5988$1577 + attribute \src "ls180.v:5984.107-5984.152" + cell $eq $eq$ls180.v:5984$1576 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98537,10 +98533,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 5'10101 - connect \Y $eq$ls180.v:5988$1577_Y + connect \Y $eq$ls180.v:5984$1576_Y end - attribute \src "ls180.v:5990.104-5990.149" - cell $eq $eq$ls180.v:5990$1580 + attribute \src "ls180.v:5986.104-5986.149" + cell $eq $eq$ls180.v:5986$1579 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98548,10 +98544,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 5'10110 - connect \Y $eq$ls180.v:5990$1580_Y + connect \Y $eq$ls180.v:5986$1579_Y end - attribute \src "ls180.v:5991.107-5991.152" - cell $eq $eq$ls180.v:5991$1584 + attribute \src "ls180.v:5987.107-5987.152" + cell $eq $eq$ls180.v:5987$1583 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98559,10 +98555,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 5'10110 - connect \Y $eq$ls180.v:5991$1584_Y + connect \Y $eq$ls180.v:5987$1583_Y end - attribute \src "ls180.v:5993.104-5993.149" - cell $eq $eq$ls180.v:5993$1587 + attribute \src "ls180.v:5989.104-5989.149" + cell $eq $eq$ls180.v:5989$1586 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98570,10 +98566,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 5'10111 - connect \Y $eq$ls180.v:5993$1587_Y + connect \Y $eq$ls180.v:5989$1586_Y end - attribute \src "ls180.v:5994.107-5994.152" - cell $eq $eq$ls180.v:5994$1591 + attribute \src "ls180.v:5990.107-5990.152" + cell $eq $eq$ls180.v:5990$1590 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98581,10 +98577,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 5'10111 - connect \Y $eq$ls180.v:5994$1591_Y + connect \Y $eq$ls180.v:5990$1590_Y end - attribute \src "ls180.v:5996.104-5996.149" - cell $eq $eq$ls180.v:5996$1594 + attribute \src "ls180.v:5992.104-5992.149" + cell $eq $eq$ls180.v:5992$1593 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98592,10 +98588,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 5'11000 - connect \Y $eq$ls180.v:5996$1594_Y + connect \Y $eq$ls180.v:5992$1593_Y end - attribute \src "ls180.v:5997.107-5997.152" - cell $eq $eq$ls180.v:5997$1598 + attribute \src "ls180.v:5993.107-5993.152" + cell $eq $eq$ls180.v:5993$1597 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98603,10 +98599,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 5'11000 - connect \Y $eq$ls180.v:5997$1598_Y + connect \Y $eq$ls180.v:5993$1597_Y end - attribute \src "ls180.v:5999.100-5999.145" - cell $eq $eq$ls180.v:5999$1601 + attribute \src "ls180.v:5995.100-5995.145" + cell $eq $eq$ls180.v:5995$1600 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98614,10 +98610,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 5'11001 - connect \Y $eq$ls180.v:5999$1601_Y + connect \Y $eq$ls180.v:5995$1600_Y end - attribute \src "ls180.v:6000.103-6000.148" - cell $eq $eq$ls180.v:6000$1605 + attribute \src "ls180.v:5996.103-5996.148" + cell $eq $eq$ls180.v:5996$1604 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98625,10 +98621,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 5'11001 - connect \Y $eq$ls180.v:6000$1605_Y + connect \Y $eq$ls180.v:5996$1604_Y end - attribute \src "ls180.v:6002.101-6002.146" - cell $eq $eq$ls180.v:6002$1608 + attribute \src "ls180.v:5998.101-5998.146" + cell $eq $eq$ls180.v:5998$1607 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98636,10 +98632,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 5'11010 - connect \Y $eq$ls180.v:6002$1608_Y + connect \Y $eq$ls180.v:5998$1607_Y end - attribute \src "ls180.v:6003.104-6003.149" - cell $eq $eq$ls180.v:6003$1612 + attribute \src "ls180.v:5999.104-5999.149" + cell $eq $eq$ls180.v:5999$1611 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98647,10 +98643,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 5'11010 - connect \Y $eq$ls180.v:6003$1612_Y + connect \Y $eq$ls180.v:5999$1611_Y end - attribute \src "ls180.v:6005.104-6005.149" - cell $eq $eq$ls180.v:6005$1615 + attribute \src "ls180.v:6001.104-6001.149" + cell $eq $eq$ls180.v:6001$1614 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98658,10 +98654,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 5'11011 - connect \Y $eq$ls180.v:6005$1615_Y + connect \Y $eq$ls180.v:6001$1614_Y end - attribute \src "ls180.v:6006.107-6006.152" - cell $eq $eq$ls180.v:6006$1619 + attribute \src "ls180.v:6002.107-6002.152" + cell $eq $eq$ls180.v:6002$1618 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98669,10 +98665,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 5'11011 - connect \Y $eq$ls180.v:6006$1619_Y + connect \Y $eq$ls180.v:6002$1618_Y end - attribute \src "ls180.v:6008.104-6008.149" - cell $eq $eq$ls180.v:6008$1622 + attribute \src "ls180.v:6004.104-6004.149" + cell $eq $eq$ls180.v:6004$1621 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98680,10 +98676,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 5'11100 - connect \Y $eq$ls180.v:6008$1622_Y + connect \Y $eq$ls180.v:6004$1621_Y end - attribute \src "ls180.v:6009.107-6009.152" - cell $eq $eq$ls180.v:6009$1626 + attribute \src "ls180.v:6005.107-6005.152" + cell $eq $eq$ls180.v:6005$1625 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98691,10 +98687,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 5'11100 - connect \Y $eq$ls180.v:6009$1626_Y + connect \Y $eq$ls180.v:6005$1625_Y end - attribute \src "ls180.v:6011.103-6011.148" - cell $eq $eq$ls180.v:6011$1629 + attribute \src "ls180.v:6007.103-6007.148" + cell $eq $eq$ls180.v:6007$1628 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98702,10 +98698,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 5'11101 - connect \Y $eq$ls180.v:6011$1629_Y + connect \Y $eq$ls180.v:6007$1628_Y end - attribute \src "ls180.v:6012.106-6012.151" - cell $eq $eq$ls180.v:6012$1633 + attribute \src "ls180.v:6008.106-6008.151" + cell $eq $eq$ls180.v:6008$1632 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98713,10 +98709,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 5'11101 - connect \Y $eq$ls180.v:6012$1633_Y + connect \Y $eq$ls180.v:6008$1632_Y end - attribute \src "ls180.v:6014.103-6014.148" - cell $eq $eq$ls180.v:6014$1636 + attribute \src "ls180.v:6010.103-6010.148" + cell $eq $eq$ls180.v:6010$1635 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98724,10 +98720,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 5'11110 - connect \Y $eq$ls180.v:6014$1636_Y + connect \Y $eq$ls180.v:6010$1635_Y end - attribute \src "ls180.v:6015.106-6015.151" - cell $eq $eq$ls180.v:6015$1640 + attribute \src "ls180.v:6011.106-6011.151" + cell $eq $eq$ls180.v:6011$1639 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98735,10 +98731,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 5'11110 - connect \Y $eq$ls180.v:6015$1640_Y + connect \Y $eq$ls180.v:6011$1639_Y end - attribute \src "ls180.v:6017.103-6017.148" - cell $eq $eq$ls180.v:6017$1643 + attribute \src "ls180.v:6013.103-6013.148" + cell $eq $eq$ls180.v:6013$1642 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98746,10 +98742,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 5'11111 - connect \Y $eq$ls180.v:6017$1643_Y + connect \Y $eq$ls180.v:6013$1642_Y end - attribute \src "ls180.v:6018.106-6018.151" - cell $eq $eq$ls180.v:6018$1647 + attribute \src "ls180.v:6014.106-6014.151" + cell $eq $eq$ls180.v:6014$1646 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98757,10 +98753,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 5'11111 - connect \Y $eq$ls180.v:6018$1647_Y + connect \Y $eq$ls180.v:6014$1646_Y end - attribute \src "ls180.v:6020.103-6020.148" - cell $eq $eq$ls180.v:6020$1650 + attribute \src "ls180.v:6016.103-6016.148" + cell $eq $eq$ls180.v:6016$1649 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98768,10 +98764,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 6'100000 - connect \Y $eq$ls180.v:6020$1650_Y + connect \Y $eq$ls180.v:6016$1649_Y end - attribute \src "ls180.v:6021.106-6021.151" - cell $eq $eq$ls180.v:6021$1654 + attribute \src "ls180.v:6017.106-6017.151" + cell $eq $eq$ls180.v:6017$1653 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -98779,10 +98775,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [5:0] connect \B 6'100000 - connect \Y $eq$ls180.v:6021$1654_Y + connect \Y $eq$ls180.v:6017$1653_Y end - attribute \src "ls180.v:6057.32-6057.78" - cell $eq $eq$ls180.v:6057$1656 + attribute \src "ls180.v:6053.32-6053.78" + cell $eq $eq$ls180.v:6053$1655 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -98790,10 +98786,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [13:9] connect \B 4'1101 - connect \Y $eq$ls180.v:6057$1656_Y + connect \Y $eq$ls180.v:6053$1655_Y end - attribute \src "ls180.v:6059.100-6059.144" - cell $eq $eq$ls180.v:6059$1658 + attribute \src "ls180.v:6055.100-6055.144" + cell $eq $eq$ls180.v:6055$1657 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -98801,10 +98797,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [4:0] connect \B 1'0 - connect \Y $eq$ls180.v:6059$1658_Y + connect \Y $eq$ls180.v:6055$1657_Y end - attribute \src "ls180.v:6060.103-6060.147" - cell $eq $eq$ls180.v:6060$1662 + attribute \src "ls180.v:6056.103-6056.147" + cell $eq $eq$ls180.v:6056$1661 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -98812,10 +98808,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [4:0] connect \B 1'0 - connect \Y $eq$ls180.v:6060$1662_Y + connect \Y $eq$ls180.v:6056$1661_Y end - attribute \src "ls180.v:6062.100-6062.144" - cell $eq $eq$ls180.v:6062$1665 + attribute \src "ls180.v:6058.100-6058.144" + cell $eq $eq$ls180.v:6058$1664 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -98823,10 +98819,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [4:0] connect \B 1'1 - connect \Y $eq$ls180.v:6062$1665_Y + connect \Y $eq$ls180.v:6058$1664_Y end - attribute \src "ls180.v:6063.103-6063.147" - cell $eq $eq$ls180.v:6063$1669 + attribute \src "ls180.v:6059.103-6059.147" + cell $eq $eq$ls180.v:6059$1668 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -98834,10 +98830,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [4:0] connect \B 1'1 - connect \Y $eq$ls180.v:6063$1669_Y + connect \Y $eq$ls180.v:6059$1668_Y end - attribute \src "ls180.v:6065.100-6065.144" - cell $eq $eq$ls180.v:6065$1672 + attribute \src "ls180.v:6061.100-6061.144" + cell $eq $eq$ls180.v:6061$1671 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -98845,10 +98841,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [4:0] connect \B 2'10 - connect \Y $eq$ls180.v:6065$1672_Y + connect \Y $eq$ls180.v:6061$1671_Y end - attribute \src "ls180.v:6066.103-6066.147" - cell $eq $eq$ls180.v:6066$1676 + attribute \src "ls180.v:6062.103-6062.147" + cell $eq $eq$ls180.v:6062$1675 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -98856,10 +98852,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [4:0] connect \B 2'10 - connect \Y $eq$ls180.v:6066$1676_Y + connect \Y $eq$ls180.v:6062$1675_Y end - attribute \src "ls180.v:6068.100-6068.144" - cell $eq $eq$ls180.v:6068$1679 + attribute \src "ls180.v:6064.100-6064.144" + cell $eq $eq$ls180.v:6064$1678 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -98867,10 +98863,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [4:0] connect \B 2'11 - connect \Y $eq$ls180.v:6068$1679_Y + connect \Y $eq$ls180.v:6064$1678_Y end - attribute \src "ls180.v:6069.103-6069.147" - cell $eq $eq$ls180.v:6069$1683 + attribute \src "ls180.v:6065.103-6065.147" + cell $eq $eq$ls180.v:6065$1682 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -98878,10 +98874,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [4:0] connect \B 2'11 - connect \Y $eq$ls180.v:6069$1683_Y + connect \Y $eq$ls180.v:6065$1682_Y end - attribute \src "ls180.v:6071.100-6071.144" - cell $eq $eq$ls180.v:6071$1686 + attribute \src "ls180.v:6067.100-6067.144" + cell $eq $eq$ls180.v:6067$1685 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -98889,10 +98885,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [4:0] connect \B 3'100 - connect \Y $eq$ls180.v:6071$1686_Y + connect \Y $eq$ls180.v:6067$1685_Y end - attribute \src "ls180.v:6072.103-6072.147" - cell $eq $eq$ls180.v:6072$1690 + attribute \src "ls180.v:6068.103-6068.147" + cell $eq $eq$ls180.v:6068$1689 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -98900,10 +98896,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [4:0] connect \B 3'100 - connect \Y $eq$ls180.v:6072$1690_Y + connect \Y $eq$ls180.v:6068$1689_Y end - attribute \src "ls180.v:6074.100-6074.144" - cell $eq $eq$ls180.v:6074$1693 + attribute \src "ls180.v:6070.100-6070.144" + cell $eq $eq$ls180.v:6070$1692 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -98911,10 +98907,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [4:0] connect \B 3'101 - connect \Y $eq$ls180.v:6074$1693_Y + connect \Y $eq$ls180.v:6070$1692_Y end - attribute \src "ls180.v:6075.103-6075.147" - cell $eq $eq$ls180.v:6075$1697 + attribute \src "ls180.v:6071.103-6071.147" + cell $eq $eq$ls180.v:6071$1696 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -98922,10 +98918,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [4:0] connect \B 3'101 - connect \Y $eq$ls180.v:6075$1697_Y + connect \Y $eq$ls180.v:6071$1696_Y end - attribute \src "ls180.v:6077.100-6077.144" - cell $eq $eq$ls180.v:6077$1700 + attribute \src "ls180.v:6073.100-6073.144" + cell $eq $eq$ls180.v:6073$1699 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -98933,10 +98929,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [4:0] connect \B 3'110 - connect \Y $eq$ls180.v:6077$1700_Y + connect \Y $eq$ls180.v:6073$1699_Y end - attribute \src "ls180.v:6078.103-6078.147" - cell $eq $eq$ls180.v:6078$1704 + attribute \src "ls180.v:6074.103-6074.147" + cell $eq $eq$ls180.v:6074$1703 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -98944,10 +98940,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [4:0] connect \B 3'110 - connect \Y $eq$ls180.v:6078$1704_Y + connect \Y $eq$ls180.v:6074$1703_Y end - attribute \src "ls180.v:6080.100-6080.144" - cell $eq $eq$ls180.v:6080$1707 + attribute \src "ls180.v:6076.100-6076.144" + cell $eq $eq$ls180.v:6076$1706 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -98955,10 +98951,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [4:0] connect \B 3'111 - connect \Y $eq$ls180.v:6080$1707_Y + connect \Y $eq$ls180.v:6076$1706_Y end - attribute \src "ls180.v:6081.103-6081.147" - cell $eq $eq$ls180.v:6081$1711 + attribute \src "ls180.v:6077.103-6077.147" + cell $eq $eq$ls180.v:6077$1710 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -98966,10 +98962,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [4:0] connect \B 3'111 - connect \Y $eq$ls180.v:6081$1711_Y + connect \Y $eq$ls180.v:6077$1710_Y end - attribute \src "ls180.v:6083.102-6083.146" - cell $eq $eq$ls180.v:6083$1714 + attribute \src "ls180.v:6079.102-6079.146" + cell $eq $eq$ls180.v:6079$1713 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -98977,10 +98973,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [4:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6083$1714_Y + connect \Y $eq$ls180.v:6079$1713_Y end - attribute \src "ls180.v:6084.105-6084.149" - cell $eq $eq$ls180.v:6084$1718 + attribute \src "ls180.v:6080.105-6080.149" + cell $eq $eq$ls180.v:6080$1717 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -98988,10 +98984,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [4:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6084$1718_Y + connect \Y $eq$ls180.v:6080$1717_Y end - attribute \src "ls180.v:6086.102-6086.146" - cell $eq $eq$ls180.v:6086$1721 + attribute \src "ls180.v:6082.102-6082.146" + cell $eq $eq$ls180.v:6082$1720 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -98999,10 +98995,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [4:0] connect \B 4'1001 - connect \Y $eq$ls180.v:6086$1721_Y + connect \Y $eq$ls180.v:6082$1720_Y end - attribute \src "ls180.v:6087.105-6087.149" - cell $eq $eq$ls180.v:6087$1725 + attribute \src "ls180.v:6083.105-6083.149" + cell $eq $eq$ls180.v:6083$1724 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -99010,10 +99006,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [4:0] connect \B 4'1001 - connect \Y $eq$ls180.v:6087$1725_Y + connect \Y $eq$ls180.v:6083$1724_Y end - attribute \src "ls180.v:6089.102-6089.147" - cell $eq $eq$ls180.v:6089$1728 + attribute \src "ls180.v:6085.102-6085.147" + cell $eq $eq$ls180.v:6085$1727 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -99021,10 +99017,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [4:0] connect \B 4'1010 - connect \Y $eq$ls180.v:6089$1728_Y + connect \Y $eq$ls180.v:6085$1727_Y end - attribute \src "ls180.v:6090.105-6090.150" - cell $eq $eq$ls180.v:6090$1732 + attribute \src "ls180.v:6086.105-6086.150" + cell $eq $eq$ls180.v:6086$1731 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -99032,10 +99028,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [4:0] connect \B 4'1010 - connect \Y $eq$ls180.v:6090$1732_Y + connect \Y $eq$ls180.v:6086$1731_Y end - attribute \src "ls180.v:6092.102-6092.147" - cell $eq $eq$ls180.v:6092$1735 + attribute \src "ls180.v:6088.102-6088.147" + cell $eq $eq$ls180.v:6088$1734 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -99043,10 +99039,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [4:0] connect \B 4'1011 - connect \Y $eq$ls180.v:6092$1735_Y + connect \Y $eq$ls180.v:6088$1734_Y end - attribute \src "ls180.v:6093.105-6093.150" - cell $eq $eq$ls180.v:6093$1739 + attribute \src "ls180.v:6089.105-6089.150" + cell $eq $eq$ls180.v:6089$1738 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -99054,10 +99050,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [4:0] connect \B 4'1011 - connect \Y $eq$ls180.v:6093$1739_Y + connect \Y $eq$ls180.v:6089$1738_Y end - attribute \src "ls180.v:6095.102-6095.147" - cell $eq $eq$ls180.v:6095$1742 + attribute \src "ls180.v:6091.102-6091.147" + cell $eq $eq$ls180.v:6091$1741 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -99065,10 +99061,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [4:0] connect \B 4'1100 - connect \Y $eq$ls180.v:6095$1742_Y + connect \Y $eq$ls180.v:6091$1741_Y end - attribute \src "ls180.v:6096.105-6096.150" - cell $eq $eq$ls180.v:6096$1746 + attribute \src "ls180.v:6092.105-6092.150" + cell $eq $eq$ls180.v:6092$1745 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -99076,10 +99072,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [4:0] connect \B 4'1100 - connect \Y $eq$ls180.v:6096$1746_Y + connect \Y $eq$ls180.v:6092$1745_Y end - attribute \src "ls180.v:6098.99-6098.144" - cell $eq $eq$ls180.v:6098$1749 + attribute \src "ls180.v:6094.99-6094.144" + cell $eq $eq$ls180.v:6094$1748 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -99087,10 +99083,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [4:0] connect \B 4'1101 - connect \Y $eq$ls180.v:6098$1749_Y + connect \Y $eq$ls180.v:6094$1748_Y end - attribute \src "ls180.v:6099.102-6099.147" - cell $eq $eq$ls180.v:6099$1753 + attribute \src "ls180.v:6095.102-6095.147" + cell $eq $eq$ls180.v:6095$1752 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -99098,10 +99094,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [4:0] connect \B 4'1101 - connect \Y $eq$ls180.v:6099$1753_Y + connect \Y $eq$ls180.v:6095$1752_Y end - attribute \src "ls180.v:6101.100-6101.145" - cell $eq $eq$ls180.v:6101$1756 + attribute \src "ls180.v:6097.100-6097.145" + cell $eq $eq$ls180.v:6097$1755 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -99109,10 +99105,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [4:0] connect \B 4'1110 - connect \Y $eq$ls180.v:6101$1756_Y + connect \Y $eq$ls180.v:6097$1755_Y end - attribute \src "ls180.v:6102.103-6102.148" - cell $eq $eq$ls180.v:6102$1760 + attribute \src "ls180.v:6098.103-6098.148" + cell $eq $eq$ls180.v:6098$1759 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -99120,10 +99116,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [4:0] connect \B 4'1110 - connect \Y $eq$ls180.v:6102$1760_Y + connect \Y $eq$ls180.v:6098$1759_Y end - attribute \src "ls180.v:6104.102-6104.147" - cell $eq $eq$ls180.v:6104$1763 + attribute \src "ls180.v:6100.102-6100.147" + cell $eq $eq$ls180.v:6100$1762 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -99131,10 +99127,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [4:0] connect \B 4'1111 - connect \Y $eq$ls180.v:6104$1763_Y + connect \Y $eq$ls180.v:6100$1762_Y end - attribute \src "ls180.v:6105.105-6105.150" - cell $eq $eq$ls180.v:6105$1767 + attribute \src "ls180.v:6101.105-6101.150" + cell $eq $eq$ls180.v:6101$1766 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -99142,10 +99138,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [4:0] connect \B 4'1111 - connect \Y $eq$ls180.v:6105$1767_Y + connect \Y $eq$ls180.v:6101$1766_Y end - attribute \src "ls180.v:6107.102-6107.147" - cell $eq $eq$ls180.v:6107$1770 + attribute \src "ls180.v:6103.102-6103.147" + cell $eq $eq$ls180.v:6103$1769 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -99153,10 +99149,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [4:0] connect \B 5'10000 - connect \Y $eq$ls180.v:6107$1770_Y + connect \Y $eq$ls180.v:6103$1769_Y end - attribute \src "ls180.v:6108.105-6108.150" - cell $eq $eq$ls180.v:6108$1774 + attribute \src "ls180.v:6104.105-6104.150" + cell $eq $eq$ls180.v:6104$1773 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -99164,10 +99160,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [4:0] connect \B 5'10000 - connect \Y $eq$ls180.v:6108$1774_Y + connect \Y $eq$ls180.v:6104$1773_Y end - attribute \src "ls180.v:6110.102-6110.147" - cell $eq $eq$ls180.v:6110$1777 + attribute \src "ls180.v:6106.102-6106.147" + cell $eq $eq$ls180.v:6106$1776 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -99175,10 +99171,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [4:0] connect \B 5'10001 - connect \Y $eq$ls180.v:6110$1777_Y + connect \Y $eq$ls180.v:6106$1776_Y end - attribute \src "ls180.v:6111.105-6111.150" - cell $eq $eq$ls180.v:6111$1781 + attribute \src "ls180.v:6107.105-6107.150" + cell $eq $eq$ls180.v:6107$1780 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -99186,10 +99182,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [4:0] connect \B 5'10001 - connect \Y $eq$ls180.v:6111$1781_Y + connect \Y $eq$ls180.v:6107$1780_Y end - attribute \src "ls180.v:6113.102-6113.147" - cell $eq $eq$ls180.v:6113$1784 + attribute \src "ls180.v:6109.102-6109.147" + cell $eq $eq$ls180.v:6109$1783 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -99197,10 +99193,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [4:0] connect \B 5'10010 - connect \Y $eq$ls180.v:6113$1784_Y + connect \Y $eq$ls180.v:6109$1783_Y end - attribute \src "ls180.v:6114.105-6114.150" - cell $eq $eq$ls180.v:6114$1788 + attribute \src "ls180.v:6110.105-6110.150" + cell $eq $eq$ls180.v:6110$1787 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -99208,10 +99204,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [4:0] connect \B 5'10010 - connect \Y $eq$ls180.v:6114$1788_Y + connect \Y $eq$ls180.v:6110$1787_Y end - attribute \src "ls180.v:6136.32-6136.78" - cell $eq $eq$ls180.v:6136$1790 + attribute \src "ls180.v:6132.32-6132.78" + cell $eq $eq$ls180.v:6132$1789 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -99219,10 +99215,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [13:9] connect \B 4'1010 - connect \Y $eq$ls180.v:6136$1790_Y + connect \Y $eq$ls180.v:6132$1789_Y end - attribute \src "ls180.v:6138.102-6138.146" - cell $eq $eq$ls180.v:6138$1792 + attribute \src "ls180.v:6134.102-6134.146" + cell $eq $eq$ls180.v:6134$1791 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -99230,10 +99226,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [1:0] connect \B 1'0 - connect \Y $eq$ls180.v:6138$1792_Y + connect \Y $eq$ls180.v:6134$1791_Y end - attribute \src "ls180.v:6139.105-6139.149" - cell $eq $eq$ls180.v:6139$1796 + attribute \src "ls180.v:6135.105-6135.149" + cell $eq $eq$ls180.v:6135$1795 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -99241,10 +99237,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [1:0] connect \B 1'0 - connect \Y $eq$ls180.v:6139$1796_Y + connect \Y $eq$ls180.v:6135$1795_Y end - attribute \src "ls180.v:6141.107-6141.151" - cell $eq $eq$ls180.v:6141$1799 + attribute \src "ls180.v:6137.107-6137.151" + cell $eq $eq$ls180.v:6137$1798 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -99252,10 +99248,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [1:0] connect \B 1'1 - connect \Y $eq$ls180.v:6141$1799_Y + connect \Y $eq$ls180.v:6137$1798_Y end - attribute \src "ls180.v:6142.110-6142.154" - cell $eq $eq$ls180.v:6142$1803 + attribute \src "ls180.v:6138.110-6138.154" + cell $eq $eq$ls180.v:6138$1802 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -99263,10 +99259,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [1:0] connect \B 1'1 - connect \Y $eq$ls180.v:6142$1803_Y + connect \Y $eq$ls180.v:6138$1802_Y end - attribute \src "ls180.v:6144.107-6144.151" - cell $eq $eq$ls180.v:6144$1806 + attribute \src "ls180.v:6140.107-6140.151" + cell $eq $eq$ls180.v:6140$1805 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -99274,10 +99270,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [1:0] connect \B 2'10 - connect \Y $eq$ls180.v:6144$1806_Y + connect \Y $eq$ls180.v:6140$1805_Y end - attribute \src "ls180.v:6145.110-6145.154" - cell $eq $eq$ls180.v:6145$1810 + attribute \src "ls180.v:6141.110-6141.154" + cell $eq $eq$ls180.v:6141$1809 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -99285,10 +99281,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [1:0] connect \B 2'10 - connect \Y $eq$ls180.v:6145$1810_Y + connect \Y $eq$ls180.v:6141$1809_Y end - attribute \src "ls180.v:6147.100-6147.144" - cell $eq $eq$ls180.v:6147$1813 + attribute \src "ls180.v:6143.100-6143.144" + cell $eq $eq$ls180.v:6143$1812 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -99296,10 +99292,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [1:0] connect \B 2'11 - connect \Y $eq$ls180.v:6147$1813_Y + connect \Y $eq$ls180.v:6143$1812_Y end - attribute \src "ls180.v:6148.103-6148.147" - cell $eq $eq$ls180.v:6148$1817 + attribute \src "ls180.v:6144.103-6144.147" + cell $eq $eq$ls180.v:6144$1816 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -99307,10 +99303,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [1:0] connect \B 2'11 - connect \Y $eq$ls180.v:6148$1817_Y + connect \Y $eq$ls180.v:6144$1816_Y end - attribute \src "ls180.v:6153.32-6153.77" - cell $eq $eq$ls180.v:6153$1819 + attribute \src "ls180.v:6149.32-6149.77" + cell $eq $eq$ls180.v:6149$1818 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -99318,10 +99314,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_adr [13:9] connect \B 2'11 - connect \Y $eq$ls180.v:6153$1819_Y + connect \Y $eq$ls180.v:6149$1818_Y end - attribute \src "ls180.v:6155.104-6155.148" - cell $eq $eq$ls180.v:6155$1821 + attribute \src "ls180.v:6151.104-6151.148" + cell $eq $eq$ls180.v:6151$1820 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -99329,10 +99325,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:6155$1821_Y + connect \Y $eq$ls180.v:6151$1820_Y end - attribute \src "ls180.v:6156.107-6156.151" - cell $eq $eq$ls180.v:6156$1825 + attribute \src "ls180.v:6152.107-6152.151" + cell $eq $eq$ls180.v:6152$1824 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -99340,10 +99336,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:6156$1825_Y + connect \Y $eq$ls180.v:6152$1824_Y end - attribute \src "ls180.v:6158.108-6158.152" - cell $eq $eq$ls180.v:6158$1828 + attribute \src "ls180.v:6154.108-6154.152" + cell $eq $eq$ls180.v:6154$1827 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -99351,10 +99347,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:6158$1828_Y + connect \Y $eq$ls180.v:6154$1827_Y end - attribute \src "ls180.v:6159.111-6159.155" - cell $eq $eq$ls180.v:6159$1832 + attribute \src "ls180.v:6155.111-6155.155" + cell $eq $eq$ls180.v:6155$1831 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -99362,10 +99358,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:6159$1832_Y + connect \Y $eq$ls180.v:6155$1831_Y end - attribute \src "ls180.v:6161.98-6161.142" - cell $eq $eq$ls180.v:6161$1835 + attribute \src "ls180.v:6157.98-6157.142" + cell $eq $eq$ls180.v:6157$1834 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -99373,10 +99369,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:6161$1835_Y + connect \Y $eq$ls180.v:6157$1834_Y end - attribute \src "ls180.v:6162.101-6162.145" - cell $eq $eq$ls180.v:6162$1839 + attribute \src "ls180.v:6158.101-6158.145" + cell $eq $eq$ls180.v:6158$1838 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -99384,10 +99380,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:6162$1839_Y + connect \Y $eq$ls180.v:6158$1838_Y end - attribute \src "ls180.v:6164.108-6164.152" - cell $eq $eq$ls180.v:6164$1842 + attribute \src "ls180.v:6160.108-6160.152" + cell $eq $eq$ls180.v:6160$1841 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -99395,10 +99391,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:6164$1842_Y + connect \Y $eq$ls180.v:6160$1841_Y end - attribute \src "ls180.v:6165.111-6165.155" - cell $eq $eq$ls180.v:6165$1846 + attribute \src "ls180.v:6161.111-6161.155" + cell $eq $eq$ls180.v:6161$1845 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -99406,10 +99402,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:6165$1846_Y + connect \Y $eq$ls180.v:6161$1845_Y end - attribute \src "ls180.v:6167.108-6167.152" - cell $eq $eq$ls180.v:6167$1849 + attribute \src "ls180.v:6163.108-6163.152" + cell $eq $eq$ls180.v:6163$1848 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -99417,10 +99413,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:6167$1849_Y + connect \Y $eq$ls180.v:6163$1848_Y end - attribute \src "ls180.v:6168.111-6168.155" - cell $eq $eq$ls180.v:6168$1853 + attribute \src "ls180.v:6164.111-6164.155" + cell $eq $eq$ls180.v:6164$1852 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -99428,10 +99424,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:6168$1853_Y + connect \Y $eq$ls180.v:6164$1852_Y end - attribute \src "ls180.v:6170.109-6170.153" - cell $eq $eq$ls180.v:6170$1856 + attribute \src "ls180.v:6166.109-6166.153" + cell $eq $eq$ls180.v:6166$1855 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -99439,10 +99435,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:6170$1856_Y + connect \Y $eq$ls180.v:6166$1855_Y end - attribute \src "ls180.v:6171.112-6171.156" - cell $eq $eq$ls180.v:6171$1860 + attribute \src "ls180.v:6167.112-6167.156" + cell $eq $eq$ls180.v:6167$1859 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -99450,10 +99446,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:6171$1860_Y + connect \Y $eq$ls180.v:6167$1859_Y end - attribute \src "ls180.v:6173.107-6173.151" - cell $eq $eq$ls180.v:6173$1863 + attribute \src "ls180.v:6169.107-6169.151" + cell $eq $eq$ls180.v:6169$1862 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -99461,10 +99457,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:6173$1863_Y + connect \Y $eq$ls180.v:6169$1862_Y end - attribute \src "ls180.v:6174.110-6174.154" - cell $eq $eq$ls180.v:6174$1867 + attribute \src "ls180.v:6170.110-6170.154" + cell $eq $eq$ls180.v:6170$1866 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -99472,10 +99468,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:6174$1867_Y + connect \Y $eq$ls180.v:6170$1866_Y end - attribute \src "ls180.v:6176.107-6176.151" - cell $eq $eq$ls180.v:6176$1870 + attribute \src "ls180.v:6172.107-6172.151" + cell $eq $eq$ls180.v:6172$1869 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -99483,10 +99479,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:6176$1870_Y + connect \Y $eq$ls180.v:6172$1869_Y end - attribute \src "ls180.v:6177.110-6177.154" - cell $eq $eq$ls180.v:6177$1874 + attribute \src "ls180.v:6173.110-6173.154" + cell $eq $eq$ls180.v:6173$1873 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -99494,10 +99490,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:6177$1874_Y + connect \Y $eq$ls180.v:6173$1873_Y end - attribute \src "ls180.v:6179.107-6179.151" - cell $eq $eq$ls180.v:6179$1877 + attribute \src "ls180.v:6175.107-6175.151" + cell $eq $eq$ls180.v:6175$1876 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -99505,10 +99501,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6179$1877_Y + connect \Y $eq$ls180.v:6175$1876_Y end - attribute \src "ls180.v:6180.110-6180.154" - cell $eq $eq$ls180.v:6180$1881 + attribute \src "ls180.v:6176.110-6176.154" + cell $eq $eq$ls180.v:6176$1880 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -99516,10 +99512,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6180$1881_Y + connect \Y $eq$ls180.v:6176$1880_Y end - attribute \src "ls180.v:6182.107-6182.151" - cell $eq $eq$ls180.v:6182$1884 + attribute \src "ls180.v:6178.107-6178.151" + cell $eq $eq$ls180.v:6178$1883 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -99527,10 +99523,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_adr [3:0] connect \B 4'1001 - connect \Y $eq$ls180.v:6182$1884_Y + connect \Y $eq$ls180.v:6178$1883_Y end - attribute \src "ls180.v:6183.110-6183.154" - cell $eq $eq$ls180.v:6183$1888 + attribute \src "ls180.v:6179.110-6179.154" + cell $eq $eq$ls180.v:6179$1887 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -99538,10 +99534,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_adr [3:0] connect \B 4'1001 - connect \Y $eq$ls180.v:6183$1888_Y + connect \Y $eq$ls180.v:6179$1887_Y end - attribute \src "ls180.v:6198.32-6198.77" - cell $eq $eq$ls180.v:6198$1890 + attribute \src "ls180.v:6194.32-6194.77" + cell $eq $eq$ls180.v:6194$1889 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -99549,10 +99545,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [13:9] connect \B 3'111 - connect \Y $eq$ls180.v:6198$1890_Y + connect \Y $eq$ls180.v:6194$1889_Y end - attribute \src "ls180.v:6200.99-6200.143" - cell $eq $eq$ls180.v:6200$1892 + attribute \src "ls180.v:6196.99-6196.143" + cell $eq $eq$ls180.v:6196$1891 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -99560,10 +99556,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [2:0] connect \B 1'0 - connect \Y $eq$ls180.v:6200$1892_Y + connect \Y $eq$ls180.v:6196$1891_Y end - attribute \src "ls180.v:6201.102-6201.146" - cell $eq $eq$ls180.v:6201$1896 + attribute \src "ls180.v:6197.102-6197.146" + cell $eq $eq$ls180.v:6197$1895 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -99571,10 +99567,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [2:0] connect \B 1'0 - connect \Y $eq$ls180.v:6201$1896_Y + connect \Y $eq$ls180.v:6197$1895_Y end - attribute \src "ls180.v:6203.99-6203.143" - cell $eq $eq$ls180.v:6203$1899 + attribute \src "ls180.v:6199.99-6199.143" + cell $eq $eq$ls180.v:6199$1898 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -99582,10 +99578,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [2:0] connect \B 1'1 - connect \Y $eq$ls180.v:6203$1899_Y + connect \Y $eq$ls180.v:6199$1898_Y end - attribute \src "ls180.v:6204.102-6204.146" - cell $eq $eq$ls180.v:6204$1903 + attribute \src "ls180.v:6200.102-6200.146" + cell $eq $eq$ls180.v:6200$1902 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -99593,10 +99589,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [2:0] connect \B 1'1 - connect \Y $eq$ls180.v:6204$1903_Y + connect \Y $eq$ls180.v:6200$1902_Y end - attribute \src "ls180.v:6206.97-6206.141" - cell $eq $eq$ls180.v:6206$1906 + attribute \src "ls180.v:6202.97-6202.141" + cell $eq $eq$ls180.v:6202$1905 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -99604,10 +99600,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [2:0] connect \B 2'10 - connect \Y $eq$ls180.v:6206$1906_Y + connect \Y $eq$ls180.v:6202$1905_Y end - attribute \src "ls180.v:6207.100-6207.144" - cell $eq $eq$ls180.v:6207$1910 + attribute \src "ls180.v:6203.100-6203.144" + cell $eq $eq$ls180.v:6203$1909 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -99615,10 +99611,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [2:0] connect \B 2'10 - connect \Y $eq$ls180.v:6207$1910_Y + connect \Y $eq$ls180.v:6203$1909_Y end - attribute \src "ls180.v:6209.96-6209.140" - cell $eq $eq$ls180.v:6209$1913 + attribute \src "ls180.v:6205.96-6205.140" + cell $eq $eq$ls180.v:6205$1912 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -99626,10 +99622,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [2:0] connect \B 2'11 - connect \Y $eq$ls180.v:6209$1913_Y + connect \Y $eq$ls180.v:6205$1912_Y end - attribute \src "ls180.v:6210.99-6210.143" - cell $eq $eq$ls180.v:6210$1917 + attribute \src "ls180.v:6206.99-6206.143" + cell $eq $eq$ls180.v:6206$1916 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -99637,10 +99633,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [2:0] connect \B 2'11 - connect \Y $eq$ls180.v:6210$1917_Y + connect \Y $eq$ls180.v:6206$1916_Y end - attribute \src "ls180.v:6212.95-6212.139" - cell $eq $eq$ls180.v:6212$1920 + attribute \src "ls180.v:6208.95-6208.139" + cell $eq $eq$ls180.v:6208$1919 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -99648,10 +99644,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [2:0] connect \B 3'100 - connect \Y $eq$ls180.v:6212$1920_Y + connect \Y $eq$ls180.v:6208$1919_Y end - attribute \src "ls180.v:6213.98-6213.142" - cell $eq $eq$ls180.v:6213$1924 + attribute \src "ls180.v:6209.98-6209.142" + cell $eq $eq$ls180.v:6209$1923 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -99659,10 +99655,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [2:0] connect \B 3'100 - connect \Y $eq$ls180.v:6213$1924_Y + connect \Y $eq$ls180.v:6209$1923_Y end - attribute \src "ls180.v:6215.94-6215.138" - cell $eq $eq$ls180.v:6215$1927 + attribute \src "ls180.v:6211.94-6211.138" + cell $eq $eq$ls180.v:6211$1926 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -99670,10 +99666,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [2:0] connect \B 3'101 - connect \Y $eq$ls180.v:6215$1927_Y + connect \Y $eq$ls180.v:6211$1926_Y end - attribute \src "ls180.v:6216.97-6216.141" - cell $eq $eq$ls180.v:6216$1931 + attribute \src "ls180.v:6212.97-6212.141" + cell $eq $eq$ls180.v:6212$1930 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -99681,10 +99677,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [2:0] connect \B 3'101 - connect \Y $eq$ls180.v:6216$1931_Y + connect \Y $eq$ls180.v:6212$1930_Y end - attribute \src "ls180.v:6218.100-6218.144" - cell $eq $eq$ls180.v:6218$1934 + attribute \src "ls180.v:6214.100-6214.144" + cell $eq $eq$ls180.v:6214$1933 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -99692,10 +99688,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [2:0] connect \B 3'110 - connect \Y $eq$ls180.v:6218$1934_Y + connect \Y $eq$ls180.v:6214$1933_Y end - attribute \src "ls180.v:6219.103-6219.147" - cell $eq $eq$ls180.v:6219$1938 + attribute \src "ls180.v:6215.103-6215.147" + cell $eq $eq$ls180.v:6215$1937 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -99703,10 +99699,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [2:0] connect \B 3'110 - connect \Y $eq$ls180.v:6219$1938_Y + connect \Y $eq$ls180.v:6215$1937_Y end - attribute \src "ls180.v:6238.33-6238.80" - cell $eq $eq$ls180.v:6238$1941 + attribute \src "ls180.v:6234.33-6234.80" + cell $eq $eq$ls180.v:6234$1940 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -99714,10 +99710,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [13:9] connect \B 4'1110 - connect \Y $eq$ls180.v:6238$1941_Y + connect \Y $eq$ls180.v:6234$1940_Y end - attribute \src "ls180.v:6240.102-6240.147" - cell $eq $eq$ls180.v:6240$1943 + attribute \src "ls180.v:6236.102-6236.147" + cell $eq $eq$ls180.v:6236$1942 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -99725,10 +99721,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:6240$1943_Y + connect \Y $eq$ls180.v:6236$1942_Y end - attribute \src "ls180.v:6241.105-6241.150" - cell $eq $eq$ls180.v:6241$1947 + attribute \src "ls180.v:6237.105-6237.150" + cell $eq $eq$ls180.v:6237$1946 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -99736,10 +99732,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:6241$1947_Y + connect \Y $eq$ls180.v:6237$1946_Y end - attribute \src "ls180.v:6243.102-6243.147" - cell $eq $eq$ls180.v:6243$1950 + attribute \src "ls180.v:6239.102-6239.147" + cell $eq $eq$ls180.v:6239$1949 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -99747,10 +99743,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:6243$1950_Y + connect \Y $eq$ls180.v:6239$1949_Y end - attribute \src "ls180.v:6244.105-6244.150" - cell $eq $eq$ls180.v:6244$1954 + attribute \src "ls180.v:6240.105-6240.150" + cell $eq $eq$ls180.v:6240$1953 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -99758,10 +99754,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:6244$1954_Y + connect \Y $eq$ls180.v:6240$1953_Y end - attribute \src "ls180.v:6246.100-6246.145" - cell $eq $eq$ls180.v:6246$1957 + attribute \src "ls180.v:6242.100-6242.145" + cell $eq $eq$ls180.v:6242$1956 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -99769,10 +99765,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:6246$1957_Y + connect \Y $eq$ls180.v:6242$1956_Y end - attribute \src "ls180.v:6247.103-6247.148" - cell $eq $eq$ls180.v:6247$1961 + attribute \src "ls180.v:6243.103-6243.148" + cell $eq $eq$ls180.v:6243$1960 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -99780,10 +99776,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:6247$1961_Y + connect \Y $eq$ls180.v:6243$1960_Y end - attribute \src "ls180.v:6249.99-6249.144" - cell $eq $eq$ls180.v:6249$1964 + attribute \src "ls180.v:6245.99-6245.144" + cell $eq $eq$ls180.v:6245$1963 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -99791,10 +99787,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:6249$1964_Y + connect \Y $eq$ls180.v:6245$1963_Y end - attribute \src "ls180.v:6250.102-6250.147" - cell $eq $eq$ls180.v:6250$1968 + attribute \src "ls180.v:6246.102-6246.147" + cell $eq $eq$ls180.v:6246$1967 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -99802,10 +99798,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:6250$1968_Y + connect \Y $eq$ls180.v:6246$1967_Y end - attribute \src "ls180.v:6252.98-6252.143" - cell $eq $eq$ls180.v:6252$1971 + attribute \src "ls180.v:6248.98-6248.143" + cell $eq $eq$ls180.v:6248$1970 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -99813,10 +99809,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:6252$1971_Y + connect \Y $eq$ls180.v:6248$1970_Y end - attribute \src "ls180.v:6253.101-6253.146" - cell $eq $eq$ls180.v:6253$1975 + attribute \src "ls180.v:6249.101-6249.146" + cell $eq $eq$ls180.v:6249$1974 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -99824,10 +99820,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:6253$1975_Y + connect \Y $eq$ls180.v:6249$1974_Y end - attribute \src "ls180.v:6255.97-6255.142" - cell $eq $eq$ls180.v:6255$1978 + attribute \src "ls180.v:6251.97-6251.142" + cell $eq $eq$ls180.v:6251$1977 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -99835,10 +99831,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:6255$1978_Y + connect \Y $eq$ls180.v:6251$1977_Y end - attribute \src "ls180.v:6256.100-6256.145" - cell $eq $eq$ls180.v:6256$1982 + attribute \src "ls180.v:6252.100-6252.145" + cell $eq $eq$ls180.v:6252$1981 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -99846,10 +99842,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:6256$1982_Y + connect \Y $eq$ls180.v:6252$1981_Y end - attribute \src "ls180.v:6258.103-6258.148" - cell $eq $eq$ls180.v:6258$1985 + attribute \src "ls180.v:6254.103-6254.148" + cell $eq $eq$ls180.v:6254$1984 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -99857,10 +99853,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:6258$1985_Y + connect \Y $eq$ls180.v:6254$1984_Y end - attribute \src "ls180.v:6259.106-6259.151" - cell $eq $eq$ls180.v:6259$1989 + attribute \src "ls180.v:6255.106-6255.151" + cell $eq $eq$ls180.v:6255$1988 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -99868,10 +99864,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:6259$1989_Y + connect \Y $eq$ls180.v:6255$1988_Y end - attribute \src "ls180.v:6261.106-6261.151" - cell $eq $eq$ls180.v:6261$1992 + attribute \src "ls180.v:6257.106-6257.151" + cell $eq $eq$ls180.v:6257$1991 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -99879,10 +99875,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:6261$1992_Y + connect \Y $eq$ls180.v:6257$1991_Y end - attribute \src "ls180.v:6262.109-6262.154" - cell $eq $eq$ls180.v:6262$1996 + attribute \src "ls180.v:6258.109-6258.154" + cell $eq $eq$ls180.v:6258$1995 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -99890,10 +99886,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:6262$1996_Y + connect \Y $eq$ls180.v:6258$1995_Y end - attribute \src "ls180.v:6264.106-6264.151" - cell $eq $eq$ls180.v:6264$1999 + attribute \src "ls180.v:6260.106-6260.151" + cell $eq $eq$ls180.v:6260$1998 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -99901,10 +99897,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6264$1999_Y + connect \Y $eq$ls180.v:6260$1998_Y end - attribute \src "ls180.v:6265.109-6265.154" - cell $eq $eq$ls180.v:6265$2003 + attribute \src "ls180.v:6261.109-6261.154" + cell $eq $eq$ls180.v:6261$2002 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -99912,10 +99908,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6265$2003_Y + connect \Y $eq$ls180.v:6261$2002_Y end - attribute \src "ls180.v:6286.33-6286.79" - cell $eq $eq$ls180.v:6286$2006 + attribute \src "ls180.v:6282.33-6282.79" + cell $eq $eq$ls180.v:6282$2005 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -99923,10 +99919,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [13:9] connect \B 2'10 - connect \Y $eq$ls180.v:6286$2006_Y + connect \Y $eq$ls180.v:6282$2005_Y end - attribute \src "ls180.v:6288.99-6288.144" - cell $eq $eq$ls180.v:6288$2008 + attribute \src "ls180.v:6284.99-6284.144" + cell $eq $eq$ls180.v:6284$2007 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -99934,10 +99930,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [4:0] connect \B 1'0 - connect \Y $eq$ls180.v:6288$2008_Y + connect \Y $eq$ls180.v:6284$2007_Y end - attribute \src "ls180.v:6289.102-6289.147" - cell $eq $eq$ls180.v:6289$2012 + attribute \src "ls180.v:6285.102-6285.147" + cell $eq $eq$ls180.v:6285$2011 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -99945,10 +99941,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [4:0] connect \B 1'0 - connect \Y $eq$ls180.v:6289$2012_Y + connect \Y $eq$ls180.v:6285$2011_Y end - attribute \src "ls180.v:6291.99-6291.144" - cell $eq $eq$ls180.v:6291$2015 + attribute \src "ls180.v:6287.99-6287.144" + cell $eq $eq$ls180.v:6287$2014 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -99956,10 +99952,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [4:0] connect \B 1'1 - connect \Y $eq$ls180.v:6291$2015_Y + connect \Y $eq$ls180.v:6287$2014_Y end - attribute \src "ls180.v:6292.102-6292.147" - cell $eq $eq$ls180.v:6292$2019 + attribute \src "ls180.v:6288.102-6288.147" + cell $eq $eq$ls180.v:6288$2018 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -99967,10 +99963,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [4:0] connect \B 1'1 - connect \Y $eq$ls180.v:6292$2019_Y + connect \Y $eq$ls180.v:6288$2018_Y end - attribute \src "ls180.v:6294.99-6294.144" - cell $eq $eq$ls180.v:6294$2022 + attribute \src "ls180.v:6290.99-6290.144" + cell $eq $eq$ls180.v:6290$2021 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -99978,10 +99974,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [4:0] connect \B 2'10 - connect \Y $eq$ls180.v:6294$2022_Y + connect \Y $eq$ls180.v:6290$2021_Y end - attribute \src "ls180.v:6295.102-6295.147" - cell $eq $eq$ls180.v:6295$2026 + attribute \src "ls180.v:6291.102-6291.147" + cell $eq $eq$ls180.v:6291$2025 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -99989,10 +99985,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [4:0] connect \B 2'10 - connect \Y $eq$ls180.v:6295$2026_Y + connect \Y $eq$ls180.v:6291$2025_Y end - attribute \src "ls180.v:6297.99-6297.144" - cell $eq $eq$ls180.v:6297$2029 + attribute \src "ls180.v:6293.99-6293.144" + cell $eq $eq$ls180.v:6293$2028 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -100000,10 +99996,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [4:0] connect \B 2'11 - connect \Y $eq$ls180.v:6297$2029_Y + connect \Y $eq$ls180.v:6293$2028_Y end - attribute \src "ls180.v:6298.102-6298.147" - cell $eq $eq$ls180.v:6298$2033 + attribute \src "ls180.v:6294.102-6294.147" + cell $eq $eq$ls180.v:6294$2032 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -100011,10 +100007,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [4:0] connect \B 2'11 - connect \Y $eq$ls180.v:6298$2033_Y + connect \Y $eq$ls180.v:6294$2032_Y end - attribute \src "ls180.v:6300.101-6300.146" - cell $eq $eq$ls180.v:6300$2036 + attribute \src "ls180.v:6296.101-6296.146" + cell $eq $eq$ls180.v:6296$2035 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -100022,10 +100018,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [4:0] connect \B 3'100 - connect \Y $eq$ls180.v:6300$2036_Y + connect \Y $eq$ls180.v:6296$2035_Y end - attribute \src "ls180.v:6301.104-6301.149" - cell $eq $eq$ls180.v:6301$2040 + attribute \src "ls180.v:6297.104-6297.149" + cell $eq $eq$ls180.v:6297$2039 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -100033,10 +100029,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [4:0] connect \B 3'100 - connect \Y $eq$ls180.v:6301$2040_Y + connect \Y $eq$ls180.v:6297$2039_Y end - attribute \src "ls180.v:6303.101-6303.146" - cell $eq $eq$ls180.v:6303$2043 + attribute \src "ls180.v:6299.101-6299.146" + cell $eq $eq$ls180.v:6299$2042 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -100044,10 +100040,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [4:0] connect \B 3'101 - connect \Y $eq$ls180.v:6303$2043_Y + connect \Y $eq$ls180.v:6299$2042_Y end - attribute \src "ls180.v:6304.104-6304.149" - cell $eq $eq$ls180.v:6304$2047 + attribute \src "ls180.v:6300.104-6300.149" + cell $eq $eq$ls180.v:6300$2046 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -100055,10 +100051,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [4:0] connect \B 3'101 - connect \Y $eq$ls180.v:6304$2047_Y + connect \Y $eq$ls180.v:6300$2046_Y end - attribute \src "ls180.v:6306.101-6306.146" - cell $eq $eq$ls180.v:6306$2050 + attribute \src "ls180.v:6302.101-6302.146" + cell $eq $eq$ls180.v:6302$2049 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -100066,10 +100062,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [4:0] connect \B 3'110 - connect \Y $eq$ls180.v:6306$2050_Y + connect \Y $eq$ls180.v:6302$2049_Y end - attribute \src "ls180.v:6307.104-6307.149" - cell $eq $eq$ls180.v:6307$2054 + attribute \src "ls180.v:6303.104-6303.149" + cell $eq $eq$ls180.v:6303$2053 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -100077,10 +100073,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [4:0] connect \B 3'110 - connect \Y $eq$ls180.v:6307$2054_Y + connect \Y $eq$ls180.v:6303$2053_Y end - attribute \src "ls180.v:6309.101-6309.146" - cell $eq $eq$ls180.v:6309$2057 + attribute \src "ls180.v:6305.101-6305.146" + cell $eq $eq$ls180.v:6305$2056 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -100088,10 +100084,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [4:0] connect \B 3'111 - connect \Y $eq$ls180.v:6309$2057_Y + connect \Y $eq$ls180.v:6305$2056_Y end - attribute \src "ls180.v:6310.104-6310.149" - cell $eq $eq$ls180.v:6310$2061 + attribute \src "ls180.v:6306.104-6306.149" + cell $eq $eq$ls180.v:6306$2060 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -100099,10 +100095,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [4:0] connect \B 3'111 - connect \Y $eq$ls180.v:6310$2061_Y + connect \Y $eq$ls180.v:6306$2060_Y end - attribute \src "ls180.v:6312.97-6312.142" - cell $eq $eq$ls180.v:6312$2064 + attribute \src "ls180.v:6308.97-6308.142" + cell $eq $eq$ls180.v:6308$2063 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -100110,10 +100106,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [4:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6312$2064_Y + connect \Y $eq$ls180.v:6308$2063_Y end - attribute \src "ls180.v:6313.100-6313.145" - cell $eq $eq$ls180.v:6313$2068 + attribute \src "ls180.v:6309.100-6309.145" + cell $eq $eq$ls180.v:6309$2067 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -100121,10 +100117,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [4:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6313$2068_Y + connect \Y $eq$ls180.v:6309$2067_Y end - attribute \src "ls180.v:6315.107-6315.152" - cell $eq $eq$ls180.v:6315$2071 + attribute \src "ls180.v:6311.107-6311.152" + cell $eq $eq$ls180.v:6311$2070 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -100132,10 +100128,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [4:0] connect \B 4'1001 - connect \Y $eq$ls180.v:6315$2071_Y + connect \Y $eq$ls180.v:6311$2070_Y end - attribute \src "ls180.v:6316.110-6316.155" - cell $eq $eq$ls180.v:6316$2075 + attribute \src "ls180.v:6312.110-6312.155" + cell $eq $eq$ls180.v:6312$2074 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -100143,10 +100139,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [4:0] connect \B 4'1001 - connect \Y $eq$ls180.v:6316$2075_Y + connect \Y $eq$ls180.v:6312$2074_Y end - attribute \src "ls180.v:6318.100-6318.146" - cell $eq $eq$ls180.v:6318$2078 + attribute \src "ls180.v:6314.100-6314.146" + cell $eq $eq$ls180.v:6314$2077 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -100154,10 +100150,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [4:0] connect \B 4'1010 - connect \Y $eq$ls180.v:6318$2078_Y + connect \Y $eq$ls180.v:6314$2077_Y end - attribute \src "ls180.v:6319.103-6319.149" - cell $eq $eq$ls180.v:6319$2082 + attribute \src "ls180.v:6315.103-6315.149" + cell $eq $eq$ls180.v:6315$2081 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -100165,10 +100161,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [4:0] connect \B 4'1010 - connect \Y $eq$ls180.v:6319$2082_Y + connect \Y $eq$ls180.v:6315$2081_Y end - attribute \src "ls180.v:6321.100-6321.146" - cell $eq $eq$ls180.v:6321$2085 + attribute \src "ls180.v:6317.100-6317.146" + cell $eq $eq$ls180.v:6317$2084 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -100176,10 +100172,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [4:0] connect \B 4'1011 - connect \Y $eq$ls180.v:6321$2085_Y + connect \Y $eq$ls180.v:6317$2084_Y end - attribute \src "ls180.v:6322.103-6322.149" - cell $eq $eq$ls180.v:6322$2089 + attribute \src "ls180.v:6318.103-6318.149" + cell $eq $eq$ls180.v:6318$2088 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -100187,10 +100183,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [4:0] connect \B 4'1011 - connect \Y $eq$ls180.v:6322$2089_Y + connect \Y $eq$ls180.v:6318$2088_Y end - attribute \src "ls180.v:6324.100-6324.146" - cell $eq $eq$ls180.v:6324$2092 + attribute \src "ls180.v:6320.100-6320.146" + cell $eq $eq$ls180.v:6320$2091 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -100198,10 +100194,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [4:0] connect \B 4'1100 - connect \Y $eq$ls180.v:6324$2092_Y + connect \Y $eq$ls180.v:6320$2091_Y end - attribute \src "ls180.v:6325.103-6325.149" - cell $eq $eq$ls180.v:6325$2096 + attribute \src "ls180.v:6321.103-6321.149" + cell $eq $eq$ls180.v:6321$2095 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -100209,10 +100205,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [4:0] connect \B 4'1100 - connect \Y $eq$ls180.v:6325$2096_Y + connect \Y $eq$ls180.v:6321$2095_Y end - attribute \src "ls180.v:6327.100-6327.146" - cell $eq $eq$ls180.v:6327$2099 + attribute \src "ls180.v:6323.100-6323.146" + cell $eq $eq$ls180.v:6323$2098 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -100220,10 +100216,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [4:0] connect \B 4'1101 - connect \Y $eq$ls180.v:6327$2099_Y + connect \Y $eq$ls180.v:6323$2098_Y end - attribute \src "ls180.v:6328.103-6328.149" - cell $eq $eq$ls180.v:6328$2103 + attribute \src "ls180.v:6324.103-6324.149" + cell $eq $eq$ls180.v:6324$2102 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -100231,10 +100227,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [4:0] connect \B 4'1101 - connect \Y $eq$ls180.v:6328$2103_Y + connect \Y $eq$ls180.v:6324$2102_Y end - attribute \src "ls180.v:6330.112-6330.158" - cell $eq $eq$ls180.v:6330$2106 + attribute \src "ls180.v:6326.112-6326.158" + cell $eq $eq$ls180.v:6326$2105 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -100242,10 +100238,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [4:0] connect \B 4'1110 - connect \Y $eq$ls180.v:6330$2106_Y + connect \Y $eq$ls180.v:6326$2105_Y end - attribute \src "ls180.v:6331.115-6331.161" - cell $eq $eq$ls180.v:6331$2110 + attribute \src "ls180.v:6327.115-6327.161" + cell $eq $eq$ls180.v:6327$2109 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -100253,10 +100249,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [4:0] connect \B 4'1110 - connect \Y $eq$ls180.v:6331$2110_Y + connect \Y $eq$ls180.v:6327$2109_Y end - attribute \src "ls180.v:6333.113-6333.159" - cell $eq $eq$ls180.v:6333$2113 + attribute \src "ls180.v:6329.113-6329.159" + cell $eq $eq$ls180.v:6329$2112 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -100264,10 +100260,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [4:0] connect \B 4'1111 - connect \Y $eq$ls180.v:6333$2113_Y + connect \Y $eq$ls180.v:6329$2112_Y end - attribute \src "ls180.v:6334.116-6334.162" - cell $eq $eq$ls180.v:6334$2117 + attribute \src "ls180.v:6330.116-6330.162" + cell $eq $eq$ls180.v:6330$2116 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -100275,10 +100271,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [4:0] connect \B 4'1111 - connect \Y $eq$ls180.v:6334$2117_Y + connect \Y $eq$ls180.v:6330$2116_Y end - attribute \src "ls180.v:6336.104-6336.150" - cell $eq $eq$ls180.v:6336$2120 + attribute \src "ls180.v:6332.104-6332.150" + cell $eq $eq$ls180.v:6332$2119 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -100286,10 +100282,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [4:0] connect \B 5'10000 - connect \Y $eq$ls180.v:6336$2120_Y + connect \Y $eq$ls180.v:6332$2119_Y end - attribute \src "ls180.v:6337.107-6337.153" - cell $eq $eq$ls180.v:6337$2124 + attribute \src "ls180.v:6333.107-6333.153" + cell $eq $eq$ls180.v:6333$2123 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -100297,10 +100293,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [4:0] connect \B 5'10000 - connect \Y $eq$ls180.v:6337$2124_Y + connect \Y $eq$ls180.v:6333$2123_Y end - attribute \src "ls180.v:6354.33-6354.79" - cell $eq $eq$ls180.v:6354$2126 + attribute \src "ls180.v:6350.33-6350.79" + cell $eq $eq$ls180.v:6350$2125 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -100308,10 +100304,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [13:9] connect \B 3'101 - connect \Y $eq$ls180.v:6354$2126_Y + connect \Y $eq$ls180.v:6350$2125_Y end - attribute \src "ls180.v:6356.90-6356.135" - cell $eq $eq$ls180.v:6356$2128 + attribute \src "ls180.v:6352.90-6352.135" + cell $eq $eq$ls180.v:6352$2127 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -100319,10 +100315,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [2:0] connect \B 1'0 - connect \Y $eq$ls180.v:6356$2128_Y + connect \Y $eq$ls180.v:6352$2127_Y end - attribute \src "ls180.v:6357.93-6357.138" - cell $eq $eq$ls180.v:6357$2132 + attribute \src "ls180.v:6353.93-6353.138" + cell $eq $eq$ls180.v:6353$2131 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -100330,10 +100326,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [2:0] connect \B 1'0 - connect \Y $eq$ls180.v:6357$2132_Y + connect \Y $eq$ls180.v:6353$2131_Y end - attribute \src "ls180.v:6359.100-6359.145" - cell $eq $eq$ls180.v:6359$2135 + attribute \src "ls180.v:6355.100-6355.145" + cell $eq $eq$ls180.v:6355$2134 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -100341,10 +100337,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [2:0] connect \B 1'1 - connect \Y $eq$ls180.v:6359$2135_Y + connect \Y $eq$ls180.v:6355$2134_Y end - attribute \src "ls180.v:6360.103-6360.148" - cell $eq $eq$ls180.v:6360$2139 + attribute \src "ls180.v:6356.103-6356.148" + cell $eq $eq$ls180.v:6356$2138 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -100352,10 +100348,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [2:0] connect \B 1'1 - connect \Y $eq$ls180.v:6360$2139_Y + connect \Y $eq$ls180.v:6356$2138_Y end - attribute \src "ls180.v:6362.101-6362.146" - cell $eq $eq$ls180.v:6362$2142 + attribute \src "ls180.v:6358.101-6358.146" + cell $eq $eq$ls180.v:6358$2141 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -100363,10 +100359,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [2:0] connect \B 2'10 - connect \Y $eq$ls180.v:6362$2142_Y + connect \Y $eq$ls180.v:6358$2141_Y end - attribute \src "ls180.v:6363.104-6363.149" - cell $eq $eq$ls180.v:6363$2146 + attribute \src "ls180.v:6359.104-6359.149" + cell $eq $eq$ls180.v:6359$2145 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -100374,10 +100370,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [2:0] connect \B 2'10 - connect \Y $eq$ls180.v:6363$2146_Y + connect \Y $eq$ls180.v:6359$2145_Y end - attribute \src "ls180.v:6365.105-6365.150" - cell $eq $eq$ls180.v:6365$2149 + attribute \src "ls180.v:6361.105-6361.150" + cell $eq $eq$ls180.v:6361$2148 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -100385,10 +100381,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [2:0] connect \B 2'11 - connect \Y $eq$ls180.v:6365$2149_Y + connect \Y $eq$ls180.v:6361$2148_Y end - attribute \src "ls180.v:6366.108-6366.153" - cell $eq $eq$ls180.v:6366$2153 + attribute \src "ls180.v:6362.108-6362.153" + cell $eq $eq$ls180.v:6362$2152 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -100396,10 +100392,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [2:0] connect \B 2'11 - connect \Y $eq$ls180.v:6366$2153_Y + connect \Y $eq$ls180.v:6362$2152_Y end - attribute \src "ls180.v:6368.106-6368.151" - cell $eq $eq$ls180.v:6368$2156 + attribute \src "ls180.v:6364.106-6364.151" + cell $eq $eq$ls180.v:6364$2155 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -100407,10 +100403,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [2:0] connect \B 3'100 - connect \Y $eq$ls180.v:6368$2156_Y + connect \Y $eq$ls180.v:6364$2155_Y end - attribute \src "ls180.v:6369.109-6369.154" - cell $eq $eq$ls180.v:6369$2160 + attribute \src "ls180.v:6365.109-6365.154" + cell $eq $eq$ls180.v:6365$2159 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -100418,10 +100414,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [2:0] connect \B 3'100 - connect \Y $eq$ls180.v:6369$2160_Y + connect \Y $eq$ls180.v:6365$2159_Y end - attribute \src "ls180.v:6371.104-6371.149" - cell $eq $eq$ls180.v:6371$2163 + attribute \src "ls180.v:6367.104-6367.149" + cell $eq $eq$ls180.v:6367$2162 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -100429,10 +100425,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [2:0] connect \B 3'101 - connect \Y $eq$ls180.v:6371$2163_Y + connect \Y $eq$ls180.v:6367$2162_Y end - attribute \src "ls180.v:6372.107-6372.152" - cell $eq $eq$ls180.v:6372$2167 + attribute \src "ls180.v:6368.107-6368.152" + cell $eq $eq$ls180.v:6368$2166 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -100440,10 +100436,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [2:0] connect \B 3'101 - connect \Y $eq$ls180.v:6372$2167_Y + connect \Y $eq$ls180.v:6368$2166_Y end - attribute \src "ls180.v:6374.101-6374.146" - cell $eq $eq$ls180.v:6374$2170 + attribute \src "ls180.v:6370.101-6370.146" + cell $eq $eq$ls180.v:6370$2169 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -100451,10 +100447,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [2:0] connect \B 3'110 - connect \Y $eq$ls180.v:6374$2170_Y + connect \Y $eq$ls180.v:6370$2169_Y end - attribute \src "ls180.v:6375.104-6375.149" - cell $eq $eq$ls180.v:6375$2174 + attribute \src "ls180.v:6371.104-6371.149" + cell $eq $eq$ls180.v:6371$2173 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -100462,10 +100458,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [2:0] connect \B 3'110 - connect \Y $eq$ls180.v:6375$2174_Y + connect \Y $eq$ls180.v:6371$2173_Y end - attribute \src "ls180.v:6377.100-6377.145" - cell $eq $eq$ls180.v:6377$2177 + attribute \src "ls180.v:6373.100-6373.145" + cell $eq $eq$ls180.v:6373$2176 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -100473,10 +100469,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [2:0] connect \B 3'111 - connect \Y $eq$ls180.v:6377$2177_Y + connect \Y $eq$ls180.v:6373$2176_Y end - attribute \src "ls180.v:6378.103-6378.148" - cell $eq $eq$ls180.v:6378$2181 + attribute \src "ls180.v:6374.103-6374.148" + cell $eq $eq$ls180.v:6374$2180 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -100484,10 +100480,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [2:0] connect \B 3'111 - connect \Y $eq$ls180.v:6378$2181_Y + connect \Y $eq$ls180.v:6374$2180_Y end - attribute \src "ls180.v:6388.33-6388.79" - cell $eq $eq$ls180.v:6388$2183 + attribute \src "ls180.v:6384.33-6384.79" + cell $eq $eq$ls180.v:6384$2182 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -100495,10 +100491,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [13:9] connect \B 3'100 - connect \Y $eq$ls180.v:6388$2183_Y + connect \Y $eq$ls180.v:6384$2182_Y end - attribute \src "ls180.v:6390.106-6390.151" - cell $eq $eq$ls180.v:6390$2185 + attribute \src "ls180.v:6386.106-6386.151" + cell $eq $eq$ls180.v:6386$2184 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -100506,10 +100502,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [1:0] connect \B 1'0 - connect \Y $eq$ls180.v:6390$2185_Y + connect \Y $eq$ls180.v:6386$2184_Y end - attribute \src "ls180.v:6391.109-6391.154" - cell $eq $eq$ls180.v:6391$2189 + attribute \src "ls180.v:6387.109-6387.154" + cell $eq $eq$ls180.v:6387$2188 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -100517,10 +100513,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [1:0] connect \B 1'0 - connect \Y $eq$ls180.v:6391$2189_Y + connect \Y $eq$ls180.v:6387$2188_Y end - attribute \src "ls180.v:6393.106-6393.151" - cell $eq $eq$ls180.v:6393$2192 + attribute \src "ls180.v:6389.106-6389.151" + cell $eq $eq$ls180.v:6389$2191 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -100528,10 +100524,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [1:0] connect \B 1'1 - connect \Y $eq$ls180.v:6393$2192_Y + connect \Y $eq$ls180.v:6389$2191_Y end - attribute \src "ls180.v:6394.109-6394.154" - cell $eq $eq$ls180.v:6394$2196 + attribute \src "ls180.v:6390.109-6390.154" + cell $eq $eq$ls180.v:6390$2195 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -100539,10 +100535,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [1:0] connect \B 1'1 - connect \Y $eq$ls180.v:6394$2196_Y + connect \Y $eq$ls180.v:6390$2195_Y end - attribute \src "ls180.v:6396.106-6396.151" - cell $eq $eq$ls180.v:6396$2199 + attribute \src "ls180.v:6392.106-6392.151" + cell $eq $eq$ls180.v:6392$2198 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -100550,10 +100546,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [1:0] connect \B 2'10 - connect \Y $eq$ls180.v:6396$2199_Y + connect \Y $eq$ls180.v:6392$2198_Y end - attribute \src "ls180.v:6397.109-6397.154" - cell $eq $eq$ls180.v:6397$2203 + attribute \src "ls180.v:6393.109-6393.154" + cell $eq $eq$ls180.v:6393$2202 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -100561,10 +100557,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [1:0] connect \B 2'10 - connect \Y $eq$ls180.v:6397$2203_Y + connect \Y $eq$ls180.v:6393$2202_Y end - attribute \src "ls180.v:6399.106-6399.151" - cell $eq $eq$ls180.v:6399$2206 + attribute \src "ls180.v:6395.106-6395.151" + cell $eq $eq$ls180.v:6395$2205 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -100572,10 +100568,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [1:0] connect \B 2'11 - connect \Y $eq$ls180.v:6399$2206_Y + connect \Y $eq$ls180.v:6395$2205_Y end - attribute \src "ls180.v:6400.109-6400.154" - cell $eq $eq$ls180.v:6400$2210 + attribute \src "ls180.v:6396.109-6396.154" + cell $eq $eq$ls180.v:6396$2209 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -100583,10 +100579,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [1:0] connect \B 2'11 - connect \Y $eq$ls180.v:6400$2210_Y + connect \Y $eq$ls180.v:6396$2209_Y end - attribute \src "ls180.v:6778.41-6778.81" - cell $eq $eq$ls180.v:6778$2246 + attribute \src "ls180.v:6774.41-6774.81" + cell $eq $eq$ls180.v:6774$2245 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -100594,10 +100590,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 1'0 - connect \Y $eq$ls180.v:6778$2246_Y + connect \Y $eq$ls180.v:6774$2245_Y end - attribute \src "ls180.v:6778.144-6778.177" - cell $eq $eq$ls180.v:6778$2247 + attribute \src "ls180.v:6774.144-6774.177" + cell $eq $eq$ls180.v:6774$2246 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -100605,10 +100601,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:6778$2247_Y + connect \Y $eq$ls180.v:6774$2246_Y end - attribute \src "ls180.v:6778.219-6778.252" - cell $eq $eq$ls180.v:6778$2250 + attribute \src "ls180.v:6774.219-6774.252" + cell $eq $eq$ls180.v:6774$2249 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -100616,10 +100612,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:6778$2250_Y + connect \Y $eq$ls180.v:6774$2249_Y end - attribute \src "ls180.v:6778.294-6778.327" - cell $eq $eq$ls180.v:6778$2253 + attribute \src "ls180.v:6774.294-6774.327" + cell $eq $eq$ls180.v:6774$2252 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -100627,10 +100623,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:6778$2253_Y + connect \Y $eq$ls180.v:6774$2252_Y end - attribute \src "ls180.v:6802.41-6802.81" - cell $eq $eq$ls180.v:6802$2262 + attribute \src "ls180.v:6798.41-6798.81" + cell $eq $eq$ls180.v:6798$2261 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -100638,10 +100634,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 1'1 - connect \Y $eq$ls180.v:6802$2262_Y + connect \Y $eq$ls180.v:6798$2261_Y end - attribute \src "ls180.v:6802.144-6802.177" - cell $eq $eq$ls180.v:6802$2263 + attribute \src "ls180.v:6798.144-6798.177" + cell $eq $eq$ls180.v:6798$2262 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -100649,10 +100645,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:6802$2263_Y + connect \Y $eq$ls180.v:6798$2262_Y end - attribute \src "ls180.v:6802.219-6802.252" - cell $eq $eq$ls180.v:6802$2266 + attribute \src "ls180.v:6798.219-6798.252" + cell $eq $eq$ls180.v:6798$2265 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -100660,10 +100656,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:6802$2266_Y + connect \Y $eq$ls180.v:6798$2265_Y end - attribute \src "ls180.v:6802.294-6802.327" - cell $eq $eq$ls180.v:6802$2269 + attribute \src "ls180.v:6798.294-6798.327" + cell $eq $eq$ls180.v:6798$2268 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -100671,10 +100667,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:6802$2269_Y + connect \Y $eq$ls180.v:6798$2268_Y end - attribute \src "ls180.v:6826.41-6826.81" - cell $eq $eq$ls180.v:6826$2278 + attribute \src "ls180.v:6822.41-6822.81" + cell $eq $eq$ls180.v:6822$2277 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -100682,10 +100678,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 2'10 - connect \Y $eq$ls180.v:6826$2278_Y + connect \Y $eq$ls180.v:6822$2277_Y end - attribute \src "ls180.v:6826.144-6826.177" - cell $eq $eq$ls180.v:6826$2279 + attribute \src "ls180.v:6822.144-6822.177" + cell $eq $eq$ls180.v:6822$2278 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -100693,10 +100689,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:6826$2279_Y + connect \Y $eq$ls180.v:6822$2278_Y end - attribute \src "ls180.v:6826.219-6826.252" - cell $eq $eq$ls180.v:6826$2282 + attribute \src "ls180.v:6822.219-6822.252" + cell $eq $eq$ls180.v:6822$2281 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -100704,10 +100700,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:6826$2282_Y + connect \Y $eq$ls180.v:6822$2281_Y end - attribute \src "ls180.v:6826.294-6826.327" - cell $eq $eq$ls180.v:6826$2285 + attribute \src "ls180.v:6822.294-6822.327" + cell $eq $eq$ls180.v:6822$2284 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -100715,10 +100711,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:6826$2285_Y + connect \Y $eq$ls180.v:6822$2284_Y end - attribute \src "ls180.v:6850.41-6850.81" - cell $eq $eq$ls180.v:6850$2294 + attribute \src "ls180.v:6846.41-6846.81" + cell $eq $eq$ls180.v:6846$2293 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -100726,10 +100722,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 2'11 - connect \Y $eq$ls180.v:6850$2294_Y + connect \Y $eq$ls180.v:6846$2293_Y end - attribute \src "ls180.v:6850.144-6850.177" - cell $eq $eq$ls180.v:6850$2295 + attribute \src "ls180.v:6846.144-6846.177" + cell $eq $eq$ls180.v:6846$2294 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -100737,10 +100733,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:6850$2295_Y + connect \Y $eq$ls180.v:6846$2294_Y end - attribute \src "ls180.v:6850.219-6850.252" - cell $eq $eq$ls180.v:6850$2298 + attribute \src "ls180.v:6846.219-6846.252" + cell $eq $eq$ls180.v:6846$2297 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -100748,10 +100744,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:6850$2298_Y + connect \Y $eq$ls180.v:6846$2297_Y end - attribute \src "ls180.v:6850.294-6850.327" - cell $eq $eq$ls180.v:6850$2301 + attribute \src "ls180.v:6846.294-6846.327" + cell $eq $eq$ls180.v:6846$2300 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -100759,10 +100755,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:6850$2301_Y + connect \Y $eq$ls180.v:6846$2300_Y end - attribute \src "ls180.v:7446.8-7446.38" - cell $eq $eq$ls180.v:7446$2411 + attribute \src "ls180.v:7445.8-7445.38" + cell $eq $eq$ls180.v:7445$2409 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -100770,10 +100766,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_value connect \B 1'0 - connect \Y $eq$ls180.v:7446$2411_Y + connect \Y $eq$ls180.v:7445$2409_Y end - attribute \src "ls180.v:7479.8-7479.42" - cell $eq $eq$ls180.v:7479$2419 + attribute \src "ls180.v:7476.8-7476.42" + cell $eq $eq$ls180.v:7476$2417 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -100781,10 +100777,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_postponer_count connect \B 1'0 - connect \Y $eq$ls180.v:7479$2419_Y + connect \Y $eq$ls180.v:7476$2417_Y end - attribute \src "ls180.v:7499.38-7499.74" - cell $eq $eq$ls180.v:7499$2422 + attribute \src "ls180.v:7496.38-7496.74" + cell $eq $eq$ls180.v:7496$2420 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -100792,10 +100788,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_counter connect \B 1'0 - connect \Y $eq$ls180.v:7499$2422_Y + connect \Y $eq$ls180.v:7496$2420_Y end - attribute \src "ls180.v:7506.7-7506.43" - cell $eq $eq$ls180.v:7506$2424 + attribute \src "ls180.v:7503.7-7503.43" + cell $eq $eq$ls180.v:7503$2422 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -100803,10 +100799,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_counter connect \B 2'10 - connect \Y $eq$ls180.v:7506$2424_Y + connect \Y $eq$ls180.v:7503$2422_Y end - attribute \src "ls180.v:7513.7-7513.43" - cell $eq $eq$ls180.v:7513$2425 + attribute \src "ls180.v:7510.7-7510.43" + cell $eq $eq$ls180.v:7510$2423 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -100814,10 +100810,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_counter connect \B 4'1000 - connect \Y $eq$ls180.v:7513$2425_Y + connect \Y $eq$ls180.v:7510$2423_Y end - attribute \src "ls180.v:7521.7-7521.43" - cell $eq $eq$ls180.v:7521$2426 + attribute \src "ls180.v:7518.7-7518.43" + cell $eq $eq$ls180.v:7518$2424 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -100825,10 +100821,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_counter connect \B 4'1000 - connect \Y $eq$ls180.v:7521$2426_Y + connect \Y $eq$ls180.v:7518$2424_Y end - attribute \src "ls180.v:7573.9-7573.54" - cell $eq $eq$ls180.v:7573$2444 + attribute \src "ls180.v:7570.9-7570.54" + cell $eq $eq$ls180.v:7570$2442 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -100836,10 +100832,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_twtpcon_count connect \B 1'1 - connect \Y $eq$ls180.v:7573$2444_Y + connect \Y $eq$ls180.v:7570$2442_Y end - attribute \src "ls180.v:7619.9-7619.54" - cell $eq $eq$ls180.v:7619$2460 + attribute \src "ls180.v:7616.9-7616.54" + cell $eq $eq$ls180.v:7616$2458 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -100847,10 +100843,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_twtpcon_count connect \B 1'1 - connect \Y $eq$ls180.v:7619$2460_Y + connect \Y $eq$ls180.v:7616$2458_Y end - attribute \src "ls180.v:7665.9-7665.54" - cell $eq $eq$ls180.v:7665$2476 + attribute \src "ls180.v:7662.9-7662.54" + cell $eq $eq$ls180.v:7662$2474 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -100858,10 +100854,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_twtpcon_count connect \B 1'1 - connect \Y $eq$ls180.v:7665$2476_Y + connect \Y $eq$ls180.v:7662$2474_Y end - attribute \src "ls180.v:7711.9-7711.54" - cell $eq $eq$ls180.v:7711$2492 + attribute \src "ls180.v:7708.9-7708.54" + cell $eq $eq$ls180.v:7708$2490 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -100869,10 +100865,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_twtpcon_count connect \B 1'1 - connect \Y $eq$ls180.v:7711$2492_Y + connect \Y $eq$ls180.v:7708$2490_Y end - attribute \src "ls180.v:7861.9-7861.41" - cell $eq $eq$ls180.v:7861$2504 + attribute \src "ls180.v:7858.9-7858.41" + cell $eq $eq$ls180.v:7858$2502 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -100880,10 +100876,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_tccdcon_count connect \B 1'1 - connect \Y $eq$ls180.v:7861$2504_Y + connect \Y $eq$ls180.v:7858$2502_Y end - attribute \src "ls180.v:7876.9-7876.41" - cell $eq $eq$ls180.v:7876$2507 + attribute \src "ls180.v:7873.9-7873.41" + cell $eq $eq$ls180.v:7873$2505 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -100891,10 +100887,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_twtrcon_count connect \B 1'1 - connect \Y $eq$ls180.v:7876$2507_Y + connect \Y $eq$ls180.v:7873$2505_Y end - attribute \src "ls180.v:7882.49-7882.82" - cell $eq $eq$ls180.v:7882$2508 + attribute \src "ls180.v:7879.49-7879.82" + cell $eq $eq$ls180.v:7879$2506 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -100902,10 +100898,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:7882$2508_Y + connect \Y $eq$ls180.v:7879$2506_Y end - attribute \src "ls180.v:7882.131-7882.164" - cell $eq $eq$ls180.v:7882$2511 + attribute \src "ls180.v:7879.131-7879.164" + cell $eq $eq$ls180.v:7879$2509 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -100913,10 +100909,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:7882$2511_Y + connect \Y $eq$ls180.v:7879$2509_Y end - attribute \src "ls180.v:7882.213-7882.246" - cell $eq $eq$ls180.v:7882$2514 + attribute \src "ls180.v:7879.213-7879.246" + cell $eq $eq$ls180.v:7879$2512 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -100924,10 +100920,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:7882$2514_Y + connect \Y $eq$ls180.v:7879$2512_Y end - attribute \src "ls180.v:7882.295-7882.328" - cell $eq $eq$ls180.v:7882$2517 + attribute \src "ls180.v:7879.295-7879.328" + cell $eq $eq$ls180.v:7879$2515 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -100935,10 +100931,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:7882$2517_Y + connect \Y $eq$ls180.v:7879$2515_Y end - attribute \src "ls180.v:7883.50-7883.83" - cell $eq $eq$ls180.v:7883$2520 + attribute \src "ls180.v:7880.50-7880.83" + cell $eq $eq$ls180.v:7880$2518 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -100946,10 +100942,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:7883$2520_Y + connect \Y $eq$ls180.v:7880$2518_Y end - attribute \src "ls180.v:7883.132-7883.165" - cell $eq $eq$ls180.v:7883$2523 + attribute \src "ls180.v:7880.132-7880.165" + cell $eq $eq$ls180.v:7880$2521 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -100957,10 +100953,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:7883$2523_Y + connect \Y $eq$ls180.v:7880$2521_Y end - attribute \src "ls180.v:7883.214-7883.247" - cell $eq $eq$ls180.v:7883$2526 + attribute \src "ls180.v:7880.214-7880.247" + cell $eq $eq$ls180.v:7880$2524 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -100968,10 +100964,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:7883$2526_Y + connect \Y $eq$ls180.v:7880$2524_Y end - attribute \src "ls180.v:7883.296-7883.329" - cell $eq $eq$ls180.v:7883$2529 + attribute \src "ls180.v:7880.296-7880.329" + cell $eq $eq$ls180.v:7880$2527 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -100979,10 +100975,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:7883$2529_Y + connect \Y $eq$ls180.v:7880$2527_Y end - attribute \src "ls180.v:7918.9-7918.33" - cell $eq $eq$ls180.v:7918$2541 + attribute \src "ls180.v:7915.9-7915.33" + cell $eq $eq$ls180.v:7915$2539 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -100990,10 +100986,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_tx_bitcount connect \B 4'1000 - connect \Y $eq$ls180.v:7918$2541_Y + connect \Y $eq$ls180.v:7915$2539_Y end - attribute \src "ls180.v:7921.10-7921.34" - cell $eq $eq$ls180.v:7921$2542 + attribute \src "ls180.v:7918.10-7918.34" + cell $eq $eq$ls180.v:7918$2540 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -101001,10 +100997,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_tx_bitcount connect \B 4'1001 - connect \Y $eq$ls180.v:7921$2542_Y + connect \Y $eq$ls180.v:7918$2540_Y end - attribute \src "ls180.v:7947.9-7947.33" - cell $eq $eq$ls180.v:7947$2548 + attribute \src "ls180.v:7944.9-7944.33" + cell $eq $eq$ls180.v:7944$2546 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -101012,10 +101008,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_rx_bitcount connect \B 1'0 - connect \Y $eq$ls180.v:7947$2548_Y + connect \Y $eq$ls180.v:7944$2546_Y end - attribute \src "ls180.v:7952.10-7952.34" - cell $eq $eq$ls180.v:7952$2549 + attribute \src "ls180.v:7949.10-7949.34" + cell $eq $eq$ls180.v:7949$2547 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -101023,10 +101019,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_rx_bitcount connect \B 4'1001 - connect \Y $eq$ls180.v:7952$2549_Y + connect \Y $eq$ls180.v:7949$2547_Y end - attribute \src "ls180.v:8124.9-8124.53" - cell $eq $eq$ls180.v:8124$2593 + attribute \src "ls180.v:8121.9-8121.53" + cell $eq $eq$ls180.v:8121$2591 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -101034,10 +101030,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_demux connect \B 3'111 - connect \Y $eq$ls180.v:8124$2593_Y + connect \Y $eq$ls180.v:8121$2591_Y end - attribute \src "ls180.v:8205.9-8205.54" - cell $eq $eq$ls180.v:8205$2605 + attribute \src "ls180.v:8202.9-8202.54" + cell $eq $eq$ls180.v:8202$2603 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -101045,10 +101041,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_demux connect \B 3'111 - connect \Y $eq$ls180.v:8205$2605_Y + connect \Y $eq$ls180.v:8202$2603_Y end - attribute \src "ls180.v:8284.9-8284.55" - cell $eq $eq$ls180.v:8284$2617 + attribute \src "ls180.v:8281.9-8281.55" + cell $eq $eq$ls180.v:8281$2615 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -101056,10 +101052,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_demux connect \B 1'1 - connect \Y $eq$ls180.v:8284$2617_Y + connect \Y $eq$ls180.v:8281$2615_Y end - attribute \src "ls180.v:8507.9-8507.49" - cell $eq $eq$ls180.v:8507$2650 + attribute \src "ls180.v:8504.9-8504.49" + cell $eq $eq$ls180.v:8504$2648 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -101067,32 +101063,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_demux connect \B 2'11 - connect \Y $eq$ls180.v:8507$2650_Y + connect \Y $eq$ls180.v:8504$2648_Y end - attribute \src "ls180.v:8083.8-8083.54" - cell $ge $ge$ls180.v:8083$2585 + attribute \src "ls180.v:8080.8-8080.54" + cell $ge $ge$ls180.v:8080$2583 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 1 connect \A \main_pwm0_counter - connect \B $sub$ls180.v:8083$2584_Y - connect \Y $ge$ls180.v:8083$2585_Y + connect \B $sub$ls180.v:8080$2582_Y + connect \Y $ge$ls180.v:8080$2583_Y end - attribute \src "ls180.v:8097.8-8097.54" - cell $ge $ge$ls180.v:8097$2589 + attribute \src "ls180.v:8094.8-8094.54" + cell $ge $ge$ls180.v:8094$2587 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 1 connect \A \main_pwm1_counter - connect \B $sub$ls180.v:8097$2588_Y - connect \Y $ge$ls180.v:8097$2589_Y + connect \B $sub$ls180.v:8094$2586_Y + connect \Y $ge$ls180.v:8094$2587_Y end - attribute \src "ls180.v:5045.47-5045.83" - cell $gt $gt$ls180.v:5045$907 + attribute \src "ls180.v:5041.47-5041.83" + cell $gt $gt$ls180.v:5041$906 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -101100,10 +101096,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_cnt connect \B 3'111 - connect \Y $gt$ls180.v:5045$907_Y + connect \Y $gt$ls180.v:5041$906_Y end - attribute \src "ls180.v:5051.7-5051.43" - cell $lt $lt$ls180.v:5051$910 + attribute \src "ls180.v:5047.7-5047.43" + cell $lt $lt$ls180.v:5047$909 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -101111,10 +101107,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_cnt connect \B 4'1000 - connect \Y $lt$ls180.v:5051$910_Y + connect \Y $lt$ls180.v:5047$909_Y end - attribute \src "ls180.v:8078.8-8078.43" - cell $lt $lt$ls180.v:8078$2583 + attribute \src "ls180.v:8075.8-8075.43" + cell $lt $lt$ls180.v:8075$2581 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -101122,10 +101118,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_pwm0_counter connect \B \main_pwm0_width - connect \Y $lt$ls180.v:8078$2583_Y + connect \Y $lt$ls180.v:8075$2581_Y end - attribute \src "ls180.v:8092.8-8092.43" - cell $lt $lt$ls180.v:8092$2587 + attribute \src "ls180.v:8089.8-8089.43" + cell $lt $lt$ls180.v:8089$2585 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -101133,10 +101129,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_pwm1_counter connect \B \main_pwm1_width - connect \Y $lt$ls180.v:8092$2587_Y + connect \Y $lt$ls180.v:8089$2585_Y end - attribute \src "ls180.v:9993.33-9993.36" - cell $memrd $memrd$\mem$ls180.v:9993$2697 + attribute \src "ls180.v:9989.33-9989.36" + cell $memrd $memrd$\mem$ls180.v:9989$2695 parameter \ABITS 7 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -101145,11 +101141,11 @@ module \ls180 parameter \WIDTH 32 connect \ADDR \memadr connect \CLK 1'x - connect \DATA $memrd$\mem$ls180.v:9993$2697_DATA + connect \DATA $memrd$\mem$ls180.v:9989$2695_DATA connect \EN 1'x end - attribute \src "ls180.v:10004.12-10004.19" - cell $memrd $memrd$\storage$ls180.v:10004$2702 + attribute \src "ls180.v:10000.12-10000.19" + cell $memrd $memrd$\storage$ls180.v:10000$2700 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -101158,11 +101154,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage$ls180.v:10004$2702_DATA + connect \DATA $memrd$\storage$ls180.v:10000$2700_DATA connect \EN 1'x end - attribute \src "ls180.v:10011.68-10011.75" - cell $memrd $memrd$\storage$ls180.v:10011$2704 + attribute \src "ls180.v:10007.68-10007.75" + cell $memrd $memrd$\storage$ls180.v:10007$2702 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -101171,11 +101167,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage$ls180.v:10011$2704_DATA + connect \DATA $memrd$\storage$ls180.v:10007$2702_DATA connect \EN 1'x end - attribute \src "ls180.v:10018.14-10018.23" - cell $memrd $memrd$\storage_1$ls180.v:10018$2709 + attribute \src "ls180.v:10014.14-10014.23" + cell $memrd $memrd$\storage_1$ls180.v:10014$2707 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -101184,11 +101180,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_1$ls180.v:10018$2709_DATA + connect \DATA $memrd$\storage_1$ls180.v:10014$2707_DATA connect \EN 1'x end - attribute \src "ls180.v:10025.68-10025.77" - cell $memrd $memrd$\storage_1$ls180.v:10025$2711 + attribute \src "ls180.v:10021.68-10021.77" + cell $memrd $memrd$\storage_1$ls180.v:10021$2709 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -101197,11 +101193,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_1$ls180.v:10025$2711_DATA + connect \DATA $memrd$\storage_1$ls180.v:10021$2709_DATA connect \EN 1'x end - attribute \src "ls180.v:10032.14-10032.23" - cell $memrd $memrd$\storage_2$ls180.v:10032$2716 + attribute \src "ls180.v:10028.14-10028.23" + cell $memrd $memrd$\storage_2$ls180.v:10028$2714 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -101210,11 +101206,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_2$ls180.v:10032$2716_DATA + connect \DATA $memrd$\storage_2$ls180.v:10028$2714_DATA connect \EN 1'x end - attribute \src "ls180.v:10039.68-10039.77" - cell $memrd $memrd$\storage_2$ls180.v:10039$2718 + attribute \src "ls180.v:10035.68-10035.77" + cell $memrd $memrd$\storage_2$ls180.v:10035$2716 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -101223,11 +101219,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_2$ls180.v:10039$2718_DATA + connect \DATA $memrd$\storage_2$ls180.v:10035$2716_DATA connect \EN 1'x end - attribute \src "ls180.v:10046.14-10046.23" - cell $memrd $memrd$\storage_3$ls180.v:10046$2723 + attribute \src "ls180.v:10042.14-10042.23" + cell $memrd $memrd$\storage_3$ls180.v:10042$2721 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -101236,11 +101232,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_3$ls180.v:10046$2723_DATA + connect \DATA $memrd$\storage_3$ls180.v:10042$2721_DATA connect \EN 1'x end - attribute \src "ls180.v:10053.68-10053.77" - cell $memrd $memrd$\storage_3$ls180.v:10053$2725 + attribute \src "ls180.v:10049.68-10049.77" + cell $memrd $memrd$\storage_3$ls180.v:10049$2723 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -101249,11 +101245,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_3$ls180.v:10053$2725_DATA + connect \DATA $memrd$\storage_3$ls180.v:10049$2723_DATA connect \EN 1'x end - attribute \src "ls180.v:10061.14-10061.23" - cell $memrd $memrd$\storage_4$ls180.v:10061$2730 + attribute \src "ls180.v:10057.14-10057.23" + cell $memrd $memrd$\storage_4$ls180.v:10057$2728 parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -101262,11 +101258,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_uart_tx_fifo_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_4$ls180.v:10061$2730_DATA + connect \DATA $memrd$\storage_4$ls180.v:10057$2728_DATA connect \EN 1'x end - attribute \src "ls180.v:10066.15-10066.24" - cell $memrd $memrd$\storage_4$ls180.v:10066$2732 + attribute \src "ls180.v:10062.15-10062.24" + cell $memrd $memrd$\storage_4$ls180.v:10062$2730 parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -101275,11 +101271,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_uart_tx_fifo_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_4$ls180.v:10066$2732_DATA + connect \DATA $memrd$\storage_4$ls180.v:10062$2730_DATA connect \EN 1'x end - attribute \src "ls180.v:10078.14-10078.23" - cell $memrd $memrd$\storage_5$ls180.v:10078$2737 + attribute \src "ls180.v:10074.14-10074.23" + cell $memrd $memrd$\storage_5$ls180.v:10074$2735 parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -101288,11 +101284,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_uart_rx_fifo_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_5$ls180.v:10078$2737_DATA + connect \DATA $memrd$\storage_5$ls180.v:10074$2735_DATA connect \EN 1'x end - attribute \src "ls180.v:10083.15-10083.24" - cell $memrd $memrd$\storage_5$ls180.v:10083$2739 + attribute \src "ls180.v:10079.15-10079.24" + cell $memrd $memrd$\storage_5$ls180.v:10079$2737 parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -101301,11 +101297,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_uart_rx_fifo_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_5$ls180.v:10083$2739_DATA + connect \DATA $memrd$\storage_5$ls180.v:10079$2737_DATA connect \EN 1'x end - attribute \src "ls180.v:10094.14-10094.23" - cell $memrd $memrd$\storage_6$ls180.v:10094$2744 + attribute \src "ls180.v:10090.14-10090.23" + cell $memrd $memrd$\storage_6$ls180.v:10090$2742 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -101314,11 +101310,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_sdblock2mem_fifo_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_6$ls180.v:10094$2744_DATA + connect \DATA $memrd$\storage_6$ls180.v:10090$2742_DATA connect \EN 1'x end - attribute \src "ls180.v:10101.45-10101.54" - cell $memrd $memrd$\storage_6$ls180.v:10101$2746 + attribute \src "ls180.v:10097.45-10097.54" + cell $memrd $memrd$\storage_6$ls180.v:10097$2744 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -101327,11 +101323,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_sdblock2mem_fifo_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_6$ls180.v:10101$2746_DATA + connect \DATA $memrd$\storage_6$ls180.v:10097$2744_DATA connect \EN 1'x end - attribute \src "ls180.v:10108.14-10108.23" - cell $memrd $memrd$\storage_7$ls180.v:10108$2751 + attribute \src "ls180.v:10104.14-10104.23" + cell $memrd $memrd$\storage_7$ls180.v:10104$2749 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -101340,11 +101336,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_sdmem2block_fifo_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_7$ls180.v:10108$2751_DATA + connect \DATA $memrd$\storage_7$ls180.v:10104$2749_DATA connect \EN 1'x end - attribute \src "ls180.v:10115.45-10115.54" - cell $memrd $memrd$\storage_7$ls180.v:10115$2753 + attribute \src "ls180.v:10111.45-10111.54" + cell $memrd $memrd$\storage_7$ls180.v:10111$2751 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -101353,167 +101349,167 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_sdmem2block_fifo_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_7$ls180.v:10115$2753_DATA + connect \DATA $memrd$\storage_7$ls180.v:10111$2751_DATA connect \EN 1'x end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$2755 + cell $memwr $memwr$\mem$ls180.v:0$2753 parameter \ABITS 7 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem" - parameter \PRIORITY 2755 + parameter \PRIORITY 2753 parameter \WIDTH 32 - connect \ADDR $memwr$\mem$ls180.v:9983$1_ADDR + connect \ADDR $memwr$\mem$ls180.v:9979$1_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:9983$1_DATA - connect \EN $memwr$\mem$ls180.v:9983$1_EN + connect \DATA $memwr$\mem$ls180.v:9979$1_DATA + connect \EN $memwr$\mem$ls180.v:9979$1_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$2756 + cell $memwr $memwr$\mem$ls180.v:0$2754 parameter \ABITS 7 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem" - parameter \PRIORITY 2756 + parameter \PRIORITY 2754 parameter \WIDTH 32 - connect \ADDR $memwr$\mem$ls180.v:9985$2_ADDR + connect \ADDR $memwr$\mem$ls180.v:9981$2_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:9985$2_DATA - connect \EN $memwr$\mem$ls180.v:9985$2_EN + connect \DATA $memwr$\mem$ls180.v:9981$2_DATA + connect \EN $memwr$\mem$ls180.v:9981$2_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$2757 + cell $memwr $memwr$\mem$ls180.v:0$2755 parameter \ABITS 7 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem" - parameter \PRIORITY 2757 + parameter \PRIORITY 2755 parameter \WIDTH 32 - connect \ADDR $memwr$\mem$ls180.v:9987$3_ADDR + connect \ADDR $memwr$\mem$ls180.v:9983$3_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:9987$3_DATA - connect \EN $memwr$\mem$ls180.v:9987$3_EN + connect \DATA $memwr$\mem$ls180.v:9983$3_DATA + connect \EN $memwr$\mem$ls180.v:9983$3_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$2758 + cell $memwr $memwr$\mem$ls180.v:0$2756 parameter \ABITS 7 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem" - parameter \PRIORITY 2758 + parameter \PRIORITY 2756 parameter \WIDTH 32 - connect \ADDR $memwr$\mem$ls180.v:9989$4_ADDR + connect \ADDR $memwr$\mem$ls180.v:9985$4_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:9989$4_DATA - connect \EN $memwr$\mem$ls180.v:9989$4_EN + connect \DATA $memwr$\mem$ls180.v:9985$4_DATA + connect \EN $memwr$\mem$ls180.v:9985$4_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage$ls180.v:0$2759 + cell $memwr $memwr$\storage$ls180.v:0$2757 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage" - parameter \PRIORITY 2759 + parameter \PRIORITY 2757 parameter \WIDTH 25 - connect \ADDR $memwr$\storage$ls180.v:10003$5_ADDR + connect \ADDR $memwr$\storage$ls180.v:9999$5_ADDR connect \CLK 1'x - connect \DATA $memwr$\storage$ls180.v:10003$5_DATA - connect \EN $memwr$\storage$ls180.v:10003$5_EN + connect \DATA $memwr$\storage$ls180.v:9999$5_DATA + connect \EN $memwr$\storage$ls180.v:9999$5_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_1$ls180.v:0$2760 + cell $memwr $memwr$\storage_1$ls180.v:0$2758 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_1" - parameter \PRIORITY 2760 + parameter \PRIORITY 2758 parameter \WIDTH 25 - connect \ADDR $memwr$\storage_1$ls180.v:10017$6_ADDR + connect \ADDR $memwr$\storage_1$ls180.v:10013$6_ADDR connect \CLK 1'x - connect \DATA $memwr$\storage_1$ls180.v:10017$6_DATA - connect \EN $memwr$\storage_1$ls180.v:10017$6_EN + connect \DATA $memwr$\storage_1$ls180.v:10013$6_DATA + connect \EN $memwr$\storage_1$ls180.v:10013$6_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_2$ls180.v:0$2761 + cell $memwr $memwr$\storage_2$ls180.v:0$2759 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_2" - parameter \PRIORITY 2761 + parameter \PRIORITY 2759 parameter \WIDTH 25 - connect \ADDR $memwr$\storage_2$ls180.v:10031$7_ADDR + connect \ADDR $memwr$\storage_2$ls180.v:10027$7_ADDR connect \CLK 1'x - connect \DATA $memwr$\storage_2$ls180.v:10031$7_DATA - connect \EN $memwr$\storage_2$ls180.v:10031$7_EN + connect \DATA $memwr$\storage_2$ls180.v:10027$7_DATA + connect \EN $memwr$\storage_2$ls180.v:10027$7_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_3$ls180.v:0$2762 + cell $memwr $memwr$\storage_3$ls180.v:0$2760 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_3" - parameter \PRIORITY 2762 + parameter \PRIORITY 2760 parameter \WIDTH 25 - connect \ADDR $memwr$\storage_3$ls180.v:10045$8_ADDR + connect \ADDR $memwr$\storage_3$ls180.v:10041$8_ADDR connect \CLK 1'x - connect \DATA $memwr$\storage_3$ls180.v:10045$8_DATA - connect \EN $memwr$\storage_3$ls180.v:10045$8_EN + connect \DATA $memwr$\storage_3$ls180.v:10041$8_DATA + connect \EN $memwr$\storage_3$ls180.v:10041$8_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_4$ls180.v:0$2763 + cell $memwr $memwr$\storage_4$ls180.v:0$2761 parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_4" - parameter \PRIORITY 2763 + parameter \PRIORITY 2761 parameter \WIDTH 10 - connect \ADDR $memwr$\storage_4$ls180.v:10060$9_ADDR + connect \ADDR $memwr$\storage_4$ls180.v:10056$9_ADDR connect \CLK 1'x - connect \DATA $memwr$\storage_4$ls180.v:10060$9_DATA - connect \EN $memwr$\storage_4$ls180.v:10060$9_EN + connect \DATA $memwr$\storage_4$ls180.v:10056$9_DATA + connect \EN $memwr$\storage_4$ls180.v:10056$9_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_5$ls180.v:0$2764 + cell $memwr $memwr$\storage_5$ls180.v:0$2762 parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_5" - parameter \PRIORITY 2764 + parameter \PRIORITY 2762 parameter \WIDTH 10 - connect \ADDR $memwr$\storage_5$ls180.v:10077$10_ADDR + connect \ADDR $memwr$\storage_5$ls180.v:10073$10_ADDR connect \CLK 1'x - connect \DATA $memwr$\storage_5$ls180.v:10077$10_DATA - connect \EN $memwr$\storage_5$ls180.v:10077$10_EN + connect \DATA $memwr$\storage_5$ls180.v:10073$10_DATA + connect \EN $memwr$\storage_5$ls180.v:10073$10_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_6$ls180.v:0$2765 + cell $memwr $memwr$\storage_6$ls180.v:0$2763 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_6" - parameter \PRIORITY 2765 + parameter \PRIORITY 2763 parameter \WIDTH 10 - connect \ADDR $memwr$\storage_6$ls180.v:10093$11_ADDR + connect \ADDR $memwr$\storage_6$ls180.v:10089$11_ADDR connect \CLK 1'x - connect \DATA $memwr$\storage_6$ls180.v:10093$11_DATA - connect \EN $memwr$\storage_6$ls180.v:10093$11_EN + connect \DATA $memwr$\storage_6$ls180.v:10089$11_DATA + connect \EN $memwr$\storage_6$ls180.v:10089$11_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_7$ls180.v:0$2766 + cell $memwr $memwr$\storage_7$ls180.v:0$2764 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_7" - parameter \PRIORITY 2766 + parameter \PRIORITY 2764 parameter \WIDTH 10 - connect \ADDR $memwr$\storage_7$ls180.v:10107$12_ADDR + connect \ADDR $memwr$\storage_7$ls180.v:10103$12_ADDR connect \CLK 1'x - connect \DATA $memwr$\storage_7$ls180.v:10107$12_DATA - connect \EN $memwr$\storage_7$ls180.v:10107$12_EN + connect \DATA $memwr$\storage_7$ls180.v:10103$12_DATA + connect \EN $memwr$\storage_7$ls180.v:10103$12_EN end - attribute \src "ls180.v:2917.41-2917.71" - cell $ne $ne$ls180.v:2917$60 + attribute \src "ls180.v:2918.41-2918.71" + cell $ne $ne$ls180.v:2918$60 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -101521,10 +101517,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_value connect \B 1'0 - connect \Y $ne$ls180.v:2917$60_Y + connect \Y $ne$ls180.v:2918$60_Y end - attribute \src "ls180.v:3083.70-3083.104" - cell $ne $ne$ls180.v:3083$75 + attribute \src "ls180.v:3079.70-3079.104" + cell $ne $ne$ls180.v:3079$74 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -101532,10 +101528,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_count connect \B 1'0 - connect \Y $ne$ls180.v:3083$75_Y + connect \Y $ne$ls180.v:3079$74_Y end - attribute \src "ls180.v:3144.8-3144.142" - cell $ne $ne$ls180.v:3144$94 + attribute \src "ls180.v:3140.8-3140.142" + cell $ne $ne$ls180.v:3140$93 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -101543,10 +101539,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr [21:9] connect \B \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] - connect \Y $ne$ls180.v:3144$94_Y + connect \Y $ne$ls180.v:3140$93_Y end - attribute \src "ls180.v:3176.75-3176.133" - cell $ne $ne$ls180.v:3176$101 + attribute \src "ls180.v:3172.75-3172.133" + cell $ne $ne$ls180.v:3172$100 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -101554,10 +101550,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level connect \B 4'1000 - connect \Y $ne$ls180.v:3176$101_Y + connect \Y $ne$ls180.v:3172$100_Y end - attribute \src "ls180.v:3177.75-3177.133" - cell $ne $ne$ls180.v:3177$102 + attribute \src "ls180.v:3173.75-3173.133" + cell $ne $ne$ls180.v:3173$101 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -101565,10 +101561,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level connect \B 1'0 - connect \Y $ne$ls180.v:3177$102_Y + connect \Y $ne$ls180.v:3173$101_Y end - attribute \src "ls180.v:3301.8-3301.142" - cell $ne $ne$ls180.v:3301$124 + attribute \src "ls180.v:3297.8-3297.142" + cell $ne $ne$ls180.v:3297$123 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -101576,10 +101572,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr [21:9] connect \B \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] - connect \Y $ne$ls180.v:3301$124_Y + connect \Y $ne$ls180.v:3297$123_Y end - attribute \src "ls180.v:3333.75-3333.133" - cell $ne $ne$ls180.v:3333$131 + attribute \src "ls180.v:3329.75-3329.133" + cell $ne $ne$ls180.v:3329$130 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -101587,10 +101583,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level connect \B 4'1000 - connect \Y $ne$ls180.v:3333$131_Y + connect \Y $ne$ls180.v:3329$130_Y end - attribute \src "ls180.v:3334.75-3334.133" - cell $ne $ne$ls180.v:3334$132 + attribute \src "ls180.v:3330.75-3330.133" + cell $ne $ne$ls180.v:3330$131 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -101598,10 +101594,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level connect \B 1'0 - connect \Y $ne$ls180.v:3334$132_Y + connect \Y $ne$ls180.v:3330$131_Y end - attribute \src "ls180.v:3458.8-3458.142" - cell $ne $ne$ls180.v:3458$154 + attribute \src "ls180.v:3454.8-3454.142" + cell $ne $ne$ls180.v:3454$153 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -101609,10 +101605,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr [21:9] connect \B \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] - connect \Y $ne$ls180.v:3458$154_Y + connect \Y $ne$ls180.v:3454$153_Y end - attribute \src "ls180.v:3490.75-3490.133" - cell $ne $ne$ls180.v:3490$161 + attribute \src "ls180.v:3486.75-3486.133" + cell $ne $ne$ls180.v:3486$160 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -101620,10 +101616,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level connect \B 4'1000 - connect \Y $ne$ls180.v:3490$161_Y + connect \Y $ne$ls180.v:3486$160_Y end - attribute \src "ls180.v:3491.75-3491.133" - cell $ne $ne$ls180.v:3491$162 + attribute \src "ls180.v:3487.75-3487.133" + cell $ne $ne$ls180.v:3487$161 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -101631,10 +101627,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level connect \B 1'0 - connect \Y $ne$ls180.v:3491$162_Y + connect \Y $ne$ls180.v:3487$161_Y end - attribute \src "ls180.v:3615.8-3615.142" - cell $ne $ne$ls180.v:3615$184 + attribute \src "ls180.v:3611.8-3611.142" + cell $ne $ne$ls180.v:3611$183 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -101642,10 +101638,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr [21:9] connect \B \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] - connect \Y $ne$ls180.v:3615$184_Y + connect \Y $ne$ls180.v:3611$183_Y end - attribute \src "ls180.v:3647.75-3647.133" - cell $ne $ne$ls180.v:3647$191 + attribute \src "ls180.v:3643.75-3643.133" + cell $ne $ne$ls180.v:3643$190 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -101653,10 +101649,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level connect \B 4'1000 - connect \Y $ne$ls180.v:3647$191_Y + connect \Y $ne$ls180.v:3643$190_Y end - attribute \src "ls180.v:3648.75-3648.133" - cell $ne $ne$ls180.v:3648$192 + attribute \src "ls180.v:3644.75-3644.133" + cell $ne $ne$ls180.v:3644$191 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -101664,10 +101660,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level connect \B 1'0 - connect \Y $ne$ls180.v:3648$192_Y + connect \Y $ne$ls180.v:3644$191_Y end - attribute \src "ls180.v:4140.47-4140.80" - cell $ne $ne$ls180.v:4140$590 + attribute \src "ls180.v:4136.47-4136.80" + cell $ne $ne$ls180.v:4136$589 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -101675,10 +101671,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_level0 connect \B 5'10000 - connect \Y $ne$ls180.v:4140$590_Y + connect \Y $ne$ls180.v:4136$589_Y end - attribute \src "ls180.v:4141.47-4141.79" - cell $ne $ne$ls180.v:4141$591 + attribute \src "ls180.v:4137.47-4137.79" + cell $ne $ne$ls180.v:4137$590 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -101686,10 +101682,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_level0 connect \B 1'0 - connect \Y $ne$ls180.v:4141$591_Y + connect \Y $ne$ls180.v:4137$590_Y end - attribute \src "ls180.v:4170.47-4170.80" - cell $ne $ne$ls180.v:4170$601 + attribute \src "ls180.v:4166.47-4166.80" + cell $ne $ne$ls180.v:4166$600 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -101697,10 +101693,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_level0 connect \B 5'10000 - connect \Y $ne$ls180.v:4170$601_Y + connect \Y $ne$ls180.v:4166$600_Y end - attribute \src "ls180.v:4171.47-4171.79" - cell $ne $ne$ls180.v:4171$602 + attribute \src "ls180.v:4167.47-4167.79" + cell $ne $ne$ls180.v:4167$601 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -101708,10 +101704,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_level0 connect \B 1'0 - connect \Y $ne$ls180.v:4171$602_Y + connect \Y $ne$ls180.v:4167$601_Y end - attribute \src "ls180.v:4577.32-4577.89" - cell $ne $ne$ls180.v:4577$674 + attribute \src "ls180.v:4573.32-4573.89" + cell $ne $ne$ls180.v:4573$673 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -101719,10 +101715,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_source_source_payload_data0 connect \B 3'101 - connect \Y $ne$ls180.v:4577$674_Y + connect \Y $ne$ls180.v:4573$673_Y end - attribute \src "ls180.v:5224.10-5224.56" - cell $ne $ne$ls180.v:5224$971 + attribute \src "ls180.v:5220.10-5220.56" + cell $ne $ne$ls180.v:5220$970 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -101730,10 +101726,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_source_payload_status connect \B 2'10 - connect \Y $ne$ls180.v:5224$971_Y + connect \Y $ne$ls180.v:5220$970_Y end - attribute \src "ls180.v:5329.51-5329.87" - cell $ne $ne$ls180.v:5329$985 + attribute \src "ls180.v:5325.51-5325.87" + cell $ne $ne$ls180.v:5325$984 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -101741,10 +101737,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_level connect \B 6'100000 - connect \Y $ne$ls180.v:5329$985_Y + connect \Y $ne$ls180.v:5325$984_Y end - attribute \src "ls180.v:5330.51-5330.86" - cell $ne $ne$ls180.v:5330$986 + attribute \src "ls180.v:5326.51-5326.86" + cell $ne $ne$ls180.v:5326$985 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -101752,10 +101748,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_level connect \B 1'0 - connect \Y $ne$ls180.v:5330$986_Y + connect \Y $ne$ls180.v:5326$985_Y end - attribute \src "ls180.v:5537.51-5537.87" - cell $ne $ne$ls180.v:5537$1016 + attribute \src "ls180.v:5533.51-5533.87" + cell $ne $ne$ls180.v:5533$1015 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -101763,10 +101759,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_level connect \B 6'100000 - connect \Y $ne$ls180.v:5537$1016_Y + connect \Y $ne$ls180.v:5533$1015_Y end - attribute \src "ls180.v:5538.51-5538.86" - cell $ne $ne$ls180.v:5538$1017 + attribute \src "ls180.v:5534.51-5534.86" + cell $ne $ne$ls180.v:5534$1016 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -101774,10 +101770,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_level connect \B 1'0 - connect \Y $ne$ls180.v:5538$1017_Y + connect \Y $ne$ls180.v:5534$1016_Y end - attribute \src "ls180.v:5628.79-5628.119" - cell $ne $ne$ls180.v:5628$1028 + attribute \src "ls180.v:5624.79-5624.119" + cell $ne $ne$ls180.v:5624$1027 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -101785,10 +101781,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_libresocsim_wishbone_sel connect \B 1'0 - connect \Y $ne$ls180.v:5628$1028_Y + connect \Y $ne$ls180.v:5624$1027_Y end - attribute \src "ls180.v:7436.7-7436.52" - cell $ne $ne$ls180.v:7436$2406 + attribute \src "ls180.v:7435.7-7435.52" + cell $ne $ne$ls180.v:7435$2404 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -101796,10 +101792,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_bus_errors connect \B 32'11111111111111111111111111111111 - connect \Y $ne$ls180.v:7436$2406_Y + connect \Y $ne$ls180.v:7435$2404_Y end - attribute \src "ls180.v:7488.9-7488.43" - cell $ne $ne$ls180.v:7488$2420 + attribute \src "ls180.v:7485.9-7485.43" + cell $ne $ne$ls180.v:7485$2418 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -101807,10 +101803,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_count connect \B 1'0 - connect \Y $ne$ls180.v:7488$2420_Y + connect \Y $ne$ls180.v:7485$2418_Y end - attribute \src "ls180.v:7524.8-7524.44" - cell $ne $ne$ls180.v:7524$2427 + attribute \src "ls180.v:7521.8-7521.44" + cell $ne $ne$ls180.v:7521$2425 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -101818,10 +101814,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_counter connect \B 1'0 - connect \Y $ne$ls180.v:7524$2427_Y + connect \Y $ne$ls180.v:7521$2425_Y end - attribute \src "ls180.v:8427.9-8427.47" - cell $ne $ne$ls180.v:8427$2637 + attribute \src "ls180.v:8424.9-8424.47" + cell $ne $ne$ls180.v:8424$2635 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -101829,2690 +101825,2690 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_cnt connect \B 4'1010 - connect \Y $ne$ls180.v:8427$2637_Y + connect \Y $ne$ls180.v:8424$2635_Y end - attribute \src "ls180.v:2725.45-2725.80" - cell $not $not$ls180.v:2725$14 + attribute \src "ls180.v:2726.45-2726.80" + cell $not $not$ls180.v:2726$14 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_libresocsim_libresoc_ibus_cyc - connect \Y $not$ls180.v:2725$14_Y + connect \Y $not$ls180.v:2726$14_Y end - attribute \src "ls180.v:2764.61-2764.94" - cell $not $not$ls180.v:2764$19 + attribute \src "ls180.v:2765.61-2765.94" + cell $not $not$ls180.v:2765$19 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_libresocsim_converter0_skip - connect \Y $not$ls180.v:2764$19_Y + connect \Y $not$ls180.v:2765$19_Y end - attribute \src "ls180.v:2765.61-2765.94" - cell $not $not$ls180.v:2765$20 + attribute \src "ls180.v:2766.61-2766.94" + cell $not $not$ls180.v:2766$20 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_libresocsim_converter0_skip - connect \Y $not$ls180.v:2765$20_Y + connect \Y $not$ls180.v:2766$20_Y end - attribute \src "ls180.v:2785.45-2785.80" - cell $not $not$ls180.v:2785$25 + attribute \src "ls180.v:2786.45-2786.80" + cell $not $not$ls180.v:2786$25 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_libresocsim_libresoc_dbus_cyc - connect \Y $not$ls180.v:2785$25_Y + connect \Y $not$ls180.v:2786$25_Y end - attribute \src "ls180.v:2824.61-2824.94" - cell $not $not$ls180.v:2824$30 + attribute \src "ls180.v:2825.61-2825.94" + cell $not $not$ls180.v:2825$30 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_libresocsim_converter1_skip - connect \Y $not$ls180.v:2824$30_Y + connect \Y $not$ls180.v:2825$30_Y end - attribute \src "ls180.v:2825.61-2825.94" - cell $not $not$ls180.v:2825$31 + attribute \src "ls180.v:2826.61-2826.94" + cell $not $not$ls180.v:2826$31 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_libresocsim_converter1_skip - connect \Y $not$ls180.v:2825$31_Y + connect \Y $not$ls180.v:2826$31_Y end - attribute \src "ls180.v:2845.45-2845.83" - cell $not $not$ls180.v:2845$36 + attribute \src "ls180.v:2846.45-2846.83" + cell $not $not$ls180.v:2846$36 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_libresocsim_libresoc_jtag_wb_cyc - connect \Y $not$ls180.v:2845$36_Y + connect \Y $not$ls180.v:2846$36_Y end - attribute \src "ls180.v:2884.61-2884.94" - cell $not $not$ls180.v:2884$41 + attribute \src "ls180.v:2885.61-2885.94" + cell $not $not$ls180.v:2885$41 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_libresocsim_converter2_skip - connect \Y $not$ls180.v:2884$41_Y + connect \Y $not$ls180.v:2885$41_Y end - attribute \src "ls180.v:2885.61-2885.94" - cell $not $not$ls180.v:2885$42 + attribute \src "ls180.v:2886.61-2886.94" + cell $not $not$ls180.v:2886$42 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_libresocsim_converter2_skip - connect \Y $not$ls180.v:2885$42_Y + connect \Y $not$ls180.v:2886$42_Y end - attribute \src "ls180.v:3032.34-3032.64" - cell $not $not$ls180.v:3032$67 + attribute \src "ls180.v:3028.34-3028.64" + cell $not $not$ls180.v:3028$66 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_command_storage [0] - connect \Y $not$ls180.v:3032$67_Y + connect \Y $not$ls180.v:3028$66_Y end - attribute \src "ls180.v:3033.31-3033.61" - cell $not $not$ls180.v:3033$68 + attribute \src "ls180.v:3029.31-3029.61" + cell $not $not$ls180.v:3029$67 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_command_storage [1] - connect \Y $not$ls180.v:3033$68_Y + connect \Y $not$ls180.v:3029$67_Y end - attribute \src "ls180.v:3034.32-3034.62" - cell $not $not$ls180.v:3034$69 + attribute \src "ls180.v:3030.32-3030.62" + cell $not $not$ls180.v:3030$68 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_command_storage [2] - connect \Y $not$ls180.v:3034$69_Y + connect \Y $not$ls180.v:3030$68_Y end - attribute \src "ls180.v:3035.32-3035.62" - cell $not $not$ls180.v:3035$70 + attribute \src "ls180.v:3031.32-3031.62" + cell $not $not$ls180.v:3031$69 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_command_storage [3] - connect \Y $not$ls180.v:3035$70_Y + connect \Y $not$ls180.v:3031$69_Y end - attribute \src "ls180.v:3077.33-3077.56" - cell $not $not$ls180.v:3077$73 + attribute \src "ls180.v:3073.33-3073.56" + cell $not $not$ls180.v:3073$72 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_timer_done0 - connect \Y $not$ls180.v:3077$73_Y + connect \Y $not$ls180.v:3073$72_Y end - attribute \src "ls180.v:3178.58-3178.106" - cell $not $not$ls180.v:3178$103 + attribute \src "ls180.v:3174.58-3174.106" + cell $not $not$ls180.v:3174$102 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_source_valid - connect \Y $not$ls180.v:3178$103_Y + connect \Y $not$ls180.v:3174$102_Y end - attribute \src "ls180.v:3232.9-3232.45" - cell $not $not$ls180.v:3232$108 + attribute \src "ls180.v:3228.9-3228.45" + cell $not $not$ls180.v:3228$107 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_refresh_req - connect \Y $not$ls180.v:3232$108_Y + connect \Y $not$ls180.v:3228$107_Y end - attribute \src "ls180.v:3335.58-3335.106" - cell $not $not$ls180.v:3335$133 + attribute \src "ls180.v:3331.58-3331.106" + cell $not $not$ls180.v:3331$132 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_source_valid - connect \Y $not$ls180.v:3335$133_Y + connect \Y $not$ls180.v:3331$132_Y end - attribute \src "ls180.v:3389.9-3389.45" - cell $not $not$ls180.v:3389$138 + attribute \src "ls180.v:3385.9-3385.45" + cell $not $not$ls180.v:3385$137 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_refresh_req - connect \Y $not$ls180.v:3389$138_Y + connect \Y $not$ls180.v:3385$137_Y end - attribute \src "ls180.v:3492.58-3492.106" - cell $not $not$ls180.v:3492$163 + attribute \src "ls180.v:3488.58-3488.106" + cell $not $not$ls180.v:3488$162 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_source_valid - connect \Y $not$ls180.v:3492$163_Y + connect \Y $not$ls180.v:3488$162_Y end - attribute \src "ls180.v:3546.9-3546.45" - cell $not $not$ls180.v:3546$168 + attribute \src "ls180.v:3542.9-3542.45" + cell $not $not$ls180.v:3542$167 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_refresh_req - connect \Y $not$ls180.v:3546$168_Y + connect \Y $not$ls180.v:3542$167_Y end - attribute \src "ls180.v:3649.58-3649.106" - cell $not $not$ls180.v:3649$193 + attribute \src "ls180.v:3645.58-3645.106" + cell $not $not$ls180.v:3645$192 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_source_valid - connect \Y $not$ls180.v:3649$193_Y + connect \Y $not$ls180.v:3645$192_Y end - attribute \src "ls180.v:3703.9-3703.45" - cell $not $not$ls180.v:3703$198 + attribute \src "ls180.v:3699.9-3699.45" + cell $not $not$ls180.v:3699$197 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_refresh_req - connect \Y $not$ls180.v:3703$198_Y + connect \Y $not$ls180.v:3699$197_Y end - attribute \src "ls180.v:3745.149-3745.187" - cell $not $not$ls180.v:3745$201 + attribute \src "ls180.v:3741.149-3741.187" + cell $not $not$ls180.v:3741$200 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_cas - connect \Y $not$ls180.v:3745$201_Y + connect \Y $not$ls180.v:3741$200_Y end - attribute \src "ls180.v:3745.193-3745.230" - cell $not $not$ls180.v:3745$203 + attribute \src "ls180.v:3741.193-3741.230" + cell $not $not$ls180.v:3741$202 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_we - connect \Y $not$ls180.v:3745$203_Y + connect \Y $not$ls180.v:3741$202_Y end - attribute \src "ls180.v:3746.149-3746.187" - cell $not $not$ls180.v:3746$207 + attribute \src "ls180.v:3742.149-3742.187" + cell $not $not$ls180.v:3742$206 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_cas - connect \Y $not$ls180.v:3746$207_Y + connect \Y $not$ls180.v:3742$206_Y end - attribute \src "ls180.v:3746.193-3746.230" - cell $not $not$ls180.v:3746$209 + attribute \src "ls180.v:3742.193-3742.230" + cell $not $not$ls180.v:3742$208 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_we - connect \Y $not$ls180.v:3746$209_Y + connect \Y $not$ls180.v:3742$208_Y end - attribute \src "ls180.v:3762.43-3762.73" - cell $not $not$ls180.v:3762$237 + attribute \src "ls180.v:3758.43-3758.73" + cell $not $not$ls180.v:3758$236 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \main_sdram_interface_wdata_we - connect \Y $not$ls180.v:3762$237_Y + connect \Y $not$ls180.v:3758$236_Y end - attribute \src "ls180.v:3765.205-3765.245" - cell $not $not$ls180.v:3765$240 + attribute \src "ls180.v:3761.205-3761.245" + cell $not $not$ls180.v:3761$239 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_cas - connect \Y $not$ls180.v:3765$240_Y + connect \Y $not$ls180.v:3761$239_Y end - attribute \src "ls180.v:3765.251-3765.290" - cell $not $not$ls180.v:3765$242 + attribute \src "ls180.v:3761.251-3761.290" + cell $not $not$ls180.v:3761$241 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_we - connect \Y $not$ls180.v:3765$242_Y + connect \Y $not$ls180.v:3761$241_Y end - attribute \src "ls180.v:3765.159-3765.292" - cell $not $not$ls180.v:3765$244 + attribute \src "ls180.v:3761.159-3761.292" + cell $not $not$ls180.v:3761$243 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3765$243_Y - connect \Y $not$ls180.v:3765$244_Y + connect \A $and$ls180.v:3761$242_Y + connect \Y $not$ls180.v:3761$243_Y end - attribute \src "ls180.v:3766.205-3766.245" - cell $not $not$ls180.v:3766$253 + attribute \src "ls180.v:3762.205-3762.245" + cell $not $not$ls180.v:3762$252 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_cas - connect \Y $not$ls180.v:3766$253_Y + connect \Y $not$ls180.v:3762$252_Y end - attribute \src "ls180.v:3766.251-3766.290" - cell $not $not$ls180.v:3766$255 + attribute \src "ls180.v:3762.251-3762.290" + cell $not $not$ls180.v:3762$254 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_we - connect \Y $not$ls180.v:3766$255_Y + connect \Y $not$ls180.v:3762$254_Y end - attribute \src "ls180.v:3766.159-3766.292" - cell $not $not$ls180.v:3766$257 + attribute \src "ls180.v:3762.159-3762.292" + cell $not $not$ls180.v:3762$256 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3766$256_Y - connect \Y $not$ls180.v:3766$257_Y + connect \A $and$ls180.v:3762$255_Y + connect \Y $not$ls180.v:3762$256_Y end - attribute \src "ls180.v:3767.205-3767.245" - cell $not $not$ls180.v:3767$266 + attribute \src "ls180.v:3763.205-3763.245" + cell $not $not$ls180.v:3763$265 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_cas - connect \Y $not$ls180.v:3767$266_Y + connect \Y $not$ls180.v:3763$265_Y end - attribute \src "ls180.v:3767.251-3767.290" - cell $not $not$ls180.v:3767$268 + attribute \src "ls180.v:3763.251-3763.290" + cell $not $not$ls180.v:3763$267 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_we - connect \Y $not$ls180.v:3767$268_Y + connect \Y $not$ls180.v:3763$267_Y end - attribute \src "ls180.v:3767.159-3767.292" - cell $not $not$ls180.v:3767$270 + attribute \src "ls180.v:3763.159-3763.292" + cell $not $not$ls180.v:3763$269 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3767$269_Y - connect \Y $not$ls180.v:3767$270_Y + connect \A $and$ls180.v:3763$268_Y + connect \Y $not$ls180.v:3763$269_Y end - attribute \src "ls180.v:3768.205-3768.245" - cell $not $not$ls180.v:3768$279 + attribute \src "ls180.v:3764.205-3764.245" + cell $not $not$ls180.v:3764$278 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_cas - connect \Y $not$ls180.v:3768$279_Y + connect \Y $not$ls180.v:3764$278_Y end - attribute \src "ls180.v:3768.251-3768.290" - cell $not $not$ls180.v:3768$281 + attribute \src "ls180.v:3764.251-3764.290" + cell $not $not$ls180.v:3764$280 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_we - connect \Y $not$ls180.v:3768$281_Y + connect \Y $not$ls180.v:3764$280_Y end - attribute \src "ls180.v:3768.159-3768.292" - cell $not $not$ls180.v:3768$283 + attribute \src "ls180.v:3764.159-3764.292" + cell $not $not$ls180.v:3764$282 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3768$282_Y - connect \Y $not$ls180.v:3768$283_Y + connect \A $and$ls180.v:3764$281_Y + connect \Y $not$ls180.v:3764$282_Y end - attribute \src "ls180.v:3795.71-3795.103" - cell $not $not$ls180.v:3795$294 + attribute \src "ls180.v:3791.71-3791.103" + cell $not $not$ls180.v:3791$293 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_cmd_valid - connect \Y $not$ls180.v:3795$294_Y + connect \Y $not$ls180.v:3791$293_Y end - attribute \src "ls180.v:3798.205-3798.245" - cell $not $not$ls180.v:3798$298 + attribute \src "ls180.v:3794.205-3794.245" + cell $not $not$ls180.v:3794$297 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_cas - connect \Y $not$ls180.v:3798$298_Y + connect \Y $not$ls180.v:3794$297_Y end - attribute \src "ls180.v:3798.251-3798.290" - cell $not $not$ls180.v:3798$300 + attribute \src "ls180.v:3794.251-3794.290" + cell $not $not$ls180.v:3794$299 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_we - connect \Y $not$ls180.v:3798$300_Y + connect \Y $not$ls180.v:3794$299_Y end - attribute \src "ls180.v:3798.159-3798.292" - cell $not $not$ls180.v:3798$302 + attribute \src "ls180.v:3794.159-3794.292" + cell $not $not$ls180.v:3794$301 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3798$301_Y - connect \Y $not$ls180.v:3798$302_Y + connect \A $and$ls180.v:3794$300_Y + connect \Y $not$ls180.v:3794$301_Y end - attribute \src "ls180.v:3799.205-3799.245" - cell $not $not$ls180.v:3799$311 + attribute \src "ls180.v:3795.205-3795.245" + cell $not $not$ls180.v:3795$310 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_cas - connect \Y $not$ls180.v:3799$311_Y + connect \Y $not$ls180.v:3795$310_Y end - attribute \src "ls180.v:3799.251-3799.290" - cell $not $not$ls180.v:3799$313 + attribute \src "ls180.v:3795.251-3795.290" + cell $not $not$ls180.v:3795$312 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_we - connect \Y $not$ls180.v:3799$313_Y + connect \Y $not$ls180.v:3795$312_Y end - attribute \src "ls180.v:3799.159-3799.292" - cell $not $not$ls180.v:3799$315 + attribute \src "ls180.v:3795.159-3795.292" + cell $not $not$ls180.v:3795$314 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3799$314_Y - connect \Y $not$ls180.v:3799$315_Y + connect \A $and$ls180.v:3795$313_Y + connect \Y $not$ls180.v:3795$314_Y end - attribute \src "ls180.v:3800.205-3800.245" - cell $not $not$ls180.v:3800$324 + attribute \src "ls180.v:3796.205-3796.245" + cell $not $not$ls180.v:3796$323 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_cas - connect \Y $not$ls180.v:3800$324_Y + connect \Y $not$ls180.v:3796$323_Y end - attribute \src "ls180.v:3800.251-3800.290" - cell $not $not$ls180.v:3800$326 + attribute \src "ls180.v:3796.251-3796.290" + cell $not $not$ls180.v:3796$325 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_we - connect \Y $not$ls180.v:3800$326_Y + connect \Y $not$ls180.v:3796$325_Y end - attribute \src "ls180.v:3800.159-3800.292" - cell $not $not$ls180.v:3800$328 + attribute \src "ls180.v:3796.159-3796.292" + cell $not $not$ls180.v:3796$327 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3800$327_Y - connect \Y $not$ls180.v:3800$328_Y + connect \A $and$ls180.v:3796$326_Y + connect \Y $not$ls180.v:3796$327_Y end - attribute \src "ls180.v:3801.205-3801.245" - cell $not $not$ls180.v:3801$337 + attribute \src "ls180.v:3797.205-3797.245" + cell $not $not$ls180.v:3797$336 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_cas - connect \Y $not$ls180.v:3801$337_Y + connect \Y $not$ls180.v:3797$336_Y end - attribute \src "ls180.v:3801.251-3801.290" - cell $not $not$ls180.v:3801$339 + attribute \src "ls180.v:3797.251-3797.290" + cell $not $not$ls180.v:3797$338 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_we - connect \Y $not$ls180.v:3801$339_Y + connect \Y $not$ls180.v:3797$338_Y end - attribute \src "ls180.v:3801.159-3801.292" - cell $not $not$ls180.v:3801$341 + attribute \src "ls180.v:3797.159-3797.292" + cell $not $not$ls180.v:3797$340 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3801$340_Y - connect \Y $not$ls180.v:3801$341_Y + connect \A $and$ls180.v:3797$339_Y + connect \Y $not$ls180.v:3797$340_Y end - attribute \src "ls180.v:3864.71-3864.103" - cell $not $not$ls180.v:3864$380 + attribute \src "ls180.v:3860.71-3860.103" + cell $not $not$ls180.v:3860$379 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid - connect \Y $not$ls180.v:3864$380_Y + connect \Y $not$ls180.v:3860$379_Y end - attribute \src "ls180.v:3885.112-3885.150" - cell $not $not$ls180.v:3885$383 + attribute \src "ls180.v:3881.112-3881.150" + cell $not $not$ls180.v:3881$382 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_cas - connect \Y $not$ls180.v:3885$383_Y + connect \Y $not$ls180.v:3881$382_Y end - attribute \src "ls180.v:3885.156-3885.193" - cell $not $not$ls180.v:3885$385 + attribute \src "ls180.v:3881.156-3881.193" + cell $not $not$ls180.v:3881$384 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_we - connect \Y $not$ls180.v:3885$385_Y + connect \Y $not$ls180.v:3881$384_Y end - attribute \src "ls180.v:3885.68-3885.195" - cell $not $not$ls180.v:3885$387 + attribute \src "ls180.v:3881.68-3881.195" + cell $not $not$ls180.v:3881$386 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3885$386_Y - connect \Y $not$ls180.v:3885$387_Y + connect \A $and$ls180.v:3881$385_Y + connect \Y $not$ls180.v:3881$386_Y end - attribute \src "ls180.v:3893.11-3893.38" - cell $not $not$ls180.v:3893$390 + attribute \src "ls180.v:3889.11-3889.38" + cell $not $not$ls180.v:3889$389 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_write_available - connect \Y $not$ls180.v:3893$390_Y + connect \Y $not$ls180.v:3889$389_Y end - attribute \src "ls180.v:3923.112-3923.150" - cell $not $not$ls180.v:3923$392 + attribute \src "ls180.v:3919.112-3919.150" + cell $not $not$ls180.v:3919$391 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_cas - connect \Y $not$ls180.v:3923$392_Y + connect \Y $not$ls180.v:3919$391_Y end - attribute \src "ls180.v:3923.156-3923.193" - cell $not $not$ls180.v:3923$394 + attribute \src "ls180.v:3919.156-3919.193" + cell $not $not$ls180.v:3919$393 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_we - connect \Y $not$ls180.v:3923$394_Y + connect \Y $not$ls180.v:3919$393_Y end - attribute \src "ls180.v:3923.68-3923.195" - cell $not $not$ls180.v:3923$396 + attribute \src "ls180.v:3919.68-3919.195" + cell $not $not$ls180.v:3919$395 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3923$395_Y - connect \Y $not$ls180.v:3923$396_Y + connect \A $and$ls180.v:3919$394_Y + connect \Y $not$ls180.v:3919$395_Y end - attribute \src "ls180.v:3931.11-3931.37" - cell $not $not$ls180.v:3931$399 + attribute \src "ls180.v:3927.11-3927.37" + cell $not $not$ls180.v:3927$398 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_read_available - connect \Y $not$ls180.v:3931$399_Y + connect \Y $not$ls180.v:3927$398_Y end - attribute \src "ls180.v:3941.87-3941.331" - cell $not $not$ls180.v:3941$411 + attribute \src "ls180.v:3937.87-3937.331" + cell $not $not$ls180.v:3937$410 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3941$410_Y - connect \Y $not$ls180.v:3941$411_Y + connect \A $or$ls180.v:3937$409_Y + connect \Y $not$ls180.v:3937$410_Y end - attribute \src "ls180.v:3942.35-3942.68" - cell $not $not$ls180.v:3942$414 + attribute \src "ls180.v:3938.35-3938.68" + cell $not $not$ls180.v:3938$413 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_valid - connect \Y $not$ls180.v:3942$414_Y + connect \Y $not$ls180.v:3938$413_Y end - attribute \src "ls180.v:3942.73-3942.105" - cell $not $not$ls180.v:3942$415 + attribute \src "ls180.v:3938.73-3938.105" + cell $not $not$ls180.v:3938$414 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \Y $not$ls180.v:3942$415_Y + connect \Y $not$ls180.v:3938$414_Y end - attribute \src "ls180.v:3946.87-3946.331" - cell $not $not$ls180.v:3946$427 + attribute \src "ls180.v:3942.87-3942.331" + cell $not $not$ls180.v:3942$426 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3946$426_Y - connect \Y $not$ls180.v:3946$427_Y + connect \A $or$ls180.v:3942$425_Y + connect \Y $not$ls180.v:3942$426_Y end - attribute \src "ls180.v:3947.35-3947.68" - cell $not $not$ls180.v:3947$430 + attribute \src "ls180.v:3943.35-3943.68" + cell $not $not$ls180.v:3943$429 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_valid - connect \Y $not$ls180.v:3947$430_Y + connect \Y $not$ls180.v:3943$429_Y end - attribute \src "ls180.v:3947.73-3947.105" - cell $not $not$ls180.v:3947$431 + attribute \src "ls180.v:3943.73-3943.105" + cell $not $not$ls180.v:3943$430 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \Y $not$ls180.v:3947$431_Y + connect \Y $not$ls180.v:3943$430_Y end - attribute \src "ls180.v:3951.87-3951.331" - cell $not $not$ls180.v:3951$443 + attribute \src "ls180.v:3947.87-3947.331" + cell $not $not$ls180.v:3947$442 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3951$442_Y - connect \Y $not$ls180.v:3951$443_Y + connect \A $or$ls180.v:3947$441_Y + connect \Y $not$ls180.v:3947$442_Y end - attribute \src "ls180.v:3952.35-3952.68" - cell $not $not$ls180.v:3952$446 + attribute \src "ls180.v:3948.35-3948.68" + cell $not $not$ls180.v:3948$445 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_valid - connect \Y $not$ls180.v:3952$446_Y + connect \Y $not$ls180.v:3948$445_Y end - attribute \src "ls180.v:3952.73-3952.105" - cell $not $not$ls180.v:3952$447 + attribute \src "ls180.v:3948.73-3948.105" + cell $not $not$ls180.v:3948$446 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \Y $not$ls180.v:3952$447_Y + connect \Y $not$ls180.v:3948$446_Y end - attribute \src "ls180.v:3956.87-3956.331" - cell $not $not$ls180.v:3956$459 + attribute \src "ls180.v:3952.87-3952.331" + cell $not $not$ls180.v:3952$458 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3956$458_Y - connect \Y $not$ls180.v:3956$459_Y + connect \A $or$ls180.v:3952$457_Y + connect \Y $not$ls180.v:3952$458_Y end - attribute \src "ls180.v:3957.35-3957.68" - cell $not $not$ls180.v:3957$462 + attribute \src "ls180.v:3953.35-3953.68" + cell $not $not$ls180.v:3953$461 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_valid - connect \Y $not$ls180.v:3957$462_Y + connect \Y $not$ls180.v:3953$461_Y end - attribute \src "ls180.v:3957.73-3957.105" - cell $not $not$ls180.v:3957$463 + attribute \src "ls180.v:3953.73-3953.105" + cell $not $not$ls180.v:3953$462 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \Y $not$ls180.v:3957$463_Y + connect \Y $not$ls180.v:3953$462_Y end - attribute \src "ls180.v:3961.128-3961.372" - cell $not $not$ls180.v:3961$476 + attribute \src "ls180.v:3957.128-3957.372" + cell $not $not$ls180.v:3957$475 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3961$475_Y - connect \Y $not$ls180.v:3961$476_Y + connect \A $or$ls180.v:3957$474_Y + connect \Y $not$ls180.v:3957$475_Y end - attribute \src "ls180.v:3961.502-3961.746" - cell $not $not$ls180.v:3961$492 + attribute \src "ls180.v:3957.502-3957.746" + cell $not $not$ls180.v:3957$491 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3961$491_Y - connect \Y $not$ls180.v:3961$492_Y + connect \A $or$ls180.v:3957$490_Y + connect \Y $not$ls180.v:3957$491_Y end - attribute \src "ls180.v:3961.876-3961.1120" - cell $not $not$ls180.v:3961$508 + attribute \src "ls180.v:3957.876-3957.1120" + cell $not $not$ls180.v:3957$507 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3961$507_Y - connect \Y $not$ls180.v:3961$508_Y + connect \A $or$ls180.v:3957$506_Y + connect \Y $not$ls180.v:3957$507_Y end - attribute \src "ls180.v:3961.1250-3961.1494" - cell $not $not$ls180.v:3961$524 + attribute \src "ls180.v:3957.1250-3957.1494" + cell $not $not$ls180.v:3957$523 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3961$523_Y - connect \Y $not$ls180.v:3961$524_Y + connect \A $or$ls180.v:3957$522_Y + connect \Y $not$ls180.v:3957$523_Y end - attribute \src "ls180.v:3983.32-3983.50" - cell $not $not$ls180.v:3983$530 + attribute \src "ls180.v:3979.32-3979.50" + cell $not $not$ls180.v:3979$529 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_wb_sdram_cyc - connect \Y $not$ls180.v:3983$530_Y + connect \Y $not$ls180.v:3979$529_Y end - attribute \src "ls180.v:4022.30-4022.50" - cell $not $not$ls180.v:4022$535 + attribute \src "ls180.v:4018.30-4018.50" + cell $not $not$ls180.v:4018$534 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_converter_skip - connect \Y $not$ls180.v:4022$535_Y + connect \Y $not$ls180.v:4018$534_Y end - attribute \src "ls180.v:4023.30-4023.50" - cell $not $not$ls180.v:4023$536 + attribute \src "ls180.v:4019.30-4019.50" + cell $not $not$ls180.v:4019$535 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_converter_skip - connect \Y $not$ls180.v:4023$536_Y + connect \Y $not$ls180.v:4019$535_Y end - attribute \src "ls180.v:4048.27-4048.48" - cell $not $not$ls180.v:4048$542 + attribute \src "ls180.v:4044.27-4044.48" + cell $not $not$ls180.v:4044$541 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_litedram_wb_cyc - connect \Y $not$ls180.v:4048$542_Y + connect \Y $not$ls180.v:4044$541_Y end - attribute \src "ls180.v:4049.30-4049.50" - cell $not $not$ls180.v:4049$543 + attribute \src "ls180.v:4045.30-4045.50" + cell $not $not$ls180.v:4045$542 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_litedram_wb_we - connect \Y $not$ls180.v:4049$543_Y + connect \Y $not$ls180.v:4045$542_Y end - attribute \src "ls180.v:4050.80-4050.98" - cell $not $not$ls180.v:4050$545 + attribute \src "ls180.v:4046.80-4046.98" + cell $not $not$ls180.v:4046$544 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_cmd_consumed - connect \Y $not$ls180.v:4050$545_Y + connect \Y $not$ls180.v:4046$544_Y end - attribute \src "ls180.v:4051.107-4051.127" - cell $not $not$ls180.v:4051$549 + attribute \src "ls180.v:4047.107-4047.127" + cell $not $not$ls180.v:4047$548 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_wdata_consumed - connect \Y $not$ls180.v:4051$549_Y + connect \Y $not$ls180.v:4047$548_Y end - attribute \src "ls180.v:4052.78-4052.103" - cell $not $not$ls180.v:4052$552 + attribute \src "ls180.v:4048.78-4048.103" + cell $not $not$ls180.v:4048$551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_we - connect \Y $not$ls180.v:4052$552_Y + connect \Y $not$ls180.v:4048$551_Y end - attribute \src "ls180.v:4053.91-4053.111" - cell $not $not$ls180.v:4053$555 + attribute \src "ls180.v:4049.91-4049.111" + cell $not $not$ls180.v:4049$554 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_litedram_wb_we - connect \Y $not$ls180.v:4053$555_Y + connect \Y $not$ls180.v:4049$554_Y end - attribute \src "ls180.v:4069.35-4069.64" - cell $not $not$ls180.v:4069$564 + attribute \src "ls180.v:4065.35-4065.64" + cell $not $not$ls180.v:4065$563 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_sink_ready - connect \Y $not$ls180.v:4069$564_Y + connect \Y $not$ls180.v:4065$563_Y end - attribute \src "ls180.v:4070.36-4070.67" - cell $not $not$ls180.v:4070$565 + attribute \src "ls180.v:4066.36-4066.67" + cell $not $not$ls180.v:4066$564 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_source_valid - connect \Y $not$ls180.v:4070$565_Y + connect \Y $not$ls180.v:4066$564_Y end - attribute \src "ls180.v:4076.32-4076.61" - cell $not $not$ls180.v:4076$566 + attribute \src "ls180.v:4072.32-4072.61" + cell $not $not$ls180.v:4072$565 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_sink_ready - connect \Y $not$ls180.v:4076$566_Y + connect \Y $not$ls180.v:4072$565_Y end - attribute \src "ls180.v:4082.36-4082.67" - cell $not $not$ls180.v:4082$567 + attribute \src "ls180.v:4078.36-4078.67" + cell $not $not$ls180.v:4078$566 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_source_valid - connect \Y $not$ls180.v:4082$567_Y + connect \Y $not$ls180.v:4078$566_Y end - attribute \src "ls180.v:4083.35-4083.64" - cell $not $not$ls180.v:4083$568 + attribute \src "ls180.v:4079.35-4079.64" + cell $not $not$ls180.v:4079$567 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_sink_ready - connect \Y $not$ls180.v:4083$568_Y + connect \Y $not$ls180.v:4079$567_Y end - attribute \src "ls180.v:4086.32-4086.63" - cell $not $not$ls180.v:4086$571 + attribute \src "ls180.v:4082.32-4082.63" + cell $not $not$ls180.v:4082$570 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_source_valid - connect \Y $not$ls180.v:4086$571_Y + connect \Y $not$ls180.v:4082$570_Y end - attribute \src "ls180.v:4124.81-4124.108" - cell $not $not$ls180.v:4124$581 + attribute \src "ls180.v:4120.81-4120.108" + cell $not $not$ls180.v:4120$580 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_readable - connect \Y $not$ls180.v:4124$581_Y + connect \Y $not$ls180.v:4120$580_Y end - attribute \src "ls180.v:4154.81-4154.108" - cell $not $not$ls180.v:4154$592 + attribute \src "ls180.v:4150.81-4150.108" + cell $not $not$ls180.v:4150$591 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_readable - connect \Y $not$ls180.v:4154$592_Y + connect \Y $not$ls180.v:4150$591_Y end - attribute \src "ls180.v:4291.60-4291.85" - cell $not $not$ls180.v:4291$633 + attribute \src "ls180.v:4287.60-4287.85" + cell $not $not$ls180.v:4287$632 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_clocker_clk_d - connect \Y $not$ls180.v:4291$633_Y + connect \Y $not$ls180.v:4287$632_Y end - attribute \src "ls180.v:4432.54-4432.96" - cell $not $not$ls180.v:4432$647 + attribute \src "ls180.v:4428.54-4428.96" + cell $not $not$ls180.v:4428$646 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_strobe_all - connect \Y $not$ls180.v:4432$647_Y + connect \Y $not$ls180.v:4428$646_Y end - attribute \src "ls180.v:4435.48-4435.86" - cell $not $not$ls180.v:4435$650 + attribute \src "ls180.v:4431.48-4431.86" + cell $not $not$ls180.v:4431$649 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_buf_source_valid - connect \Y $not$ls180.v:4435$650_Y + connect \Y $not$ls180.v:4431$649_Y end - attribute \src "ls180.v:4559.55-4559.98" - cell $not $not$ls180.v:4559$668 + attribute \src "ls180.v:4555.55-4555.98" + cell $not $not$ls180.v:4555$667 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_strobe_all - connect \Y $not$ls180.v:4559$668_Y + connect \Y $not$ls180.v:4555$667_Y end - attribute \src "ls180.v:4562.49-4562.88" - cell $not $not$ls180.v:4562$671 + attribute \src "ls180.v:4558.49-4558.88" + cell $not $not$ls180.v:4558$670 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_buf_source_valid - connect \Y $not$ls180.v:4562$671_Y + connect \Y $not$ls180.v:4558$670_Y end - attribute \src "ls180.v:4612.30-4612.58" - cell $not $not$ls180.v:4612$677 + attribute \src "ls180.v:4608.30-4608.58" + cell $not $not$ls180.v:4608$676 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_sink_valid - connect \Y $not$ls180.v:4612$677_Y + connect \Y $not$ls180.v:4608$676_Y end - attribute \src "ls180.v:4693.56-4693.100" - cell $not $not$ls180.v:4693$683 + attribute \src "ls180.v:4689.56-4689.100" + cell $not $not$ls180.v:4689$682 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_strobe_all - connect \Y $not$ls180.v:4693$683_Y + connect \Y $not$ls180.v:4689$682_Y end - attribute \src "ls180.v:4696.50-4696.90" - cell $not $not$ls180.v:4696$686 + attribute \src "ls180.v:4692.50-4692.90" + cell $not $not$ls180.v:4692$685 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_buf_source_valid - connect \Y $not$ls180.v:4696$686_Y + connect \Y $not$ls180.v:4692$685_Y end - attribute \src "ls180.v:4812.42-4812.74" - cell $not $not$ls180.v:4812$702 + attribute \src "ls180.v:4808.42-4808.74" + cell $not $not$ls180.v:4808$701 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_valid - connect \Y $not$ls180.v:4812$702_Y + connect \Y $not$ls180.v:4808$701_Y end - attribute \src "ls180.v:5336.50-5336.88" - cell $not $not$ls180.v:5336$987 + attribute \src "ls180.v:5332.50-5332.88" + cell $not $not$ls180.v:5332$986 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_strobe_all - connect \Y $not$ls180.v:5336$987_Y + connect \Y $not$ls180.v:5332$986_Y end - attribute \src "ls180.v:5348.52-5348.102" - cell $not $not$ls180.v:5348$990 + attribute \src "ls180.v:5344.52-5344.102" + cell $not $not$ls180.v:5344$989 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_wishbonedmawriter_enable_storage - connect \Y $not$ls180.v:5348$990_Y + connect \Y $not$ls180.v:5344$989_Y end - attribute \src "ls180.v:5407.38-5407.74" - cell $not $not$ls180.v:5407$997 + attribute \src "ls180.v:5403.38-5403.74" + cell $not $not$ls180.v:5403$996 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_dma_enable_storage - connect \Y $not$ls180.v:5407$997_Y + connect \Y $not$ls180.v:5403$996_Y end - attribute \src "ls180.v:5708.69-5708.88" - cell $not $not$ls180.v:5708$1066 + attribute \src "ls180.v:5704.69-5704.88" + cell $not $not$ls180.v:5704$1065 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_ack - connect \Y $not$ls180.v:5708$1066_Y + connect \Y $not$ls180.v:5704$1065_Y end - attribute \src "ls180.v:5725.63-5725.94" - cell $not $not$ls180.v:5725$1087 + attribute \src "ls180.v:5721.63-5721.94" + cell $not $not$ls180.v:5721$1086 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5725$1087_Y + connect \Y $not$ls180.v:5721$1086_Y end - attribute \src "ls180.v:5728.65-5728.96" - cell $not $not$ls180.v:5728$1094 + attribute \src "ls180.v:5724.65-5724.96" + cell $not $not$ls180.v:5724$1093 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5728$1094_Y + connect \Y $not$ls180.v:5724$1093_Y end - attribute \src "ls180.v:5731.65-5731.96" - cell $not $not$ls180.v:5731$1101 + attribute \src "ls180.v:5727.65-5727.96" + cell $not $not$ls180.v:5727$1100 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5731$1101_Y + connect \Y $not$ls180.v:5727$1100_Y end - attribute \src "ls180.v:5734.65-5734.96" - cell $not $not$ls180.v:5734$1108 + attribute \src "ls180.v:5730.65-5730.96" + cell $not $not$ls180.v:5730$1107 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5734$1108_Y + connect \Y $not$ls180.v:5730$1107_Y end - attribute \src "ls180.v:5737.65-5737.96" - cell $not $not$ls180.v:5737$1115 + attribute \src "ls180.v:5733.65-5733.96" + cell $not $not$ls180.v:5733$1114 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5737$1115_Y + connect \Y $not$ls180.v:5733$1114_Y end - attribute \src "ls180.v:5740.68-5740.99" - cell $not $not$ls180.v:5740$1122 + attribute \src "ls180.v:5736.68-5736.99" + cell $not $not$ls180.v:5736$1121 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5740$1122_Y + connect \Y $not$ls180.v:5736$1121_Y end - attribute \src "ls180.v:5743.68-5743.99" - cell $not $not$ls180.v:5743$1129 + attribute \src "ls180.v:5739.68-5739.99" + cell $not $not$ls180.v:5739$1128 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5743$1129_Y + connect \Y $not$ls180.v:5739$1128_Y end - attribute \src "ls180.v:5746.68-5746.99" - cell $not $not$ls180.v:5746$1136 + attribute \src "ls180.v:5742.68-5742.99" + cell $not $not$ls180.v:5742$1135 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5746$1136_Y + connect \Y $not$ls180.v:5742$1135_Y end - attribute \src "ls180.v:5749.68-5749.99" - cell $not $not$ls180.v:5749$1143 + attribute \src "ls180.v:5745.68-5745.99" + cell $not $not$ls180.v:5745$1142 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5749$1143_Y + connect \Y $not$ls180.v:5745$1142_Y end - attribute \src "ls180.v:5763.60-5763.91" - cell $not $not$ls180.v:5763$1151 + attribute \src "ls180.v:5759.60-5759.91" + cell $not $not$ls180.v:5759$1150 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:5763$1151_Y + connect \Y $not$ls180.v:5759$1150_Y end - attribute \src "ls180.v:5766.60-5766.91" - cell $not $not$ls180.v:5766$1158 + attribute \src "ls180.v:5762.60-5762.91" + cell $not $not$ls180.v:5762$1157 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:5766$1158_Y + connect \Y $not$ls180.v:5762$1157_Y end - attribute \src "ls180.v:5769.60-5769.91" - cell $not $not$ls180.v:5769$1165 + attribute \src "ls180.v:5765.60-5765.91" + cell $not $not$ls180.v:5765$1164 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:5769$1165_Y + connect \Y $not$ls180.v:5765$1164_Y end - attribute \src "ls180.v:5772.60-5772.91" - cell $not $not$ls180.v:5772$1172 + attribute \src "ls180.v:5768.60-5768.91" + cell $not $not$ls180.v:5768$1171 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:5772$1172_Y + connect \Y $not$ls180.v:5768$1171_Y end - attribute \src "ls180.v:5775.61-5775.92" - cell $not $not$ls180.v:5775$1179 + attribute \src "ls180.v:5771.61-5771.92" + cell $not $not$ls180.v:5771$1178 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:5775$1179_Y + connect \Y $not$ls180.v:5771$1178_Y end - attribute \src "ls180.v:5778.61-5778.92" - cell $not $not$ls180.v:5778$1186 + attribute \src "ls180.v:5774.61-5774.92" + cell $not $not$ls180.v:5774$1185 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:5778$1186_Y + connect \Y $not$ls180.v:5774$1185_Y end - attribute \src "ls180.v:5789.64-5789.95" - cell $not $not$ls180.v:5789$1194 + attribute \src "ls180.v:5785.64-5785.95" + cell $not $not$ls180.v:5785$1193 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface2_bank_bus_we - connect \Y $not$ls180.v:5789$1194_Y + connect \Y $not$ls180.v:5785$1193_Y end - attribute \src "ls180.v:5792.63-5792.94" - cell $not $not$ls180.v:5792$1201 + attribute \src "ls180.v:5788.63-5788.94" + cell $not $not$ls180.v:5788$1200 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface2_bank_bus_we - connect \Y $not$ls180.v:5792$1201_Y + connect \Y $not$ls180.v:5788$1200_Y end - attribute \src "ls180.v:5795.63-5795.94" - cell $not $not$ls180.v:5795$1208 + attribute \src "ls180.v:5791.63-5791.94" + cell $not $not$ls180.v:5791$1207 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface2_bank_bus_we - connect \Y $not$ls180.v:5795$1208_Y + connect \Y $not$ls180.v:5791$1207_Y end - attribute \src "ls180.v:5798.63-5798.94" - cell $not $not$ls180.v:5798$1215 + attribute \src "ls180.v:5794.63-5794.94" + cell $not $not$ls180.v:5794$1214 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface2_bank_bus_we - connect \Y $not$ls180.v:5798$1215_Y + connect \Y $not$ls180.v:5794$1214_Y end - attribute \src "ls180.v:5801.63-5801.94" - cell $not $not$ls180.v:5801$1222 + attribute \src "ls180.v:5797.63-5797.94" + cell $not $not$ls180.v:5797$1221 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface2_bank_bus_we - connect \Y $not$ls180.v:5801$1222_Y + connect \Y $not$ls180.v:5797$1221_Y end - attribute \src "ls180.v:5804.64-5804.95" - cell $not $not$ls180.v:5804$1229 + attribute \src "ls180.v:5800.64-5800.95" + cell $not $not$ls180.v:5800$1228 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface2_bank_bus_we - connect \Y $not$ls180.v:5804$1229_Y + connect \Y $not$ls180.v:5800$1228_Y end - attribute \src "ls180.v:5807.64-5807.95" - cell $not $not$ls180.v:5807$1236 + attribute \src "ls180.v:5803.64-5803.95" + cell $not $not$ls180.v:5803$1235 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface2_bank_bus_we - connect \Y $not$ls180.v:5807$1236_Y + connect \Y $not$ls180.v:5803$1235_Y end - attribute \src "ls180.v:5810.64-5810.95" - cell $not $not$ls180.v:5810$1243 + attribute \src "ls180.v:5806.64-5806.95" + cell $not $not$ls180.v:5806$1242 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface2_bank_bus_we - connect \Y $not$ls180.v:5810$1243_Y + connect \Y $not$ls180.v:5806$1242_Y end - attribute \src "ls180.v:5813.64-5813.95" - cell $not $not$ls180.v:5813$1250 + attribute \src "ls180.v:5809.64-5809.95" + cell $not $not$ls180.v:5809$1249 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface2_bank_bus_we - connect \Y $not$ls180.v:5813$1250_Y + connect \Y $not$ls180.v:5809$1249_Y end - attribute \src "ls180.v:5826.64-5826.95" - cell $not $not$ls180.v:5826$1258 + attribute \src "ls180.v:5822.64-5822.95" + cell $not $not$ls180.v:5822$1257 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5826$1258_Y + connect \Y $not$ls180.v:5822$1257_Y end - attribute \src "ls180.v:5829.63-5829.94" - cell $not $not$ls180.v:5829$1265 + attribute \src "ls180.v:5825.63-5825.94" + cell $not $not$ls180.v:5825$1264 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5829$1265_Y + connect \Y $not$ls180.v:5825$1264_Y end - attribute \src "ls180.v:5832.63-5832.94" - cell $not $not$ls180.v:5832$1272 + attribute \src "ls180.v:5828.63-5828.94" + cell $not $not$ls180.v:5828$1271 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5832$1272_Y + connect \Y $not$ls180.v:5828$1271_Y end - attribute \src "ls180.v:5835.63-5835.94" - cell $not $not$ls180.v:5835$1279 + attribute \src "ls180.v:5831.63-5831.94" + cell $not $not$ls180.v:5831$1278 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5835$1279_Y + connect \Y $not$ls180.v:5831$1278_Y end - attribute \src "ls180.v:5838.63-5838.94" - cell $not $not$ls180.v:5838$1286 + attribute \src "ls180.v:5834.63-5834.94" + cell $not $not$ls180.v:5834$1285 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5838$1286_Y + connect \Y $not$ls180.v:5834$1285_Y end - attribute \src "ls180.v:5841.64-5841.95" - cell $not $not$ls180.v:5841$1293 + attribute \src "ls180.v:5837.64-5837.95" + cell $not $not$ls180.v:5837$1292 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5841$1293_Y + connect \Y $not$ls180.v:5837$1292_Y end - attribute \src "ls180.v:5844.64-5844.95" - cell $not $not$ls180.v:5844$1300 + attribute \src "ls180.v:5840.64-5840.95" + cell $not $not$ls180.v:5840$1299 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5844$1300_Y + connect \Y $not$ls180.v:5840$1299_Y end - attribute \src "ls180.v:5847.64-5847.95" - cell $not $not$ls180.v:5847$1307 + attribute \src "ls180.v:5843.64-5843.95" + cell $not $not$ls180.v:5843$1306 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5847$1307_Y + connect \Y $not$ls180.v:5843$1306_Y end - attribute \src "ls180.v:5850.64-5850.95" - cell $not $not$ls180.v:5850$1314 + attribute \src "ls180.v:5846.64-5846.95" + cell $not $not$ls180.v:5846$1313 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5850$1314_Y + connect \Y $not$ls180.v:5846$1313_Y end - attribute \src "ls180.v:5863.66-5863.97" - cell $not $not$ls180.v:5863$1322 + attribute \src "ls180.v:5859.66-5859.97" + cell $not $not$ls180.v:5859$1321 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5863$1322_Y + connect \Y $not$ls180.v:5859$1321_Y end - attribute \src "ls180.v:5866.66-5866.97" - cell $not $not$ls180.v:5866$1329 + attribute \src "ls180.v:5862.66-5862.97" + cell $not $not$ls180.v:5862$1328 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5866$1329_Y + connect \Y $not$ls180.v:5862$1328_Y end - attribute \src "ls180.v:5869.66-5869.97" - cell $not $not$ls180.v:5869$1336 + attribute \src "ls180.v:5865.66-5865.97" + cell $not $not$ls180.v:5865$1335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5869$1336_Y + connect \Y $not$ls180.v:5865$1335_Y end - attribute \src "ls180.v:5872.66-5872.97" - cell $not $not$ls180.v:5872$1343 + attribute \src "ls180.v:5868.66-5868.97" + cell $not $not$ls180.v:5868$1342 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5872$1343_Y + connect \Y $not$ls180.v:5868$1342_Y end - attribute \src "ls180.v:5875.66-5875.97" - cell $not $not$ls180.v:5875$1350 + attribute \src "ls180.v:5871.66-5871.97" + cell $not $not$ls180.v:5871$1349 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5875$1350_Y + connect \Y $not$ls180.v:5871$1349_Y end - attribute \src "ls180.v:5878.66-5878.97" - cell $not $not$ls180.v:5878$1357 + attribute \src "ls180.v:5874.66-5874.97" + cell $not $not$ls180.v:5874$1356 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5878$1357_Y + connect \Y $not$ls180.v:5874$1356_Y end - attribute \src "ls180.v:5881.66-5881.97" - cell $not $not$ls180.v:5881$1364 + attribute \src "ls180.v:5877.66-5877.97" + cell $not $not$ls180.v:5877$1363 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5881$1364_Y + connect \Y $not$ls180.v:5877$1363_Y end - attribute \src "ls180.v:5884.66-5884.97" - cell $not $not$ls180.v:5884$1371 + attribute \src "ls180.v:5880.66-5880.97" + cell $not $not$ls180.v:5880$1370 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5884$1371_Y + connect \Y $not$ls180.v:5880$1370_Y end - attribute \src "ls180.v:5887.68-5887.99" - cell $not $not$ls180.v:5887$1378 + attribute \src "ls180.v:5883.68-5883.99" + cell $not $not$ls180.v:5883$1377 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5887$1378_Y + connect \Y $not$ls180.v:5883$1377_Y end - attribute \src "ls180.v:5890.68-5890.99" - cell $not $not$ls180.v:5890$1385 + attribute \src "ls180.v:5886.68-5886.99" + cell $not $not$ls180.v:5886$1384 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5890$1385_Y + connect \Y $not$ls180.v:5886$1384_Y end - attribute \src "ls180.v:5893.68-5893.99" - cell $not $not$ls180.v:5893$1392 + attribute \src "ls180.v:5889.68-5889.99" + cell $not $not$ls180.v:5889$1391 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5893$1392_Y + connect \Y $not$ls180.v:5889$1391_Y end - attribute \src "ls180.v:5896.68-5896.99" - cell $not $not$ls180.v:5896$1399 + attribute \src "ls180.v:5892.68-5892.99" + cell $not $not$ls180.v:5892$1398 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5896$1399_Y + connect \Y $not$ls180.v:5892$1398_Y end - attribute \src "ls180.v:5899.68-5899.99" - cell $not $not$ls180.v:5899$1406 + attribute \src "ls180.v:5895.68-5895.99" + cell $not $not$ls180.v:5895$1405 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5899$1406_Y + connect \Y $not$ls180.v:5895$1405_Y end - attribute \src "ls180.v:5902.65-5902.96" - cell $not $not$ls180.v:5902$1413 + attribute \src "ls180.v:5898.65-5898.96" + cell $not $not$ls180.v:5898$1412 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5902$1413_Y + connect \Y $not$ls180.v:5898$1412_Y end - attribute \src "ls180.v:5905.66-5905.97" - cell $not $not$ls180.v:5905$1420 + attribute \src "ls180.v:5901.66-5901.97" + cell $not $not$ls180.v:5901$1419 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5905$1420_Y + connect \Y $not$ls180.v:5901$1419_Y end - attribute \src "ls180.v:5925.70-5925.101" - cell $not $not$ls180.v:5925$1428 + attribute \src "ls180.v:5921.70-5921.101" + cell $not $not$ls180.v:5921$1427 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5925$1428_Y + connect \Y $not$ls180.v:5921$1427_Y end - attribute \src "ls180.v:5928.70-5928.101" - cell $not $not$ls180.v:5928$1435 + attribute \src "ls180.v:5924.70-5924.101" + cell $not $not$ls180.v:5924$1434 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5928$1435_Y + connect \Y $not$ls180.v:5924$1434_Y end - attribute \src "ls180.v:5931.70-5931.101" - cell $not $not$ls180.v:5931$1442 + attribute \src "ls180.v:5927.70-5927.101" + cell $not $not$ls180.v:5927$1441 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5931$1442_Y + connect \Y $not$ls180.v:5927$1441_Y end - attribute \src "ls180.v:5934.70-5934.101" - cell $not $not$ls180.v:5934$1449 + attribute \src "ls180.v:5930.70-5930.101" + cell $not $not$ls180.v:5930$1448 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5934$1449_Y + connect \Y $not$ls180.v:5930$1448_Y end - attribute \src "ls180.v:5937.69-5937.100" - cell $not $not$ls180.v:5937$1456 + attribute \src "ls180.v:5933.69-5933.100" + cell $not $not$ls180.v:5933$1455 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5937$1456_Y + connect \Y $not$ls180.v:5933$1455_Y end - attribute \src "ls180.v:5940.69-5940.100" - cell $not $not$ls180.v:5940$1463 + attribute \src "ls180.v:5936.69-5936.100" + cell $not $not$ls180.v:5936$1462 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5940$1463_Y + connect \Y $not$ls180.v:5936$1462_Y end - attribute \src "ls180.v:5943.69-5943.100" - cell $not $not$ls180.v:5943$1470 + attribute \src "ls180.v:5939.69-5939.100" + cell $not $not$ls180.v:5939$1469 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5943$1470_Y + connect \Y $not$ls180.v:5939$1469_Y end - attribute \src "ls180.v:5946.69-5946.100" - cell $not $not$ls180.v:5946$1477 + attribute \src "ls180.v:5942.69-5942.100" + cell $not $not$ls180.v:5942$1476 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5946$1477_Y + connect \Y $not$ls180.v:5942$1476_Y end - attribute \src "ls180.v:5949.60-5949.91" - cell $not $not$ls180.v:5949$1484 + attribute \src "ls180.v:5945.60-5945.91" + cell $not $not$ls180.v:5945$1483 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5949$1484_Y + connect \Y $not$ls180.v:5945$1483_Y end - attribute \src "ls180.v:5952.71-5952.102" - cell $not $not$ls180.v:5952$1491 + attribute \src "ls180.v:5948.71-5948.102" + cell $not $not$ls180.v:5948$1490 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5952$1491_Y + connect \Y $not$ls180.v:5948$1490_Y end - attribute \src "ls180.v:5955.71-5955.102" - cell $not $not$ls180.v:5955$1498 + attribute \src "ls180.v:5951.71-5951.102" + cell $not $not$ls180.v:5951$1497 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5955$1498_Y + connect \Y $not$ls180.v:5951$1497_Y end - attribute \src "ls180.v:5958.71-5958.102" - cell $not $not$ls180.v:5958$1505 + attribute \src "ls180.v:5954.71-5954.102" + cell $not $not$ls180.v:5954$1504 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5958$1505_Y + connect \Y $not$ls180.v:5954$1504_Y end - attribute \src "ls180.v:5961.71-5961.102" - cell $not $not$ls180.v:5961$1512 + attribute \src "ls180.v:5957.71-5957.102" + cell $not $not$ls180.v:5957$1511 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5961$1512_Y + connect \Y $not$ls180.v:5957$1511_Y end - attribute \src "ls180.v:5964.71-5964.102" - cell $not $not$ls180.v:5964$1519 + attribute \src "ls180.v:5960.71-5960.102" + cell $not $not$ls180.v:5960$1518 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5964$1519_Y + connect \Y $not$ls180.v:5960$1518_Y end - attribute \src "ls180.v:5967.71-5967.102" - cell $not $not$ls180.v:5967$1526 + attribute \src "ls180.v:5963.71-5963.102" + cell $not $not$ls180.v:5963$1525 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5967$1526_Y + connect \Y $not$ls180.v:5963$1525_Y end - attribute \src "ls180.v:5970.70-5970.101" - cell $not $not$ls180.v:5970$1533 + attribute \src "ls180.v:5966.70-5966.101" + cell $not $not$ls180.v:5966$1532 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5970$1533_Y + connect \Y $not$ls180.v:5966$1532_Y end - attribute \src "ls180.v:5973.70-5973.101" - cell $not $not$ls180.v:5973$1540 + attribute \src "ls180.v:5969.70-5969.101" + cell $not $not$ls180.v:5969$1539 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5973$1540_Y + connect \Y $not$ls180.v:5969$1539_Y end - attribute \src "ls180.v:5976.70-5976.101" - cell $not $not$ls180.v:5976$1547 + attribute \src "ls180.v:5972.70-5972.101" + cell $not $not$ls180.v:5972$1546 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5976$1547_Y + connect \Y $not$ls180.v:5972$1546_Y end - attribute \src "ls180.v:5979.70-5979.101" - cell $not $not$ls180.v:5979$1554 + attribute \src "ls180.v:5975.70-5975.101" + cell $not $not$ls180.v:5975$1553 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5979$1554_Y + connect \Y $not$ls180.v:5975$1553_Y end - attribute \src "ls180.v:5982.70-5982.101" - cell $not $not$ls180.v:5982$1561 + attribute \src "ls180.v:5978.70-5978.101" + cell $not $not$ls180.v:5978$1560 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5982$1561_Y + connect \Y $not$ls180.v:5978$1560_Y end - attribute \src "ls180.v:5985.70-5985.101" - cell $not $not$ls180.v:5985$1568 + attribute \src "ls180.v:5981.70-5981.101" + cell $not $not$ls180.v:5981$1567 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5985$1568_Y + connect \Y $not$ls180.v:5981$1567_Y end - attribute \src "ls180.v:5988.70-5988.101" - cell $not $not$ls180.v:5988$1575 + attribute \src "ls180.v:5984.70-5984.101" + cell $not $not$ls180.v:5984$1574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5988$1575_Y + connect \Y $not$ls180.v:5984$1574_Y end - attribute \src "ls180.v:5991.70-5991.101" - cell $not $not$ls180.v:5991$1582 + attribute \src "ls180.v:5987.70-5987.101" + cell $not $not$ls180.v:5987$1581 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5991$1582_Y + connect \Y $not$ls180.v:5987$1581_Y end - attribute \src "ls180.v:5994.70-5994.101" - cell $not $not$ls180.v:5994$1589 + attribute \src "ls180.v:5990.70-5990.101" + cell $not $not$ls180.v:5990$1588 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5994$1589_Y + connect \Y $not$ls180.v:5990$1588_Y end - attribute \src "ls180.v:5997.70-5997.101" - cell $not $not$ls180.v:5997$1596 + attribute \src "ls180.v:5993.70-5993.101" + cell $not $not$ls180.v:5993$1595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5997$1596_Y + connect \Y $not$ls180.v:5993$1595_Y end - attribute \src "ls180.v:6000.66-6000.97" - cell $not $not$ls180.v:6000$1603 + attribute \src "ls180.v:5996.66-5996.97" + cell $not $not$ls180.v:5996$1602 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6000$1603_Y + connect \Y $not$ls180.v:5996$1602_Y end - attribute \src "ls180.v:6003.67-6003.98" - cell $not $not$ls180.v:6003$1610 + attribute \src "ls180.v:5999.67-5999.98" + cell $not $not$ls180.v:5999$1609 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6003$1610_Y + connect \Y $not$ls180.v:5999$1609_Y end - attribute \src "ls180.v:6006.70-6006.101" - cell $not $not$ls180.v:6006$1617 + attribute \src "ls180.v:6002.70-6002.101" + cell $not $not$ls180.v:6002$1616 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6006$1617_Y + connect \Y $not$ls180.v:6002$1616_Y end - attribute \src "ls180.v:6009.70-6009.101" - cell $not $not$ls180.v:6009$1624 + attribute \src "ls180.v:6005.70-6005.101" + cell $not $not$ls180.v:6005$1623 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6009$1624_Y + connect \Y $not$ls180.v:6005$1623_Y end - attribute \src "ls180.v:6012.69-6012.100" - cell $not $not$ls180.v:6012$1631 + attribute \src "ls180.v:6008.69-6008.100" + cell $not $not$ls180.v:6008$1630 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6012$1631_Y + connect \Y $not$ls180.v:6008$1630_Y end - attribute \src "ls180.v:6015.69-6015.100" - cell $not $not$ls180.v:6015$1638 + attribute \src "ls180.v:6011.69-6011.100" + cell $not $not$ls180.v:6011$1637 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6015$1638_Y + connect \Y $not$ls180.v:6011$1637_Y end - attribute \src "ls180.v:6018.69-6018.100" - cell $not $not$ls180.v:6018$1645 + attribute \src "ls180.v:6014.69-6014.100" + cell $not $not$ls180.v:6014$1644 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6018$1645_Y + connect \Y $not$ls180.v:6014$1644_Y end - attribute \src "ls180.v:6021.69-6021.100" - cell $not $not$ls180.v:6021$1652 + attribute \src "ls180.v:6017.69-6017.100" + cell $not $not$ls180.v:6017$1651 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6021$1652_Y + connect \Y $not$ls180.v:6017$1651_Y end - attribute \src "ls180.v:6060.66-6060.97" - cell $not $not$ls180.v:6060$1660 + attribute \src "ls180.v:6056.66-6056.97" + cell $not $not$ls180.v:6056$1659 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6060$1660_Y + connect \Y $not$ls180.v:6056$1659_Y end - attribute \src "ls180.v:6063.66-6063.97" - cell $not $not$ls180.v:6063$1667 + attribute \src "ls180.v:6059.66-6059.97" + cell $not $not$ls180.v:6059$1666 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6063$1667_Y + connect \Y $not$ls180.v:6059$1666_Y end - attribute \src "ls180.v:6066.66-6066.97" - cell $not $not$ls180.v:6066$1674 + attribute \src "ls180.v:6062.66-6062.97" + cell $not $not$ls180.v:6062$1673 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6066$1674_Y + connect \Y $not$ls180.v:6062$1673_Y end - attribute \src "ls180.v:6069.66-6069.97" - cell $not $not$ls180.v:6069$1681 + attribute \src "ls180.v:6065.66-6065.97" + cell $not $not$ls180.v:6065$1680 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6069$1681_Y + connect \Y $not$ls180.v:6065$1680_Y end - attribute \src "ls180.v:6072.66-6072.97" - cell $not $not$ls180.v:6072$1688 + attribute \src "ls180.v:6068.66-6068.97" + cell $not $not$ls180.v:6068$1687 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6072$1688_Y + connect \Y $not$ls180.v:6068$1687_Y end - attribute \src "ls180.v:6075.66-6075.97" - cell $not $not$ls180.v:6075$1695 + attribute \src "ls180.v:6071.66-6071.97" + cell $not $not$ls180.v:6071$1694 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6075$1695_Y + connect \Y $not$ls180.v:6071$1694_Y end - attribute \src "ls180.v:6078.66-6078.97" - cell $not $not$ls180.v:6078$1702 + attribute \src "ls180.v:6074.66-6074.97" + cell $not $not$ls180.v:6074$1701 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6078$1702_Y + connect \Y $not$ls180.v:6074$1701_Y end - attribute \src "ls180.v:6081.66-6081.97" - cell $not $not$ls180.v:6081$1709 + attribute \src "ls180.v:6077.66-6077.97" + cell $not $not$ls180.v:6077$1708 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6081$1709_Y + connect \Y $not$ls180.v:6077$1708_Y end - attribute \src "ls180.v:6084.68-6084.99" - cell $not $not$ls180.v:6084$1716 + attribute \src "ls180.v:6080.68-6080.99" + cell $not $not$ls180.v:6080$1715 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6084$1716_Y + connect \Y $not$ls180.v:6080$1715_Y end - attribute \src "ls180.v:6087.68-6087.99" - cell $not $not$ls180.v:6087$1723 + attribute \src "ls180.v:6083.68-6083.99" + cell $not $not$ls180.v:6083$1722 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6087$1723_Y + connect \Y $not$ls180.v:6083$1722_Y end - attribute \src "ls180.v:6090.68-6090.99" - cell $not $not$ls180.v:6090$1730 + attribute \src "ls180.v:6086.68-6086.99" + cell $not $not$ls180.v:6086$1729 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6090$1730_Y + connect \Y $not$ls180.v:6086$1729_Y end - attribute \src "ls180.v:6093.68-6093.99" - cell $not $not$ls180.v:6093$1737 + attribute \src "ls180.v:6089.68-6089.99" + cell $not $not$ls180.v:6089$1736 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6093$1737_Y + connect \Y $not$ls180.v:6089$1736_Y end - attribute \src "ls180.v:6096.68-6096.99" - cell $not $not$ls180.v:6096$1744 + attribute \src "ls180.v:6092.68-6092.99" + cell $not $not$ls180.v:6092$1743 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6096$1744_Y + connect \Y $not$ls180.v:6092$1743_Y end - attribute \src "ls180.v:6099.65-6099.96" - cell $not $not$ls180.v:6099$1751 + attribute \src "ls180.v:6095.65-6095.96" + cell $not $not$ls180.v:6095$1750 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6099$1751_Y + connect \Y $not$ls180.v:6095$1750_Y end - attribute \src "ls180.v:6102.66-6102.97" - cell $not $not$ls180.v:6102$1758 + attribute \src "ls180.v:6098.66-6098.97" + cell $not $not$ls180.v:6098$1757 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6102$1758_Y + connect \Y $not$ls180.v:6098$1757_Y end - attribute \src "ls180.v:6105.68-6105.99" - cell $not $not$ls180.v:6105$1765 + attribute \src "ls180.v:6101.68-6101.99" + cell $not $not$ls180.v:6101$1764 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6105$1765_Y + connect \Y $not$ls180.v:6101$1764_Y end - attribute \src "ls180.v:6108.68-6108.99" - cell $not $not$ls180.v:6108$1772 + attribute \src "ls180.v:6104.68-6104.99" + cell $not $not$ls180.v:6104$1771 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6108$1772_Y + connect \Y $not$ls180.v:6104$1771_Y end - attribute \src "ls180.v:6111.68-6111.99" - cell $not $not$ls180.v:6111$1779 + attribute \src "ls180.v:6107.68-6107.99" + cell $not $not$ls180.v:6107$1778 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6111$1779_Y + connect \Y $not$ls180.v:6107$1778_Y end - attribute \src "ls180.v:6114.68-6114.99" - cell $not $not$ls180.v:6114$1786 + attribute \src "ls180.v:6110.68-6110.99" + cell $not $not$ls180.v:6110$1785 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6114$1786_Y + connect \Y $not$ls180.v:6110$1785_Y end - attribute \src "ls180.v:6139.68-6139.99" - cell $not $not$ls180.v:6139$1794 + attribute \src "ls180.v:6135.68-6135.99" + cell $not $not$ls180.v:6135$1793 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6139$1794_Y + connect \Y $not$ls180.v:6135$1793_Y end - attribute \src "ls180.v:6142.73-6142.104" - cell $not $not$ls180.v:6142$1801 + attribute \src "ls180.v:6138.73-6138.104" + cell $not $not$ls180.v:6138$1800 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6142$1801_Y + connect \Y $not$ls180.v:6138$1800_Y end - attribute \src "ls180.v:6145.73-6145.104" - cell $not $not$ls180.v:6145$1808 + attribute \src "ls180.v:6141.73-6141.104" + cell $not $not$ls180.v:6141$1807 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6145$1808_Y + connect \Y $not$ls180.v:6141$1807_Y end - attribute \src "ls180.v:6148.66-6148.97" - cell $not $not$ls180.v:6148$1815 + attribute \src "ls180.v:6144.66-6144.97" + cell $not $not$ls180.v:6144$1814 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6148$1815_Y + connect \Y $not$ls180.v:6144$1814_Y end - attribute \src "ls180.v:6156.70-6156.101" - cell $not $not$ls180.v:6156$1823 + attribute \src "ls180.v:6152.70-6152.101" + cell $not $not$ls180.v:6152$1822 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_we - connect \Y $not$ls180.v:6156$1823_Y + connect \Y $not$ls180.v:6152$1822_Y end - attribute \src "ls180.v:6159.74-6159.105" - cell $not $not$ls180.v:6159$1830 + attribute \src "ls180.v:6155.74-6155.105" + cell $not $not$ls180.v:6155$1829 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_we - connect \Y $not$ls180.v:6159$1830_Y + connect \Y $not$ls180.v:6155$1829_Y end - attribute \src "ls180.v:6162.64-6162.95" - cell $not $not$ls180.v:6162$1837 + attribute \src "ls180.v:6158.64-6158.95" + cell $not $not$ls180.v:6158$1836 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_we - connect \Y $not$ls180.v:6162$1837_Y + connect \Y $not$ls180.v:6158$1836_Y end - attribute \src "ls180.v:6165.74-6165.105" - cell $not $not$ls180.v:6165$1844 + attribute \src "ls180.v:6161.74-6161.105" + cell $not $not$ls180.v:6161$1843 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_we - connect \Y $not$ls180.v:6165$1844_Y + connect \Y $not$ls180.v:6161$1843_Y end - attribute \src "ls180.v:6168.74-6168.105" - cell $not $not$ls180.v:6168$1851 + attribute \src "ls180.v:6164.74-6164.105" + cell $not $not$ls180.v:6164$1850 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_we - connect \Y $not$ls180.v:6168$1851_Y + connect \Y $not$ls180.v:6164$1850_Y end - attribute \src "ls180.v:6171.75-6171.106" - cell $not $not$ls180.v:6171$1858 + attribute \src "ls180.v:6167.75-6167.106" + cell $not $not$ls180.v:6167$1857 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_we - connect \Y $not$ls180.v:6171$1858_Y + connect \Y $not$ls180.v:6167$1857_Y end - attribute \src "ls180.v:6174.73-6174.104" - cell $not $not$ls180.v:6174$1865 + attribute \src "ls180.v:6170.73-6170.104" + cell $not $not$ls180.v:6170$1864 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_we - connect \Y $not$ls180.v:6174$1865_Y + connect \Y $not$ls180.v:6170$1864_Y end - attribute \src "ls180.v:6177.73-6177.104" - cell $not $not$ls180.v:6177$1872 + attribute \src "ls180.v:6173.73-6173.104" + cell $not $not$ls180.v:6173$1871 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_we - connect \Y $not$ls180.v:6177$1872_Y + connect \Y $not$ls180.v:6173$1871_Y end - attribute \src "ls180.v:6180.73-6180.104" - cell $not $not$ls180.v:6180$1879 + attribute \src "ls180.v:6176.73-6176.104" + cell $not $not$ls180.v:6176$1878 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_we - connect \Y $not$ls180.v:6180$1879_Y + connect \Y $not$ls180.v:6176$1878_Y end - attribute \src "ls180.v:6183.73-6183.104" - cell $not $not$ls180.v:6183$1886 + attribute \src "ls180.v:6179.73-6179.104" + cell $not $not$ls180.v:6179$1885 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_we - connect \Y $not$ls180.v:6183$1886_Y + connect \Y $not$ls180.v:6179$1885_Y end - attribute \src "ls180.v:6201.65-6201.96" - cell $not $not$ls180.v:6201$1894 + attribute \src "ls180.v:6197.65-6197.96" + cell $not $not$ls180.v:6197$1893 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6201$1894_Y + connect \Y $not$ls180.v:6197$1893_Y end - attribute \src "ls180.v:6204.65-6204.96" - cell $not $not$ls180.v:6204$1901 + attribute \src "ls180.v:6200.65-6200.96" + cell $not $not$ls180.v:6200$1900 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6204$1901_Y + connect \Y $not$ls180.v:6200$1900_Y end - attribute \src "ls180.v:6207.63-6207.94" - cell $not $not$ls180.v:6207$1908 + attribute \src "ls180.v:6203.63-6203.94" + cell $not $not$ls180.v:6203$1907 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6207$1908_Y + connect \Y $not$ls180.v:6203$1907_Y end - attribute \src "ls180.v:6210.62-6210.93" - cell $not $not$ls180.v:6210$1915 + attribute \src "ls180.v:6206.62-6206.93" + cell $not $not$ls180.v:6206$1914 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6210$1915_Y + connect \Y $not$ls180.v:6206$1914_Y end - attribute \src "ls180.v:6213.61-6213.92" - cell $not $not$ls180.v:6213$1922 + attribute \src "ls180.v:6209.61-6209.92" + cell $not $not$ls180.v:6209$1921 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6213$1922_Y + connect \Y $not$ls180.v:6209$1921_Y end - attribute \src "ls180.v:6216.60-6216.91" - cell $not $not$ls180.v:6216$1929 + attribute \src "ls180.v:6212.60-6212.91" + cell $not $not$ls180.v:6212$1928 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6216$1929_Y + connect \Y $not$ls180.v:6212$1928_Y end - attribute \src "ls180.v:6219.66-6219.97" - cell $not $not$ls180.v:6219$1936 + attribute \src "ls180.v:6215.66-6215.97" + cell $not $not$ls180.v:6215$1935 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6219$1936_Y + connect \Y $not$ls180.v:6215$1935_Y end - attribute \src "ls180.v:6241.67-6241.99" - cell $not $not$ls180.v:6241$1945 + attribute \src "ls180.v:6237.67-6237.99" + cell $not $not$ls180.v:6237$1944 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6241$1945_Y + connect \Y $not$ls180.v:6237$1944_Y end - attribute \src "ls180.v:6244.67-6244.99" - cell $not $not$ls180.v:6244$1952 + attribute \src "ls180.v:6240.67-6240.99" + cell $not $not$ls180.v:6240$1951 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6244$1952_Y + connect \Y $not$ls180.v:6240$1951_Y end - attribute \src "ls180.v:6247.65-6247.97" - cell $not $not$ls180.v:6247$1959 + attribute \src "ls180.v:6243.65-6243.97" + cell $not $not$ls180.v:6243$1958 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6247$1959_Y + connect \Y $not$ls180.v:6243$1958_Y end - attribute \src "ls180.v:6250.64-6250.96" - cell $not $not$ls180.v:6250$1966 + attribute \src "ls180.v:6246.64-6246.96" + cell $not $not$ls180.v:6246$1965 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6250$1966_Y + connect \Y $not$ls180.v:6246$1965_Y end - attribute \src "ls180.v:6253.63-6253.95" - cell $not $not$ls180.v:6253$1973 + attribute \src "ls180.v:6249.63-6249.95" + cell $not $not$ls180.v:6249$1972 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6253$1973_Y + connect \Y $not$ls180.v:6249$1972_Y end - attribute \src "ls180.v:6256.62-6256.94" - cell $not $not$ls180.v:6256$1980 + attribute \src "ls180.v:6252.62-6252.94" + cell $not $not$ls180.v:6252$1979 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6256$1980_Y + connect \Y $not$ls180.v:6252$1979_Y end - attribute \src "ls180.v:6259.68-6259.100" - cell $not $not$ls180.v:6259$1987 + attribute \src "ls180.v:6255.68-6255.100" + cell $not $not$ls180.v:6255$1986 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6259$1987_Y + connect \Y $not$ls180.v:6255$1986_Y end - attribute \src "ls180.v:6262.71-6262.103" - cell $not $not$ls180.v:6262$1994 + attribute \src "ls180.v:6258.71-6258.103" + cell $not $not$ls180.v:6258$1993 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6262$1994_Y + connect \Y $not$ls180.v:6258$1993_Y end - attribute \src "ls180.v:6265.71-6265.103" - cell $not $not$ls180.v:6265$2001 + attribute \src "ls180.v:6261.71-6261.103" + cell $not $not$ls180.v:6261$2000 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6265$2001_Y + connect \Y $not$ls180.v:6261$2000_Y end - attribute \src "ls180.v:6289.64-6289.96" - cell $not $not$ls180.v:6289$2010 + attribute \src "ls180.v:6285.64-6285.96" + cell $not $not$ls180.v:6285$2009 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6289$2010_Y + connect \Y $not$ls180.v:6285$2009_Y end - attribute \src "ls180.v:6292.64-6292.96" - cell $not $not$ls180.v:6292$2017 + attribute \src "ls180.v:6288.64-6288.96" + cell $not $not$ls180.v:6288$2016 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6292$2017_Y + connect \Y $not$ls180.v:6288$2016_Y end - attribute \src "ls180.v:6295.64-6295.96" - cell $not $not$ls180.v:6295$2024 + attribute \src "ls180.v:6291.64-6291.96" + cell $not $not$ls180.v:6291$2023 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6295$2024_Y + connect \Y $not$ls180.v:6291$2023_Y end - attribute \src "ls180.v:6298.64-6298.96" - cell $not $not$ls180.v:6298$2031 + attribute \src "ls180.v:6294.64-6294.96" + cell $not $not$ls180.v:6294$2030 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6298$2031_Y + connect \Y $not$ls180.v:6294$2030_Y end - attribute \src "ls180.v:6301.66-6301.98" - cell $not $not$ls180.v:6301$2038 + attribute \src "ls180.v:6297.66-6297.98" + cell $not $not$ls180.v:6297$2037 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6301$2038_Y + connect \Y $not$ls180.v:6297$2037_Y end - attribute \src "ls180.v:6304.66-6304.98" - cell $not $not$ls180.v:6304$2045 + attribute \src "ls180.v:6300.66-6300.98" + cell $not $not$ls180.v:6300$2044 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6304$2045_Y + connect \Y $not$ls180.v:6300$2044_Y end - attribute \src "ls180.v:6307.66-6307.98" - cell $not $not$ls180.v:6307$2052 + attribute \src "ls180.v:6303.66-6303.98" + cell $not $not$ls180.v:6303$2051 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6307$2052_Y + connect \Y $not$ls180.v:6303$2051_Y end - attribute \src "ls180.v:6310.66-6310.98" - cell $not $not$ls180.v:6310$2059 + attribute \src "ls180.v:6306.66-6306.98" + cell $not $not$ls180.v:6306$2058 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6310$2059_Y + connect \Y $not$ls180.v:6306$2058_Y end - attribute \src "ls180.v:6313.62-6313.94" - cell $not $not$ls180.v:6313$2066 + attribute \src "ls180.v:6309.62-6309.94" + cell $not $not$ls180.v:6309$2065 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6313$2066_Y + connect \Y $not$ls180.v:6309$2065_Y end - attribute \src "ls180.v:6316.72-6316.104" - cell $not $not$ls180.v:6316$2073 + attribute \src "ls180.v:6312.72-6312.104" + cell $not $not$ls180.v:6312$2072 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6316$2073_Y + connect \Y $not$ls180.v:6312$2072_Y end - attribute \src "ls180.v:6319.65-6319.97" - cell $not $not$ls180.v:6319$2080 + attribute \src "ls180.v:6315.65-6315.97" + cell $not $not$ls180.v:6315$2079 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6319$2080_Y + connect \Y $not$ls180.v:6315$2079_Y end - attribute \src "ls180.v:6322.65-6322.97" - cell $not $not$ls180.v:6322$2087 + attribute \src "ls180.v:6318.65-6318.97" + cell $not $not$ls180.v:6318$2086 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6322$2087_Y + connect \Y $not$ls180.v:6318$2086_Y end - attribute \src "ls180.v:6325.65-6325.97" - cell $not $not$ls180.v:6325$2094 + attribute \src "ls180.v:6321.65-6321.97" + cell $not $not$ls180.v:6321$2093 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6325$2094_Y + connect \Y $not$ls180.v:6321$2093_Y end - attribute \src "ls180.v:6328.65-6328.97" - cell $not $not$ls180.v:6328$2101 + attribute \src "ls180.v:6324.65-6324.97" + cell $not $not$ls180.v:6324$2100 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6328$2101_Y + connect \Y $not$ls180.v:6324$2100_Y end - attribute \src "ls180.v:6331.77-6331.109" - cell $not $not$ls180.v:6331$2108 + attribute \src "ls180.v:6327.77-6327.109" + cell $not $not$ls180.v:6327$2107 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6331$2108_Y + connect \Y $not$ls180.v:6327$2107_Y end - attribute \src "ls180.v:6334.78-6334.110" - cell $not $not$ls180.v:6334$2115 + attribute \src "ls180.v:6330.78-6330.110" + cell $not $not$ls180.v:6330$2114 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6334$2115_Y + connect \Y $not$ls180.v:6330$2114_Y end - attribute \src "ls180.v:6337.69-6337.101" - cell $not $not$ls180.v:6337$2122 + attribute \src "ls180.v:6333.69-6333.101" + cell $not $not$ls180.v:6333$2121 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6337$2122_Y + connect \Y $not$ls180.v:6333$2121_Y end - attribute \src "ls180.v:6357.55-6357.87" - cell $not $not$ls180.v:6357$2130 + attribute \src "ls180.v:6353.55-6353.87" + cell $not $not$ls180.v:6353$2129 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6357$2130_Y + connect \Y $not$ls180.v:6353$2129_Y end - attribute \src "ls180.v:6360.65-6360.97" - cell $not $not$ls180.v:6360$2137 + attribute \src "ls180.v:6356.65-6356.97" + cell $not $not$ls180.v:6356$2136 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6360$2137_Y + connect \Y $not$ls180.v:6356$2136_Y end - attribute \src "ls180.v:6363.66-6363.98" - cell $not $not$ls180.v:6363$2144 + attribute \src "ls180.v:6359.66-6359.98" + cell $not $not$ls180.v:6359$2143 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6363$2144_Y + connect \Y $not$ls180.v:6359$2143_Y end - attribute \src "ls180.v:6366.70-6366.102" - cell $not $not$ls180.v:6366$2151 + attribute \src "ls180.v:6362.70-6362.102" + cell $not $not$ls180.v:6362$2150 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6366$2151_Y + connect \Y $not$ls180.v:6362$2150_Y end - attribute \src "ls180.v:6369.71-6369.103" - cell $not $not$ls180.v:6369$2158 + attribute \src "ls180.v:6365.71-6365.103" + cell $not $not$ls180.v:6365$2157 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6369$2158_Y + connect \Y $not$ls180.v:6365$2157_Y end - attribute \src "ls180.v:6372.69-6372.101" - cell $not $not$ls180.v:6372$2165 + attribute \src "ls180.v:6368.69-6368.101" + cell $not $not$ls180.v:6368$2164 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6372$2165_Y + connect \Y $not$ls180.v:6368$2164_Y end - attribute \src "ls180.v:6375.66-6375.98" - cell $not $not$ls180.v:6375$2172 + attribute \src "ls180.v:6371.66-6371.98" + cell $not $not$ls180.v:6371$2171 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6375$2172_Y + connect \Y $not$ls180.v:6371$2171_Y end - attribute \src "ls180.v:6378.65-6378.97" - cell $not $not$ls180.v:6378$2179 + attribute \src "ls180.v:6374.65-6374.97" + cell $not $not$ls180.v:6374$2178 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6378$2179_Y + connect \Y $not$ls180.v:6374$2178_Y end - attribute \src "ls180.v:6391.71-6391.103" - cell $not $not$ls180.v:6391$2187 + attribute \src "ls180.v:6387.71-6387.103" + cell $not $not$ls180.v:6387$2186 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6391$2187_Y + connect \Y $not$ls180.v:6387$2186_Y end - attribute \src "ls180.v:6394.71-6394.103" - cell $not $not$ls180.v:6394$2194 + attribute \src "ls180.v:6390.71-6390.103" + cell $not $not$ls180.v:6390$2193 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6394$2194_Y + connect \Y $not$ls180.v:6390$2193_Y end - attribute \src "ls180.v:6397.71-6397.103" - cell $not $not$ls180.v:6397$2201 + attribute \src "ls180.v:6393.71-6393.103" + cell $not $not$ls180.v:6393$2200 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6397$2201_Y + connect \Y $not$ls180.v:6393$2200_Y end - attribute \src "ls180.v:6400.71-6400.103" - cell $not $not$ls180.v:6400$2208 + attribute \src "ls180.v:6396.71-6396.103" + cell $not $not$ls180.v:6396$2207 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6400$2208_Y + connect \Y $not$ls180.v:6396$2207_Y end - attribute \src "ls180.v:6778.86-6778.330" - cell $not $not$ls180.v:6778$2256 + attribute \src "ls180.v:6774.86-6774.330" + cell $not $not$ls180.v:6774$2255 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6778$2255_Y - connect \Y $not$ls180.v:6778$2256_Y + connect \A $or$ls180.v:6774$2254_Y + connect \Y $not$ls180.v:6774$2255_Y end - attribute \src "ls180.v:6802.86-6802.330" - cell $not $not$ls180.v:6802$2272 + attribute \src "ls180.v:6798.86-6798.330" + cell $not $not$ls180.v:6798$2271 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6802$2271_Y - connect \Y $not$ls180.v:6802$2272_Y + connect \A $or$ls180.v:6798$2270_Y + connect \Y $not$ls180.v:6798$2271_Y end - attribute \src "ls180.v:6826.86-6826.330" - cell $not $not$ls180.v:6826$2288 + attribute \src "ls180.v:6822.86-6822.330" + cell $not $not$ls180.v:6822$2287 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6826$2287_Y - connect \Y $not$ls180.v:6826$2288_Y + connect \A $or$ls180.v:6822$2286_Y + connect \Y $not$ls180.v:6822$2287_Y end - attribute \src "ls180.v:6850.86-6850.330" - cell $not $not$ls180.v:6850$2304 + attribute \src "ls180.v:6846.86-6846.330" + cell $not $not$ls180.v:6846$2303 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6850$2303_Y - connect \Y $not$ls180.v:6850$2304_Y + connect \A $or$ls180.v:6846$2302_Y + connect \Y $not$ls180.v:6846$2303_Y end attribute \src "ls180.v:7344.18-7344.42" - cell $not $not$ls180.v:7344$2357 + cell $not $not$ls180.v:7344$2356 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_clocker_clk0 - connect \Y $not$ls180.v:7344$2357_Y + connect \Y $not$ls180.v:7344$2356_Y end - attribute \src "ls180.v:7442.72-7442.101" - cell $not $not$ls180.v:7442$2409 + attribute \src "ls180.v:7441.72-7441.101" + cell $not $not$ls180.v:7441$2407 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_ack - connect \Y $not$ls180.v:7442$2409_Y + connect \Y $not$ls180.v:7441$2407_Y end - attribute \src "ls180.v:7461.8-7461.38" - cell $not $not$ls180.v:7461$2413 + attribute \src "ls180.v:7460.8-7460.38" + cell $not $not$ls180.v:7460$2411 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_libresocsim_zero_trigger - connect \Y $not$ls180.v:7461$2413_Y + connect \Y $not$ls180.v:7460$2411_Y end - attribute \src "ls180.v:7471.32-7471.55" - cell $not $not$ls180.v:7471$2415 + attribute \src "ls180.v:7468.32-7468.55" + cell $not $not$ls180.v:7468$2413 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_timer_done0 - connect \Y $not$ls180.v:7471$2415_Y + connect \Y $not$ls180.v:7468$2413_Y end - attribute \src "ls180.v:7541.136-7541.189" - cell $not $not$ls180.v:7541$2430 + attribute \src "ls180.v:7538.136-7538.189" + cell $not $not$ls180.v:7538$2428 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7541$2430_Y + connect \Y $not$ls180.v:7538$2428_Y end - attribute \src "ls180.v:7547.136-7547.189" - cell $not $not$ls180.v:7547$2435 + attribute \src "ls180.v:7544.136-7544.189" + cell $not $not$ls180.v:7544$2433 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7547$2435_Y + connect \Y $not$ls180.v:7544$2433_Y end - attribute \src "ls180.v:7548.8-7548.61" - cell $not $not$ls180.v:7548$2437 + attribute \src "ls180.v:7545.8-7545.61" + cell $not $not$ls180.v:7545$2435 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read - connect \Y $not$ls180.v:7548$2437_Y + connect \Y $not$ls180.v:7545$2435_Y end - attribute \src "ls180.v:7556.8-7556.56" - cell $not $not$ls180.v:7556$2440 + attribute \src "ls180.v:7553.8-7553.56" + cell $not $not$ls180.v:7553$2438 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_source_valid - connect \Y $not$ls180.v:7556$2440_Y + connect \Y $not$ls180.v:7553$2438_Y end - attribute \src "ls180.v:7571.8-7571.46" - cell $not $not$ls180.v:7571$2442 + attribute \src "ls180.v:7568.8-7568.46" + cell $not $not$ls180.v:7568$2440 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_twtpcon_ready - connect \Y $not$ls180.v:7571$2442_Y + connect \Y $not$ls180.v:7568$2440_Y end - attribute \src "ls180.v:7587.136-7587.189" - cell $not $not$ls180.v:7587$2446 + attribute \src "ls180.v:7584.136-7584.189" + cell $not $not$ls180.v:7584$2444 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7587$2446_Y + connect \Y $not$ls180.v:7584$2444_Y end - attribute \src "ls180.v:7593.136-7593.189" - cell $not $not$ls180.v:7593$2451 + attribute \src "ls180.v:7590.136-7590.189" + cell $not $not$ls180.v:7590$2449 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7593$2451_Y + connect \Y $not$ls180.v:7590$2449_Y end - attribute \src "ls180.v:7594.8-7594.61" - cell $not $not$ls180.v:7594$2453 + attribute \src "ls180.v:7591.8-7591.61" + cell $not $not$ls180.v:7591$2451 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read - connect \Y $not$ls180.v:7594$2453_Y + connect \Y $not$ls180.v:7591$2451_Y end - attribute \src "ls180.v:7602.8-7602.56" - cell $not $not$ls180.v:7602$2456 + attribute \src "ls180.v:7599.8-7599.56" + cell $not $not$ls180.v:7599$2454 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_source_valid - connect \Y $not$ls180.v:7602$2456_Y + connect \Y $not$ls180.v:7599$2454_Y end - attribute \src "ls180.v:7617.8-7617.46" - cell $not $not$ls180.v:7617$2458 + attribute \src "ls180.v:7614.8-7614.46" + cell $not $not$ls180.v:7614$2456 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_twtpcon_ready - connect \Y $not$ls180.v:7617$2458_Y + connect \Y $not$ls180.v:7614$2456_Y end - attribute \src "ls180.v:7633.136-7633.189" - cell $not $not$ls180.v:7633$2462 + attribute \src "ls180.v:7630.136-7630.189" + cell $not $not$ls180.v:7630$2460 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7633$2462_Y + connect \Y $not$ls180.v:7630$2460_Y end - attribute \src "ls180.v:7639.136-7639.189" - cell $not $not$ls180.v:7639$2467 + attribute \src "ls180.v:7636.136-7636.189" + cell $not $not$ls180.v:7636$2465 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7639$2467_Y + connect \Y $not$ls180.v:7636$2465_Y end - attribute \src "ls180.v:7640.8-7640.61" - cell $not $not$ls180.v:7640$2469 + attribute \src "ls180.v:7637.8-7637.61" + cell $not $not$ls180.v:7637$2467 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read - connect \Y $not$ls180.v:7640$2469_Y + connect \Y $not$ls180.v:7637$2467_Y end - attribute \src "ls180.v:7648.8-7648.56" - cell $not $not$ls180.v:7648$2472 + attribute \src "ls180.v:7645.8-7645.56" + cell $not $not$ls180.v:7645$2470 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_source_valid - connect \Y $not$ls180.v:7648$2472_Y + connect \Y $not$ls180.v:7645$2470_Y end - attribute \src "ls180.v:7663.8-7663.46" - cell $not $not$ls180.v:7663$2474 + attribute \src "ls180.v:7660.8-7660.46" + cell $not $not$ls180.v:7660$2472 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_twtpcon_ready - connect \Y $not$ls180.v:7663$2474_Y + connect \Y $not$ls180.v:7660$2472_Y end - attribute \src "ls180.v:7679.136-7679.189" - cell $not $not$ls180.v:7679$2478 + attribute \src "ls180.v:7676.136-7676.189" + cell $not $not$ls180.v:7676$2476 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7679$2478_Y + connect \Y $not$ls180.v:7676$2476_Y end - attribute \src "ls180.v:7685.136-7685.189" - cell $not $not$ls180.v:7685$2483 + attribute \src "ls180.v:7682.136-7682.189" + cell $not $not$ls180.v:7682$2481 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7685$2483_Y + connect \Y $not$ls180.v:7682$2481_Y end - attribute \src "ls180.v:7686.8-7686.61" - cell $not $not$ls180.v:7686$2485 + attribute \src "ls180.v:7683.8-7683.61" + cell $not $not$ls180.v:7683$2483 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read - connect \Y $not$ls180.v:7686$2485_Y + connect \Y $not$ls180.v:7683$2483_Y end - attribute \src "ls180.v:7694.8-7694.56" - cell $not $not$ls180.v:7694$2488 + attribute \src "ls180.v:7691.8-7691.56" + cell $not $not$ls180.v:7691$2486 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_source_valid - connect \Y $not$ls180.v:7694$2488_Y + connect \Y $not$ls180.v:7691$2486_Y end - attribute \src "ls180.v:7709.8-7709.46" - cell $not $not$ls180.v:7709$2490 + attribute \src "ls180.v:7706.8-7706.46" + cell $not $not$ls180.v:7706$2488 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_twtpcon_ready - connect \Y $not$ls180.v:7709$2490_Y + connect \Y $not$ls180.v:7706$2488_Y end - attribute \src "ls180.v:7717.7-7717.22" - cell $not $not$ls180.v:7717$2493 + attribute \src "ls180.v:7714.7-7714.22" + cell $not $not$ls180.v:7714$2491 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_en0 - connect \Y $not$ls180.v:7717$2493_Y + connect \Y $not$ls180.v:7714$2491_Y end - attribute \src "ls180.v:7720.8-7720.29" - cell $not $not$ls180.v:7720$2494 + attribute \src "ls180.v:7717.8-7717.29" + cell $not $not$ls180.v:7717$2492 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_max_time0 - connect \Y $not$ls180.v:7720$2494_Y + connect \Y $not$ls180.v:7717$2492_Y end - attribute \src "ls180.v:7724.7-7724.22" - cell $not $not$ls180.v:7724$2496 + attribute \src "ls180.v:7721.7-7721.22" + cell $not $not$ls180.v:7721$2494 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_en1 - connect \Y $not$ls180.v:7724$2496_Y + connect \Y $not$ls180.v:7721$2494_Y end - attribute \src "ls180.v:7727.8-7727.29" - cell $not $not$ls180.v:7727$2497 + attribute \src "ls180.v:7724.8-7724.29" + cell $not $not$ls180.v:7724$2495 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_max_time1 - connect \Y $not$ls180.v:7727$2497_Y + connect \Y $not$ls180.v:7724$2495_Y end - attribute \src "ls180.v:7846.30-7846.60" - cell $not $not$ls180.v:7846$2499 + attribute \src "ls180.v:7843.30-7843.60" + cell $not $not$ls180.v:7843$2497 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_sync_rhs_array_muxed2 - connect \Y $not$ls180.v:7846$2499_Y + connect \Y $not$ls180.v:7843$2497_Y end - attribute \src "ls180.v:7847.30-7847.60" - cell $not $not$ls180.v:7847$2500 + attribute \src "ls180.v:7844.30-7844.60" + cell $not $not$ls180.v:7844$2498 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_sync_rhs_array_muxed3 - connect \Y $not$ls180.v:7847$2500_Y + connect \Y $not$ls180.v:7844$2498_Y end - attribute \src "ls180.v:7848.29-7848.59" - cell $not $not$ls180.v:7848$2501 + attribute \src "ls180.v:7845.29-7845.59" + cell $not $not$ls180.v:7845$2499 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_sync_rhs_array_muxed4 - connect \Y $not$ls180.v:7848$2501_Y + connect \Y $not$ls180.v:7845$2499_Y end - attribute \src "ls180.v:7859.8-7859.33" - cell $not $not$ls180.v:7859$2502 + attribute \src "ls180.v:7856.8-7856.33" + cell $not $not$ls180.v:7856$2500 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_tccdcon_ready - connect \Y $not$ls180.v:7859$2502_Y + connect \Y $not$ls180.v:7856$2500_Y end - attribute \src "ls180.v:7874.8-7874.33" - cell $not $not$ls180.v:7874$2505 + attribute \src "ls180.v:7871.8-7871.33" + cell $not $not$ls180.v:7871$2503 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_twtrcon_ready - connect \Y $not$ls180.v:7874$2505_Y + connect \Y $not$ls180.v:7871$2503_Y end - attribute \src "ls180.v:7910.27-7910.40" - cell $not $not$ls180.v:7910$2535 + attribute \src "ls180.v:7907.27-7907.40" + cell $not $not$ls180.v:7907$2533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_tx_busy - connect \Y $not$ls180.v:7910$2535_Y + connect \Y $not$ls180.v:7907$2533_Y end - attribute \src "ls180.v:7910.46-7910.62" - cell $not $not$ls180.v:7910$2537 + attribute \src "ls180.v:7907.46-7907.62" + cell $not $not$ls180.v:7907$2535 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sink_ready - connect \Y $not$ls180.v:7910$2537_Y + connect \Y $not$ls180.v:7907$2535_Y end - attribute \src "ls180.v:7939.7-7939.20" - cell $not $not$ls180.v:7939$2544 + attribute \src "ls180.v:7936.7-7936.20" + cell $not $not$ls180.v:7936$2542 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_rx_busy - connect \Y $not$ls180.v:7939$2544_Y + connect \Y $not$ls180.v:7936$2542_Y end - attribute \src "ls180.v:7940.9-7940.17" - cell $not $not$ls180.v:7940$2545 + attribute \src "ls180.v:7937.9-7937.17" + cell $not $not$ls180.v:7937$2543 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_rx - connect \Y $not$ls180.v:7940$2545_Y + connect \Y $not$ls180.v:7937$2543_Y end - attribute \src "ls180.v:7973.8-7973.29" - cell $not $not$ls180.v:7973$2551 + attribute \src "ls180.v:7970.8-7970.29" + cell $not $not$ls180.v:7970$2549 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_trigger - connect \Y $not$ls180.v:7973$2551_Y + connect \Y $not$ls180.v:7970$2549_Y end - attribute \src "ls180.v:7980.8-7980.29" - cell $not $not$ls180.v:7980$2553 + attribute \src "ls180.v:7977.8-7977.29" + cell $not $not$ls180.v:7977$2551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_trigger - connect \Y $not$ls180.v:7980$2553_Y + connect \Y $not$ls180.v:7977$2551_Y end - attribute \src "ls180.v:7990.80-7990.106" - cell $not $not$ls180.v:7990$2556 + attribute \src "ls180.v:7987.80-7987.106" + cell $not $not$ls180.v:7987$2554 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_replace - connect \Y $not$ls180.v:7990$2556_Y + connect \Y $not$ls180.v:7987$2554_Y end - attribute \src "ls180.v:7996.80-7996.106" - cell $not $not$ls180.v:7996$2561 + attribute \src "ls180.v:7993.80-7993.106" + cell $not $not$ls180.v:7993$2559 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_replace - connect \Y $not$ls180.v:7996$2561_Y + connect \Y $not$ls180.v:7993$2559_Y end - attribute \src "ls180.v:7997.8-7997.34" - cell $not $not$ls180.v:7997$2563 + attribute \src "ls180.v:7994.8-7994.34" + cell $not $not$ls180.v:7994$2561 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_do_read - connect \Y $not$ls180.v:7997$2563_Y + connect \Y $not$ls180.v:7994$2561_Y end - attribute \src "ls180.v:8012.80-8012.106" - cell $not $not$ls180.v:8012$2567 + attribute \src "ls180.v:8009.80-8009.106" + cell $not $not$ls180.v:8009$2565 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_replace - connect \Y $not$ls180.v:8012$2567_Y + connect \Y $not$ls180.v:8009$2565_Y end - attribute \src "ls180.v:8018.80-8018.106" - cell $not $not$ls180.v:8018$2572 + attribute \src "ls180.v:8015.80-8015.106" + cell $not $not$ls180.v:8015$2570 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_replace - connect \Y $not$ls180.v:8018$2572_Y + connect \Y $not$ls180.v:8015$2570_Y end - attribute \src "ls180.v:8019.8-8019.34" - cell $not $not$ls180.v:8019$2574 + attribute \src "ls180.v:8016.8-8016.34" + cell $not $not$ls180.v:8016$2572 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_do_read - connect \Y $not$ls180.v:8019$2574_Y + connect \Y $not$ls180.v:8016$2572_Y end - attribute \src "ls180.v:8050.23-8050.42" - cell $not $not$ls180.v:8050$2578 + attribute \src "ls180.v:8047.23-8047.42" + cell $not $not$ls180.v:8047$2576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_spi_master_cs - connect \Y $not$ls180.v:8050$2578_Y + connect \Y $not$ls180.v:8047$2576_Y end - attribute \src "ls180.v:8050.47-8050.73" - cell $not $not$ls180.v:8050$2579 + attribute \src "ls180.v:8047.47-8047.73" + cell $not $not$ls180.v:8047$2577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_spi_master_cs_enable - connect \Y $not$ls180.v:8050$2579_Y + connect \Y $not$ls180.v:8047$2577_Y end - attribute \src "ls180.v:8104.7-8104.31" - cell $not $not$ls180.v:8104$2590 + attribute \src "ls180.v:8101.7-8101.31" + cell $not $not$ls180.v:8101$2588 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_clocker_stop - connect \Y $not$ls180.v:8104$2590_Y + connect \Y $not$ls180.v:8101$2588_Y end - attribute \src "ls180.v:8176.8-8176.46" - cell $not $not$ls180.v:8176$2602 + attribute \src "ls180.v:8173.8-8173.46" + cell $not $not$ls180.v:8173$2600 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_buf_source_valid - connect \Y $not$ls180.v:8176$2602_Y + connect \Y $not$ls180.v:8173$2600_Y end - attribute \src "ls180.v:8257.8-8257.47" - cell $not $not$ls180.v:8257$2614 + attribute \src "ls180.v:8254.8-8254.47" + cell $not $not$ls180.v:8254$2612 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_buf_source_valid - connect \Y $not$ls180.v:8257$2614_Y + connect \Y $not$ls180.v:8254$2612_Y end - attribute \src "ls180.v:8318.8-8318.48" - cell $not $not$ls180.v:8318$2626 + attribute \src "ls180.v:8315.8-8315.48" + cell $not $not$ls180.v:8315$2624 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_buf_source_valid - connect \Y $not$ls180.v:8318$2626_Y + connect \Y $not$ls180.v:8315$2624_Y end - attribute \src "ls180.v:8488.88-8488.118" - cell $not $not$ls180.v:8488$2640 + attribute \src "ls180.v:8485.88-8485.118" + cell $not $not$ls180.v:8485$2638 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_replace - connect \Y $not$ls180.v:8488$2640_Y + connect \Y $not$ls180.v:8485$2638_Y end - attribute \src "ls180.v:8494.88-8494.118" - cell $not $not$ls180.v:8494$2645 + attribute \src "ls180.v:8491.88-8491.118" + cell $not $not$ls180.v:8491$2643 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_replace - connect \Y $not$ls180.v:8494$2645_Y + connect \Y $not$ls180.v:8491$2643_Y end - attribute \src "ls180.v:8495.8-8495.38" - cell $not $not$ls180.v:8495$2647 + attribute \src "ls180.v:8492.8-8492.38" + cell $not $not$ls180.v:8492$2645 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_do_read - connect \Y $not$ls180.v:8495$2647_Y + connect \Y $not$ls180.v:8492$2645_Y end - attribute \src "ls180.v:8574.88-8574.118" - cell $not $not$ls180.v:8574$2662 + attribute \src "ls180.v:8571.88-8571.118" + cell $not $not$ls180.v:8571$2660 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_replace - connect \Y $not$ls180.v:8574$2662_Y + connect \Y $not$ls180.v:8571$2660_Y end - attribute \src "ls180.v:8580.88-8580.118" - cell $not $not$ls180.v:8580$2667 + attribute \src "ls180.v:8577.88-8577.118" + cell $not $not$ls180.v:8577$2665 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_replace - connect \Y $not$ls180.v:8580$2667_Y + connect \Y $not$ls180.v:8577$2665_Y end - attribute \src "ls180.v:8581.8-8581.38" - cell $not $not$ls180.v:8581$2669 + attribute \src "ls180.v:8578.8-8578.38" + cell $not $not$ls180.v:8578$2667 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_do_read - connect \Y $not$ls180.v:8581$2669_Y + connect \Y $not$ls180.v:8578$2667_Y end - attribute \src "ls180.v:8598.22-8598.37" - cell $not $not$ls180.v:8598$2673 + attribute \src "ls180.v:8595.22-8595.37" + cell $not $not$ls180.v:8595$2671 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_cs - connect \Y $not$ls180.v:8598$2673_Y + connect \Y $not$ls180.v:8595$2671_Y end - attribute \src "ls180.v:8598.42-8598.64" - cell $not $not$ls180.v:8598$2674 + attribute \src "ls180.v:8595.42-8595.64" + cell $not $not$ls180.v:8595$2672 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_cs_enable - connect \Y $not$ls180.v:8598$2674_Y + connect \Y $not$ls180.v:8595$2672_Y end - attribute \src "ls180.v:8636.9-8636.28" - cell $not $not$ls180.v:8636$2677 + attribute \src "ls180.v:8633.9-8633.28" + cell $not $not$ls180.v:8633$2675 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_request [0] - connect \Y $not$ls180.v:8636$2677_Y + connect \Y $not$ls180.v:8633$2675_Y end - attribute \src "ls180.v:8655.9-8655.28" - cell $not $not$ls180.v:8655$2678 + attribute \src "ls180.v:8652.9-8652.28" + cell $not $not$ls180.v:8652$2676 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_request [1] - connect \Y $not$ls180.v:8655$2678_Y + connect \Y $not$ls180.v:8652$2676_Y end - attribute \src "ls180.v:8674.9-8674.28" - cell $not $not$ls180.v:8674$2679 + attribute \src "ls180.v:8671.9-8671.28" + cell $not $not$ls180.v:8671$2677 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_request [2] - connect \Y $not$ls180.v:8674$2679_Y + connect \Y $not$ls180.v:8671$2677_Y end - attribute \src "ls180.v:8693.9-8693.28" - cell $not $not$ls180.v:8693$2680 + attribute \src "ls180.v:8690.9-8690.28" + cell $not $not$ls180.v:8690$2678 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_request [3] - connect \Y $not$ls180.v:8693$2680_Y + connect \Y $not$ls180.v:8690$2678_Y end - attribute \src "ls180.v:8712.9-8712.28" - cell $not $not$ls180.v:8712$2681 + attribute \src "ls180.v:8709.9-8709.28" + cell $not $not$ls180.v:8709$2679 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_request [4] - connect \Y $not$ls180.v:8712$2681_Y + connect \Y $not$ls180.v:8709$2679_Y end - attribute \src "ls180.v:8733.8-8733.21" - cell $not $not$ls180.v:8733$2682 + attribute \src "ls180.v:8730.8-8730.21" + cell $not $not$ls180.v:8730$2680 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_done - connect \Y $not$ls180.v:8733$2682_Y + connect \Y $not$ls180.v:8730$2680_Y end - attribute \src "ls180.v:10199.8-10199.51" - cell $or $or$ls180.v:10199$2754 + attribute \src "ls180.v:10195.8-10195.51" + cell $or $or$ls180.v:10195$2752 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -104520,10 +104516,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sys_rst_1 connect \B \main_libresocsim_libresoc_reset - connect \Y $or$ls180.v:10199$2754_Y + connect \Y $or$ls180.v:10195$2752_Y end - attribute \src "ls180.v:2766.10-2766.96" - cell $or $or$ls180.v:2766$21 + attribute \src "ls180.v:2767.10-2767.96" + cell $or $or$ls180.v:2767$21 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -104531,10 +104527,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_interface0_converted_interface_ack connect \B \main_libresocsim_converter0_skip - connect \Y $or$ls180.v:2766$21_Y + connect \Y $or$ls180.v:2767$21_Y end - attribute \src "ls180.v:2826.10-2826.96" - cell $or $or$ls180.v:2826$32 + attribute \src "ls180.v:2827.10-2827.96" + cell $or $or$ls180.v:2827$32 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -104542,10 +104538,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_interface1_converted_interface_ack connect \B \main_libresocsim_converter1_skip - connect \Y $or$ls180.v:2826$32_Y + connect \Y $or$ls180.v:2827$32_Y end - attribute \src "ls180.v:2886.10-2886.96" - cell $or $or$ls180.v:2886$43 + attribute \src "ls180.v:2887.10-2887.96" + cell $or $or$ls180.v:2887$43 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -104553,21 +104549,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_interface2_converted_interface_ack connect \B \main_libresocsim_converter2_skip - connect \Y $or$ls180.v:2886$43_Y + connect \Y $or$ls180.v:2887$43_Y end - attribute \src "ls180.v:3083.39-3083.105" - cell $or $or$ls180.v:3083$76 + attribute \src "ls180.v:3079.39-3079.105" + cell $or $or$ls180.v:3079$75 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_start0 - connect \B $ne$ls180.v:3083$75_Y - connect \Y $or$ls180.v:3083$76_Y + connect \B $ne$ls180.v:3079$74_Y + connect \Y $or$ls180.v:3079$75_Y end - attribute \src "ls180.v:3126.59-3126.140" - cell $or $or$ls180.v:3126$80 + attribute \src "ls180.v:3122.59-3122.140" + cell $or $or$ls180.v:3122$79 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -104575,10 +104571,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_req_wdata_ready connect \B \main_sdram_bankmachine0_req_rdata_valid - connect \Y $or$ls180.v:3126$80_Y + connect \Y $or$ls180.v:3122$79_Y end - attribute \src "ls180.v:3127.44-3127.151" - cell $or $or$ls180.v:3127$81 + attribute \src "ls180.v:3123.44-3123.151" + cell $or $or$ls180.v:3123$80 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -104586,21 +104582,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid connect \B \main_sdram_bankmachine0_cmd_buffer_source_valid - connect \Y $or$ls180.v:3127$81_Y + connect \Y $or$ls180.v:3123$80_Y end - attribute \src "ls180.v:3135.45-3135.170" - cell $or $or$ls180.v:3135$85 + attribute \src "ls180.v:3131.45-3131.170" + cell $or $or$ls180.v:3131$84 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 parameter \B_WIDTH 13 parameter \Y_WIDTH 13 - connect \A $sshl$ls180.v:3135$84_Y + connect \A $sshl$ls180.v:3131$83_Y connect \B { 4'0000 \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [8:0] } - connect \Y $or$ls180.v:3135$85_Y + connect \Y $or$ls180.v:3131$84_Y end - attribute \src "ls180.v:3172.127-3172.245" - cell $or $or$ls180.v:3172$98 + attribute \src "ls180.v:3168.127-3168.245" + cell $or $or$ls180.v:3168$97 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -104608,21 +104604,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - connect \Y $or$ls180.v:3172$98_Y + connect \Y $or$ls180.v:3168$97_Y end - attribute \src "ls180.v:3178.57-3178.157" - cell $or $or$ls180.v:3178$104 + attribute \src "ls180.v:3174.57-3174.157" + cell $or $or$ls180.v:3174$103 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3178$103_Y + connect \A $not$ls180.v:3174$102_Y connect \B \main_sdram_bankmachine0_cmd_buffer_source_ready - connect \Y $or$ls180.v:3178$104_Y + connect \Y $or$ls180.v:3174$103_Y end - attribute \src "ls180.v:3283.59-3283.140" - cell $or $or$ls180.v:3283$110 + attribute \src "ls180.v:3279.59-3279.140" + cell $or $or$ls180.v:3279$109 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -104630,10 +104626,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_req_wdata_ready connect \B \main_sdram_bankmachine1_req_rdata_valid - connect \Y $or$ls180.v:3283$110_Y + connect \Y $or$ls180.v:3279$109_Y end - attribute \src "ls180.v:3284.44-3284.151" - cell $or $or$ls180.v:3284$111 + attribute \src "ls180.v:3280.44-3280.151" + cell $or $or$ls180.v:3280$110 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -104641,21 +104637,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid connect \B \main_sdram_bankmachine1_cmd_buffer_source_valid - connect \Y $or$ls180.v:3284$111_Y + connect \Y $or$ls180.v:3280$110_Y end - attribute \src "ls180.v:3292.45-3292.170" - cell $or $or$ls180.v:3292$115 + attribute \src "ls180.v:3288.45-3288.170" + cell $or $or$ls180.v:3288$114 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 parameter \B_WIDTH 13 parameter \Y_WIDTH 13 - connect \A $sshl$ls180.v:3292$114_Y + connect \A $sshl$ls180.v:3288$113_Y connect \B { 4'0000 \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [8:0] } - connect \Y $or$ls180.v:3292$115_Y + connect \Y $or$ls180.v:3288$114_Y end - attribute \src "ls180.v:3329.127-3329.245" - cell $or $or$ls180.v:3329$128 + attribute \src "ls180.v:3325.127-3325.245" + cell $or $or$ls180.v:3325$127 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -104663,21 +104659,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - connect \Y $or$ls180.v:3329$128_Y + connect \Y $or$ls180.v:3325$127_Y end - attribute \src "ls180.v:3335.57-3335.157" - cell $or $or$ls180.v:3335$134 + attribute \src "ls180.v:3331.57-3331.157" + cell $or $or$ls180.v:3331$133 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3335$133_Y + connect \A $not$ls180.v:3331$132_Y connect \B \main_sdram_bankmachine1_cmd_buffer_source_ready - connect \Y $or$ls180.v:3335$134_Y + connect \Y $or$ls180.v:3331$133_Y end - attribute \src "ls180.v:3440.59-3440.140" - cell $or $or$ls180.v:3440$140 + attribute \src "ls180.v:3436.59-3436.140" + cell $or $or$ls180.v:3436$139 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -104685,10 +104681,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_req_wdata_ready connect \B \main_sdram_bankmachine2_req_rdata_valid - connect \Y $or$ls180.v:3440$140_Y + connect \Y $or$ls180.v:3436$139_Y end - attribute \src "ls180.v:3441.44-3441.151" - cell $or $or$ls180.v:3441$141 + attribute \src "ls180.v:3437.44-3437.151" + cell $or $or$ls180.v:3437$140 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -104696,21 +104692,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid connect \B \main_sdram_bankmachine2_cmd_buffer_source_valid - connect \Y $or$ls180.v:3441$141_Y + connect \Y $or$ls180.v:3437$140_Y end - attribute \src "ls180.v:3449.45-3449.170" - cell $or $or$ls180.v:3449$145 + attribute \src "ls180.v:3445.45-3445.170" + cell $or $or$ls180.v:3445$144 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 parameter \B_WIDTH 13 parameter \Y_WIDTH 13 - connect \A $sshl$ls180.v:3449$144_Y + connect \A $sshl$ls180.v:3445$143_Y connect \B { 4'0000 \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [8:0] } - connect \Y $or$ls180.v:3449$145_Y + connect \Y $or$ls180.v:3445$144_Y end - attribute \src "ls180.v:3486.127-3486.245" - cell $or $or$ls180.v:3486$158 + attribute \src "ls180.v:3482.127-3482.245" + cell $or $or$ls180.v:3482$157 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -104718,21 +104714,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - connect \Y $or$ls180.v:3486$158_Y + connect \Y $or$ls180.v:3482$157_Y end - attribute \src "ls180.v:3492.57-3492.157" - cell $or $or$ls180.v:3492$164 + attribute \src "ls180.v:3488.57-3488.157" + cell $or $or$ls180.v:3488$163 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3492$163_Y + connect \A $not$ls180.v:3488$162_Y connect \B \main_sdram_bankmachine2_cmd_buffer_source_ready - connect \Y $or$ls180.v:3492$164_Y + connect \Y $or$ls180.v:3488$163_Y end - attribute \src "ls180.v:3597.59-3597.140" - cell $or $or$ls180.v:3597$170 + attribute \src "ls180.v:3593.59-3593.140" + cell $or $or$ls180.v:3593$169 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -104740,10 +104736,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_req_wdata_ready connect \B \main_sdram_bankmachine3_req_rdata_valid - connect \Y $or$ls180.v:3597$170_Y + connect \Y $or$ls180.v:3593$169_Y end - attribute \src "ls180.v:3598.44-3598.151" - cell $or $or$ls180.v:3598$171 + attribute \src "ls180.v:3594.44-3594.151" + cell $or $or$ls180.v:3594$170 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -104751,21 +104747,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid connect \B \main_sdram_bankmachine3_cmd_buffer_source_valid - connect \Y $or$ls180.v:3598$171_Y + connect \Y $or$ls180.v:3594$170_Y end - attribute \src "ls180.v:3606.45-3606.170" - cell $or $or$ls180.v:3606$175 + attribute \src "ls180.v:3602.45-3602.170" + cell $or $or$ls180.v:3602$174 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 parameter \B_WIDTH 13 parameter \Y_WIDTH 13 - connect \A $sshl$ls180.v:3606$174_Y + connect \A $sshl$ls180.v:3602$173_Y connect \B { 4'0000 \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [8:0] } - connect \Y $or$ls180.v:3606$175_Y + connect \Y $or$ls180.v:3602$174_Y end - attribute \src "ls180.v:3643.127-3643.245" - cell $or $or$ls180.v:3643$188 + attribute \src "ls180.v:3639.127-3639.245" + cell $or $or$ls180.v:3639$187 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -104773,21 +104769,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - connect \Y $or$ls180.v:3643$188_Y + connect \Y $or$ls180.v:3639$187_Y end - attribute \src "ls180.v:3649.57-3649.157" - cell $or $or$ls180.v:3649$194 + attribute \src "ls180.v:3645.57-3645.157" + cell $or $or$ls180.v:3645$193 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3649$193_Y + connect \A $not$ls180.v:3645$192_Y connect \B \main_sdram_bankmachine3_cmd_buffer_source_ready - connect \Y $or$ls180.v:3649$194_Y + connect \Y $or$ls180.v:3645$193_Y end - attribute \src "ls180.v:3748.107-3748.193" - cell $or $or$ls180.v:3748$214 + attribute \src "ls180.v:3744.107-3744.193" + cell $or $or$ls180.v:3744$213 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -104795,626 +104791,626 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_is_write connect \B \main_sdram_choose_req_cmd_payload_is_read - connect \Y $or$ls180.v:3748$214_Y + connect \Y $or$ls180.v:3744$213_Y end - attribute \src "ls180.v:3751.39-3751.204" - cell $or $or$ls180.v:3751$220 + attribute \src "ls180.v:3747.39-3747.204" + cell $or $or$ls180.v:3747$219 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3751$218_Y - connect \B $and$ls180.v:3751$219_Y - connect \Y $or$ls180.v:3751$220_Y + connect \A $and$ls180.v:3747$217_Y + connect \B $and$ls180.v:3747$218_Y + connect \Y $or$ls180.v:3747$219_Y end - attribute \src "ls180.v:3751.38-3751.289" - cell $or $or$ls180.v:3751$222 + attribute \src "ls180.v:3747.38-3747.289" + cell $or $or$ls180.v:3747$221 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3751$220_Y - connect \B $and$ls180.v:3751$221_Y - connect \Y $or$ls180.v:3751$222_Y + connect \A $or$ls180.v:3747$219_Y + connect \B $and$ls180.v:3747$220_Y + connect \Y $or$ls180.v:3747$221_Y end - attribute \src "ls180.v:3751.37-3751.374" - cell $or $or$ls180.v:3751$224 + attribute \src "ls180.v:3747.37-3747.374" + cell $or $or$ls180.v:3747$223 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3751$222_Y - connect \B $and$ls180.v:3751$223_Y - connect \Y $or$ls180.v:3751$224_Y + connect \A $or$ls180.v:3747$221_Y + connect \B $and$ls180.v:3747$222_Y + connect \Y $or$ls180.v:3747$223_Y end - attribute \src "ls180.v:3752.40-3752.207" - cell $or $or$ls180.v:3752$227 + attribute \src "ls180.v:3748.40-3748.207" + cell $or $or$ls180.v:3748$226 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3752$225_Y - connect \B $and$ls180.v:3752$226_Y - connect \Y $or$ls180.v:3752$227_Y + connect \A $and$ls180.v:3748$224_Y + connect \B $and$ls180.v:3748$225_Y + connect \Y $or$ls180.v:3748$226_Y end - attribute \src "ls180.v:3752.39-3752.293" - cell $or $or$ls180.v:3752$229 + attribute \src "ls180.v:3748.39-3748.293" + cell $or $or$ls180.v:3748$228 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3752$227_Y - connect \B $and$ls180.v:3752$228_Y - connect \Y $or$ls180.v:3752$229_Y + connect \A $or$ls180.v:3748$226_Y + connect \B $and$ls180.v:3748$227_Y + connect \Y $or$ls180.v:3748$228_Y end - attribute \src "ls180.v:3752.38-3752.379" - cell $or $or$ls180.v:3752$231 + attribute \src "ls180.v:3748.38-3748.379" + cell $or $or$ls180.v:3748$230 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3752$229_Y - connect \B $and$ls180.v:3752$230_Y - connect \Y $or$ls180.v:3752$231_Y + connect \A $or$ls180.v:3748$228_Y + connect \B $and$ls180.v:3748$229_Y + connect \Y $or$ls180.v:3748$230_Y end - attribute \src "ls180.v:3765.158-3765.332" - cell $or $or$ls180.v:3765$245 + attribute \src "ls180.v:3761.158-3761.332" + cell $or $or$ls180.v:3761$244 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3765$244_Y + connect \A $not$ls180.v:3761$243_Y connect \B \main_sdram_choose_cmd_want_activates - connect \Y $or$ls180.v:3765$245_Y + connect \Y $or$ls180.v:3761$244_Y end - attribute \src "ls180.v:3765.75-3765.506" - cell $or $or$ls180.v:3765$250 + attribute \src "ls180.v:3761.75-3761.506" + cell $or $or$ls180.v:3761$249 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3765$246_Y - connect \B $and$ls180.v:3765$249_Y - connect \Y $or$ls180.v:3765$250_Y + connect \A $and$ls180.v:3761$245_Y + connect \B $and$ls180.v:3761$248_Y + connect \Y $or$ls180.v:3761$249_Y end - attribute \src "ls180.v:3766.158-3766.332" - cell $or $or$ls180.v:3766$258 + attribute \src "ls180.v:3762.158-3762.332" + cell $or $or$ls180.v:3762$257 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3766$257_Y + connect \A $not$ls180.v:3762$256_Y connect \B \main_sdram_choose_cmd_want_activates - connect \Y $or$ls180.v:3766$258_Y + connect \Y $or$ls180.v:3762$257_Y end - attribute \src "ls180.v:3766.75-3766.506" - cell $or $or$ls180.v:3766$263 + attribute \src "ls180.v:3762.75-3762.506" + cell $or $or$ls180.v:3762$262 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3766$259_Y - connect \B $and$ls180.v:3766$262_Y - connect \Y $or$ls180.v:3766$263_Y + connect \A $and$ls180.v:3762$258_Y + connect \B $and$ls180.v:3762$261_Y + connect \Y $or$ls180.v:3762$262_Y end - attribute \src "ls180.v:3767.158-3767.332" - cell $or $or$ls180.v:3767$271 + attribute \src "ls180.v:3763.158-3763.332" + cell $or $or$ls180.v:3763$270 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3767$270_Y + connect \A $not$ls180.v:3763$269_Y connect \B \main_sdram_choose_cmd_want_activates - connect \Y $or$ls180.v:3767$271_Y + connect \Y $or$ls180.v:3763$270_Y end - attribute \src "ls180.v:3767.75-3767.506" - cell $or $or$ls180.v:3767$276 + attribute \src "ls180.v:3763.75-3763.506" + cell $or $or$ls180.v:3763$275 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3767$272_Y - connect \B $and$ls180.v:3767$275_Y - connect \Y $or$ls180.v:3767$276_Y + connect \A $and$ls180.v:3763$271_Y + connect \B $and$ls180.v:3763$274_Y + connect \Y $or$ls180.v:3763$275_Y end - attribute \src "ls180.v:3768.158-3768.332" - cell $or $or$ls180.v:3768$284 + attribute \src "ls180.v:3764.158-3764.332" + cell $or $or$ls180.v:3764$283 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3768$283_Y + connect \A $not$ls180.v:3764$282_Y connect \B \main_sdram_choose_cmd_want_activates - connect \Y $or$ls180.v:3768$284_Y + connect \Y $or$ls180.v:3764$283_Y end - attribute \src "ls180.v:3768.75-3768.506" - cell $or $or$ls180.v:3768$289 + attribute \src "ls180.v:3764.75-3764.506" + cell $or $or$ls180.v:3764$288 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3768$285_Y - connect \B $and$ls180.v:3768$288_Y - connect \Y $or$ls180.v:3768$289_Y + connect \A $and$ls180.v:3764$284_Y + connect \B $and$ls180.v:3764$287_Y + connect \Y $or$ls180.v:3764$288_Y end - attribute \src "ls180.v:3795.36-3795.104" - cell $or $or$ls180.v:3795$295 + attribute \src "ls180.v:3791.36-3791.104" + cell $or $or$ls180.v:3791$294 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_cmd_ready - connect \B $not$ls180.v:3795$294_Y - connect \Y $or$ls180.v:3795$295_Y + connect \B $not$ls180.v:3791$293_Y + connect \Y $or$ls180.v:3791$294_Y end - attribute \src "ls180.v:3798.158-3798.332" - cell $or $or$ls180.v:3798$303 + attribute \src "ls180.v:3794.158-3794.332" + cell $or $or$ls180.v:3794$302 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3798$302_Y + connect \A $not$ls180.v:3794$301_Y connect \B \main_sdram_choose_req_want_activates - connect \Y $or$ls180.v:3798$303_Y + connect \Y $or$ls180.v:3794$302_Y end - attribute \src "ls180.v:3798.75-3798.506" - cell $or $or$ls180.v:3798$308 + attribute \src "ls180.v:3794.75-3794.506" + cell $or $or$ls180.v:3794$307 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3798$304_Y - connect \B $and$ls180.v:3798$307_Y - connect \Y $or$ls180.v:3798$308_Y + connect \A $and$ls180.v:3794$303_Y + connect \B $and$ls180.v:3794$306_Y + connect \Y $or$ls180.v:3794$307_Y end - attribute \src "ls180.v:3799.158-3799.332" - cell $or $or$ls180.v:3799$316 + attribute \src "ls180.v:3795.158-3795.332" + cell $or $or$ls180.v:3795$315 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3799$315_Y + connect \A $not$ls180.v:3795$314_Y connect \B \main_sdram_choose_req_want_activates - connect \Y $or$ls180.v:3799$316_Y + connect \Y $or$ls180.v:3795$315_Y end - attribute \src "ls180.v:3799.75-3799.506" - cell $or $or$ls180.v:3799$321 + attribute \src "ls180.v:3795.75-3795.506" + cell $or $or$ls180.v:3795$320 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3799$317_Y - connect \B $and$ls180.v:3799$320_Y - connect \Y $or$ls180.v:3799$321_Y + connect \A $and$ls180.v:3795$316_Y + connect \B $and$ls180.v:3795$319_Y + connect \Y $or$ls180.v:3795$320_Y end - attribute \src "ls180.v:3800.158-3800.332" - cell $or $or$ls180.v:3800$329 + attribute \src "ls180.v:3796.158-3796.332" + cell $or $or$ls180.v:3796$328 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3800$328_Y + connect \A $not$ls180.v:3796$327_Y connect \B \main_sdram_choose_req_want_activates - connect \Y $or$ls180.v:3800$329_Y + connect \Y $or$ls180.v:3796$328_Y end - attribute \src "ls180.v:3800.75-3800.506" - cell $or $or$ls180.v:3800$334 + attribute \src "ls180.v:3796.75-3796.506" + cell $or $or$ls180.v:3796$333 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3800$330_Y - connect \B $and$ls180.v:3800$333_Y - connect \Y $or$ls180.v:3800$334_Y + connect \A $and$ls180.v:3796$329_Y + connect \B $and$ls180.v:3796$332_Y + connect \Y $or$ls180.v:3796$333_Y end - attribute \src "ls180.v:3801.158-3801.332" - cell $or $or$ls180.v:3801$342 + attribute \src "ls180.v:3797.158-3797.332" + cell $or $or$ls180.v:3797$341 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3801$341_Y + connect \A $not$ls180.v:3797$340_Y connect \B \main_sdram_choose_req_want_activates - connect \Y $or$ls180.v:3801$342_Y + connect \Y $or$ls180.v:3797$341_Y end - attribute \src "ls180.v:3801.75-3801.506" - cell $or $or$ls180.v:3801$347 + attribute \src "ls180.v:3797.75-3797.506" + cell $or $or$ls180.v:3797$346 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3801$343_Y - connect \B $and$ls180.v:3801$346_Y - connect \Y $or$ls180.v:3801$347_Y + connect \A $and$ls180.v:3797$342_Y + connect \B $and$ls180.v:3797$345_Y + connect \Y $or$ls180.v:3797$346_Y end - attribute \src "ls180.v:3864.36-3864.104" - cell $or $or$ls180.v:3864$381 + attribute \src "ls180.v:3860.36-3860.104" + cell $or $or$ls180.v:3860$380 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_ready - connect \B $not$ls180.v:3864$380_Y - connect \Y $or$ls180.v:3864$381_Y + connect \B $not$ls180.v:3860$379_Y + connect \Y $or$ls180.v:3860$380_Y end - attribute \src "ls180.v:3885.67-3885.221" - cell $or $or$ls180.v:3885$388 + attribute \src "ls180.v:3881.67-3881.221" + cell $or $or$ls180.v:3881$387 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3885$387_Y + connect \A $not$ls180.v:3881$386_Y connect \B \main_sdram_ras_allowed - connect \Y $or$ls180.v:3885$388_Y + connect \Y $or$ls180.v:3881$387_Y end - attribute \src "ls180.v:3893.10-3893.62" - cell $or $or$ls180.v:3893$391 + attribute \src "ls180.v:3889.10-3889.62" + cell $or $or$ls180.v:3889$390 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3893$390_Y + connect \A $not$ls180.v:3889$389_Y connect \B \main_sdram_max_time1 - connect \Y $or$ls180.v:3893$391_Y + connect \Y $or$ls180.v:3889$390_Y end - attribute \src "ls180.v:3923.67-3923.221" - cell $or $or$ls180.v:3923$397 + attribute \src "ls180.v:3919.67-3919.221" + cell $or $or$ls180.v:3919$396 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3923$396_Y + connect \A $not$ls180.v:3919$395_Y connect \B \main_sdram_ras_allowed - connect \Y $or$ls180.v:3923$397_Y + connect \Y $or$ls180.v:3919$396_Y end - attribute \src "ls180.v:3931.10-3931.61" - cell $or $or$ls180.v:3931$400 + attribute \src "ls180.v:3927.10-3927.61" + cell $or $or$ls180.v:3927$399 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3931$399_Y + connect \A $not$ls180.v:3927$398_Y connect \B \main_sdram_max_time0 - connect \Y $or$ls180.v:3931$400_Y + connect \Y $or$ls180.v:3927$399_Y end - attribute \src "ls180.v:3941.91-3941.180" - cell $or $or$ls180.v:3941$404 + attribute \src "ls180.v:3937.91-3937.180" + cell $or $or$ls180.v:3937$403 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked0 - connect \B $and$ls180.v:3941$403_Y - connect \Y $or$ls180.v:3941$404_Y + connect \B $and$ls180.v:3937$402_Y + connect \Y $or$ls180.v:3937$403_Y end - attribute \src "ls180.v:3941.90-3941.255" - cell $or $or$ls180.v:3941$407 + attribute \src "ls180.v:3937.90-3937.255" + cell $or $or$ls180.v:3937$406 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3941$404_Y - connect \B $and$ls180.v:3941$406_Y - connect \Y $or$ls180.v:3941$407_Y + connect \A $or$ls180.v:3937$403_Y + connect \B $and$ls180.v:3937$405_Y + connect \Y $or$ls180.v:3937$406_Y end - attribute \src "ls180.v:3941.89-3941.330" - cell $or $or$ls180.v:3941$410 + attribute \src "ls180.v:3937.89-3937.330" + cell $or $or$ls180.v:3937$409 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3941$407_Y - connect \B $and$ls180.v:3941$409_Y - connect \Y $or$ls180.v:3941$410_Y + connect \A $or$ls180.v:3937$406_Y + connect \B $and$ls180.v:3937$408_Y + connect \Y $or$ls180.v:3937$409_Y end - attribute \src "ls180.v:3946.91-3946.180" - cell $or $or$ls180.v:3946$420 + attribute \src "ls180.v:3942.91-3942.180" + cell $or $or$ls180.v:3942$419 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked1 - connect \B $and$ls180.v:3946$419_Y - connect \Y $or$ls180.v:3946$420_Y + connect \B $and$ls180.v:3942$418_Y + connect \Y $or$ls180.v:3942$419_Y end - attribute \src "ls180.v:3946.90-3946.255" - cell $or $or$ls180.v:3946$423 + attribute \src "ls180.v:3942.90-3942.255" + cell $or $or$ls180.v:3942$422 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3946$420_Y - connect \B $and$ls180.v:3946$422_Y - connect \Y $or$ls180.v:3946$423_Y + connect \A $or$ls180.v:3942$419_Y + connect \B $and$ls180.v:3942$421_Y + connect \Y $or$ls180.v:3942$422_Y end - attribute \src "ls180.v:3946.89-3946.330" - cell $or $or$ls180.v:3946$426 + attribute \src "ls180.v:3942.89-3942.330" + cell $or $or$ls180.v:3942$425 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3946$423_Y - connect \B $and$ls180.v:3946$425_Y - connect \Y $or$ls180.v:3946$426_Y + connect \A $or$ls180.v:3942$422_Y + connect \B $and$ls180.v:3942$424_Y + connect \Y $or$ls180.v:3942$425_Y end - attribute \src "ls180.v:3951.91-3951.180" - cell $or $or$ls180.v:3951$436 + attribute \src "ls180.v:3947.91-3947.180" + cell $or $or$ls180.v:3947$435 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked2 - connect \B $and$ls180.v:3951$435_Y - connect \Y $or$ls180.v:3951$436_Y + connect \B $and$ls180.v:3947$434_Y + connect \Y $or$ls180.v:3947$435_Y end - attribute \src "ls180.v:3951.90-3951.255" - cell $or $or$ls180.v:3951$439 + attribute \src "ls180.v:3947.90-3947.255" + cell $or $or$ls180.v:3947$438 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3951$436_Y - connect \B $and$ls180.v:3951$438_Y - connect \Y $or$ls180.v:3951$439_Y + connect \A $or$ls180.v:3947$435_Y + connect \B $and$ls180.v:3947$437_Y + connect \Y $or$ls180.v:3947$438_Y end - attribute \src "ls180.v:3951.89-3951.330" - cell $or $or$ls180.v:3951$442 + attribute \src "ls180.v:3947.89-3947.330" + cell $or $or$ls180.v:3947$441 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3951$439_Y - connect \B $and$ls180.v:3951$441_Y - connect \Y $or$ls180.v:3951$442_Y + connect \A $or$ls180.v:3947$438_Y + connect \B $and$ls180.v:3947$440_Y + connect \Y $or$ls180.v:3947$441_Y end - attribute \src "ls180.v:3956.91-3956.180" - cell $or $or$ls180.v:3956$452 + attribute \src "ls180.v:3952.91-3952.180" + cell $or $or$ls180.v:3952$451 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked3 - connect \B $and$ls180.v:3956$451_Y - connect \Y $or$ls180.v:3956$452_Y + connect \B $and$ls180.v:3952$450_Y + connect \Y $or$ls180.v:3952$451_Y end - attribute \src "ls180.v:3956.90-3956.255" - cell $or $or$ls180.v:3956$455 + attribute \src "ls180.v:3952.90-3952.255" + cell $or $or$ls180.v:3952$454 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3956$452_Y - connect \B $and$ls180.v:3956$454_Y - connect \Y $or$ls180.v:3956$455_Y + connect \A $or$ls180.v:3952$451_Y + connect \B $and$ls180.v:3952$453_Y + connect \Y $or$ls180.v:3952$454_Y end - attribute \src "ls180.v:3956.89-3956.330" - cell $or $or$ls180.v:3956$458 + attribute \src "ls180.v:3952.89-3952.330" + cell $or $or$ls180.v:3952$457 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3956$455_Y - connect \B $and$ls180.v:3956$457_Y - connect \Y $or$ls180.v:3956$458_Y + connect \A $or$ls180.v:3952$454_Y + connect \B $and$ls180.v:3952$456_Y + connect \Y $or$ls180.v:3952$457_Y end - attribute \src "ls180.v:3961.132-3961.221" - cell $or $or$ls180.v:3961$469 + attribute \src "ls180.v:3957.132-3957.221" + cell $or $or$ls180.v:3957$468 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked0 - connect \B $and$ls180.v:3961$468_Y - connect \Y $or$ls180.v:3961$469_Y + connect \B $and$ls180.v:3957$467_Y + connect \Y $or$ls180.v:3957$468_Y end - attribute \src "ls180.v:3961.131-3961.296" - cell $or $or$ls180.v:3961$472 + attribute \src "ls180.v:3957.131-3957.296" + cell $or $or$ls180.v:3957$471 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3961$469_Y - connect \B $and$ls180.v:3961$471_Y - connect \Y $or$ls180.v:3961$472_Y + connect \A $or$ls180.v:3957$468_Y + connect \B $and$ls180.v:3957$470_Y + connect \Y $or$ls180.v:3957$471_Y end - attribute \src "ls180.v:3961.130-3961.371" - cell $or $or$ls180.v:3961$475 + attribute \src "ls180.v:3957.130-3957.371" + cell $or $or$ls180.v:3957$474 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3961$472_Y - connect \B $and$ls180.v:3961$474_Y - connect \Y $or$ls180.v:3961$475_Y + connect \A $or$ls180.v:3957$471_Y + connect \B $and$ls180.v:3957$473_Y + connect \Y $or$ls180.v:3957$474_Y end - attribute \src "ls180.v:3961.34-3961.411" - cell $or $or$ls180.v:3961$480 + attribute \src "ls180.v:3957.34-3957.411" + cell $or $or$ls180.v:3957$479 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A 1'0 - connect \B $and$ls180.v:3961$479_Y - connect \Y $or$ls180.v:3961$480_Y + connect \B $and$ls180.v:3957$478_Y + connect \Y $or$ls180.v:3957$479_Y end - attribute \src "ls180.v:3961.506-3961.595" - cell $or $or$ls180.v:3961$485 + attribute \src "ls180.v:3957.506-3957.595" + cell $or $or$ls180.v:3957$484 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked1 - connect \B $and$ls180.v:3961$484_Y - connect \Y $or$ls180.v:3961$485_Y + connect \B $and$ls180.v:3957$483_Y + connect \Y $or$ls180.v:3957$484_Y end - attribute \src "ls180.v:3961.505-3961.670" - cell $or $or$ls180.v:3961$488 + attribute \src "ls180.v:3957.505-3957.670" + cell $or $or$ls180.v:3957$487 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3961$485_Y - connect \B $and$ls180.v:3961$487_Y - connect \Y $or$ls180.v:3961$488_Y + connect \A $or$ls180.v:3957$484_Y + connect \B $and$ls180.v:3957$486_Y + connect \Y $or$ls180.v:3957$487_Y end - attribute \src "ls180.v:3961.504-3961.745" - cell $or $or$ls180.v:3961$491 + attribute \src "ls180.v:3957.504-3957.745" + cell $or $or$ls180.v:3957$490 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3961$488_Y - connect \B $and$ls180.v:3961$490_Y - connect \Y $or$ls180.v:3961$491_Y + connect \A $or$ls180.v:3957$487_Y + connect \B $and$ls180.v:3957$489_Y + connect \Y $or$ls180.v:3957$490_Y end - attribute \src "ls180.v:3961.33-3961.785" - cell $or $or$ls180.v:3961$496 + attribute \src "ls180.v:3957.33-3957.785" + cell $or $or$ls180.v:3957$495 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3961$480_Y - connect \B $and$ls180.v:3961$495_Y - connect \Y $or$ls180.v:3961$496_Y + connect \A $or$ls180.v:3957$479_Y + connect \B $and$ls180.v:3957$494_Y + connect \Y $or$ls180.v:3957$495_Y end - attribute \src "ls180.v:3961.880-3961.969" - cell $or $or$ls180.v:3961$501 + attribute \src "ls180.v:3957.880-3957.969" + cell $or $or$ls180.v:3957$500 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked2 - connect \B $and$ls180.v:3961$500_Y - connect \Y $or$ls180.v:3961$501_Y + connect \B $and$ls180.v:3957$499_Y + connect \Y $or$ls180.v:3957$500_Y end - attribute \src "ls180.v:3961.879-3961.1044" - cell $or $or$ls180.v:3961$504 + attribute \src "ls180.v:3957.879-3957.1044" + cell $or $or$ls180.v:3957$503 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3961$501_Y - connect \B $and$ls180.v:3961$503_Y - connect \Y $or$ls180.v:3961$504_Y + connect \A $or$ls180.v:3957$500_Y + connect \B $and$ls180.v:3957$502_Y + connect \Y $or$ls180.v:3957$503_Y end - attribute \src "ls180.v:3961.878-3961.1119" - cell $or $or$ls180.v:3961$507 + attribute \src "ls180.v:3957.878-3957.1119" + cell $or $or$ls180.v:3957$506 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3961$504_Y - connect \B $and$ls180.v:3961$506_Y - connect \Y $or$ls180.v:3961$507_Y + connect \A $or$ls180.v:3957$503_Y + connect \B $and$ls180.v:3957$505_Y + connect \Y $or$ls180.v:3957$506_Y end - attribute \src "ls180.v:3961.32-3961.1159" - cell $or $or$ls180.v:3961$512 + attribute \src "ls180.v:3957.32-3957.1159" + cell $or $or$ls180.v:3957$511 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3961$496_Y - connect \B $and$ls180.v:3961$511_Y - connect \Y $or$ls180.v:3961$512_Y + connect \A $or$ls180.v:3957$495_Y + connect \B $and$ls180.v:3957$510_Y + connect \Y $or$ls180.v:3957$511_Y end - attribute \src "ls180.v:3961.1254-3961.1343" - cell $or $or$ls180.v:3961$517 + attribute \src "ls180.v:3957.1254-3957.1343" + cell $or $or$ls180.v:3957$516 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked3 - connect \B $and$ls180.v:3961$516_Y - connect \Y $or$ls180.v:3961$517_Y + connect \B $and$ls180.v:3957$515_Y + connect \Y $or$ls180.v:3957$516_Y end - attribute \src "ls180.v:3961.1253-3961.1418" - cell $or $or$ls180.v:3961$520 + attribute \src "ls180.v:3957.1253-3957.1418" + cell $or $or$ls180.v:3957$519 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3961$517_Y - connect \B $and$ls180.v:3961$519_Y - connect \Y $or$ls180.v:3961$520_Y + connect \A $or$ls180.v:3957$516_Y + connect \B $and$ls180.v:3957$518_Y + connect \Y $or$ls180.v:3957$519_Y end - attribute \src "ls180.v:3961.1252-3961.1493" - cell $or $or$ls180.v:3961$523 + attribute \src "ls180.v:3957.1252-3957.1493" + cell $or $or$ls180.v:3957$522 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3961$520_Y - connect \B $and$ls180.v:3961$522_Y - connect \Y $or$ls180.v:3961$523_Y + connect \A $or$ls180.v:3957$519_Y + connect \B $and$ls180.v:3957$521_Y + connect \Y $or$ls180.v:3957$522_Y end - attribute \src "ls180.v:3961.31-3961.1533" - cell $or $or$ls180.v:3961$528 + attribute \src "ls180.v:3957.31-3957.1533" + cell $or $or$ls180.v:3957$527 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3961$512_Y - connect \B $and$ls180.v:3961$527_Y - connect \Y $or$ls180.v:3961$528_Y + connect \A $or$ls180.v:3957$511_Y + connect \B $and$ls180.v:3957$526_Y + connect \Y $or$ls180.v:3957$527_Y end - attribute \src "ls180.v:4024.10-4024.52" - cell $or $or$ls180.v:4024$537 + attribute \src "ls180.v:4020.10-4020.52" + cell $or $or$ls180.v:4020$536 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -105422,10 +105418,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_litedram_wb_ack connect \B \main_converter_skip - connect \Y $or$ls180.v:4024$537_Y + connect \Y $or$ls180.v:4020$536_Y end - attribute \src "ls180.v:4051.35-4051.74" - cell $or $or$ls180.v:4051$547 + attribute \src "ls180.v:4047.35-4047.74" + cell $or $or$ls180.v:4047$546 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -105433,10 +105429,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_valid connect \B \main_cmd_consumed - connect \Y $or$ls180.v:4051$547_Y + connect \Y $or$ls180.v:4047$546_Y end - attribute \src "ls180.v:4052.34-4052.73" - cell $or $or$ls180.v:4052$551 + attribute \src "ls180.v:4048.34-4048.73" + cell $or $or$ls180.v:4048$550 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -105444,76 +105440,76 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_valid connect \B \main_cmd_consumed - connect \Y $or$ls180.v:4052$551_Y + connect \Y $or$ls180.v:4048$550_Y end - attribute \src "ls180.v:4053.48-4053.130" - cell $or $or$ls180.v:4053$557 + attribute \src "ls180.v:4049.48-4049.130" + cell $or $or$ls180.v:4049$556 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4053$554_Y - connect \B $and$ls180.v:4053$556_Y - connect \Y $or$ls180.v:4053$557_Y + connect \A $and$ls180.v:4049$553_Y + connect \B $and$ls180.v:4049$555_Y + connect \Y $or$ls180.v:4049$556_Y end - attribute \src "ls180.v:4054.24-4054.87" - cell $or $or$ls180.v:4054$560 + attribute \src "ls180.v:4050.24-4050.87" + cell $or $or$ls180.v:4050$559 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4054$559_Y + connect \A $and$ls180.v:4050$558_Y connect \B \main_cmd_consumed - connect \Y $or$ls180.v:4054$560_Y + connect \Y $or$ls180.v:4050$559_Y end - attribute \src "ls180.v:4055.26-4055.95" - cell $or $or$ls180.v:4055$562 + attribute \src "ls180.v:4051.26-4051.95" + cell $or $or$ls180.v:4051$561 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4055$561_Y + connect \A $and$ls180.v:4051$560_Y connect \B \main_wdata_consumed - connect \Y $or$ls180.v:4055$562_Y + connect \Y $or$ls180.v:4051$561_Y end - attribute \src "ls180.v:4085.42-4085.89" - cell $or $or$ls180.v:4085$570 + attribute \src "ls180.v:4081.42-4081.89" + cell $or $or$ls180.v:4081$569 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_clear - connect \B $and$ls180.v:4085$569_Y - connect \Y $or$ls180.v:4085$570_Y + connect \B $and$ls180.v:4081$568_Y + connect \Y $or$ls180.v:4081$569_Y end - attribute \src "ls180.v:4109.25-4109.174" - cell $or $or$ls180.v:4109$580 + attribute \src "ls180.v:4105.25-4105.174" + cell $or $or$ls180.v:4105$579 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4109$578_Y - connect \B $and$ls180.v:4109$579_Y - connect \Y $or$ls180.v:4109$580_Y + connect \A $and$ls180.v:4105$577_Y + connect \B $and$ls180.v:4105$578_Y + connect \Y $or$ls180.v:4105$579_Y end - attribute \src "ls180.v:4124.80-4124.132" - cell $or $or$ls180.v:4124$582 + attribute \src "ls180.v:4120.80-4120.132" + cell $or $or$ls180.v:4120$581 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4124$581_Y + connect \A $not$ls180.v:4120$580_Y connect \B \main_uart_tx_fifo_re - connect \Y $or$ls180.v:4124$582_Y + connect \Y $or$ls180.v:4120$581_Y end - attribute \src "ls180.v:4135.72-4135.135" - cell $or $or$ls180.v:4135$587 + attribute \src "ls180.v:4131.72-4131.135" + cell $or $or$ls180.v:4131$586 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -105521,21 +105517,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_syncfifo_writable connect \B \main_uart_tx_fifo_replace - connect \Y $or$ls180.v:4135$587_Y + connect \Y $or$ls180.v:4131$586_Y end - attribute \src "ls180.v:4154.80-4154.132" - cell $or $or$ls180.v:4154$593 + attribute \src "ls180.v:4150.80-4150.132" + cell $or $or$ls180.v:4150$592 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4154$592_Y + connect \A $not$ls180.v:4150$591_Y connect \B \main_uart_rx_fifo_re - connect \Y $or$ls180.v:4154$593_Y + connect \Y $or$ls180.v:4150$592_Y end - attribute \src "ls180.v:4165.72-4165.135" - cell $or $or$ls180.v:4165$598 + attribute \src "ls180.v:4161.72-4161.135" + cell $or $or$ls180.v:4161$597 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -105543,10 +105539,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_syncfifo_writable connect \B \main_uart_rx_fifo_replace - connect \Y $or$ls180.v:4165$598_Y + connect \Y $or$ls180.v:4161$597_Y end - attribute \src "ls180.v:4236.36-4236.111" - cell $or $or$ls180.v:4236$611 + attribute \src "ls180.v:4232.36-4232.111" + cell $or $or$ls180.v:4232$610 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -105554,43 +105550,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_init_pads_out_payload_clk connect \B \main_sdphy_cmdw_pads_out_payload_clk - connect \Y $or$ls180.v:4236$611_Y + connect \Y $or$ls180.v:4232$610_Y end - attribute \src "ls180.v:4236.35-4236.151" - cell $or $or$ls180.v:4236$612 + attribute \src "ls180.v:4232.35-4232.151" + cell $or $or$ls180.v:4232$611 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4236$611_Y + connect \A $or$ls180.v:4232$610_Y connect \B \main_sdphy_cmdr_pads_out_payload_clk - connect \Y $or$ls180.v:4236$612_Y + connect \Y $or$ls180.v:4232$611_Y end - attribute \src "ls180.v:4236.34-4236.192" - cell $or $or$ls180.v:4236$613 + attribute \src "ls180.v:4232.34-4232.192" + cell $or $or$ls180.v:4232$612 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4236$612_Y + connect \A $or$ls180.v:4232$611_Y connect \B \main_sdphy_dataw_pads_out_payload_clk - connect \Y $or$ls180.v:4236$613_Y + connect \Y $or$ls180.v:4232$612_Y end - attribute \src "ls180.v:4236.33-4236.233" - cell $or $or$ls180.v:4236$614 + attribute \src "ls180.v:4232.33-4232.233" + cell $or $or$ls180.v:4232$613 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4236$613_Y + connect \A $or$ls180.v:4232$612_Y connect \B \main_sdphy_datar_pads_out_payload_clk - connect \Y $or$ls180.v:4236$614_Y + connect \Y $or$ls180.v:4232$613_Y end - attribute \src "ls180.v:4237.39-4237.120" - cell $or $or$ls180.v:4237$615 + attribute \src "ls180.v:4233.39-4233.120" + cell $or $or$ls180.v:4233$614 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -105598,43 +105594,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_init_pads_out_payload_cmd_oe connect \B \main_sdphy_cmdw_pads_out_payload_cmd_oe - connect \Y $or$ls180.v:4237$615_Y + connect \Y $or$ls180.v:4233$614_Y end - attribute \src "ls180.v:4237.38-4237.163" - cell $or $or$ls180.v:4237$616 + attribute \src "ls180.v:4233.38-4233.163" + cell $or $or$ls180.v:4233$615 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4237$615_Y + connect \A $or$ls180.v:4233$614_Y connect \B \main_sdphy_cmdr_pads_out_payload_cmd_oe - connect \Y $or$ls180.v:4237$616_Y + connect \Y $or$ls180.v:4233$615_Y end - attribute \src "ls180.v:4237.37-4237.207" - cell $or $or$ls180.v:4237$617 + attribute \src "ls180.v:4233.37-4233.207" + cell $or $or$ls180.v:4233$616 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4237$616_Y + connect \A $or$ls180.v:4233$615_Y connect \B \main_sdphy_dataw_pads_out_payload_cmd_oe - connect \Y $or$ls180.v:4237$617_Y + connect \Y $or$ls180.v:4233$616_Y end - attribute \src "ls180.v:4237.36-4237.251" - cell $or $or$ls180.v:4237$618 + attribute \src "ls180.v:4233.36-4233.251" + cell $or $or$ls180.v:4233$617 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4237$617_Y + connect \A $or$ls180.v:4233$616_Y connect \B \main_sdphy_datar_pads_out_payload_cmd_oe - connect \Y $or$ls180.v:4237$618_Y + connect \Y $or$ls180.v:4233$617_Y end - attribute \src "ls180.v:4238.38-4238.117" - cell $or $or$ls180.v:4238$619 + attribute \src "ls180.v:4234.38-4234.117" + cell $or $or$ls180.v:4234$618 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -105642,43 +105638,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_init_pads_out_payload_cmd_o connect \B \main_sdphy_cmdw_pads_out_payload_cmd_o - connect \Y $or$ls180.v:4238$619_Y + connect \Y $or$ls180.v:4234$618_Y end - attribute \src "ls180.v:4238.37-4238.159" - cell $or $or$ls180.v:4238$620 + attribute \src "ls180.v:4234.37-4234.159" + cell $or $or$ls180.v:4234$619 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4238$619_Y + connect \A $or$ls180.v:4234$618_Y connect \B \main_sdphy_cmdr_pads_out_payload_cmd_o - connect \Y $or$ls180.v:4238$620_Y + connect \Y $or$ls180.v:4234$619_Y end - attribute \src "ls180.v:4238.36-4238.202" - cell $or $or$ls180.v:4238$621 + attribute \src "ls180.v:4234.36-4234.202" + cell $or $or$ls180.v:4234$620 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4238$620_Y + connect \A $or$ls180.v:4234$619_Y connect \B \main_sdphy_dataw_pads_out_payload_cmd_o - connect \Y $or$ls180.v:4238$621_Y + connect \Y $or$ls180.v:4234$620_Y end - attribute \src "ls180.v:4238.35-4238.245" - cell $or $or$ls180.v:4238$622 + attribute \src "ls180.v:4234.35-4234.245" + cell $or $or$ls180.v:4234$621 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4238$621_Y + connect \A $or$ls180.v:4234$620_Y connect \B \main_sdphy_datar_pads_out_payload_cmd_o - connect \Y $or$ls180.v:4238$622_Y + connect \Y $or$ls180.v:4234$621_Y end - attribute \src "ls180.v:4239.40-4239.123" - cell $or $or$ls180.v:4239$623 + attribute \src "ls180.v:4235.40-4235.123" + cell $or $or$ls180.v:4235$622 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -105686,43 +105682,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_init_pads_out_payload_data_oe connect \B \main_sdphy_cmdw_pads_out_payload_data_oe - connect \Y $or$ls180.v:4239$623_Y + connect \Y $or$ls180.v:4235$622_Y end - attribute \src "ls180.v:4239.39-4239.167" - cell $or $or$ls180.v:4239$624 + attribute \src "ls180.v:4235.39-4235.167" + cell $or $or$ls180.v:4235$623 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4239$623_Y + connect \A $or$ls180.v:4235$622_Y connect \B \main_sdphy_cmdr_pads_out_payload_data_oe - connect \Y $or$ls180.v:4239$624_Y + connect \Y $or$ls180.v:4235$623_Y end - attribute \src "ls180.v:4239.38-4239.212" - cell $or $or$ls180.v:4239$625 + attribute \src "ls180.v:4235.38-4235.212" + cell $or $or$ls180.v:4235$624 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4239$624_Y + connect \A $or$ls180.v:4235$623_Y connect \B \main_sdphy_dataw_pads_out_payload_data_oe - connect \Y $or$ls180.v:4239$625_Y + connect \Y $or$ls180.v:4235$624_Y end - attribute \src "ls180.v:4239.37-4239.257" - cell $or $or$ls180.v:4239$626 + attribute \src "ls180.v:4235.37-4235.257" + cell $or $or$ls180.v:4235$625 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4239$625_Y + connect \A $or$ls180.v:4235$624_Y connect \B \main_sdphy_datar_pads_out_payload_data_oe - connect \Y $or$ls180.v:4239$626_Y + connect \Y $or$ls180.v:4235$625_Y end - attribute \src "ls180.v:4240.39-4240.120" - cell $or $or$ls180.v:4240$627 + attribute \src "ls180.v:4236.39-4236.120" + cell $or $or$ls180.v:4236$626 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -105730,43 +105726,43 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdphy_init_pads_out_payload_data_o connect \B \main_sdphy_cmdw_pads_out_payload_data_o - connect \Y $or$ls180.v:4240$627_Y + connect \Y $or$ls180.v:4236$626_Y end - attribute \src "ls180.v:4240.38-4240.163" - cell $or $or$ls180.v:4240$628 + attribute \src "ls180.v:4236.38-4236.163" + cell $or $or$ls180.v:4236$627 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A $or$ls180.v:4240$627_Y + connect \A $or$ls180.v:4236$626_Y connect \B \main_sdphy_cmdr_pads_out_payload_data_o - connect \Y $or$ls180.v:4240$628_Y + connect \Y $or$ls180.v:4236$627_Y end - attribute \src "ls180.v:4240.37-4240.207" - cell $or $or$ls180.v:4240$629 + attribute \src "ls180.v:4236.37-4236.207" + cell $or $or$ls180.v:4236$628 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A $or$ls180.v:4240$628_Y + connect \A $or$ls180.v:4236$627_Y connect \B \main_sdphy_dataw_pads_out_payload_data_o - connect \Y $or$ls180.v:4240$629_Y + connect \Y $or$ls180.v:4236$628_Y end - attribute \src "ls180.v:4240.36-4240.251" - cell $or $or$ls180.v:4240$630 + attribute \src "ls180.v:4236.36-4236.251" + cell $or $or$ls180.v:4236$629 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A $or$ls180.v:4240$629_Y + connect \A $or$ls180.v:4236$628_Y connect \B \main_sdphy_datar_pads_out_payload_data_o - connect \Y $or$ls180.v:4240$630_Y + connect \Y $or$ls180.v:4236$629_Y end - attribute \src "ls180.v:4261.35-4261.80" - cell $or $or$ls180.v:4261$631 + attribute \src "ls180.v:4257.35-4257.80" + cell $or $or$ls180.v:4257$630 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -105774,10 +105770,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_stop connect \B \main_sdphy_datar_stop - connect \Y $or$ls180.v:4261$631_Y + connect \Y $or$ls180.v:4257$630_Y end - attribute \src "ls180.v:4415.91-4415.144" - cell $or $or$ls180.v:4415$645 + attribute \src "ls180.v:4411.91-4411.144" + cell $or $or$ls180.v:4411$644 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -105785,76 +105781,76 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_start connect \B \main_sdphy_cmdr_cmdr_run - connect \Y $or$ls180.v:4415$645_Y + connect \Y $or$ls180.v:4411$644_Y end - attribute \src "ls180.v:4432.53-4432.143" - cell $or $or$ls180.v:4432$648 + attribute \src "ls180.v:4428.53-4428.143" + cell $or $or$ls180.v:4428$647 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4432$647_Y + connect \A $not$ls180.v:4428$646_Y connect \B \main_sdphy_cmdr_cmdr_converter_source_ready - connect \Y $or$ls180.v:4432$648_Y + connect \Y $or$ls180.v:4428$647_Y end - attribute \src "ls180.v:4435.47-4435.127" - cell $or $or$ls180.v:4435$651 + attribute \src "ls180.v:4431.47-4431.127" + cell $or $or$ls180.v:4431$650 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4435$650_Y + connect \A $not$ls180.v:4431$649_Y connect \B \main_sdphy_cmdr_cmdr_buf_source_ready - connect \Y $or$ls180.v:4435$651_Y + connect \Y $or$ls180.v:4431$650_Y end - attribute \src "ls180.v:4559.54-4559.146" - cell $or $or$ls180.v:4559$669 + attribute \src "ls180.v:4555.54-4555.146" + cell $or $or$ls180.v:4555$668 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4559$668_Y + connect \A $not$ls180.v:4555$667_Y connect \B \main_sdphy_dataw_crcr_converter_source_ready - connect \Y $or$ls180.v:4559$669_Y + connect \Y $or$ls180.v:4555$668_Y end - attribute \src "ls180.v:4562.48-4562.130" - cell $or $or$ls180.v:4562$672 + attribute \src "ls180.v:4558.48-4558.130" + cell $or $or$ls180.v:4558$671 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4562$671_Y + connect \A $not$ls180.v:4558$670_Y connect \B \main_sdphy_dataw_crcr_buf_source_ready - connect \Y $or$ls180.v:4562$672_Y + connect \Y $or$ls180.v:4558$671_Y end - attribute \src "ls180.v:4693.55-4693.149" - cell $or $or$ls180.v:4693$684 + attribute \src "ls180.v:4689.55-4689.149" + cell $or $or$ls180.v:4689$683 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4693$683_Y + connect \A $not$ls180.v:4689$682_Y connect \B \main_sdphy_datar_datar_converter_source_ready - connect \Y $or$ls180.v:4693$684_Y + connect \Y $or$ls180.v:4689$683_Y end - attribute \src "ls180.v:4696.49-4696.133" - cell $or $or$ls180.v:4696$687 + attribute \src "ls180.v:4692.49-4692.133" + cell $or $or$ls180.v:4692$686 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4696$686_Y + connect \A $not$ls180.v:4692$685_Y connect \B \main_sdphy_datar_datar_buf_source_ready - connect \Y $or$ls180.v:4696$687_Y + connect \Y $or$ls180.v:4692$686_Y end - attribute \src "ls180.v:5325.80-5325.151" - cell $or $or$ls180.v:5325$982 + attribute \src "ls180.v:5321.80-5321.151" + cell $or $or$ls180.v:5321$981 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -105862,21 +105858,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_syncfifo_writable connect \B \main_sdblock2mem_fifo_replace - connect \Y $or$ls180.v:5325$982_Y + connect \Y $or$ls180.v:5321$981_Y end - attribute \src "ls180.v:5336.49-5336.131" - cell $or $or$ls180.v:5336$988 + attribute \src "ls180.v:5332.49-5332.131" + cell $or $or$ls180.v:5332$987 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:5336$987_Y + connect \A $not$ls180.v:5332$986_Y connect \B \main_sdblock2mem_converter_source_ready - connect \Y $or$ls180.v:5336$988_Y + connect \Y $or$ls180.v:5332$987_Y end - attribute \src "ls180.v:5533.80-5533.151" - cell $or $or$ls180.v:5533$1013 + attribute \src "ls180.v:5529.80-5529.151" + cell $or $or$ls180.v:5529$1012 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -105884,10 +105880,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_syncfifo_writable connect \B \main_sdmem2block_fifo_replace - connect \Y $or$ls180.v:5533$1013_Y + connect \Y $or$ls180.v:5529$1012_Y end - attribute \src "ls180.v:5707.33-5707.102" - cell $or $or$ls180.v:5707$1061 + attribute \src "ls180.v:5703.33-5703.102" + cell $or $or$ls180.v:5703$1060 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -105895,43 +105891,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_err connect \B \main_libresocsim_libresoc_xics_icp_err - connect \Y $or$ls180.v:5707$1061_Y + connect \Y $or$ls180.v:5703$1060_Y end - attribute \src "ls180.v:5707.32-5707.144" - cell $or $or$ls180.v:5707$1062 + attribute \src "ls180.v:5703.32-5703.144" + cell $or $or$ls180.v:5703$1061 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5707$1061_Y + connect \A $or$ls180.v:5703$1060_Y connect \B \main_libresocsim_libresoc_xics_ics_err - connect \Y $or$ls180.v:5707$1062_Y + connect \Y $or$ls180.v:5703$1061_Y end - attribute \src "ls180.v:5707.31-5707.165" - cell $or $or$ls180.v:5707$1063 + attribute \src "ls180.v:5703.31-5703.165" + cell $or $or$ls180.v:5703$1062 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5707$1062_Y + connect \A $or$ls180.v:5703$1061_Y connect \B \main_wb_sdram_err - connect \Y $or$ls180.v:5707$1063_Y + connect \Y $or$ls180.v:5703$1062_Y end - attribute \src "ls180.v:5707.30-5707.201" - cell $or $or$ls180.v:5707$1064 + attribute \src "ls180.v:5703.30-5703.201" + cell $or $or$ls180.v:5703$1063 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5707$1063_Y + connect \A $or$ls180.v:5703$1062_Y connect \B \builder_libresocsim_wishbone_err - connect \Y $or$ls180.v:5707$1064_Y + connect \Y $or$ls180.v:5703$1063_Y end - attribute \src "ls180.v:5713.28-5713.97" - cell $or $or$ls180.v:5713$1069 + attribute \src "ls180.v:5709.28-5709.97" + cell $or $or$ls180.v:5709$1068 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -105939,87 +105935,87 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_ack connect \B \main_libresocsim_libresoc_xics_icp_ack - connect \Y $or$ls180.v:5713$1069_Y + connect \Y $or$ls180.v:5709$1068_Y end - attribute \src "ls180.v:5713.27-5713.139" - cell $or $or$ls180.v:5713$1070 + attribute \src "ls180.v:5709.27-5709.139" + cell $or $or$ls180.v:5709$1069 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5713$1069_Y + connect \A $or$ls180.v:5709$1068_Y connect \B \main_libresocsim_libresoc_xics_ics_ack - connect \Y $or$ls180.v:5713$1070_Y + connect \Y $or$ls180.v:5709$1069_Y end - attribute \src "ls180.v:5713.26-5713.160" - cell $or $or$ls180.v:5713$1071 + attribute \src "ls180.v:5709.26-5709.160" + cell $or $or$ls180.v:5709$1070 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5713$1070_Y + connect \A $or$ls180.v:5709$1069_Y connect \B \main_wb_sdram_ack - connect \Y $or$ls180.v:5713$1071_Y + connect \Y $or$ls180.v:5709$1070_Y end - attribute \src "ls180.v:5713.25-5713.196" - cell $or $or$ls180.v:5713$1072 + attribute \src "ls180.v:5709.25-5709.196" + cell $or $or$ls180.v:5709$1071 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5713$1071_Y + connect \A $or$ls180.v:5709$1070_Y connect \B \builder_libresocsim_wishbone_ack - connect \Y $or$ls180.v:5713$1072_Y + connect \Y $or$ls180.v:5709$1071_Y end - attribute \src "ls180.v:5714.30-5714.169" - cell $or $or$ls180.v:5714$1075 + attribute \src "ls180.v:5710.30-5710.169" + cell $or $or$ls180.v:5710$1074 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 32 - connect \A $and$ls180.v:5714$1073_Y - connect \B $and$ls180.v:5714$1074_Y - connect \Y $or$ls180.v:5714$1075_Y + connect \A $and$ls180.v:5710$1072_Y + connect \B $and$ls180.v:5710$1073_Y + connect \Y $or$ls180.v:5710$1074_Y end - attribute \src "ls180.v:5714.29-5714.246" - cell $or $or$ls180.v:5714$1077 + attribute \src "ls180.v:5710.29-5710.246" + cell $or $or$ls180.v:5710$1076 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 32 - connect \A $or$ls180.v:5714$1075_Y - connect \B $and$ls180.v:5714$1076_Y - connect \Y $or$ls180.v:5714$1077_Y + connect \A $or$ls180.v:5710$1074_Y + connect \B $and$ls180.v:5710$1075_Y + connect \Y $or$ls180.v:5710$1076_Y end - attribute \src "ls180.v:5714.28-5714.302" - cell $or $or$ls180.v:5714$1079 + attribute \src "ls180.v:5710.28-5710.302" + cell $or $or$ls180.v:5710$1078 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 32 - connect \A $or$ls180.v:5714$1077_Y - connect \B $and$ls180.v:5714$1078_Y - connect \Y $or$ls180.v:5714$1079_Y + connect \A $or$ls180.v:5710$1076_Y + connect \B $and$ls180.v:5710$1077_Y + connect \Y $or$ls180.v:5710$1078_Y end - attribute \src "ls180.v:5714.27-5714.373" - cell $or $or$ls180.v:5714$1081 + attribute \src "ls180.v:5710.27-5710.373" + cell $or $or$ls180.v:5710$1080 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 32 - connect \A $or$ls180.v:5714$1079_Y - connect \B $and$ls180.v:5714$1080_Y - connect \Y $or$ls180.v:5714$1081_Y + connect \A $or$ls180.v:5710$1078_Y + connect \B $and$ls180.v:5710$1079_Y + connect \Y $or$ls180.v:5710$1080_Y end - attribute \src "ls180.v:6451.54-6451.123" - cell $or $or$ls180.v:6451$2212 + attribute \src "ls180.v:6447.54-6447.123" + cell $or $or$ls180.v:6447$2211 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -106027,274 +106023,274 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \builder_interface0_bank_bus_dat_r connect \B \builder_interface1_bank_bus_dat_r - connect \Y $or$ls180.v:6451$2212_Y + connect \Y $or$ls180.v:6447$2211_Y end - attribute \src "ls180.v:6451.53-6451.160" - cell $or $or$ls180.v:6451$2213 + attribute \src "ls180.v:6447.53-6447.160" + cell $or $or$ls180.v:6447$2212 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6451$2212_Y + connect \A $or$ls180.v:6447$2211_Y connect \B \builder_interface2_bank_bus_dat_r - connect \Y $or$ls180.v:6451$2213_Y + connect \Y $or$ls180.v:6447$2212_Y end - attribute \src "ls180.v:6451.52-6451.197" - cell $or $or$ls180.v:6451$2214 + attribute \src "ls180.v:6447.52-6447.197" + cell $or $or$ls180.v:6447$2213 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6451$2213_Y + connect \A $or$ls180.v:6447$2212_Y connect \B \builder_interface3_bank_bus_dat_r - connect \Y $or$ls180.v:6451$2214_Y + connect \Y $or$ls180.v:6447$2213_Y end - attribute \src "ls180.v:6451.51-6451.234" - cell $or $or$ls180.v:6451$2215 + attribute \src "ls180.v:6447.51-6447.234" + cell $or $or$ls180.v:6447$2214 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6451$2214_Y + connect \A $or$ls180.v:6447$2213_Y connect \B \builder_interface4_bank_bus_dat_r - connect \Y $or$ls180.v:6451$2215_Y + connect \Y $or$ls180.v:6447$2214_Y end - attribute \src "ls180.v:6451.50-6451.271" - cell $or $or$ls180.v:6451$2216 + attribute \src "ls180.v:6447.50-6447.271" + cell $or $or$ls180.v:6447$2215 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6451$2215_Y + connect \A $or$ls180.v:6447$2214_Y connect \B \builder_interface5_bank_bus_dat_r - connect \Y $or$ls180.v:6451$2216_Y + connect \Y $or$ls180.v:6447$2215_Y end - attribute \src "ls180.v:6451.49-6451.308" - cell $or $or$ls180.v:6451$2217 + attribute \src "ls180.v:6447.49-6447.308" + cell $or $or$ls180.v:6447$2216 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6451$2216_Y + connect \A $or$ls180.v:6447$2215_Y connect \B \builder_interface6_bank_bus_dat_r - connect \Y $or$ls180.v:6451$2217_Y + connect \Y $or$ls180.v:6447$2216_Y end - attribute \src "ls180.v:6451.48-6451.345" - cell $or $or$ls180.v:6451$2218 + attribute \src "ls180.v:6447.48-6447.345" + cell $or $or$ls180.v:6447$2217 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6451$2217_Y + connect \A $or$ls180.v:6447$2216_Y connect \B \builder_interface7_bank_bus_dat_r - connect \Y $or$ls180.v:6451$2218_Y + connect \Y $or$ls180.v:6447$2217_Y end - attribute \src "ls180.v:6451.47-6451.382" - cell $or $or$ls180.v:6451$2219 + attribute \src "ls180.v:6447.47-6447.382" + cell $or $or$ls180.v:6447$2218 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6451$2218_Y + connect \A $or$ls180.v:6447$2217_Y connect \B \builder_interface8_bank_bus_dat_r - connect \Y $or$ls180.v:6451$2219_Y + connect \Y $or$ls180.v:6447$2218_Y end - attribute \src "ls180.v:6451.46-6451.419" - cell $or $or$ls180.v:6451$2220 + attribute \src "ls180.v:6447.46-6447.419" + cell $or $or$ls180.v:6447$2219 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6451$2219_Y + connect \A $or$ls180.v:6447$2218_Y connect \B \builder_interface9_bank_bus_dat_r - connect \Y $or$ls180.v:6451$2220_Y + connect \Y $or$ls180.v:6447$2219_Y end - attribute \src "ls180.v:6451.45-6451.457" - cell $or $or$ls180.v:6451$2221 + attribute \src "ls180.v:6447.45-6447.457" + cell $or $or$ls180.v:6447$2220 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6451$2220_Y + connect \A $or$ls180.v:6447$2219_Y connect \B \builder_interface10_bank_bus_dat_r - connect \Y $or$ls180.v:6451$2221_Y + connect \Y $or$ls180.v:6447$2220_Y end - attribute \src "ls180.v:6451.44-6451.495" - cell $or $or$ls180.v:6451$2222 + attribute \src "ls180.v:6447.44-6447.495" + cell $or $or$ls180.v:6447$2221 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6451$2221_Y + connect \A $or$ls180.v:6447$2220_Y connect \B \builder_interface11_bank_bus_dat_r - connect \Y $or$ls180.v:6451$2222_Y + connect \Y $or$ls180.v:6447$2221_Y end - attribute \src "ls180.v:6451.43-6451.533" - cell $or $or$ls180.v:6451$2223 + attribute \src "ls180.v:6447.43-6447.533" + cell $or $or$ls180.v:6447$2222 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6451$2222_Y + connect \A $or$ls180.v:6447$2221_Y connect \B \builder_interface12_bank_bus_dat_r - connect \Y $or$ls180.v:6451$2223_Y + connect \Y $or$ls180.v:6447$2222_Y end - attribute \src "ls180.v:6451.42-6451.571" - cell $or $or$ls180.v:6451$2224 + attribute \src "ls180.v:6447.42-6447.571" + cell $or $or$ls180.v:6447$2223 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6451$2223_Y + connect \A $or$ls180.v:6447$2222_Y connect \B \builder_interface13_bank_bus_dat_r - connect \Y $or$ls180.v:6451$2224_Y + connect \Y $or$ls180.v:6447$2223_Y end - attribute \src "ls180.v:6778.90-6778.179" - cell $or $or$ls180.v:6778$2249 + attribute \src "ls180.v:6774.90-6774.179" + cell $or $or$ls180.v:6774$2248 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked0 - connect \B $and$ls180.v:6778$2248_Y - connect \Y $or$ls180.v:6778$2249_Y + connect \B $and$ls180.v:6774$2247_Y + connect \Y $or$ls180.v:6774$2248_Y end - attribute \src "ls180.v:6778.89-6778.254" - cell $or $or$ls180.v:6778$2252 + attribute \src "ls180.v:6774.89-6774.254" + cell $or $or$ls180.v:6774$2251 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6778$2249_Y - connect \B $and$ls180.v:6778$2251_Y - connect \Y $or$ls180.v:6778$2252_Y + connect \A $or$ls180.v:6774$2248_Y + connect \B $and$ls180.v:6774$2250_Y + connect \Y $or$ls180.v:6774$2251_Y end - attribute \src "ls180.v:6778.88-6778.329" - cell $or $or$ls180.v:6778$2255 + attribute \src "ls180.v:6774.88-6774.329" + cell $or $or$ls180.v:6774$2254 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6778$2252_Y - connect \B $and$ls180.v:6778$2254_Y - connect \Y $or$ls180.v:6778$2255_Y + connect \A $or$ls180.v:6774$2251_Y + connect \B $and$ls180.v:6774$2253_Y + connect \Y $or$ls180.v:6774$2254_Y end - attribute \src "ls180.v:6802.90-6802.179" - cell $or $or$ls180.v:6802$2265 + attribute \src "ls180.v:6798.90-6798.179" + cell $or $or$ls180.v:6798$2264 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked1 - connect \B $and$ls180.v:6802$2264_Y - connect \Y $or$ls180.v:6802$2265_Y + connect \B $and$ls180.v:6798$2263_Y + connect \Y $or$ls180.v:6798$2264_Y end - attribute \src "ls180.v:6802.89-6802.254" - cell $or $or$ls180.v:6802$2268 + attribute \src "ls180.v:6798.89-6798.254" + cell $or $or$ls180.v:6798$2267 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6802$2265_Y - connect \B $and$ls180.v:6802$2267_Y - connect \Y $or$ls180.v:6802$2268_Y + connect \A $or$ls180.v:6798$2264_Y + connect \B $and$ls180.v:6798$2266_Y + connect \Y $or$ls180.v:6798$2267_Y end - attribute \src "ls180.v:6802.88-6802.329" - cell $or $or$ls180.v:6802$2271 + attribute \src "ls180.v:6798.88-6798.329" + cell $or $or$ls180.v:6798$2270 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6802$2268_Y - connect \B $and$ls180.v:6802$2270_Y - connect \Y $or$ls180.v:6802$2271_Y + connect \A $or$ls180.v:6798$2267_Y + connect \B $and$ls180.v:6798$2269_Y + connect \Y $or$ls180.v:6798$2270_Y end - attribute \src "ls180.v:6826.90-6826.179" - cell $or $or$ls180.v:6826$2281 + attribute \src "ls180.v:6822.90-6822.179" + cell $or $or$ls180.v:6822$2280 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked2 - connect \B $and$ls180.v:6826$2280_Y - connect \Y $or$ls180.v:6826$2281_Y + connect \B $and$ls180.v:6822$2279_Y + connect \Y $or$ls180.v:6822$2280_Y end - attribute \src "ls180.v:6826.89-6826.254" - cell $or $or$ls180.v:6826$2284 + attribute \src "ls180.v:6822.89-6822.254" + cell $or $or$ls180.v:6822$2283 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6826$2281_Y - connect \B $and$ls180.v:6826$2283_Y - connect \Y $or$ls180.v:6826$2284_Y + connect \A $or$ls180.v:6822$2280_Y + connect \B $and$ls180.v:6822$2282_Y + connect \Y $or$ls180.v:6822$2283_Y end - attribute \src "ls180.v:6826.88-6826.329" - cell $or $or$ls180.v:6826$2287 + attribute \src "ls180.v:6822.88-6822.329" + cell $or $or$ls180.v:6822$2286 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6826$2284_Y - connect \B $and$ls180.v:6826$2286_Y - connect \Y $or$ls180.v:6826$2287_Y + connect \A $or$ls180.v:6822$2283_Y + connect \B $and$ls180.v:6822$2285_Y + connect \Y $or$ls180.v:6822$2286_Y end - attribute \src "ls180.v:6850.90-6850.179" - cell $or $or$ls180.v:6850$2297 + attribute \src "ls180.v:6846.90-6846.179" + cell $or $or$ls180.v:6846$2296 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked3 - connect \B $and$ls180.v:6850$2296_Y - connect \Y $or$ls180.v:6850$2297_Y + connect \B $and$ls180.v:6846$2295_Y + connect \Y $or$ls180.v:6846$2296_Y end - attribute \src "ls180.v:6850.89-6850.254" - cell $or $or$ls180.v:6850$2300 + attribute \src "ls180.v:6846.89-6846.254" + cell $or $or$ls180.v:6846$2299 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6850$2297_Y - connect \B $and$ls180.v:6850$2299_Y - connect \Y $or$ls180.v:6850$2300_Y + connect \A $or$ls180.v:6846$2296_Y + connect \B $and$ls180.v:6846$2298_Y + connect \Y $or$ls180.v:6846$2299_Y end - attribute \src "ls180.v:6850.88-6850.329" - cell $or $or$ls180.v:6850$2303 + attribute \src "ls180.v:6846.88-6846.329" + cell $or $or$ls180.v:6846$2302 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6850$2300_Y - connect \B $and$ls180.v:6850$2302_Y - connect \Y $or$ls180.v:6850$2303_Y + connect \A $or$ls180.v:6846$2299_Y + connect \B $and$ls180.v:6846$2301_Y + connect \Y $or$ls180.v:6846$2302_Y end attribute \src "ls180.v:7360.20-7360.71" - cell $or $or$ls180.v:7360$2360 + cell $or $or$ls180.v:7360$2359 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -106302,10 +106298,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [0] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7360$2360_Y + connect \Y $or$ls180.v:7360$2359_Y end attribute \src "ls180.v:7361.20-7361.71" - cell $or $or$ls180.v:7361$2361 + cell $or $or$ls180.v:7361$2360 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -106313,10 +106309,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [1] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7361$2361_Y + connect \Y $or$ls180.v:7361$2360_Y end attribute \src "ls180.v:7362.20-7362.71" - cell $or $or$ls180.v:7362$2362 + cell $or $or$ls180.v:7362$2361 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -106324,10 +106320,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [2] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7362$2362_Y + connect \Y $or$ls180.v:7362$2361_Y end attribute \src "ls180.v:7363.20-7363.71" - cell $or $or$ls180.v:7363$2363 + cell $or $or$ls180.v:7363$2362 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -106335,10 +106331,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [3] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7363$2363_Y + connect \Y $or$ls180.v:7363$2362_Y end attribute \src "ls180.v:7364.20-7364.71" - cell $or $or$ls180.v:7364$2364 + cell $or $or$ls180.v:7364$2363 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -106346,10 +106342,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [4] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7364$2364_Y + connect \Y $or$ls180.v:7364$2363_Y end attribute \src "ls180.v:7365.20-7365.71" - cell $or $or$ls180.v:7365$2365 + cell $or $or$ls180.v:7365$2364 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -106357,10 +106353,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [5] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7365$2365_Y + connect \Y $or$ls180.v:7365$2364_Y end attribute \src "ls180.v:7366.20-7366.71" - cell $or $or$ls180.v:7366$2366 + cell $or $or$ls180.v:7366$2365 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -106368,10 +106364,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [6] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7366$2366_Y + connect \Y $or$ls180.v:7366$2365_Y end attribute \src "ls180.v:7367.20-7367.71" - cell $or $or$ls180.v:7367$2367 + cell $or $or$ls180.v:7367$2366 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -106379,10 +106375,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [7] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7367$2367_Y + connect \Y $or$ls180.v:7367$2366_Y end attribute \src "ls180.v:7368.20-7368.71" - cell $or $or$ls180.v:7368$2368 + cell $or $or$ls180.v:7368$2367 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -106390,10 +106386,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [8] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7368$2368_Y + connect \Y $or$ls180.v:7368$2367_Y end attribute \src "ls180.v:7369.20-7369.71" - cell $or $or$ls180.v:7369$2369 + cell $or $or$ls180.v:7369$2368 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -106401,10 +106397,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [9] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7369$2369_Y + connect \Y $or$ls180.v:7369$2368_Y end attribute \src "ls180.v:7370.21-7370.73" - cell $or $or$ls180.v:7370$2370 + cell $or $or$ls180.v:7370$2369 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -106412,10 +106408,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [10] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7370$2370_Y + connect \Y $or$ls180.v:7370$2369_Y end attribute \src "ls180.v:7371.21-7371.73" - cell $or $or$ls180.v:7371$2371 + cell $or $or$ls180.v:7371$2370 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -106423,10 +106419,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [11] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7371$2371_Y + connect \Y $or$ls180.v:7371$2370_Y end attribute \src "ls180.v:7372.21-7372.73" - cell $or $or$ls180.v:7372$2372 + cell $or $or$ls180.v:7372$2371 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -106434,10 +106430,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [12] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7372$2372_Y + connect \Y $or$ls180.v:7372$2371_Y end attribute \src "ls180.v:7373.21-7373.73" - cell $or $or$ls180.v:7373$2373 + cell $or $or$ls180.v:7373$2372 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -106445,10 +106441,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [13] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7373$2373_Y + connect \Y $or$ls180.v:7373$2372_Y end attribute \src "ls180.v:7374.21-7374.73" - cell $or $or$ls180.v:7374$2374 + cell $or $or$ls180.v:7374$2373 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -106456,10 +106452,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [14] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7374$2374_Y + connect \Y $or$ls180.v:7374$2373_Y end attribute \src "ls180.v:7375.21-7375.73" - cell $or $or$ls180.v:7375$2375 + cell $or $or$ls180.v:7375$2374 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -106467,10 +106463,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [15] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7375$2375_Y + connect \Y $or$ls180.v:7375$2374_Y end attribute \src "ls180.v:7376.21-7376.73" - cell $or $or$ls180.v:7376$2376 + cell $or $or$ls180.v:7376$2375 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -106478,10 +106474,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [16] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7376$2376_Y + connect \Y $or$ls180.v:7376$2375_Y end attribute \src "ls180.v:7377.21-7377.73" - cell $or $or$ls180.v:7377$2377 + cell $or $or$ls180.v:7377$2376 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -106489,10 +106485,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [17] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7377$2377_Y + connect \Y $or$ls180.v:7377$2376_Y end attribute \src "ls180.v:7378.21-7378.73" - cell $or $or$ls180.v:7378$2378 + cell $or $or$ls180.v:7378$2377 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -106500,10 +106496,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [18] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7378$2378_Y + connect \Y $or$ls180.v:7378$2377_Y end attribute \src "ls180.v:7379.21-7379.73" - cell $or $or$ls180.v:7379$2379 + cell $or $or$ls180.v:7379$2378 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -106511,10 +106507,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [19] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7379$2379_Y + connect \Y $or$ls180.v:7379$2378_Y end attribute \src "ls180.v:7380.21-7380.73" - cell $or $or$ls180.v:7380$2380 + cell $or $or$ls180.v:7380$2379 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -106522,10 +106518,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [20] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7380$2380_Y + connect \Y $or$ls180.v:7380$2379_Y end attribute \src "ls180.v:7381.21-7381.73" - cell $or $or$ls180.v:7381$2381 + cell $or $or$ls180.v:7381$2380 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -106533,10 +106529,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [21] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7381$2381_Y + connect \Y $or$ls180.v:7381$2380_Y end attribute \src "ls180.v:7382.21-7382.73" - cell $or $or$ls180.v:7382$2382 + cell $or $or$ls180.v:7382$2381 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -106544,10 +106540,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [22] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7382$2382_Y + connect \Y $or$ls180.v:7382$2381_Y end attribute \src "ls180.v:7383.21-7383.73" - cell $or $or$ls180.v:7383$2383 + cell $or $or$ls180.v:7383$2382 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -106555,10 +106551,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [23] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7383$2383_Y + connect \Y $or$ls180.v:7383$2382_Y end attribute \src "ls180.v:7384.21-7384.73" - cell $or $or$ls180.v:7384$2384 + cell $or $or$ls180.v:7384$2383 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -106566,10 +106562,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [24] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7384$2384_Y + connect \Y $or$ls180.v:7384$2383_Y end attribute \src "ls180.v:7385.21-7385.73" - cell $or $or$ls180.v:7385$2385 + cell $or $or$ls180.v:7385$2384 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -106577,10 +106573,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [25] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7385$2385_Y + connect \Y $or$ls180.v:7385$2384_Y end attribute \src "ls180.v:7386.21-7386.73" - cell $or $or$ls180.v:7386$2386 + cell $or $or$ls180.v:7386$2385 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -106588,10 +106584,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [26] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7386$2386_Y + connect \Y $or$ls180.v:7386$2385_Y end attribute \src "ls180.v:7387.21-7387.73" - cell $or $or$ls180.v:7387$2387 + cell $or $or$ls180.v:7387$2386 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -106599,10 +106595,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [27] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7387$2387_Y + connect \Y $or$ls180.v:7387$2386_Y end attribute \src "ls180.v:7388.21-7388.73" - cell $or $or$ls180.v:7388$2388 + cell $or $or$ls180.v:7388$2387 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -106610,10 +106606,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [28] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7388$2388_Y + connect \Y $or$ls180.v:7388$2387_Y end attribute \src "ls180.v:7389.21-7389.73" - cell $or $or$ls180.v:7389$2389 + cell $or $or$ls180.v:7389$2388 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -106621,10 +106617,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [29] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7389$2389_Y + connect \Y $or$ls180.v:7389$2388_Y end attribute \src "ls180.v:7390.21-7390.73" - cell $or $or$ls180.v:7390$2390 + cell $or $or$ls180.v:7390$2389 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -106632,10 +106628,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [30] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7390$2390_Y + connect \Y $or$ls180.v:7390$2389_Y end attribute \src "ls180.v:7391.21-7391.73" - cell $or $or$ls180.v:7391$2391 + cell $or $or$ls180.v:7391$2390 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -106643,10 +106639,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [31] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7391$2391_Y + connect \Y $or$ls180.v:7391$2390_Y end attribute \src "ls180.v:7392.21-7392.73" - cell $or $or$ls180.v:7392$2392 + cell $or $or$ls180.v:7392$2391 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -106654,10 +106650,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [32] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7392$2392_Y + connect \Y $or$ls180.v:7392$2391_Y end attribute \src "ls180.v:7393.21-7393.73" - cell $or $or$ls180.v:7393$2393 + cell $or $or$ls180.v:7393$2392 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -106665,10 +106661,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [33] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7393$2393_Y + connect \Y $or$ls180.v:7393$2392_Y end attribute \src "ls180.v:7394.21-7394.73" - cell $or $or$ls180.v:7394$2394 + cell $or $or$ls180.v:7394$2393 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -106676,10 +106672,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [34] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7394$2394_Y + connect \Y $or$ls180.v:7394$2393_Y end attribute \src "ls180.v:7395.21-7395.73" - cell $or $or$ls180.v:7395$2395 + cell $or $or$ls180.v:7395$2394 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -106687,10 +106683,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [35] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7395$2395_Y + connect \Y $or$ls180.v:7395$2394_Y end attribute \src "ls180.v:7396.21-7396.73" - cell $or $or$ls180.v:7396$2396 + cell $or $or$ls180.v:7396$2395 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -106698,10 +106694,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [36] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7396$2396_Y + connect \Y $or$ls180.v:7396$2395_Y end attribute \src "ls180.v:7397.21-7397.73" - cell $or $or$ls180.v:7397$2397 + cell $or $or$ls180.v:7397$2396 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -106709,10 +106705,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [37] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7397$2397_Y + connect \Y $or$ls180.v:7397$2396_Y end attribute \src "ls180.v:7398.21-7398.73" - cell $or $or$ls180.v:7398$2398 + cell $or $or$ls180.v:7398$2397 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -106720,10 +106716,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [38] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7398$2398_Y + connect \Y $or$ls180.v:7398$2397_Y end attribute \src "ls180.v:7399.21-7399.73" - cell $or $or$ls180.v:7399$2399 + cell $or $or$ls180.v:7399$2398 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -106731,10 +106727,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [39] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7399$2399_Y + connect \Y $or$ls180.v:7399$2398_Y end attribute \src "ls180.v:7400.21-7400.73" - cell $or $or$ls180.v:7400$2400 + cell $or $or$ls180.v:7400$2399 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -106742,10 +106738,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [40] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7400$2400_Y + connect \Y $or$ls180.v:7400$2399_Y end attribute \src "ls180.v:7401.21-7401.73" - cell $or $or$ls180.v:7401$2401 + cell $or $or$ls180.v:7401$2400 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -106753,21 +106749,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [41] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7401$2401_Y + connect \Y $or$ls180.v:7401$2400_Y end - attribute \src "ls180.v:7402.21-7402.73" - cell $or $or$ls180.v:7402$2402 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [42] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7402$2402_Y - end - attribute \src "ls180.v:7403.7-7403.93" - cell $or $or$ls180.v:7403$2403 + attribute \src "ls180.v:7402.7-7402.93" + cell $or $or$ls180.v:7402$2401 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -106775,10 +106760,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_interface0_converted_interface_ack connect \B \main_libresocsim_converter0_skip - connect \Y $or$ls180.v:7403$2403_Y + connect \Y $or$ls180.v:7402$2401_Y end - attribute \src "ls180.v:7414.7-7414.93" - cell $or $or$ls180.v:7414$2404 + attribute \src "ls180.v:7413.7-7413.93" + cell $or $or$ls180.v:7413$2402 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -106786,10 +106771,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_interface1_converted_interface_ack connect \B \main_libresocsim_converter1_skip - connect \Y $or$ls180.v:7414$2404_Y + connect \Y $or$ls180.v:7413$2402_Y end - attribute \src "ls180.v:7425.7-7425.93" - cell $or $or$ls180.v:7425$2405 + attribute \src "ls180.v:7424.7-7424.93" + cell $or $or$ls180.v:7424$2403 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -106797,142 +106782,142 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_interface2_converted_interface_ack connect \B \main_libresocsim_converter2_skip - connect \Y $or$ls180.v:7425$2405_Y + connect \Y $or$ls180.v:7424$2403_Y end - attribute \src "ls180.v:7556.7-7556.107" - cell $or $or$ls180.v:7556$2441 + attribute \src "ls180.v:7553.7-7553.107" + cell $or $or$ls180.v:7553$2439 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7556$2440_Y + connect \A $not$ls180.v:7553$2438_Y connect \B \main_sdram_bankmachine0_cmd_buffer_source_ready - connect \Y $or$ls180.v:7556$2441_Y + connect \Y $or$ls180.v:7553$2439_Y end - attribute \src "ls180.v:7602.7-7602.107" - cell $or $or$ls180.v:7602$2457 + attribute \src "ls180.v:7599.7-7599.107" + cell $or $or$ls180.v:7599$2455 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7602$2456_Y + connect \A $not$ls180.v:7599$2454_Y connect \B \main_sdram_bankmachine1_cmd_buffer_source_ready - connect \Y $or$ls180.v:7602$2457_Y + connect \Y $or$ls180.v:7599$2455_Y end - attribute \src "ls180.v:7648.7-7648.107" - cell $or $or$ls180.v:7648$2473 + attribute \src "ls180.v:7645.7-7645.107" + cell $or $or$ls180.v:7645$2471 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7648$2472_Y + connect \A $not$ls180.v:7645$2470_Y connect \B \main_sdram_bankmachine2_cmd_buffer_source_ready - connect \Y $or$ls180.v:7648$2473_Y + connect \Y $or$ls180.v:7645$2471_Y end - attribute \src "ls180.v:7694.7-7694.107" - cell $or $or$ls180.v:7694$2489 + attribute \src "ls180.v:7691.7-7691.107" + cell $or $or$ls180.v:7691$2487 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7694$2488_Y + connect \A $not$ls180.v:7691$2486_Y connect \B \main_sdram_bankmachine3_cmd_buffer_source_ready - connect \Y $or$ls180.v:7694$2489_Y + connect \Y $or$ls180.v:7691$2487_Y end - attribute \src "ls180.v:7882.40-7882.125" - cell $or $or$ls180.v:7882$2510 + attribute \src "ls180.v:7879.40-7879.125" + cell $or $or$ls180.v:7879$2508 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A 1'0 - connect \B $and$ls180.v:7882$2509_Y - connect \Y $or$ls180.v:7882$2510_Y + connect \B $and$ls180.v:7879$2507_Y + connect \Y $or$ls180.v:7879$2508_Y end - attribute \src "ls180.v:7882.39-7882.207" - cell $or $or$ls180.v:7882$2513 + attribute \src "ls180.v:7879.39-7879.207" + cell $or $or$ls180.v:7879$2511 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7882$2510_Y - connect \B $and$ls180.v:7882$2512_Y - connect \Y $or$ls180.v:7882$2513_Y + connect \A $or$ls180.v:7879$2508_Y + connect \B $and$ls180.v:7879$2510_Y + connect \Y $or$ls180.v:7879$2511_Y end - attribute \src "ls180.v:7882.38-7882.289" - cell $or $or$ls180.v:7882$2516 + attribute \src "ls180.v:7879.38-7879.289" + cell $or $or$ls180.v:7879$2514 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7882$2513_Y - connect \B $and$ls180.v:7882$2515_Y - connect \Y $or$ls180.v:7882$2516_Y + connect \A $or$ls180.v:7879$2511_Y + connect \B $and$ls180.v:7879$2513_Y + connect \Y $or$ls180.v:7879$2514_Y end - attribute \src "ls180.v:7882.37-7882.371" - cell $or $or$ls180.v:7882$2519 + attribute \src "ls180.v:7879.37-7879.371" + cell $or $or$ls180.v:7879$2517 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7882$2516_Y - connect \B $and$ls180.v:7882$2518_Y - connect \Y $or$ls180.v:7882$2519_Y + connect \A $or$ls180.v:7879$2514_Y + connect \B $and$ls180.v:7879$2516_Y + connect \Y $or$ls180.v:7879$2517_Y end - attribute \src "ls180.v:7883.41-7883.126" - cell $or $or$ls180.v:7883$2522 + attribute \src "ls180.v:7880.41-7880.126" + cell $or $or$ls180.v:7880$2520 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A 1'0 - connect \B $and$ls180.v:7883$2521_Y - connect \Y $or$ls180.v:7883$2522_Y + connect \B $and$ls180.v:7880$2519_Y + connect \Y $or$ls180.v:7880$2520_Y end - attribute \src "ls180.v:7883.40-7883.208" - cell $or $or$ls180.v:7883$2525 + attribute \src "ls180.v:7880.40-7880.208" + cell $or $or$ls180.v:7880$2523 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7883$2522_Y - connect \B $and$ls180.v:7883$2524_Y - connect \Y $or$ls180.v:7883$2525_Y + connect \A $or$ls180.v:7880$2520_Y + connect \B $and$ls180.v:7880$2522_Y + connect \Y $or$ls180.v:7880$2523_Y end - attribute \src "ls180.v:7883.39-7883.290" - cell $or $or$ls180.v:7883$2528 + attribute \src "ls180.v:7880.39-7880.290" + cell $or $or$ls180.v:7880$2526 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7883$2525_Y - connect \B $and$ls180.v:7883$2527_Y - connect \Y $or$ls180.v:7883$2528_Y + connect \A $or$ls180.v:7880$2523_Y + connect \B $and$ls180.v:7880$2525_Y + connect \Y $or$ls180.v:7880$2526_Y end - attribute \src "ls180.v:7883.38-7883.372" - cell $or $or$ls180.v:7883$2531 + attribute \src "ls180.v:7880.38-7880.372" + cell $or $or$ls180.v:7880$2529 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7883$2528_Y - connect \B $and$ls180.v:7883$2530_Y - connect \Y $or$ls180.v:7883$2531_Y + connect \A $or$ls180.v:7880$2526_Y + connect \B $and$ls180.v:7880$2528_Y + connect \Y $or$ls180.v:7880$2529_Y end - attribute \src "ls180.v:7887.7-7887.49" - cell $or $or$ls180.v:7887$2532 + attribute \src "ls180.v:7884.7-7884.49" + cell $or $or$ls180.v:7884$2530 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -106940,21 +106925,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_litedram_wb_ack connect \B \main_converter_skip - connect \Y $or$ls180.v:7887$2532_Y + connect \Y $or$ls180.v:7884$2530_Y end - attribute \src "ls180.v:8050.22-8050.74" - cell $or $or$ls180.v:8050$2580 + attribute \src "ls180.v:8047.22-8047.74" + cell $or $or$ls180.v:8047$2578 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8050$2578_Y - connect \B $not$ls180.v:8050$2579_Y - connect \Y $or$ls180.v:8050$2580_Y + connect \A $not$ls180.v:8047$2576_Y + connect \B $not$ls180.v:8047$2577_Y + connect \Y $or$ls180.v:8047$2578_Y end - attribute \src "ls180.v:8118.32-8118.85" - cell $or $or$ls180.v:8118$2592 + attribute \src "ls180.v:8115.32-8115.85" + cell $or $or$ls180.v:8115$2590 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -106962,21 +106947,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_start connect \B \main_sdphy_cmdr_cmdr_run - connect \Y $or$ls180.v:8118$2592_Y + connect \Y $or$ls180.v:8115$2590_Y end - attribute \src "ls180.v:8124.8-8124.97" - cell $or $or$ls180.v:8124$2594 + attribute \src "ls180.v:8121.8-8121.97" + cell $or $or$ls180.v:8121$2592 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8124$2593_Y + connect \A $eq$ls180.v:8121$2591_Y connect \B \main_sdphy_cmdr_cmdr_converter_sink_last - connect \Y $or$ls180.v:8124$2594_Y + connect \Y $or$ls180.v:8121$2592_Y end - attribute \src "ls180.v:8141.52-8141.139" - cell $or $or$ls180.v:8141$2599 + attribute \src "ls180.v:8138.52-8138.139" + cell $or $or$ls180.v:8138$2597 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -106984,10 +106969,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_sink_first connect \B \main_sdphy_cmdr_cmdr_converter_source_first - connect \Y $or$ls180.v:8141$2599_Y + connect \Y $or$ls180.v:8138$2597_Y end - attribute \src "ls180.v:8142.51-8142.136" - cell $or $or$ls180.v:8142$2600 + attribute \src "ls180.v:8139.51-8139.136" + cell $or $or$ls180.v:8139$2598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -106995,21 +106980,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_sink_last connect \B \main_sdphy_cmdr_cmdr_converter_source_last - connect \Y $or$ls180.v:8142$2600_Y + connect \Y $or$ls180.v:8139$2598_Y end - attribute \src "ls180.v:8176.7-8176.87" - cell $or $or$ls180.v:8176$2603 + attribute \src "ls180.v:8173.7-8173.87" + cell $or $or$ls180.v:8173$2601 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8176$2602_Y + connect \A $not$ls180.v:8173$2600_Y connect \B \main_sdphy_cmdr_cmdr_buf_source_ready - connect \Y $or$ls180.v:8176$2603_Y + connect \Y $or$ls180.v:8173$2601_Y end - attribute \src "ls180.v:8199.33-8199.88" - cell $or $or$ls180.v:8199$2604 + attribute \src "ls180.v:8196.33-8196.88" + cell $or $or$ls180.v:8196$2602 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -107017,21 +107002,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_start connect \B \main_sdphy_dataw_crcr_run - connect \Y $or$ls180.v:8199$2604_Y + connect \Y $or$ls180.v:8196$2602_Y end - attribute \src "ls180.v:8205.8-8205.99" - cell $or $or$ls180.v:8205$2606 + attribute \src "ls180.v:8202.8-8202.99" + cell $or $or$ls180.v:8202$2604 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8205$2605_Y + connect \A $eq$ls180.v:8202$2603_Y connect \B \main_sdphy_dataw_crcr_converter_sink_last - connect \Y $or$ls180.v:8205$2606_Y + connect \Y $or$ls180.v:8202$2604_Y end - attribute \src "ls180.v:8222.53-8222.142" - cell $or $or$ls180.v:8222$2611 + attribute \src "ls180.v:8219.53-8219.142" + cell $or $or$ls180.v:8219$2609 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -107039,10 +107024,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_sink_first connect \B \main_sdphy_dataw_crcr_converter_source_first - connect \Y $or$ls180.v:8222$2611_Y + connect \Y $or$ls180.v:8219$2609_Y end - attribute \src "ls180.v:8223.52-8223.139" - cell $or $or$ls180.v:8223$2612 + attribute \src "ls180.v:8220.52-8220.139" + cell $or $or$ls180.v:8220$2610 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -107050,21 +107035,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_sink_last connect \B \main_sdphy_dataw_crcr_converter_source_last - connect \Y $or$ls180.v:8223$2612_Y + connect \Y $or$ls180.v:8220$2610_Y end - attribute \src "ls180.v:8257.7-8257.89" - cell $or $or$ls180.v:8257$2615 + attribute \src "ls180.v:8254.7-8254.89" + cell $or $or$ls180.v:8254$2613 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8257$2614_Y + connect \A $not$ls180.v:8254$2612_Y connect \B \main_sdphy_dataw_crcr_buf_source_ready - connect \Y $or$ls180.v:8257$2615_Y + connect \Y $or$ls180.v:8254$2613_Y end - attribute \src "ls180.v:8278.34-8278.91" - cell $or $or$ls180.v:8278$2616 + attribute \src "ls180.v:8275.34-8275.91" + cell $or $or$ls180.v:8275$2614 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -107072,21 +107057,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_start connect \B \main_sdphy_datar_datar_run - connect \Y $or$ls180.v:8278$2616_Y + connect \Y $or$ls180.v:8275$2614_Y end - attribute \src "ls180.v:8284.8-8284.101" - cell $or $or$ls180.v:8284$2618 + attribute \src "ls180.v:8281.8-8281.101" + cell $or $or$ls180.v:8281$2616 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8284$2617_Y + connect \A $eq$ls180.v:8281$2615_Y connect \B \main_sdphy_datar_datar_converter_sink_last - connect \Y $or$ls180.v:8284$2618_Y + connect \Y $or$ls180.v:8281$2616_Y end - attribute \src "ls180.v:8301.54-8301.145" - cell $or $or$ls180.v:8301$2623 + attribute \src "ls180.v:8298.54-8298.145" + cell $or $or$ls180.v:8298$2621 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -107094,10 +107079,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_sink_first connect \B \main_sdphy_datar_datar_converter_source_first - connect \Y $or$ls180.v:8301$2623_Y + connect \Y $or$ls180.v:8298$2621_Y end - attribute \src "ls180.v:8302.53-8302.142" - cell $or $or$ls180.v:8302$2624 + attribute \src "ls180.v:8299.53-8299.142" + cell $or $or$ls180.v:8299$2622 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -107105,32 +107090,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_sink_last connect \B \main_sdphy_datar_datar_converter_source_last - connect \Y $or$ls180.v:8302$2624_Y + connect \Y $or$ls180.v:8299$2622_Y end - attribute \src "ls180.v:8318.7-8318.91" - cell $or $or$ls180.v:8318$2627 + attribute \src "ls180.v:8315.7-8315.91" + cell $or $or$ls180.v:8315$2625 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8318$2626_Y + connect \A $not$ls180.v:8315$2624_Y connect \B \main_sdphy_datar_datar_buf_source_ready - connect \Y $or$ls180.v:8318$2627_Y + connect \Y $or$ls180.v:8315$2625_Y end - attribute \src "ls180.v:8507.8-8507.89" - cell $or $or$ls180.v:8507$2651 + attribute \src "ls180.v:8504.8-8504.89" + cell $or $or$ls180.v:8504$2649 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8507$2650_Y + connect \A $eq$ls180.v:8504$2648_Y connect \B \main_sdblock2mem_converter_sink_last - connect \Y $or$ls180.v:8507$2651_Y + connect \Y $or$ls180.v:8504$2649_Y end - attribute \src "ls180.v:8524.48-8524.127" - cell $or $or$ls180.v:8524$2656 + attribute \src "ls180.v:8521.48-8521.127" + cell $or $or$ls180.v:8521$2654 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -107138,10 +107123,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_sink_first connect \B \main_sdblock2mem_converter_source_first - connect \Y $or$ls180.v:8524$2656_Y + connect \Y $or$ls180.v:8521$2654_Y end - attribute \src "ls180.v:8525.47-8525.124" - cell $or $or$ls180.v:8525$2657 + attribute \src "ls180.v:8522.47-8522.124" + cell $or $or$ls180.v:8522$2655 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -107149,21 +107134,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_sink_last connect \B \main_sdblock2mem_converter_source_last - connect \Y $or$ls180.v:8525$2657_Y + connect \Y $or$ls180.v:8522$2655_Y end - attribute \src "ls180.v:8598.21-8598.65" - cell $or $or$ls180.v:8598$2675 + attribute \src "ls180.v:8595.21-8595.65" + cell $or $or$ls180.v:8595$2673 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8598$2673_Y - connect \B $not$ls180.v:8598$2674_Y - connect \Y $or$ls180.v:8598$2675_Y + connect \A $not$ls180.v:8595$2671_Y + connect \B $not$ls180.v:8595$2672_Y + connect \Y $or$ls180.v:8595$2673_Y end - attribute \src "ls180.v:3135.46-3135.94" - cell $sshl $sshl$ls180.v:3135$84 + attribute \src "ls180.v:3131.46-3131.94" + cell $sshl $sshl$ls180.v:3131$83 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -107171,10 +107156,10 @@ module \ls180 parameter \Y_WIDTH 13 connect \A \main_sdram_bankmachine0_auto_precharge connect \B 4'1010 - connect \Y $sshl$ls180.v:3135$84_Y + connect \Y $sshl$ls180.v:3131$83_Y end - attribute \src "ls180.v:3292.46-3292.94" - cell $sshl $sshl$ls180.v:3292$114 + attribute \src "ls180.v:3288.46-3288.94" + cell $sshl $sshl$ls180.v:3288$113 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -107182,10 +107167,10 @@ module \ls180 parameter \Y_WIDTH 13 connect \A \main_sdram_bankmachine1_auto_precharge connect \B 4'1010 - connect \Y $sshl$ls180.v:3292$114_Y + connect \Y $sshl$ls180.v:3288$113_Y end - attribute \src "ls180.v:3449.46-3449.94" - cell $sshl $sshl$ls180.v:3449$144 + attribute \src "ls180.v:3445.46-3445.94" + cell $sshl $sshl$ls180.v:3445$143 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -107193,10 +107178,10 @@ module \ls180 parameter \Y_WIDTH 13 connect \A \main_sdram_bankmachine2_auto_precharge connect \B 4'1010 - connect \Y $sshl$ls180.v:3449$144_Y + connect \Y $sshl$ls180.v:3445$143_Y end - attribute \src "ls180.v:3606.46-3606.94" - cell $sshl $sshl$ls180.v:3606$174 + attribute \src "ls180.v:3602.46-3602.94" + cell $sshl $sshl$ls180.v:3602$173 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -107204,10 +107189,10 @@ module \ls180 parameter \Y_WIDTH 13 connect \A \main_sdram_bankmachine3_auto_precharge connect \B 4'1010 - connect \Y $sshl$ls180.v:3606$174_Y + connect \Y $sshl$ls180.v:3602$173_Y end - attribute \src "ls180.v:3166.63-3166.122" - cell $sub $sub$ls180.v:3166$97 + attribute \src "ls180.v:3162.63-3162.122" + cell $sub $sub$ls180.v:3162$96 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -107215,10 +107200,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $sub$ls180.v:3166$97_Y + connect \Y $sub$ls180.v:3162$96_Y end - attribute \src "ls180.v:3323.63-3323.122" - cell $sub $sub$ls180.v:3323$127 + attribute \src "ls180.v:3319.63-3319.122" + cell $sub $sub$ls180.v:3319$126 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -107226,10 +107211,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $sub$ls180.v:3323$127_Y + connect \Y $sub$ls180.v:3319$126_Y end - attribute \src "ls180.v:3480.63-3480.122" - cell $sub $sub$ls180.v:3480$157 + attribute \src "ls180.v:3476.63-3476.122" + cell $sub $sub$ls180.v:3476$156 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -107237,10 +107222,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $sub$ls180.v:3480$157_Y + connect \Y $sub$ls180.v:3476$156_Y end - attribute \src "ls180.v:3637.63-3637.122" - cell $sub $sub$ls180.v:3637$187 + attribute \src "ls180.v:3633.63-3633.122" + cell $sub $sub$ls180.v:3633$186 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -107248,10 +107233,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $sub$ls180.v:3637$187_Y + connect \Y $sub$ls180.v:3633$186_Y end - attribute \src "ls180.v:4043.38-4043.75" - cell $sub $sub$ls180.v:4043$541 + attribute \src "ls180.v:4039.38-4039.75" + cell $sub $sub$ls180.v:4039$540 parameter \A_SIGNED 0 parameter \A_WIDTH 30 parameter \B_SIGNED 0 @@ -107259,10 +107244,10 @@ module \ls180 parameter \Y_WIDTH 31 connect \A \main_litedram_wb_adr connect \B 31'1001000000000000000000000000000 - connect \Y $sub$ls180.v:4043$541_Y + connect \Y $sub$ls180.v:4039$540_Y end - attribute \src "ls180.v:4129.36-4129.68" - cell $sub $sub$ls180.v:4129$586 + attribute \src "ls180.v:4125.36-4125.68" + cell $sub $sub$ls180.v:4125$585 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -107270,10 +107255,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_uart_tx_fifo_produce connect \B 1'1 - connect \Y $sub$ls180.v:4129$586_Y + connect \Y $sub$ls180.v:4125$585_Y end - attribute \src "ls180.v:4159.36-4159.68" - cell $sub $sub$ls180.v:4159$597 + attribute \src "ls180.v:4155.36-4155.68" + cell $sub $sub$ls180.v:4155$596 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -107281,10 +107266,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_uart_rx_fifo_produce connect \B 1'1 - connect \Y $sub$ls180.v:4159$597_Y + connect \Y $sub$ls180.v:4155$596_Y end - attribute \src "ls180.v:4184.69-4184.110" - cell $sub $sub$ls180.v:4184$603 + attribute \src "ls180.v:4180.69-4180.110" + cell $sub $sub$ls180.v:4180$602 parameter \A_SIGNED 0 parameter \A_WIDTH 15 parameter \B_SIGNED 0 @@ -107292,10 +107277,10 @@ module \ls180 parameter \Y_WIDTH 16 connect \A \main_spi_master_clk_divider0 [15:1] connect \B 1'1 - connect \Y $sub$ls180.v:4184$603_Y + connect \Y $sub$ls180.v:4180$602_Y end - attribute \src "ls180.v:4185.69-4185.104" - cell $sub $sub$ls180.v:4185$605 + attribute \src "ls180.v:4181.69-4181.104" + cell $sub $sub$ls180.v:4181$604 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -107303,10 +107288,10 @@ module \ls180 parameter \Y_WIDTH 16 connect \A \main_spi_master_clk_divider0 connect \B 1'1 - connect \Y $sub$ls180.v:4185$605_Y + connect \Y $sub$ls180.v:4181$604_Y end - attribute \src "ls180.v:4212.36-4212.66" - cell $sub $sub$ls180.v:4212$609 + attribute \src "ls180.v:4208.36-4208.66" + cell $sub $sub$ls180.v:4208$608 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -107314,10 +107299,10 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \main_spi_master_length0 connect \B 1'1 - connect \Y $sub$ls180.v:4212$609_Y + connect \Y $sub$ls180.v:4208$608_Y end - attribute \src "ls180.v:4462.60-4462.90" - cell $sub $sub$ls180.v:4462$653 + attribute \src "ls180.v:4458.60-4458.90" + cell $sub $sub$ls180.v:4458$652 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -107325,10 +107310,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdphy_cmdr_timeout connect \B 1'1 - connect \Y $sub$ls180.v:4462$653_Y + connect \Y $sub$ls180.v:4458$652_Y end - attribute \src "ls180.v:4473.62-4473.104" - cell $sub $sub$ls180.v:4473$655 + attribute \src "ls180.v:4469.62-4469.104" + cell $sub $sub$ls180.v:4469$654 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -107336,10 +107321,10 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \main_sdphy_cmdr_sink_payload_length connect \B 1'1 - connect \Y $sub$ls180.v:4473$655_Y + connect \Y $sub$ls180.v:4469$654_Y end - attribute \src "ls180.v:4490.60-4490.90" - cell $sub $sub$ls180.v:4490$659 + attribute \src "ls180.v:4486.60-4486.90" + cell $sub $sub$ls180.v:4486$658 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -107347,10 +107332,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdphy_cmdr_timeout connect \B 1'1 - connect \Y $sub$ls180.v:4490$659_Y + connect \Y $sub$ls180.v:4486$658_Y end - attribute \src "ls180.v:4719.62-4719.93" - cell $sub $sub$ls180.v:4719$689 + attribute \src "ls180.v:4715.62-4715.93" + cell $sub $sub$ls180.v:4715$688 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -107358,10 +107343,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdphy_datar_timeout connect \B 1'1 - connect \Y $sub$ls180.v:4719$689_Y + connect \Y $sub$ls180.v:4715$688_Y end - attribute \src "ls180.v:4724.62-4724.93" - cell $sub $sub$ls180.v:4724$690 + attribute \src "ls180.v:4720.62-4720.93" + cell $sub $sub$ls180.v:4720$689 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -107369,21 +107354,21 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdphy_datar_timeout connect \B 1'1 - connect \Y $sub$ls180.v:4724$690_Y + connect \Y $sub$ls180.v:4720$689_Y end - attribute \src "ls180.v:4735.64-4735.122" - cell $sub $sub$ls180.v:4735$693 + attribute \src "ls180.v:4731.64-4731.122" + cell $sub $sub$ls180.v:4731$692 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 10 - connect \A $add$ls180.v:4735$692_Y + connect \A $add$ls180.v:4731$691_Y connect \B 1'1 - connect \Y $sub$ls180.v:4735$693_Y + connect \Y $sub$ls180.v:4731$692_Y end - attribute \src "ls180.v:4756.62-4756.93" - cell $sub $sub$ls180.v:4756$696 + attribute \src "ls180.v:4752.62-4752.93" + cell $sub $sub$ls180.v:4752$695 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -107391,10 +107376,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdphy_datar_timeout connect \B 1'1 - connect \Y $sub$ls180.v:4756$696_Y + connect \Y $sub$ls180.v:4752$695_Y end - attribute \src "ls180.v:5218.37-5218.75" - cell $sub $sub$ls180.v:5218$969 + attribute \src "ls180.v:5214.37-5214.75" + cell $sub $sub$ls180.v:5214$968 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -107402,10 +107387,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdcore_block_count_storage connect \B 1'1 - connect \Y $sub$ls180.v:5218$969_Y + connect \Y $sub$ls180.v:5214$968_Y end - attribute \src "ls180.v:5233.62-5233.100" - cell $sub $sub$ls180.v:5233$972 + attribute \src "ls180.v:5229.62-5229.100" + cell $sub $sub$ls180.v:5229$971 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -107413,10 +107398,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdcore_block_count_storage connect \B 1'1 - connect \Y $sub$ls180.v:5233$972_Y + connect \Y $sub$ls180.v:5229$971_Y end - attribute \src "ls180.v:5244.39-5244.77" - cell $sub $sub$ls180.v:5244$977 + attribute \src "ls180.v:5240.39-5240.77" + cell $sub $sub$ls180.v:5240$976 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -107424,10 +107409,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdcore_block_count_storage connect \B 1'1 - connect \Y $sub$ls180.v:5244$977_Y + connect \Y $sub$ls180.v:5240$976_Y end - attribute \src "ls180.v:5319.40-5319.76" - cell $sub $sub$ls180.v:5319$981 + attribute \src "ls180.v:5315.40-5315.76" + cell $sub $sub$ls180.v:5315$980 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -107435,10 +107420,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_sdblock2mem_fifo_produce connect \B 1'1 - connect \Y $sub$ls180.v:5319$981_Y + connect \Y $sub$ls180.v:5315$980_Y end - attribute \src "ls180.v:5368.56-5368.104" - cell $sub $sub$ls180.v:5368$995 + attribute \src "ls180.v:5364.56-5364.104" + cell $sub $sub$ls180.v:5364$994 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -107446,10 +107431,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdblock2mem_wishbonedmawriter_length connect \B 1'1 - connect \Y $sub$ls180.v:5368$995_Y + connect \Y $sub$ls180.v:5364$994_Y end - attribute \src "ls180.v:5458.71-5458.105" - cell $sub $sub$ls180.v:5458$1001 + attribute \src "ls180.v:5454.71-5454.105" + cell $sub $sub$ls180.v:5454$1000 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -107457,10 +107442,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdmem2block_dma_length connect \B 1'1 - connect \Y $sub$ls180.v:5458$1001_Y + connect \Y $sub$ls180.v:5454$1000_Y end - attribute \src "ls180.v:5527.40-5527.76" - cell $sub $sub$ls180.v:5527$1012 + attribute \src "ls180.v:5523.40-5523.76" + cell $sub $sub$ls180.v:5523$1011 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -107468,10 +107453,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_sdmem2block_fifo_produce connect \B 1'1 - connect \Y $sub$ls180.v:5527$1012_Y + connect \Y $sub$ls180.v:5523$1011_Y end - attribute \src "ls180.v:5546.61-5546.98" - cell $sub $sub$ls180.v:5546$1018 + attribute \src "ls180.v:5542.61-5542.98" + cell $sub $sub$ls180.v:5542$1017 parameter \A_SIGNED 0 parameter \A_WIDTH 15 parameter \B_SIGNED 0 @@ -107479,10 +107464,10 @@ module \ls180 parameter \Y_WIDTH 16 connect \A \libresocsim_clk_divider0 [15:1] connect \B 1'1 - connect \Y $sub$ls180.v:5546$1018_Y + connect \Y $sub$ls180.v:5542$1017_Y end - attribute \src "ls180.v:5547.61-5547.92" - cell $sub $sub$ls180.v:5547$1020 + attribute \src "ls180.v:5543.61-5543.92" + cell $sub $sub$ls180.v:5543$1019 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -107490,10 +107475,10 @@ module \ls180 parameter \Y_WIDTH 16 connect \A \libresocsim_clk_divider0 connect \B 1'1 - connect \Y $sub$ls180.v:5547$1020_Y + connect \Y $sub$ls180.v:5543$1019_Y end - attribute \src "ls180.v:5575.32-5575.58" - cell $sub $sub$ls180.v:5575$1024 + attribute \src "ls180.v:5571.32-5571.58" + cell $sub $sub$ls180.v:5571$1023 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -107501,10 +107486,10 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \libresocsim_length0 connect \B 1'1 - connect \Y $sub$ls180.v:5575$1024_Y + connect \Y $sub$ls180.v:5571$1023_Y end - attribute \src "ls180.v:7449.31-7449.60" - cell $sub $sub$ls180.v:7449$2412 + attribute \src "ls180.v:7448.31-7448.60" + cell $sub $sub$ls180.v:7448$2410 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -107512,10 +107497,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_libresocsim_value connect \B 1'1 - connect \Y $sub$ls180.v:7449$2412_Y + connect \Y $sub$ls180.v:7448$2410_Y end - attribute \src "ls180.v:7472.31-7472.61" - cell $sub $sub$ls180.v:7472$2417 + attribute \src "ls180.v:7469.31-7469.61" + cell $sub $sub$ls180.v:7469$2415 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -107523,10 +107508,10 @@ module \ls180 parameter \Y_WIDTH 10 connect \A \main_sdram_timer_count1 connect \B 1'1 - connect \Y $sub$ls180.v:7472$2417_Y + connect \Y $sub$ls180.v:7469$2415_Y end - attribute \src "ls180.v:7478.34-7478.67" - cell $sub $sub$ls180.v:7478$2418 + attribute \src "ls180.v:7475.34-7475.67" + cell $sub $sub$ls180.v:7475$2416 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -107534,10 +107519,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_postponer_count connect \B 1'1 - connect \Y $sub$ls180.v:7478$2418_Y + connect \Y $sub$ls180.v:7475$2416_Y end - attribute \src "ls180.v:7489.36-7489.69" - cell $sub $sub$ls180.v:7489$2421 + attribute \src "ls180.v:7486.36-7486.69" + cell $sub $sub$ls180.v:7486$2419 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -107545,10 +107530,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_count connect \B 1'1 - connect \Y $sub$ls180.v:7489$2421_Y + connect \Y $sub$ls180.v:7486$2419_Y end - attribute \src "ls180.v:7553.59-7553.116" - cell $sub $sub$ls180.v:7553$2439 + attribute \src "ls180.v:7550.59-7550.116" + cell $sub $sub$ls180.v:7550$2437 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -107556,10 +107541,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $sub$ls180.v:7553$2439_Y + connect \Y $sub$ls180.v:7550$2437_Y end - attribute \src "ls180.v:7572.46-7572.90" - cell $sub $sub$ls180.v:7572$2443 + attribute \src "ls180.v:7569.46-7569.90" + cell $sub $sub$ls180.v:7569$2441 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -107567,10 +107552,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine0_twtpcon_count connect \B 1'1 - connect \Y $sub$ls180.v:7572$2443_Y + connect \Y $sub$ls180.v:7569$2441_Y end - attribute \src "ls180.v:7599.59-7599.116" - cell $sub $sub$ls180.v:7599$2455 + attribute \src "ls180.v:7596.59-7596.116" + cell $sub $sub$ls180.v:7596$2453 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -107578,10 +107563,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $sub$ls180.v:7599$2455_Y + connect \Y $sub$ls180.v:7596$2453_Y end - attribute \src "ls180.v:7618.46-7618.90" - cell $sub $sub$ls180.v:7618$2459 + attribute \src "ls180.v:7615.46-7615.90" + cell $sub $sub$ls180.v:7615$2457 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -107589,10 +107574,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine1_twtpcon_count connect \B 1'1 - connect \Y $sub$ls180.v:7618$2459_Y + connect \Y $sub$ls180.v:7615$2457_Y end - attribute \src "ls180.v:7645.59-7645.116" - cell $sub $sub$ls180.v:7645$2471 + attribute \src "ls180.v:7642.59-7642.116" + cell $sub $sub$ls180.v:7642$2469 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -107600,10 +107585,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $sub$ls180.v:7645$2471_Y + connect \Y $sub$ls180.v:7642$2469_Y end - attribute \src "ls180.v:7664.46-7664.90" - cell $sub $sub$ls180.v:7664$2475 + attribute \src "ls180.v:7661.46-7661.90" + cell $sub $sub$ls180.v:7661$2473 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -107611,10 +107596,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine2_twtpcon_count connect \B 1'1 - connect \Y $sub$ls180.v:7664$2475_Y + connect \Y $sub$ls180.v:7661$2473_Y end - attribute \src "ls180.v:7691.59-7691.116" - cell $sub $sub$ls180.v:7691$2487 + attribute \src "ls180.v:7688.59-7688.116" + cell $sub $sub$ls180.v:7688$2485 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -107622,10 +107607,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $sub$ls180.v:7691$2487_Y + connect \Y $sub$ls180.v:7688$2485_Y end - attribute \src "ls180.v:7710.46-7710.90" - cell $sub $sub$ls180.v:7710$2491 + attribute \src "ls180.v:7707.46-7707.90" + cell $sub $sub$ls180.v:7707$2489 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -107633,10 +107618,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine3_twtpcon_count connect \B 1'1 - connect \Y $sub$ls180.v:7710$2491_Y + connect \Y $sub$ls180.v:7707$2489_Y end - attribute \src "ls180.v:7721.25-7721.48" - cell $sub $sub$ls180.v:7721$2495 + attribute \src "ls180.v:7718.25-7718.48" + cell $sub $sub$ls180.v:7718$2493 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -107644,10 +107629,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_sdram_time0 connect \B 1'1 - connect \Y $sub$ls180.v:7721$2495_Y + connect \Y $sub$ls180.v:7718$2493_Y end - attribute \src "ls180.v:7728.25-7728.48" - cell $sub $sub$ls180.v:7728$2498 + attribute \src "ls180.v:7725.25-7725.48" + cell $sub $sub$ls180.v:7725$2496 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -107655,10 +107640,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_time1 connect \B 1'1 - connect \Y $sub$ls180.v:7728$2498_Y + connect \Y $sub$ls180.v:7725$2496_Y end - attribute \src "ls180.v:7860.33-7860.64" - cell $sub $sub$ls180.v:7860$2503 + attribute \src "ls180.v:7857.33-7857.64" + cell $sub $sub$ls180.v:7857$2501 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -107666,10 +107651,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_tccdcon_count connect \B 1'1 - connect \Y $sub$ls180.v:7860$2503_Y + connect \Y $sub$ls180.v:7857$2501_Y end - attribute \src "ls180.v:7875.33-7875.64" - cell $sub $sub$ls180.v:7875$2506 + attribute \src "ls180.v:7872.33-7872.64" + cell $sub $sub$ls180.v:7872$2504 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -107677,10 +107662,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_twtrcon_count connect \B 1'1 - connect \Y $sub$ls180.v:7875$2506_Y + connect \Y $sub$ls180.v:7872$2504_Y end - attribute \src "ls180.v:8002.33-8002.64" - cell $sub $sub$ls180.v:8002$2565 + attribute \src "ls180.v:7999.33-7999.64" + cell $sub $sub$ls180.v:7999$2563 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -107688,10 +107673,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_uart_tx_fifo_level0 connect \B 1'1 - connect \Y $sub$ls180.v:8002$2565_Y + connect \Y $sub$ls180.v:7999$2563_Y end - attribute \src "ls180.v:8024.33-8024.64" - cell $sub $sub$ls180.v:8024$2576 + attribute \src "ls180.v:8021.33-8021.64" + cell $sub $sub$ls180.v:8021$2574 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -107699,10 +107684,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_uart_rx_fifo_level0 connect \B 1'1 - connect \Y $sub$ls180.v:8024$2576_Y + connect \Y $sub$ls180.v:8021$2574_Y end - attribute \src "ls180.v:8059.33-8059.64" - cell $sub $sub$ls180.v:8059$2581 + attribute \src "ls180.v:8056.33-8056.64" + cell $sub $sub$ls180.v:8056$2579 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -107710,10 +107695,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_spi_master_mosi_sel connect \B 1'1 - connect \Y $sub$ls180.v:8059$2581_Y + connect \Y $sub$ls180.v:8056$2579_Y end - attribute \src "ls180.v:8083.30-8083.53" - cell $sub $sub$ls180.v:8083$2584 + attribute \src "ls180.v:8080.30-8080.53" + cell $sub $sub$ls180.v:8080$2582 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -107721,10 +107706,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_pwm0_period connect \B 1'1 - connect \Y $sub$ls180.v:8083$2584_Y + connect \Y $sub$ls180.v:8080$2582_Y end - attribute \src "ls180.v:8097.30-8097.53" - cell $sub $sub$ls180.v:8097$2588 + attribute \src "ls180.v:8094.30-8094.53" + cell $sub $sub$ls180.v:8094$2586 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -107732,10 +107717,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_pwm1_period connect \B 1'1 - connect \Y $sub$ls180.v:8097$2588_Y + connect \Y $sub$ls180.v:8094$2586_Y end - attribute \src "ls180.v:8500.36-8500.70" - cell $sub $sub$ls180.v:8500$2649 + attribute \src "ls180.v:8497.36-8497.70" + cell $sub $sub$ls180.v:8497$2647 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -107743,10 +107728,10 @@ module \ls180 parameter \Y_WIDTH 6 connect \A \main_sdblock2mem_fifo_level connect \B 1'1 - connect \Y $sub$ls180.v:8500$2649_Y + connect \Y $sub$ls180.v:8497$2647_Y end - attribute \src "ls180.v:8586.36-8586.70" - cell $sub $sub$ls180.v:8586$2671 + attribute \src "ls180.v:8583.36-8583.70" + cell $sub $sub$ls180.v:8583$2669 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -107754,10 +107739,10 @@ module \ls180 parameter \Y_WIDTH 6 connect \A \main_sdmem2block_fifo_level connect \B 1'1 - connect \Y $sub$ls180.v:8586$2671_Y + connect \Y $sub$ls180.v:8583$2669_Y end - attribute \src "ls180.v:8607.29-8607.56" - cell $sub $sub$ls180.v:8607$2676 + attribute \src "ls180.v:8604.29-8604.56" + cell $sub $sub$ls180.v:8604$2674 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -107765,10 +107750,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \libresocsim_mosi_sel connect \B 1'1 - connect \Y $sub$ls180.v:8607$2676_Y + connect \Y $sub$ls180.v:8604$2674_Y end - attribute \src "ls180.v:8734.22-8734.42" - cell $sub $sub$ls180.v:8734$2683 + attribute \src "ls180.v:8731.22-8731.42" + cell $sub $sub$ls180.v:8731$2681 parameter \A_SIGNED 0 parameter \A_WIDTH 20 parameter \B_SIGNED 0 @@ -107776,10 +107761,10 @@ module \ls180 parameter \Y_WIDTH 20 connect \A \builder_count connect \B 1'1 - connect \Y $sub$ls180.v:8734$2683_Y + connect \Y $sub$ls180.v:8731$2681_Y end - attribute \src "ls180.v:4816.353-4816.425" - cell $xor $xor$ls180.v:4816$703 + attribute \src "ls180.v:4812.353-4812.425" + cell $xor $xor$ls180.v:4812$702 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -107787,10 +107772,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [39] connect \B \main_sdcore_crc7_inserter_crcreg0 [6] - connect \Y $xor$ls180.v:4816$703_Y + connect \Y $xor$ls180.v:4812$702_Y end - attribute \src "ls180.v:4816.200-4816.272" - cell $xor $xor$ls180.v:4816$704 + attribute \src "ls180.v:4812.200-4812.272" + cell $xor $xor$ls180.v:4812$703 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -107798,21 +107783,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [39] connect \B \main_sdcore_crc7_inserter_crcreg0 [6] - connect \Y $xor$ls180.v:4816$704_Y + connect \Y $xor$ls180.v:4812$703_Y end - attribute \src "ls180.v:4816.160-4816.273" - cell $xor $xor$ls180.v:4816$705 + attribute \src "ls180.v:4812.160-4812.273" + cell $xor $xor$ls180.v:4812$704 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg0 [2] - connect \B $xor$ls180.v:4816$704_Y - connect \Y $xor$ls180.v:4816$705_Y + connect \B $xor$ls180.v:4812$703_Y + connect \Y $xor$ls180.v:4812$704_Y end - attribute \src "ls180.v:4817.353-4817.425" - cell $xor $xor$ls180.v:4817$706 + attribute \src "ls180.v:4813.353-4813.425" + cell $xor $xor$ls180.v:4813$705 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -107820,10 +107805,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [38] connect \B \main_sdcore_crc7_inserter_crcreg1 [6] - connect \Y $xor$ls180.v:4817$706_Y + connect \Y $xor$ls180.v:4813$705_Y end - attribute \src "ls180.v:4817.200-4817.272" - cell $xor $xor$ls180.v:4817$707 + attribute \src "ls180.v:4813.200-4813.272" + cell $xor $xor$ls180.v:4813$706 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -107831,21 +107816,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [38] connect \B \main_sdcore_crc7_inserter_crcreg1 [6] - connect \Y $xor$ls180.v:4817$707_Y + connect \Y $xor$ls180.v:4813$706_Y end - attribute \src "ls180.v:4817.160-4817.273" - cell $xor $xor$ls180.v:4817$708 + attribute \src "ls180.v:4813.160-4813.273" + cell $xor $xor$ls180.v:4813$707 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg1 [2] - connect \B $xor$ls180.v:4817$707_Y - connect \Y $xor$ls180.v:4817$708_Y + connect \B $xor$ls180.v:4813$706_Y + connect \Y $xor$ls180.v:4813$707_Y end - attribute \src "ls180.v:4818.353-4818.425" - cell $xor $xor$ls180.v:4818$709 + attribute \src "ls180.v:4814.353-4814.425" + cell $xor $xor$ls180.v:4814$708 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -107853,10 +107838,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [37] connect \B \main_sdcore_crc7_inserter_crcreg2 [6] - connect \Y $xor$ls180.v:4818$709_Y + connect \Y $xor$ls180.v:4814$708_Y end - attribute \src "ls180.v:4818.200-4818.272" - cell $xor $xor$ls180.v:4818$710 + attribute \src "ls180.v:4814.200-4814.272" + cell $xor $xor$ls180.v:4814$709 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -107864,21 +107849,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [37] connect \B \main_sdcore_crc7_inserter_crcreg2 [6] - connect \Y $xor$ls180.v:4818$710_Y + connect \Y $xor$ls180.v:4814$709_Y end - attribute \src "ls180.v:4818.160-4818.273" - cell $xor $xor$ls180.v:4818$711 + attribute \src "ls180.v:4814.160-4814.273" + cell $xor $xor$ls180.v:4814$710 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg2 [2] - connect \B $xor$ls180.v:4818$710_Y - connect \Y $xor$ls180.v:4818$711_Y + connect \B $xor$ls180.v:4814$709_Y + connect \Y $xor$ls180.v:4814$710_Y end - attribute \src "ls180.v:4819.353-4819.425" - cell $xor $xor$ls180.v:4819$712 + attribute \src "ls180.v:4815.353-4815.425" + cell $xor $xor$ls180.v:4815$711 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -107886,10 +107871,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [36] connect \B \main_sdcore_crc7_inserter_crcreg3 [6] - connect \Y $xor$ls180.v:4819$712_Y + connect \Y $xor$ls180.v:4815$711_Y end - attribute \src "ls180.v:4819.200-4819.272" - cell $xor $xor$ls180.v:4819$713 + attribute \src "ls180.v:4815.200-4815.272" + cell $xor $xor$ls180.v:4815$712 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -107897,21 +107882,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [36] connect \B \main_sdcore_crc7_inserter_crcreg3 [6] - connect \Y $xor$ls180.v:4819$713_Y + connect \Y $xor$ls180.v:4815$712_Y end - attribute \src "ls180.v:4819.160-4819.273" - cell $xor $xor$ls180.v:4819$714 + attribute \src "ls180.v:4815.160-4815.273" + cell $xor $xor$ls180.v:4815$713 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg3 [2] - connect \B $xor$ls180.v:4819$713_Y - connect \Y $xor$ls180.v:4819$714_Y + connect \B $xor$ls180.v:4815$712_Y + connect \Y $xor$ls180.v:4815$713_Y end - attribute \src "ls180.v:4820.353-4820.425" - cell $xor $xor$ls180.v:4820$715 + attribute \src "ls180.v:4816.353-4816.425" + cell $xor $xor$ls180.v:4816$714 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -107919,10 +107904,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [35] connect \B \main_sdcore_crc7_inserter_crcreg4 [6] - connect \Y $xor$ls180.v:4820$715_Y + connect \Y $xor$ls180.v:4816$714_Y end - attribute \src "ls180.v:4820.200-4820.272" - cell $xor $xor$ls180.v:4820$716 + attribute \src "ls180.v:4816.200-4816.272" + cell $xor $xor$ls180.v:4816$715 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -107930,21 +107915,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [35] connect \B \main_sdcore_crc7_inserter_crcreg4 [6] - connect \Y $xor$ls180.v:4820$716_Y + connect \Y $xor$ls180.v:4816$715_Y end - attribute \src "ls180.v:4820.160-4820.273" - cell $xor $xor$ls180.v:4820$717 + attribute \src "ls180.v:4816.160-4816.273" + cell $xor $xor$ls180.v:4816$716 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg4 [2] - connect \B $xor$ls180.v:4820$716_Y - connect \Y $xor$ls180.v:4820$717_Y + connect \B $xor$ls180.v:4816$715_Y + connect \Y $xor$ls180.v:4816$716_Y end - attribute \src "ls180.v:4821.353-4821.425" - cell $xor $xor$ls180.v:4821$718 + attribute \src "ls180.v:4817.353-4817.425" + cell $xor $xor$ls180.v:4817$717 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -107952,10 +107937,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [34] connect \B \main_sdcore_crc7_inserter_crcreg5 [6] - connect \Y $xor$ls180.v:4821$718_Y + connect \Y $xor$ls180.v:4817$717_Y end - attribute \src "ls180.v:4821.200-4821.272" - cell $xor $xor$ls180.v:4821$719 + attribute \src "ls180.v:4817.200-4817.272" + cell $xor $xor$ls180.v:4817$718 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -107963,21 +107948,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [34] connect \B \main_sdcore_crc7_inserter_crcreg5 [6] - connect \Y $xor$ls180.v:4821$719_Y + connect \Y $xor$ls180.v:4817$718_Y end - attribute \src "ls180.v:4821.160-4821.273" - cell $xor $xor$ls180.v:4821$720 + attribute \src "ls180.v:4817.160-4817.273" + cell $xor $xor$ls180.v:4817$719 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg5 [2] - connect \B $xor$ls180.v:4821$719_Y - connect \Y $xor$ls180.v:4821$720_Y + connect \B $xor$ls180.v:4817$718_Y + connect \Y $xor$ls180.v:4817$719_Y end - attribute \src "ls180.v:4822.353-4822.425" - cell $xor $xor$ls180.v:4822$721 + attribute \src "ls180.v:4818.353-4818.425" + cell $xor $xor$ls180.v:4818$720 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -107985,10 +107970,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [33] connect \B \main_sdcore_crc7_inserter_crcreg6 [6] - connect \Y $xor$ls180.v:4822$721_Y + connect \Y $xor$ls180.v:4818$720_Y end - attribute \src "ls180.v:4822.200-4822.272" - cell $xor $xor$ls180.v:4822$722 + attribute \src "ls180.v:4818.200-4818.272" + cell $xor $xor$ls180.v:4818$721 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -107996,21 +107981,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [33] connect \B \main_sdcore_crc7_inserter_crcreg6 [6] - connect \Y $xor$ls180.v:4822$722_Y + connect \Y $xor$ls180.v:4818$721_Y end - attribute \src "ls180.v:4822.160-4822.273" - cell $xor $xor$ls180.v:4822$723 + attribute \src "ls180.v:4818.160-4818.273" + cell $xor $xor$ls180.v:4818$722 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg6 [2] - connect \B $xor$ls180.v:4822$722_Y - connect \Y $xor$ls180.v:4822$723_Y + connect \B $xor$ls180.v:4818$721_Y + connect \Y $xor$ls180.v:4818$722_Y end - attribute \src "ls180.v:4823.353-4823.425" - cell $xor $xor$ls180.v:4823$724 + attribute \src "ls180.v:4819.353-4819.425" + cell $xor $xor$ls180.v:4819$723 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108018,10 +108003,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [32] connect \B \main_sdcore_crc7_inserter_crcreg7 [6] - connect \Y $xor$ls180.v:4823$724_Y + connect \Y $xor$ls180.v:4819$723_Y end - attribute \src "ls180.v:4823.200-4823.272" - cell $xor $xor$ls180.v:4823$725 + attribute \src "ls180.v:4819.200-4819.272" + cell $xor $xor$ls180.v:4819$724 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108029,21 +108014,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [32] connect \B \main_sdcore_crc7_inserter_crcreg7 [6] - connect \Y $xor$ls180.v:4823$725_Y + connect \Y $xor$ls180.v:4819$724_Y end - attribute \src "ls180.v:4823.160-4823.273" - cell $xor $xor$ls180.v:4823$726 + attribute \src "ls180.v:4819.160-4819.273" + cell $xor $xor$ls180.v:4819$725 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg7 [2] - connect \B $xor$ls180.v:4823$725_Y - connect \Y $xor$ls180.v:4823$726_Y + connect \B $xor$ls180.v:4819$724_Y + connect \Y $xor$ls180.v:4819$725_Y end - attribute \src "ls180.v:4824.353-4824.425" - cell $xor $xor$ls180.v:4824$727 + attribute \src "ls180.v:4820.353-4820.425" + cell $xor $xor$ls180.v:4820$726 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108051,10 +108036,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [31] connect \B \main_sdcore_crc7_inserter_crcreg8 [6] - connect \Y $xor$ls180.v:4824$727_Y + connect \Y $xor$ls180.v:4820$726_Y end - attribute \src "ls180.v:4824.200-4824.272" - cell $xor $xor$ls180.v:4824$728 + attribute \src "ls180.v:4820.200-4820.272" + cell $xor $xor$ls180.v:4820$727 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108062,21 +108047,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [31] connect \B \main_sdcore_crc7_inserter_crcreg8 [6] - connect \Y $xor$ls180.v:4824$728_Y + connect \Y $xor$ls180.v:4820$727_Y end - attribute \src "ls180.v:4824.160-4824.273" - cell $xor $xor$ls180.v:4824$729 + attribute \src "ls180.v:4820.160-4820.273" + cell $xor $xor$ls180.v:4820$728 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg8 [2] - connect \B $xor$ls180.v:4824$728_Y - connect \Y $xor$ls180.v:4824$729_Y + connect \B $xor$ls180.v:4820$727_Y + connect \Y $xor$ls180.v:4820$728_Y end - attribute \src "ls180.v:4825.354-4825.426" - cell $xor $xor$ls180.v:4825$730 + attribute \src "ls180.v:4821.354-4821.426" + cell $xor $xor$ls180.v:4821$729 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108084,10 +108069,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [30] connect \B \main_sdcore_crc7_inserter_crcreg9 [6] - connect \Y $xor$ls180.v:4825$730_Y + connect \Y $xor$ls180.v:4821$729_Y end - attribute \src "ls180.v:4825.201-4825.273" - cell $xor $xor$ls180.v:4825$731 + attribute \src "ls180.v:4821.201-4821.273" + cell $xor $xor$ls180.v:4821$730 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108095,21 +108080,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [30] connect \B \main_sdcore_crc7_inserter_crcreg9 [6] - connect \Y $xor$ls180.v:4825$731_Y + connect \Y $xor$ls180.v:4821$730_Y end - attribute \src "ls180.v:4825.161-4825.274" - cell $xor $xor$ls180.v:4825$732 + attribute \src "ls180.v:4821.161-4821.274" + cell $xor $xor$ls180.v:4821$731 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg9 [2] - connect \B $xor$ls180.v:4825$731_Y - connect \Y $xor$ls180.v:4825$732_Y + connect \B $xor$ls180.v:4821$730_Y + connect \Y $xor$ls180.v:4821$731_Y end - attribute \src "ls180.v:4826.361-4826.434" - cell $xor $xor$ls180.v:4826$733 + attribute \src "ls180.v:4822.361-4822.434" + cell $xor $xor$ls180.v:4822$732 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108117,10 +108102,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [29] connect \B \main_sdcore_crc7_inserter_crcreg10 [6] - connect \Y $xor$ls180.v:4826$733_Y + connect \Y $xor$ls180.v:4822$732_Y end - attribute \src "ls180.v:4826.205-4826.278" - cell $xor $xor$ls180.v:4826$734 + attribute \src "ls180.v:4822.205-4822.278" + cell $xor $xor$ls180.v:4822$733 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108128,21 +108113,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [29] connect \B \main_sdcore_crc7_inserter_crcreg10 [6] - connect \Y $xor$ls180.v:4826$734_Y + connect \Y $xor$ls180.v:4822$733_Y end - attribute \src "ls180.v:4826.164-4826.279" - cell $xor $xor$ls180.v:4826$735 + attribute \src "ls180.v:4822.164-4822.279" + cell $xor $xor$ls180.v:4822$734 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg10 [2] - connect \B $xor$ls180.v:4826$734_Y - connect \Y $xor$ls180.v:4826$735_Y + connect \B $xor$ls180.v:4822$733_Y + connect \Y $xor$ls180.v:4822$734_Y end - attribute \src "ls180.v:4827.361-4827.434" - cell $xor $xor$ls180.v:4827$736 + attribute \src "ls180.v:4823.361-4823.434" + cell $xor $xor$ls180.v:4823$735 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108150,10 +108135,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [28] connect \B \main_sdcore_crc7_inserter_crcreg11 [6] - connect \Y $xor$ls180.v:4827$736_Y + connect \Y $xor$ls180.v:4823$735_Y end - attribute \src "ls180.v:4827.205-4827.278" - cell $xor $xor$ls180.v:4827$737 + attribute \src "ls180.v:4823.205-4823.278" + cell $xor $xor$ls180.v:4823$736 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108161,21 +108146,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [28] connect \B \main_sdcore_crc7_inserter_crcreg11 [6] - connect \Y $xor$ls180.v:4827$737_Y + connect \Y $xor$ls180.v:4823$736_Y end - attribute \src "ls180.v:4827.164-4827.279" - cell $xor $xor$ls180.v:4827$738 + attribute \src "ls180.v:4823.164-4823.279" + cell $xor $xor$ls180.v:4823$737 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg11 [2] - connect \B $xor$ls180.v:4827$737_Y - connect \Y $xor$ls180.v:4827$738_Y + connect \B $xor$ls180.v:4823$736_Y + connect \Y $xor$ls180.v:4823$737_Y end - attribute \src "ls180.v:4828.361-4828.434" - cell $xor $xor$ls180.v:4828$739 + attribute \src "ls180.v:4824.361-4824.434" + cell $xor $xor$ls180.v:4824$738 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108183,10 +108168,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [27] connect \B \main_sdcore_crc7_inserter_crcreg12 [6] - connect \Y $xor$ls180.v:4828$739_Y + connect \Y $xor$ls180.v:4824$738_Y end - attribute \src "ls180.v:4828.205-4828.278" - cell $xor $xor$ls180.v:4828$740 + attribute \src "ls180.v:4824.205-4824.278" + cell $xor $xor$ls180.v:4824$739 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108194,21 +108179,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [27] connect \B \main_sdcore_crc7_inserter_crcreg12 [6] - connect \Y $xor$ls180.v:4828$740_Y + connect \Y $xor$ls180.v:4824$739_Y end - attribute \src "ls180.v:4828.164-4828.279" - cell $xor $xor$ls180.v:4828$741 + attribute \src "ls180.v:4824.164-4824.279" + cell $xor $xor$ls180.v:4824$740 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg12 [2] - connect \B $xor$ls180.v:4828$740_Y - connect \Y $xor$ls180.v:4828$741_Y + connect \B $xor$ls180.v:4824$739_Y + connect \Y $xor$ls180.v:4824$740_Y end - attribute \src "ls180.v:4829.361-4829.434" - cell $xor $xor$ls180.v:4829$742 + attribute \src "ls180.v:4825.361-4825.434" + cell $xor $xor$ls180.v:4825$741 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108216,10 +108201,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [26] connect \B \main_sdcore_crc7_inserter_crcreg13 [6] - connect \Y $xor$ls180.v:4829$742_Y + connect \Y $xor$ls180.v:4825$741_Y end - attribute \src "ls180.v:4829.205-4829.278" - cell $xor $xor$ls180.v:4829$743 + attribute \src "ls180.v:4825.205-4825.278" + cell $xor $xor$ls180.v:4825$742 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108227,21 +108212,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [26] connect \B \main_sdcore_crc7_inserter_crcreg13 [6] - connect \Y $xor$ls180.v:4829$743_Y + connect \Y $xor$ls180.v:4825$742_Y end - attribute \src "ls180.v:4829.164-4829.279" - cell $xor $xor$ls180.v:4829$744 + attribute \src "ls180.v:4825.164-4825.279" + cell $xor $xor$ls180.v:4825$743 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg13 [2] - connect \B $xor$ls180.v:4829$743_Y - connect \Y $xor$ls180.v:4829$744_Y + connect \B $xor$ls180.v:4825$742_Y + connect \Y $xor$ls180.v:4825$743_Y end - attribute \src "ls180.v:4830.361-4830.434" - cell $xor $xor$ls180.v:4830$745 + attribute \src "ls180.v:4826.361-4826.434" + cell $xor $xor$ls180.v:4826$744 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108249,10 +108234,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [25] connect \B \main_sdcore_crc7_inserter_crcreg14 [6] - connect \Y $xor$ls180.v:4830$745_Y + connect \Y $xor$ls180.v:4826$744_Y end - attribute \src "ls180.v:4830.205-4830.278" - cell $xor $xor$ls180.v:4830$746 + attribute \src "ls180.v:4826.205-4826.278" + cell $xor $xor$ls180.v:4826$745 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108260,21 +108245,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [25] connect \B \main_sdcore_crc7_inserter_crcreg14 [6] - connect \Y $xor$ls180.v:4830$746_Y + connect \Y $xor$ls180.v:4826$745_Y end - attribute \src "ls180.v:4830.164-4830.279" - cell $xor $xor$ls180.v:4830$747 + attribute \src "ls180.v:4826.164-4826.279" + cell $xor $xor$ls180.v:4826$746 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg14 [2] - connect \B $xor$ls180.v:4830$746_Y - connect \Y $xor$ls180.v:4830$747_Y + connect \B $xor$ls180.v:4826$745_Y + connect \Y $xor$ls180.v:4826$746_Y end - attribute \src "ls180.v:4831.361-4831.434" - cell $xor $xor$ls180.v:4831$748 + attribute \src "ls180.v:4827.361-4827.434" + cell $xor $xor$ls180.v:4827$747 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108282,10 +108267,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [24] connect \B \main_sdcore_crc7_inserter_crcreg15 [6] - connect \Y $xor$ls180.v:4831$748_Y + connect \Y $xor$ls180.v:4827$747_Y end - attribute \src "ls180.v:4831.205-4831.278" - cell $xor $xor$ls180.v:4831$749 + attribute \src "ls180.v:4827.205-4827.278" + cell $xor $xor$ls180.v:4827$748 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108293,21 +108278,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [24] connect \B \main_sdcore_crc7_inserter_crcreg15 [6] - connect \Y $xor$ls180.v:4831$749_Y + connect \Y $xor$ls180.v:4827$748_Y end - attribute \src "ls180.v:4831.164-4831.279" - cell $xor $xor$ls180.v:4831$750 + attribute \src "ls180.v:4827.164-4827.279" + cell $xor $xor$ls180.v:4827$749 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg15 [2] - connect \B $xor$ls180.v:4831$749_Y - connect \Y $xor$ls180.v:4831$750_Y + connect \B $xor$ls180.v:4827$748_Y + connect \Y $xor$ls180.v:4827$749_Y end - attribute \src "ls180.v:4832.361-4832.434" - cell $xor $xor$ls180.v:4832$751 + attribute \src "ls180.v:4828.361-4828.434" + cell $xor $xor$ls180.v:4828$750 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108315,10 +108300,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [23] connect \B \main_sdcore_crc7_inserter_crcreg16 [6] - connect \Y $xor$ls180.v:4832$751_Y + connect \Y $xor$ls180.v:4828$750_Y end - attribute \src "ls180.v:4832.205-4832.278" - cell $xor $xor$ls180.v:4832$752 + attribute \src "ls180.v:4828.205-4828.278" + cell $xor $xor$ls180.v:4828$751 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108326,21 +108311,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [23] connect \B \main_sdcore_crc7_inserter_crcreg16 [6] - connect \Y $xor$ls180.v:4832$752_Y + connect \Y $xor$ls180.v:4828$751_Y end - attribute \src "ls180.v:4832.164-4832.279" - cell $xor $xor$ls180.v:4832$753 + attribute \src "ls180.v:4828.164-4828.279" + cell $xor $xor$ls180.v:4828$752 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg16 [2] - connect \B $xor$ls180.v:4832$752_Y - connect \Y $xor$ls180.v:4832$753_Y + connect \B $xor$ls180.v:4828$751_Y + connect \Y $xor$ls180.v:4828$752_Y end - attribute \src "ls180.v:4833.361-4833.434" - cell $xor $xor$ls180.v:4833$754 + attribute \src "ls180.v:4829.361-4829.434" + cell $xor $xor$ls180.v:4829$753 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108348,10 +108333,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [22] connect \B \main_sdcore_crc7_inserter_crcreg17 [6] - connect \Y $xor$ls180.v:4833$754_Y + connect \Y $xor$ls180.v:4829$753_Y end - attribute \src "ls180.v:4833.205-4833.278" - cell $xor $xor$ls180.v:4833$755 + attribute \src "ls180.v:4829.205-4829.278" + cell $xor $xor$ls180.v:4829$754 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108359,21 +108344,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [22] connect \B \main_sdcore_crc7_inserter_crcreg17 [6] - connect \Y $xor$ls180.v:4833$755_Y + connect \Y $xor$ls180.v:4829$754_Y end - attribute \src "ls180.v:4833.164-4833.279" - cell $xor $xor$ls180.v:4833$756 + attribute \src "ls180.v:4829.164-4829.279" + cell $xor $xor$ls180.v:4829$755 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg17 [2] - connect \B $xor$ls180.v:4833$755_Y - connect \Y $xor$ls180.v:4833$756_Y + connect \B $xor$ls180.v:4829$754_Y + connect \Y $xor$ls180.v:4829$755_Y end - attribute \src "ls180.v:4834.361-4834.434" - cell $xor $xor$ls180.v:4834$757 + attribute \src "ls180.v:4830.361-4830.434" + cell $xor $xor$ls180.v:4830$756 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108381,10 +108366,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [21] connect \B \main_sdcore_crc7_inserter_crcreg18 [6] - connect \Y $xor$ls180.v:4834$757_Y + connect \Y $xor$ls180.v:4830$756_Y end - attribute \src "ls180.v:4834.205-4834.278" - cell $xor $xor$ls180.v:4834$758 + attribute \src "ls180.v:4830.205-4830.278" + cell $xor $xor$ls180.v:4830$757 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108392,21 +108377,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [21] connect \B \main_sdcore_crc7_inserter_crcreg18 [6] - connect \Y $xor$ls180.v:4834$758_Y + connect \Y $xor$ls180.v:4830$757_Y end - attribute \src "ls180.v:4834.164-4834.279" - cell $xor $xor$ls180.v:4834$759 + attribute \src "ls180.v:4830.164-4830.279" + cell $xor $xor$ls180.v:4830$758 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg18 [2] - connect \B $xor$ls180.v:4834$758_Y - connect \Y $xor$ls180.v:4834$759_Y + connect \B $xor$ls180.v:4830$757_Y + connect \Y $xor$ls180.v:4830$758_Y end - attribute \src "ls180.v:4835.361-4835.434" - cell $xor $xor$ls180.v:4835$760 + attribute \src "ls180.v:4831.361-4831.434" + cell $xor $xor$ls180.v:4831$759 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108414,10 +108399,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [20] connect \B \main_sdcore_crc7_inserter_crcreg19 [6] - connect \Y $xor$ls180.v:4835$760_Y + connect \Y $xor$ls180.v:4831$759_Y end - attribute \src "ls180.v:4835.205-4835.278" - cell $xor $xor$ls180.v:4835$761 + attribute \src "ls180.v:4831.205-4831.278" + cell $xor $xor$ls180.v:4831$760 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108425,21 +108410,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [20] connect \B \main_sdcore_crc7_inserter_crcreg19 [6] - connect \Y $xor$ls180.v:4835$761_Y + connect \Y $xor$ls180.v:4831$760_Y end - attribute \src "ls180.v:4835.164-4835.279" - cell $xor $xor$ls180.v:4835$762 + attribute \src "ls180.v:4831.164-4831.279" + cell $xor $xor$ls180.v:4831$761 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg19 [2] - connect \B $xor$ls180.v:4835$761_Y - connect \Y $xor$ls180.v:4835$762_Y + connect \B $xor$ls180.v:4831$760_Y + connect \Y $xor$ls180.v:4831$761_Y end - attribute \src "ls180.v:4836.361-4836.434" - cell $xor $xor$ls180.v:4836$763 + attribute \src "ls180.v:4832.361-4832.434" + cell $xor $xor$ls180.v:4832$762 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108447,10 +108432,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [19] connect \B \main_sdcore_crc7_inserter_crcreg20 [6] - connect \Y $xor$ls180.v:4836$763_Y + connect \Y $xor$ls180.v:4832$762_Y end - attribute \src "ls180.v:4836.205-4836.278" - cell $xor $xor$ls180.v:4836$764 + attribute \src "ls180.v:4832.205-4832.278" + cell $xor $xor$ls180.v:4832$763 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108458,21 +108443,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [19] connect \B \main_sdcore_crc7_inserter_crcreg20 [6] - connect \Y $xor$ls180.v:4836$764_Y + connect \Y $xor$ls180.v:4832$763_Y end - attribute \src "ls180.v:4836.164-4836.279" - cell $xor $xor$ls180.v:4836$765 + attribute \src "ls180.v:4832.164-4832.279" + cell $xor $xor$ls180.v:4832$764 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg20 [2] - connect \B $xor$ls180.v:4836$764_Y - connect \Y $xor$ls180.v:4836$765_Y + connect \B $xor$ls180.v:4832$763_Y + connect \Y $xor$ls180.v:4832$764_Y end - attribute \src "ls180.v:4837.361-4837.434" - cell $xor $xor$ls180.v:4837$766 + attribute \src "ls180.v:4833.361-4833.434" + cell $xor $xor$ls180.v:4833$765 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108480,10 +108465,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [18] connect \B \main_sdcore_crc7_inserter_crcreg21 [6] - connect \Y $xor$ls180.v:4837$766_Y + connect \Y $xor$ls180.v:4833$765_Y end - attribute \src "ls180.v:4837.205-4837.278" - cell $xor $xor$ls180.v:4837$767 + attribute \src "ls180.v:4833.205-4833.278" + cell $xor $xor$ls180.v:4833$766 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108491,21 +108476,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [18] connect \B \main_sdcore_crc7_inserter_crcreg21 [6] - connect \Y $xor$ls180.v:4837$767_Y + connect \Y $xor$ls180.v:4833$766_Y end - attribute \src "ls180.v:4837.164-4837.279" - cell $xor $xor$ls180.v:4837$768 + attribute \src "ls180.v:4833.164-4833.279" + cell $xor $xor$ls180.v:4833$767 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg21 [2] - connect \B $xor$ls180.v:4837$767_Y - connect \Y $xor$ls180.v:4837$768_Y + connect \B $xor$ls180.v:4833$766_Y + connect \Y $xor$ls180.v:4833$767_Y end - attribute \src "ls180.v:4838.361-4838.434" - cell $xor $xor$ls180.v:4838$769 + attribute \src "ls180.v:4834.361-4834.434" + cell $xor $xor$ls180.v:4834$768 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108513,10 +108498,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [17] connect \B \main_sdcore_crc7_inserter_crcreg22 [6] - connect \Y $xor$ls180.v:4838$769_Y + connect \Y $xor$ls180.v:4834$768_Y end - attribute \src "ls180.v:4838.205-4838.278" - cell $xor $xor$ls180.v:4838$770 + attribute \src "ls180.v:4834.205-4834.278" + cell $xor $xor$ls180.v:4834$769 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108524,21 +108509,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [17] connect \B \main_sdcore_crc7_inserter_crcreg22 [6] - connect \Y $xor$ls180.v:4838$770_Y + connect \Y $xor$ls180.v:4834$769_Y end - attribute \src "ls180.v:4838.164-4838.279" - cell $xor $xor$ls180.v:4838$771 + attribute \src "ls180.v:4834.164-4834.279" + cell $xor $xor$ls180.v:4834$770 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg22 [2] - connect \B $xor$ls180.v:4838$770_Y - connect \Y $xor$ls180.v:4838$771_Y + connect \B $xor$ls180.v:4834$769_Y + connect \Y $xor$ls180.v:4834$770_Y end - attribute \src "ls180.v:4839.361-4839.434" - cell $xor $xor$ls180.v:4839$772 + attribute \src "ls180.v:4835.361-4835.434" + cell $xor $xor$ls180.v:4835$771 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108546,10 +108531,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [16] connect \B \main_sdcore_crc7_inserter_crcreg23 [6] - connect \Y $xor$ls180.v:4839$772_Y + connect \Y $xor$ls180.v:4835$771_Y end - attribute \src "ls180.v:4839.205-4839.278" - cell $xor $xor$ls180.v:4839$773 + attribute \src "ls180.v:4835.205-4835.278" + cell $xor $xor$ls180.v:4835$772 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108557,21 +108542,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [16] connect \B \main_sdcore_crc7_inserter_crcreg23 [6] - connect \Y $xor$ls180.v:4839$773_Y + connect \Y $xor$ls180.v:4835$772_Y end - attribute \src "ls180.v:4839.164-4839.279" - cell $xor $xor$ls180.v:4839$774 + attribute \src "ls180.v:4835.164-4835.279" + cell $xor $xor$ls180.v:4835$773 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg23 [2] - connect \B $xor$ls180.v:4839$773_Y - connect \Y $xor$ls180.v:4839$774_Y + connect \B $xor$ls180.v:4835$772_Y + connect \Y $xor$ls180.v:4835$773_Y end - attribute \src "ls180.v:4840.361-4840.434" - cell $xor $xor$ls180.v:4840$775 + attribute \src "ls180.v:4836.361-4836.434" + cell $xor $xor$ls180.v:4836$774 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108579,10 +108564,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [15] connect \B \main_sdcore_crc7_inserter_crcreg24 [6] - connect \Y $xor$ls180.v:4840$775_Y + connect \Y $xor$ls180.v:4836$774_Y end - attribute \src "ls180.v:4840.205-4840.278" - cell $xor $xor$ls180.v:4840$776 + attribute \src "ls180.v:4836.205-4836.278" + cell $xor $xor$ls180.v:4836$775 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108590,21 +108575,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [15] connect \B \main_sdcore_crc7_inserter_crcreg24 [6] - connect \Y $xor$ls180.v:4840$776_Y + connect \Y $xor$ls180.v:4836$775_Y end - attribute \src "ls180.v:4840.164-4840.279" - cell $xor $xor$ls180.v:4840$777 + attribute \src "ls180.v:4836.164-4836.279" + cell $xor $xor$ls180.v:4836$776 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg24 [2] - connect \B $xor$ls180.v:4840$776_Y - connect \Y $xor$ls180.v:4840$777_Y + connect \B $xor$ls180.v:4836$775_Y + connect \Y $xor$ls180.v:4836$776_Y end - attribute \src "ls180.v:4841.361-4841.434" - cell $xor $xor$ls180.v:4841$778 + attribute \src "ls180.v:4837.361-4837.434" + cell $xor $xor$ls180.v:4837$777 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108612,10 +108597,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [14] connect \B \main_sdcore_crc7_inserter_crcreg25 [6] - connect \Y $xor$ls180.v:4841$778_Y + connect \Y $xor$ls180.v:4837$777_Y end - attribute \src "ls180.v:4841.205-4841.278" - cell $xor $xor$ls180.v:4841$779 + attribute \src "ls180.v:4837.205-4837.278" + cell $xor $xor$ls180.v:4837$778 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108623,21 +108608,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [14] connect \B \main_sdcore_crc7_inserter_crcreg25 [6] - connect \Y $xor$ls180.v:4841$779_Y + connect \Y $xor$ls180.v:4837$778_Y end - attribute \src "ls180.v:4841.164-4841.279" - cell $xor $xor$ls180.v:4841$780 + attribute \src "ls180.v:4837.164-4837.279" + cell $xor $xor$ls180.v:4837$779 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg25 [2] - connect \B $xor$ls180.v:4841$779_Y - connect \Y $xor$ls180.v:4841$780_Y + connect \B $xor$ls180.v:4837$778_Y + connect \Y $xor$ls180.v:4837$779_Y end - attribute \src "ls180.v:4842.361-4842.434" - cell $xor $xor$ls180.v:4842$781 + attribute \src "ls180.v:4838.361-4838.434" + cell $xor $xor$ls180.v:4838$780 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108645,10 +108630,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [13] connect \B \main_sdcore_crc7_inserter_crcreg26 [6] - connect \Y $xor$ls180.v:4842$781_Y + connect \Y $xor$ls180.v:4838$780_Y end - attribute \src "ls180.v:4842.205-4842.278" - cell $xor $xor$ls180.v:4842$782 + attribute \src "ls180.v:4838.205-4838.278" + cell $xor $xor$ls180.v:4838$781 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108656,21 +108641,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [13] connect \B \main_sdcore_crc7_inserter_crcreg26 [6] - connect \Y $xor$ls180.v:4842$782_Y + connect \Y $xor$ls180.v:4838$781_Y end - attribute \src "ls180.v:4842.164-4842.279" - cell $xor $xor$ls180.v:4842$783 + attribute \src "ls180.v:4838.164-4838.279" + cell $xor $xor$ls180.v:4838$782 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg26 [2] - connect \B $xor$ls180.v:4842$782_Y - connect \Y $xor$ls180.v:4842$783_Y + connect \B $xor$ls180.v:4838$781_Y + connect \Y $xor$ls180.v:4838$782_Y end - attribute \src "ls180.v:4843.361-4843.434" - cell $xor $xor$ls180.v:4843$784 + attribute \src "ls180.v:4839.361-4839.434" + cell $xor $xor$ls180.v:4839$783 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108678,10 +108663,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [12] connect \B \main_sdcore_crc7_inserter_crcreg27 [6] - connect \Y $xor$ls180.v:4843$784_Y + connect \Y $xor$ls180.v:4839$783_Y end - attribute \src "ls180.v:4843.205-4843.278" - cell $xor $xor$ls180.v:4843$785 + attribute \src "ls180.v:4839.205-4839.278" + cell $xor $xor$ls180.v:4839$784 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108689,21 +108674,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [12] connect \B \main_sdcore_crc7_inserter_crcreg27 [6] - connect \Y $xor$ls180.v:4843$785_Y + connect \Y $xor$ls180.v:4839$784_Y end - attribute \src "ls180.v:4843.164-4843.279" - cell $xor $xor$ls180.v:4843$786 + attribute \src "ls180.v:4839.164-4839.279" + cell $xor $xor$ls180.v:4839$785 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg27 [2] - connect \B $xor$ls180.v:4843$785_Y - connect \Y $xor$ls180.v:4843$786_Y + connect \B $xor$ls180.v:4839$784_Y + connect \Y $xor$ls180.v:4839$785_Y end - attribute \src "ls180.v:4844.361-4844.434" - cell $xor $xor$ls180.v:4844$787 + attribute \src "ls180.v:4840.361-4840.434" + cell $xor $xor$ls180.v:4840$786 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108711,10 +108696,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [11] connect \B \main_sdcore_crc7_inserter_crcreg28 [6] - connect \Y $xor$ls180.v:4844$787_Y + connect \Y $xor$ls180.v:4840$786_Y end - attribute \src "ls180.v:4844.205-4844.278" - cell $xor $xor$ls180.v:4844$788 + attribute \src "ls180.v:4840.205-4840.278" + cell $xor $xor$ls180.v:4840$787 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108722,21 +108707,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [11] connect \B \main_sdcore_crc7_inserter_crcreg28 [6] - connect \Y $xor$ls180.v:4844$788_Y + connect \Y $xor$ls180.v:4840$787_Y end - attribute \src "ls180.v:4844.164-4844.279" - cell $xor $xor$ls180.v:4844$789 + attribute \src "ls180.v:4840.164-4840.279" + cell $xor $xor$ls180.v:4840$788 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg28 [2] - connect \B $xor$ls180.v:4844$788_Y - connect \Y $xor$ls180.v:4844$789_Y + connect \B $xor$ls180.v:4840$787_Y + connect \Y $xor$ls180.v:4840$788_Y end - attribute \src "ls180.v:4845.361-4845.434" - cell $xor $xor$ls180.v:4845$790 + attribute \src "ls180.v:4841.361-4841.434" + cell $xor $xor$ls180.v:4841$789 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108744,10 +108729,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [10] connect \B \main_sdcore_crc7_inserter_crcreg29 [6] - connect \Y $xor$ls180.v:4845$790_Y + connect \Y $xor$ls180.v:4841$789_Y end - attribute \src "ls180.v:4845.205-4845.278" - cell $xor $xor$ls180.v:4845$791 + attribute \src "ls180.v:4841.205-4841.278" + cell $xor $xor$ls180.v:4841$790 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108755,21 +108740,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [10] connect \B \main_sdcore_crc7_inserter_crcreg29 [6] - connect \Y $xor$ls180.v:4845$791_Y + connect \Y $xor$ls180.v:4841$790_Y end - attribute \src "ls180.v:4845.164-4845.279" - cell $xor $xor$ls180.v:4845$792 + attribute \src "ls180.v:4841.164-4841.279" + cell $xor $xor$ls180.v:4841$791 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg29 [2] - connect \B $xor$ls180.v:4845$791_Y - connect \Y $xor$ls180.v:4845$792_Y + connect \B $xor$ls180.v:4841$790_Y + connect \Y $xor$ls180.v:4841$791_Y end - attribute \src "ls180.v:4846.360-4846.432" - cell $xor $xor$ls180.v:4846$793 + attribute \src "ls180.v:4842.360-4842.432" + cell $xor $xor$ls180.v:4842$792 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108777,10 +108762,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [9] connect \B \main_sdcore_crc7_inserter_crcreg30 [6] - connect \Y $xor$ls180.v:4846$793_Y + connect \Y $xor$ls180.v:4842$792_Y end - attribute \src "ls180.v:4846.205-4846.277" - cell $xor $xor$ls180.v:4846$794 + attribute \src "ls180.v:4842.205-4842.277" + cell $xor $xor$ls180.v:4842$793 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108788,21 +108773,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [9] connect \B \main_sdcore_crc7_inserter_crcreg30 [6] - connect \Y $xor$ls180.v:4846$794_Y + connect \Y $xor$ls180.v:4842$793_Y end - attribute \src "ls180.v:4846.164-4846.278" - cell $xor $xor$ls180.v:4846$795 + attribute \src "ls180.v:4842.164-4842.278" + cell $xor $xor$ls180.v:4842$794 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg30 [2] - connect \B $xor$ls180.v:4846$794_Y - connect \Y $xor$ls180.v:4846$795_Y + connect \B $xor$ls180.v:4842$793_Y + connect \Y $xor$ls180.v:4842$794_Y end - attribute \src "ls180.v:4847.360-4847.432" - cell $xor $xor$ls180.v:4847$796 + attribute \src "ls180.v:4843.360-4843.432" + cell $xor $xor$ls180.v:4843$795 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108810,10 +108795,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [8] connect \B \main_sdcore_crc7_inserter_crcreg31 [6] - connect \Y $xor$ls180.v:4847$796_Y + connect \Y $xor$ls180.v:4843$795_Y end - attribute \src "ls180.v:4847.205-4847.277" - cell $xor $xor$ls180.v:4847$797 + attribute \src "ls180.v:4843.205-4843.277" + cell $xor $xor$ls180.v:4843$796 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108821,21 +108806,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [8] connect \B \main_sdcore_crc7_inserter_crcreg31 [6] - connect \Y $xor$ls180.v:4847$797_Y + connect \Y $xor$ls180.v:4843$796_Y end - attribute \src "ls180.v:4847.164-4847.278" - cell $xor $xor$ls180.v:4847$798 + attribute \src "ls180.v:4843.164-4843.278" + cell $xor $xor$ls180.v:4843$797 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg31 [2] - connect \B $xor$ls180.v:4847$797_Y - connect \Y $xor$ls180.v:4847$798_Y + connect \B $xor$ls180.v:4843$796_Y + connect \Y $xor$ls180.v:4843$797_Y end - attribute \src "ls180.v:4848.360-4848.432" - cell $xor $xor$ls180.v:4848$799 + attribute \src "ls180.v:4844.360-4844.432" + cell $xor $xor$ls180.v:4844$798 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108843,10 +108828,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [7] connect \B \main_sdcore_crc7_inserter_crcreg32 [6] - connect \Y $xor$ls180.v:4848$799_Y + connect \Y $xor$ls180.v:4844$798_Y end - attribute \src "ls180.v:4848.205-4848.277" - cell $xor $xor$ls180.v:4848$800 + attribute \src "ls180.v:4844.205-4844.277" + cell $xor $xor$ls180.v:4844$799 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108854,21 +108839,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [7] connect \B \main_sdcore_crc7_inserter_crcreg32 [6] - connect \Y $xor$ls180.v:4848$800_Y + connect \Y $xor$ls180.v:4844$799_Y end - attribute \src "ls180.v:4848.164-4848.278" - cell $xor $xor$ls180.v:4848$801 + attribute \src "ls180.v:4844.164-4844.278" + cell $xor $xor$ls180.v:4844$800 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg32 [2] - connect \B $xor$ls180.v:4848$800_Y - connect \Y $xor$ls180.v:4848$801_Y + connect \B $xor$ls180.v:4844$799_Y + connect \Y $xor$ls180.v:4844$800_Y end - attribute \src "ls180.v:4849.360-4849.432" - cell $xor $xor$ls180.v:4849$802 + attribute \src "ls180.v:4845.360-4845.432" + cell $xor $xor$ls180.v:4845$801 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108876,10 +108861,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [6] connect \B \main_sdcore_crc7_inserter_crcreg33 [6] - connect \Y $xor$ls180.v:4849$802_Y + connect \Y $xor$ls180.v:4845$801_Y end - attribute \src "ls180.v:4849.205-4849.277" - cell $xor $xor$ls180.v:4849$803 + attribute \src "ls180.v:4845.205-4845.277" + cell $xor $xor$ls180.v:4845$802 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108887,21 +108872,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [6] connect \B \main_sdcore_crc7_inserter_crcreg33 [6] - connect \Y $xor$ls180.v:4849$803_Y + connect \Y $xor$ls180.v:4845$802_Y end - attribute \src "ls180.v:4849.164-4849.278" - cell $xor $xor$ls180.v:4849$804 + attribute \src "ls180.v:4845.164-4845.278" + cell $xor $xor$ls180.v:4845$803 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg33 [2] - connect \B $xor$ls180.v:4849$803_Y - connect \Y $xor$ls180.v:4849$804_Y + connect \B $xor$ls180.v:4845$802_Y + connect \Y $xor$ls180.v:4845$803_Y end - attribute \src "ls180.v:4850.360-4850.432" - cell $xor $xor$ls180.v:4850$805 + attribute \src "ls180.v:4846.360-4846.432" + cell $xor $xor$ls180.v:4846$804 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108909,10 +108894,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [5] connect \B \main_sdcore_crc7_inserter_crcreg34 [6] - connect \Y $xor$ls180.v:4850$805_Y + connect \Y $xor$ls180.v:4846$804_Y end - attribute \src "ls180.v:4850.205-4850.277" - cell $xor $xor$ls180.v:4850$806 + attribute \src "ls180.v:4846.205-4846.277" + cell $xor $xor$ls180.v:4846$805 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108920,21 +108905,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [5] connect \B \main_sdcore_crc7_inserter_crcreg34 [6] - connect \Y $xor$ls180.v:4850$806_Y + connect \Y $xor$ls180.v:4846$805_Y end - attribute \src "ls180.v:4850.164-4850.278" - cell $xor $xor$ls180.v:4850$807 + attribute \src "ls180.v:4846.164-4846.278" + cell $xor $xor$ls180.v:4846$806 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg34 [2] - connect \B $xor$ls180.v:4850$806_Y - connect \Y $xor$ls180.v:4850$807_Y + connect \B $xor$ls180.v:4846$805_Y + connect \Y $xor$ls180.v:4846$806_Y end - attribute \src "ls180.v:4851.360-4851.432" - cell $xor $xor$ls180.v:4851$808 + attribute \src "ls180.v:4847.360-4847.432" + cell $xor $xor$ls180.v:4847$807 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108942,10 +108927,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [4] connect \B \main_sdcore_crc7_inserter_crcreg35 [6] - connect \Y $xor$ls180.v:4851$808_Y + connect \Y $xor$ls180.v:4847$807_Y end - attribute \src "ls180.v:4851.205-4851.277" - cell $xor $xor$ls180.v:4851$809 + attribute \src "ls180.v:4847.205-4847.277" + cell $xor $xor$ls180.v:4847$808 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108953,21 +108938,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [4] connect \B \main_sdcore_crc7_inserter_crcreg35 [6] - connect \Y $xor$ls180.v:4851$809_Y + connect \Y $xor$ls180.v:4847$808_Y end - attribute \src "ls180.v:4851.164-4851.278" - cell $xor $xor$ls180.v:4851$810 + attribute \src "ls180.v:4847.164-4847.278" + cell $xor $xor$ls180.v:4847$809 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg35 [2] - connect \B $xor$ls180.v:4851$809_Y - connect \Y $xor$ls180.v:4851$810_Y + connect \B $xor$ls180.v:4847$808_Y + connect \Y $xor$ls180.v:4847$809_Y end - attribute \src "ls180.v:4852.360-4852.432" - cell $xor $xor$ls180.v:4852$811 + attribute \src "ls180.v:4848.360-4848.432" + cell $xor $xor$ls180.v:4848$810 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108975,10 +108960,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [3] connect \B \main_sdcore_crc7_inserter_crcreg36 [6] - connect \Y $xor$ls180.v:4852$811_Y + connect \Y $xor$ls180.v:4848$810_Y end - attribute \src "ls180.v:4852.205-4852.277" - cell $xor $xor$ls180.v:4852$812 + attribute \src "ls180.v:4848.205-4848.277" + cell $xor $xor$ls180.v:4848$811 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -108986,21 +108971,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [3] connect \B \main_sdcore_crc7_inserter_crcreg36 [6] - connect \Y $xor$ls180.v:4852$812_Y + connect \Y $xor$ls180.v:4848$811_Y end - attribute \src "ls180.v:4852.164-4852.278" - cell $xor $xor$ls180.v:4852$813 + attribute \src "ls180.v:4848.164-4848.278" + cell $xor $xor$ls180.v:4848$812 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg36 [2] - connect \B $xor$ls180.v:4852$812_Y - connect \Y $xor$ls180.v:4852$813_Y + connect \B $xor$ls180.v:4848$811_Y + connect \Y $xor$ls180.v:4848$812_Y end - attribute \src "ls180.v:4853.360-4853.432" - cell $xor $xor$ls180.v:4853$814 + attribute \src "ls180.v:4849.360-4849.432" + cell $xor $xor$ls180.v:4849$813 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -109008,10 +108993,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [2] connect \B \main_sdcore_crc7_inserter_crcreg37 [6] - connect \Y $xor$ls180.v:4853$814_Y + connect \Y $xor$ls180.v:4849$813_Y end - attribute \src "ls180.v:4853.205-4853.277" - cell $xor $xor$ls180.v:4853$815 + attribute \src "ls180.v:4849.205-4849.277" + cell $xor $xor$ls180.v:4849$814 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -109019,21 +109004,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [2] connect \B \main_sdcore_crc7_inserter_crcreg37 [6] - connect \Y $xor$ls180.v:4853$815_Y + connect \Y $xor$ls180.v:4849$814_Y end - attribute \src "ls180.v:4853.164-4853.278" - cell $xor $xor$ls180.v:4853$816 + attribute \src "ls180.v:4849.164-4849.278" + cell $xor $xor$ls180.v:4849$815 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg37 [2] - connect \B $xor$ls180.v:4853$815_Y - connect \Y $xor$ls180.v:4853$816_Y + connect \B $xor$ls180.v:4849$814_Y + connect \Y $xor$ls180.v:4849$815_Y end - attribute \src "ls180.v:4854.360-4854.432" - cell $xor $xor$ls180.v:4854$817 + attribute \src "ls180.v:4850.360-4850.432" + cell $xor $xor$ls180.v:4850$816 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -109041,10 +109026,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [1] connect \B \main_sdcore_crc7_inserter_crcreg38 [6] - connect \Y $xor$ls180.v:4854$817_Y + connect \Y $xor$ls180.v:4850$816_Y end - attribute \src "ls180.v:4854.205-4854.277" - cell $xor $xor$ls180.v:4854$818 + attribute \src "ls180.v:4850.205-4850.277" + cell $xor $xor$ls180.v:4850$817 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -109052,21 +109037,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [1] connect \B \main_sdcore_crc7_inserter_crcreg38 [6] - connect \Y $xor$ls180.v:4854$818_Y + connect \Y $xor$ls180.v:4850$817_Y end - attribute \src "ls180.v:4854.164-4854.278" - cell $xor $xor$ls180.v:4854$819 + attribute \src "ls180.v:4850.164-4850.278" + cell $xor $xor$ls180.v:4850$818 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg38 [2] - connect \B $xor$ls180.v:4854$818_Y - connect \Y $xor$ls180.v:4854$819_Y + connect \B $xor$ls180.v:4850$817_Y + connect \Y $xor$ls180.v:4850$818_Y end - attribute \src "ls180.v:4855.360-4855.432" - cell $xor $xor$ls180.v:4855$820 + attribute \src "ls180.v:4851.360-4851.432" + cell $xor $xor$ls180.v:4851$819 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -109074,10 +109059,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [0] connect \B \main_sdcore_crc7_inserter_crcreg39 [6] - connect \Y $xor$ls180.v:4855$820_Y + connect \Y $xor$ls180.v:4851$819_Y end - attribute \src "ls180.v:4855.205-4855.277" - cell $xor $xor$ls180.v:4855$821 + attribute \src "ls180.v:4851.205-4851.277" + cell $xor $xor$ls180.v:4851$820 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -109085,21 +109070,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [0] connect \B \main_sdcore_crc7_inserter_crcreg39 [6] - connect \Y $xor$ls180.v:4855$821_Y + connect \Y $xor$ls180.v:4851$820_Y end - attribute \src "ls180.v:4855.164-4855.278" - cell $xor $xor$ls180.v:4855$822 + attribute \src "ls180.v:4851.164-4851.278" + cell $xor $xor$ls180.v:4851$821 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg39 [2] - connect \B $xor$ls180.v:4855$821_Y - connect \Y $xor$ls180.v:4855$822_Y + connect \B $xor$ls180.v:4851$820_Y + connect \Y $xor$ls180.v:4851$821_Y end - attribute \src "ls180.v:4876.899-4876.983" - cell $xor $xor$ls180.v:4876$836 + attribute \src "ls180.v:4872.899-4872.983" + cell $xor $xor$ls180.v:4872$835 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -109107,10 +109092,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc0_val [1] connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:4876$836_Y + connect \Y $xor$ls180.v:4872$835_Y end - attribute \src "ls180.v:4876.634-4876.718" - cell $xor $xor$ls180.v:4876$837 + attribute \src "ls180.v:4872.634-4872.718" + cell $xor $xor$ls180.v:4872$836 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -109118,21 +109103,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc0_val [1] connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:4876$837_Y + connect \Y $xor$ls180.v:4872$836_Y end - attribute \src "ls180.v:4876.588-4876.719" - cell $xor $xor$ls180.v:4876$838 + attribute \src "ls180.v:4872.588-4872.719" + cell $xor $xor$ls180.v:4872$837 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc0_crcreg0 [4] - connect \B $xor$ls180.v:4876$837_Y - connect \Y $xor$ls180.v:4876$838_Y + connect \B $xor$ls180.v:4872$836_Y + connect \Y $xor$ls180.v:4872$837_Y end - attribute \src "ls180.v:4876.234-4876.318" - cell $xor $xor$ls180.v:4876$839 + attribute \src "ls180.v:4872.234-4872.318" + cell $xor $xor$ls180.v:4872$838 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -109140,21 +109125,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc0_val [1] connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:4876$839_Y + connect \Y $xor$ls180.v:4872$838_Y end - attribute \src "ls180.v:4876.187-4876.319" - cell $xor $xor$ls180.v:4876$840 + attribute \src "ls180.v:4872.187-4872.319" + cell $xor $xor$ls180.v:4872$839 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc0_crcreg0 [11] - connect \B $xor$ls180.v:4876$839_Y - connect \Y $xor$ls180.v:4876$840_Y + connect \B $xor$ls180.v:4872$838_Y + connect \Y $xor$ls180.v:4872$839_Y end - attribute \src "ls180.v:4877.899-4877.983" - cell $xor $xor$ls180.v:4877$841 + attribute \src "ls180.v:4873.899-4873.983" + cell $xor $xor$ls180.v:4873$840 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -109162,10 +109147,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc0_val [0] connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:4877$841_Y + connect \Y $xor$ls180.v:4873$840_Y end - attribute \src "ls180.v:4877.634-4877.718" - cell $xor $xor$ls180.v:4877$842 + attribute \src "ls180.v:4873.634-4873.718" + cell $xor $xor$ls180.v:4873$841 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -109173,21 +109158,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc0_val [0] connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:4877$842_Y + connect \Y $xor$ls180.v:4873$841_Y end - attribute \src "ls180.v:4877.588-4877.719" - cell $xor $xor$ls180.v:4877$843 + attribute \src "ls180.v:4873.588-4873.719" + cell $xor $xor$ls180.v:4873$842 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc0_crcreg1 [4] - connect \B $xor$ls180.v:4877$842_Y - connect \Y $xor$ls180.v:4877$843_Y + connect \B $xor$ls180.v:4873$841_Y + connect \Y $xor$ls180.v:4873$842_Y end - attribute \src "ls180.v:4877.234-4877.318" - cell $xor $xor$ls180.v:4877$844 + attribute \src "ls180.v:4873.234-4873.318" + cell $xor $xor$ls180.v:4873$843 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -109195,21 +109180,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc0_val [0] connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:4877$844_Y + connect \Y $xor$ls180.v:4873$843_Y end - attribute \src "ls180.v:4877.187-4877.319" - cell $xor $xor$ls180.v:4877$845 + attribute \src "ls180.v:4873.187-4873.319" + cell $xor $xor$ls180.v:4873$844 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc0_crcreg1 [11] - connect \B $xor$ls180.v:4877$844_Y - connect \Y $xor$ls180.v:4877$845_Y + connect \B $xor$ls180.v:4873$843_Y + connect \Y $xor$ls180.v:4873$844_Y end - attribute \src "ls180.v:4886.899-4886.983" - cell $xor $xor$ls180.v:4886$847 + attribute \src "ls180.v:4882.899-4882.983" + cell $xor $xor$ls180.v:4882$846 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -109217,10 +109202,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_val [1] connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:4886$847_Y + connect \Y $xor$ls180.v:4882$846_Y end - attribute \src "ls180.v:4886.634-4886.718" - cell $xor $xor$ls180.v:4886$848 + attribute \src "ls180.v:4882.634-4882.718" + cell $xor $xor$ls180.v:4882$847 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -109228,21 +109213,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_val [1] connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:4886$848_Y + connect \Y $xor$ls180.v:4882$847_Y end - attribute \src "ls180.v:4886.588-4886.719" - cell $xor $xor$ls180.v:4886$849 + attribute \src "ls180.v:4882.588-4882.719" + cell $xor $xor$ls180.v:4882$848 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_crcreg0 [4] - connect \B $xor$ls180.v:4886$848_Y - connect \Y $xor$ls180.v:4886$849_Y + connect \B $xor$ls180.v:4882$847_Y + connect \Y $xor$ls180.v:4882$848_Y end - attribute \src "ls180.v:4886.234-4886.318" - cell $xor $xor$ls180.v:4886$850 + attribute \src "ls180.v:4882.234-4882.318" + cell $xor $xor$ls180.v:4882$849 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -109250,21 +109235,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_val [1] connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:4886$850_Y + connect \Y $xor$ls180.v:4882$849_Y end - attribute \src "ls180.v:4886.187-4886.319" - cell $xor $xor$ls180.v:4886$851 + attribute \src "ls180.v:4882.187-4882.319" + cell $xor $xor$ls180.v:4882$850 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_crcreg0 [11] - connect \B $xor$ls180.v:4886$850_Y - connect \Y $xor$ls180.v:4886$851_Y + connect \B $xor$ls180.v:4882$849_Y + connect \Y $xor$ls180.v:4882$850_Y end - attribute \src "ls180.v:4887.899-4887.983" - cell $xor $xor$ls180.v:4887$852 + attribute \src "ls180.v:4883.899-4883.983" + cell $xor $xor$ls180.v:4883$851 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -109272,10 +109257,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_val [0] connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:4887$852_Y + connect \Y $xor$ls180.v:4883$851_Y end - attribute \src "ls180.v:4887.634-4887.718" - cell $xor $xor$ls180.v:4887$853 + attribute \src "ls180.v:4883.634-4883.718" + cell $xor $xor$ls180.v:4883$852 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -109283,21 +109268,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_val [0] connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:4887$853_Y + connect \Y $xor$ls180.v:4883$852_Y end - attribute \src "ls180.v:4887.588-4887.719" - cell $xor $xor$ls180.v:4887$854 + attribute \src "ls180.v:4883.588-4883.719" + cell $xor $xor$ls180.v:4883$853 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_crcreg1 [4] - connect \B $xor$ls180.v:4887$853_Y - connect \Y $xor$ls180.v:4887$854_Y + connect \B $xor$ls180.v:4883$852_Y + connect \Y $xor$ls180.v:4883$853_Y end - attribute \src "ls180.v:4887.234-4887.318" - cell $xor $xor$ls180.v:4887$855 + attribute \src "ls180.v:4883.234-4883.318" + cell $xor $xor$ls180.v:4883$854 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -109305,21 +109290,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_val [0] connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:4887$855_Y + connect \Y $xor$ls180.v:4883$854_Y end - attribute \src "ls180.v:4887.187-4887.319" - cell $xor $xor$ls180.v:4887$856 + attribute \src "ls180.v:4883.187-4883.319" + cell $xor $xor$ls180.v:4883$855 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_crcreg1 [11] - connect \B $xor$ls180.v:4887$855_Y - connect \Y $xor$ls180.v:4887$856_Y + connect \B $xor$ls180.v:4883$854_Y + connect \Y $xor$ls180.v:4883$855_Y end - attribute \src "ls180.v:4896.899-4896.983" - cell $xor $xor$ls180.v:4896$858 + attribute \src "ls180.v:4892.899-4892.983" + cell $xor $xor$ls180.v:4892$857 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -109327,10 +109312,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_val [1] connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:4896$858_Y + connect \Y $xor$ls180.v:4892$857_Y end - attribute \src "ls180.v:4896.634-4896.718" - cell $xor $xor$ls180.v:4896$859 + attribute \src "ls180.v:4892.634-4892.718" + cell $xor $xor$ls180.v:4892$858 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -109338,21 +109323,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_val [1] connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:4896$859_Y + connect \Y $xor$ls180.v:4892$858_Y end - attribute \src "ls180.v:4896.588-4896.719" - cell $xor $xor$ls180.v:4896$860 + attribute \src "ls180.v:4892.588-4892.719" + cell $xor $xor$ls180.v:4892$859 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_crcreg0 [4] - connect \B $xor$ls180.v:4896$859_Y - connect \Y $xor$ls180.v:4896$860_Y + connect \B $xor$ls180.v:4892$858_Y + connect \Y $xor$ls180.v:4892$859_Y end - attribute \src "ls180.v:4896.234-4896.318" - cell $xor $xor$ls180.v:4896$861 + attribute \src "ls180.v:4892.234-4892.318" + cell $xor $xor$ls180.v:4892$860 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -109360,21 +109345,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_val [1] connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:4896$861_Y + connect \Y $xor$ls180.v:4892$860_Y end - attribute \src "ls180.v:4896.187-4896.319" - cell $xor $xor$ls180.v:4896$862 + attribute \src "ls180.v:4892.187-4892.319" + cell $xor $xor$ls180.v:4892$861 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_crcreg0 [11] - connect \B $xor$ls180.v:4896$861_Y - connect \Y $xor$ls180.v:4896$862_Y + connect \B $xor$ls180.v:4892$860_Y + connect \Y $xor$ls180.v:4892$861_Y end - attribute \src "ls180.v:4897.899-4897.983" - cell $xor $xor$ls180.v:4897$863 + attribute \src "ls180.v:4893.899-4893.983" + cell $xor $xor$ls180.v:4893$862 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -109382,10 +109367,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_val [0] connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:4897$863_Y + connect \Y $xor$ls180.v:4893$862_Y end - attribute \src "ls180.v:4897.634-4897.718" - cell $xor $xor$ls180.v:4897$864 + attribute \src "ls180.v:4893.634-4893.718" + cell $xor $xor$ls180.v:4893$863 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -109393,21 +109378,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_val [0] connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:4897$864_Y + connect \Y $xor$ls180.v:4893$863_Y end - attribute \src "ls180.v:4897.588-4897.719" - cell $xor $xor$ls180.v:4897$865 + attribute \src "ls180.v:4893.588-4893.719" + cell $xor $xor$ls180.v:4893$864 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_crcreg1 [4] - connect \B $xor$ls180.v:4897$864_Y - connect \Y $xor$ls180.v:4897$865_Y + connect \B $xor$ls180.v:4893$863_Y + connect \Y $xor$ls180.v:4893$864_Y end - attribute \src "ls180.v:4897.234-4897.318" - cell $xor $xor$ls180.v:4897$866 + attribute \src "ls180.v:4893.234-4893.318" + cell $xor $xor$ls180.v:4893$865 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -109415,21 +109400,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_val [0] connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:4897$866_Y + connect \Y $xor$ls180.v:4893$865_Y end - attribute \src "ls180.v:4897.187-4897.319" - cell $xor $xor$ls180.v:4897$867 + attribute \src "ls180.v:4893.187-4893.319" + cell $xor $xor$ls180.v:4893$866 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_crcreg1 [11] - connect \B $xor$ls180.v:4897$866_Y - connect \Y $xor$ls180.v:4897$867_Y + connect \B $xor$ls180.v:4893$865_Y + connect \Y $xor$ls180.v:4893$866_Y end - attribute \src "ls180.v:4906.899-4906.983" - cell $xor $xor$ls180.v:4906$869 + attribute \src "ls180.v:4902.899-4902.983" + cell $xor $xor$ls180.v:4902$868 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -109437,10 +109422,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_val [1] connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:4906$869_Y + connect \Y $xor$ls180.v:4902$868_Y end - attribute \src "ls180.v:4906.634-4906.718" - cell $xor $xor$ls180.v:4906$870 + attribute \src "ls180.v:4902.634-4902.718" + cell $xor $xor$ls180.v:4902$869 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -109448,21 +109433,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_val [1] connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:4906$870_Y + connect \Y $xor$ls180.v:4902$869_Y end - attribute \src "ls180.v:4906.588-4906.719" - cell $xor $xor$ls180.v:4906$871 + attribute \src "ls180.v:4902.588-4902.719" + cell $xor $xor$ls180.v:4902$870 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_crcreg0 [4] - connect \B $xor$ls180.v:4906$870_Y - connect \Y $xor$ls180.v:4906$871_Y + connect \B $xor$ls180.v:4902$869_Y + connect \Y $xor$ls180.v:4902$870_Y end - attribute \src "ls180.v:4906.234-4906.318" - cell $xor $xor$ls180.v:4906$872 + attribute \src "ls180.v:4902.234-4902.318" + cell $xor $xor$ls180.v:4902$871 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -109470,21 +109455,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_val [1] connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:4906$872_Y + connect \Y $xor$ls180.v:4902$871_Y end - attribute \src "ls180.v:4906.187-4906.319" - cell $xor $xor$ls180.v:4906$873 + attribute \src "ls180.v:4902.187-4902.319" + cell $xor $xor$ls180.v:4902$872 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_crcreg0 [11] - connect \B $xor$ls180.v:4906$872_Y - connect \Y $xor$ls180.v:4906$873_Y + connect \B $xor$ls180.v:4902$871_Y + connect \Y $xor$ls180.v:4902$872_Y end - attribute \src "ls180.v:4907.899-4907.983" - cell $xor $xor$ls180.v:4907$874 + attribute \src "ls180.v:4903.899-4903.983" + cell $xor $xor$ls180.v:4903$873 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -109492,10 +109477,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_val [0] connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:4907$874_Y + connect \Y $xor$ls180.v:4903$873_Y end - attribute \src "ls180.v:4907.634-4907.718" - cell $xor $xor$ls180.v:4907$875 + attribute \src "ls180.v:4903.634-4903.718" + cell $xor $xor$ls180.v:4903$874 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -109503,21 +109488,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_val [0] connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:4907$875_Y + connect \Y $xor$ls180.v:4903$874_Y end - attribute \src "ls180.v:4907.588-4907.719" - cell $xor $xor$ls180.v:4907$876 + attribute \src "ls180.v:4903.588-4903.719" + cell $xor $xor$ls180.v:4903$875 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_crcreg1 [4] - connect \B $xor$ls180.v:4907$875_Y - connect \Y $xor$ls180.v:4907$876_Y + connect \B $xor$ls180.v:4903$874_Y + connect \Y $xor$ls180.v:4903$875_Y end - attribute \src "ls180.v:4907.234-4907.318" - cell $xor $xor$ls180.v:4907$877 + attribute \src "ls180.v:4903.234-4903.318" + cell $xor $xor$ls180.v:4903$876 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -109525,21 +109510,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_val [0] connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:4907$877_Y + connect \Y $xor$ls180.v:4903$876_Y end - attribute \src "ls180.v:4907.187-4907.319" - cell $xor $xor$ls180.v:4907$878 + attribute \src "ls180.v:4903.187-4903.319" + cell $xor $xor$ls180.v:4903$877 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_crcreg1 [11] - connect \B $xor$ls180.v:4907$877_Y - connect \Y $xor$ls180.v:4907$878_Y + connect \B $xor$ls180.v:4903$876_Y + connect \Y $xor$ls180.v:4903$877_Y end - attribute \src "ls180.v:5058.879-5058.961" - cell $xor $xor$ls180.v:5058$911 + attribute \src "ls180.v:5054.879-5054.961" + cell $xor $xor$ls180.v:5054$910 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -109547,10 +109532,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_val [1] connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:5058$911_Y + connect \Y $xor$ls180.v:5054$910_Y end - attribute \src "ls180.v:5058.620-5058.702" - cell $xor $xor$ls180.v:5058$912 + attribute \src "ls180.v:5054.620-5054.702" + cell $xor $xor$ls180.v:5054$911 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -109558,21 +109543,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_val [1] connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:5058$912_Y + connect \Y $xor$ls180.v:5054$911_Y end - attribute \src "ls180.v:5058.575-5058.703" - cell $xor $xor$ls180.v:5058$913 + attribute \src "ls180.v:5054.575-5054.703" + cell $xor $xor$ls180.v:5054$912 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_crcreg0 [4] - connect \B $xor$ls180.v:5058$912_Y - connect \Y $xor$ls180.v:5058$913_Y + connect \B $xor$ls180.v:5054$911_Y + connect \Y $xor$ls180.v:5054$912_Y end - attribute \src "ls180.v:5058.229-5058.311" - cell $xor $xor$ls180.v:5058$914 + attribute \src "ls180.v:5054.229-5054.311" + cell $xor $xor$ls180.v:5054$913 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -109580,21 +109565,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_val [1] connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:5058$914_Y + connect \Y $xor$ls180.v:5054$913_Y end - attribute \src "ls180.v:5058.183-5058.312" - cell $xor $xor$ls180.v:5058$915 + attribute \src "ls180.v:5054.183-5054.312" + cell $xor $xor$ls180.v:5054$914 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_crcreg0 [11] - connect \B $xor$ls180.v:5058$914_Y - connect \Y $xor$ls180.v:5058$915_Y + connect \B $xor$ls180.v:5054$913_Y + connect \Y $xor$ls180.v:5054$914_Y end - attribute \src "ls180.v:5059.879-5059.961" - cell $xor $xor$ls180.v:5059$916 + attribute \src "ls180.v:5055.879-5055.961" + cell $xor $xor$ls180.v:5055$915 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -109602,10 +109587,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_val [0] connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:5059$916_Y + connect \Y $xor$ls180.v:5055$915_Y end - attribute \src "ls180.v:5059.620-5059.702" - cell $xor $xor$ls180.v:5059$917 + attribute \src "ls180.v:5055.620-5055.702" + cell $xor $xor$ls180.v:5055$916 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -109613,21 +109598,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_val [0] connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:5059$917_Y + connect \Y $xor$ls180.v:5055$916_Y end - attribute \src "ls180.v:5059.575-5059.703" - cell $xor $xor$ls180.v:5059$918 + attribute \src "ls180.v:5055.575-5055.703" + cell $xor $xor$ls180.v:5055$917 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_crcreg1 [4] - connect \B $xor$ls180.v:5059$917_Y - connect \Y $xor$ls180.v:5059$918_Y + connect \B $xor$ls180.v:5055$916_Y + connect \Y $xor$ls180.v:5055$917_Y end - attribute \src "ls180.v:5059.229-5059.311" - cell $xor $xor$ls180.v:5059$919 + attribute \src "ls180.v:5055.229-5055.311" + cell $xor $xor$ls180.v:5055$918 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -109635,21 +109620,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_val [0] connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:5059$919_Y + connect \Y $xor$ls180.v:5055$918_Y end - attribute \src "ls180.v:5059.183-5059.312" - cell $xor $xor$ls180.v:5059$920 + attribute \src "ls180.v:5055.183-5055.312" + cell $xor $xor$ls180.v:5055$919 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_crcreg1 [11] - connect \B $xor$ls180.v:5059$919_Y - connect \Y $xor$ls180.v:5059$920_Y + connect \B $xor$ls180.v:5055$918_Y + connect \Y $xor$ls180.v:5055$919_Y end - attribute \src "ls180.v:5068.879-5068.961" - cell $xor $xor$ls180.v:5068$922 + attribute \src "ls180.v:5064.879-5064.961" + cell $xor $xor$ls180.v:5064$921 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -109657,10 +109642,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_val [1] connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:5068$922_Y + connect \Y $xor$ls180.v:5064$921_Y end - attribute \src "ls180.v:5068.620-5068.702" - cell $xor $xor$ls180.v:5068$923 + attribute \src "ls180.v:5064.620-5064.702" + cell $xor $xor$ls180.v:5064$922 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -109668,21 +109653,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_val [1] connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:5068$923_Y + connect \Y $xor$ls180.v:5064$922_Y end - attribute \src "ls180.v:5068.575-5068.703" - cell $xor $xor$ls180.v:5068$924 + attribute \src "ls180.v:5064.575-5064.703" + cell $xor $xor$ls180.v:5064$923 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_crcreg0 [4] - connect \B $xor$ls180.v:5068$923_Y - connect \Y $xor$ls180.v:5068$924_Y + connect \B $xor$ls180.v:5064$922_Y + connect \Y $xor$ls180.v:5064$923_Y end - attribute \src "ls180.v:5068.229-5068.311" - cell $xor $xor$ls180.v:5068$925 + attribute \src "ls180.v:5064.229-5064.311" + cell $xor $xor$ls180.v:5064$924 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -109690,21 +109675,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_val [1] connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:5068$925_Y + connect \Y $xor$ls180.v:5064$924_Y end - attribute \src "ls180.v:5068.183-5068.312" - cell $xor $xor$ls180.v:5068$926 + attribute \src "ls180.v:5064.183-5064.312" + cell $xor $xor$ls180.v:5064$925 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_crcreg0 [11] - connect \B $xor$ls180.v:5068$925_Y - connect \Y $xor$ls180.v:5068$926_Y + connect \B $xor$ls180.v:5064$924_Y + connect \Y $xor$ls180.v:5064$925_Y end - attribute \src "ls180.v:5069.879-5069.961" - cell $xor $xor$ls180.v:5069$927 + attribute \src "ls180.v:5065.879-5065.961" + cell $xor $xor$ls180.v:5065$926 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -109712,10 +109697,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_val [0] connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:5069$927_Y + connect \Y $xor$ls180.v:5065$926_Y end - attribute \src "ls180.v:5069.620-5069.702" - cell $xor $xor$ls180.v:5069$928 + attribute \src "ls180.v:5065.620-5065.702" + cell $xor $xor$ls180.v:5065$927 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -109723,21 +109708,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_val [0] connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:5069$928_Y + connect \Y $xor$ls180.v:5065$927_Y end - attribute \src "ls180.v:5069.575-5069.703" - cell $xor $xor$ls180.v:5069$929 + attribute \src "ls180.v:5065.575-5065.703" + cell $xor $xor$ls180.v:5065$928 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_crcreg1 [4] - connect \B $xor$ls180.v:5069$928_Y - connect \Y $xor$ls180.v:5069$929_Y + connect \B $xor$ls180.v:5065$927_Y + connect \Y $xor$ls180.v:5065$928_Y end - attribute \src "ls180.v:5069.229-5069.311" - cell $xor $xor$ls180.v:5069$930 + attribute \src "ls180.v:5065.229-5065.311" + cell $xor $xor$ls180.v:5065$929 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -109745,21 +109730,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_val [0] connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:5069$930_Y + connect \Y $xor$ls180.v:5065$929_Y end - attribute \src "ls180.v:5069.183-5069.312" - cell $xor $xor$ls180.v:5069$931 + attribute \src "ls180.v:5065.183-5065.312" + cell $xor $xor$ls180.v:5065$930 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_crcreg1 [11] - connect \B $xor$ls180.v:5069$930_Y - connect \Y $xor$ls180.v:5069$931_Y + connect \B $xor$ls180.v:5065$929_Y + connect \Y $xor$ls180.v:5065$930_Y end - attribute \src "ls180.v:5078.879-5078.961" - cell $xor $xor$ls180.v:5078$933 + attribute \src "ls180.v:5074.879-5074.961" + cell $xor $xor$ls180.v:5074$932 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -109767,10 +109752,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc2_val [1] connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:5078$933_Y + connect \Y $xor$ls180.v:5074$932_Y end - attribute \src "ls180.v:5078.620-5078.702" - cell $xor $xor$ls180.v:5078$934 + attribute \src "ls180.v:5074.620-5074.702" + cell $xor $xor$ls180.v:5074$933 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -109778,21 +109763,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc2_val [1] connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:5078$934_Y + connect \Y $xor$ls180.v:5074$933_Y end - attribute \src "ls180.v:5078.575-5078.703" - cell $xor $xor$ls180.v:5078$935 + attribute \src "ls180.v:5074.575-5074.703" + cell $xor $xor$ls180.v:5074$934 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc2_crcreg0 [4] - connect \B $xor$ls180.v:5078$934_Y - connect \Y $xor$ls180.v:5078$935_Y + connect \B $xor$ls180.v:5074$933_Y + connect \Y $xor$ls180.v:5074$934_Y end - attribute \src "ls180.v:5078.229-5078.311" - cell $xor $xor$ls180.v:5078$936 + attribute \src "ls180.v:5074.229-5074.311" + cell $xor $xor$ls180.v:5074$935 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -109800,21 +109785,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc2_val [1] connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:5078$936_Y + connect \Y $xor$ls180.v:5074$935_Y end - attribute \src "ls180.v:5078.183-5078.312" - cell $xor $xor$ls180.v:5078$937 + attribute \src "ls180.v:5074.183-5074.312" + cell $xor $xor$ls180.v:5074$936 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc2_crcreg0 [11] - connect \B $xor$ls180.v:5078$936_Y - connect \Y $xor$ls180.v:5078$937_Y + connect \B $xor$ls180.v:5074$935_Y + connect \Y $xor$ls180.v:5074$936_Y end - attribute \src "ls180.v:5079.879-5079.961" - cell $xor $xor$ls180.v:5079$938 + attribute \src "ls180.v:5075.879-5075.961" + cell $xor $xor$ls180.v:5075$937 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -109822,10 +109807,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc2_val [0] connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:5079$938_Y + connect \Y $xor$ls180.v:5075$937_Y end - attribute \src "ls180.v:5079.620-5079.702" - cell $xor $xor$ls180.v:5079$939 + attribute \src "ls180.v:5075.620-5075.702" + cell $xor $xor$ls180.v:5075$938 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -109833,21 +109818,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc2_val [0] connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:5079$939_Y + connect \Y $xor$ls180.v:5075$938_Y end - attribute \src "ls180.v:5079.575-5079.703" - cell $xor $xor$ls180.v:5079$940 + attribute \src "ls180.v:5075.575-5075.703" + cell $xor $xor$ls180.v:5075$939 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc2_crcreg1 [4] - connect \B $xor$ls180.v:5079$939_Y - connect \Y $xor$ls180.v:5079$940_Y + connect \B $xor$ls180.v:5075$938_Y + connect \Y $xor$ls180.v:5075$939_Y end - attribute \src "ls180.v:5079.229-5079.311" - cell $xor $xor$ls180.v:5079$941 + attribute \src "ls180.v:5075.229-5075.311" + cell $xor $xor$ls180.v:5075$940 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -109855,21 +109840,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc2_val [0] connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:5079$941_Y + connect \Y $xor$ls180.v:5075$940_Y end - attribute \src "ls180.v:5079.183-5079.312" - cell $xor $xor$ls180.v:5079$942 + attribute \src "ls180.v:5075.183-5075.312" + cell $xor $xor$ls180.v:5075$941 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc2_crcreg1 [11] - connect \B $xor$ls180.v:5079$941_Y - connect \Y $xor$ls180.v:5079$942_Y + connect \B $xor$ls180.v:5075$940_Y + connect \Y $xor$ls180.v:5075$941_Y end - attribute \src "ls180.v:5088.879-5088.961" - cell $xor $xor$ls180.v:5088$944 + attribute \src "ls180.v:5084.879-5084.961" + cell $xor $xor$ls180.v:5084$943 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -109877,10 +109862,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_val [1] connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:5088$944_Y + connect \Y $xor$ls180.v:5084$943_Y end - attribute \src "ls180.v:5088.620-5088.702" - cell $xor $xor$ls180.v:5088$945 + attribute \src "ls180.v:5084.620-5084.702" + cell $xor $xor$ls180.v:5084$944 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -109888,21 +109873,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_val [1] connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:5088$945_Y + connect \Y $xor$ls180.v:5084$944_Y end - attribute \src "ls180.v:5088.575-5088.703" - cell $xor $xor$ls180.v:5088$946 + attribute \src "ls180.v:5084.575-5084.703" + cell $xor $xor$ls180.v:5084$945 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_crcreg0 [4] - connect \B $xor$ls180.v:5088$945_Y - connect \Y $xor$ls180.v:5088$946_Y + connect \B $xor$ls180.v:5084$944_Y + connect \Y $xor$ls180.v:5084$945_Y end - attribute \src "ls180.v:5088.229-5088.311" - cell $xor $xor$ls180.v:5088$947 + attribute \src "ls180.v:5084.229-5084.311" + cell $xor $xor$ls180.v:5084$946 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -109910,21 +109895,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_val [1] connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:5088$947_Y + connect \Y $xor$ls180.v:5084$946_Y end - attribute \src "ls180.v:5088.183-5088.312" - cell $xor $xor$ls180.v:5088$948 + attribute \src "ls180.v:5084.183-5084.312" + cell $xor $xor$ls180.v:5084$947 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_crcreg0 [11] - connect \B $xor$ls180.v:5088$947_Y - connect \Y $xor$ls180.v:5088$948_Y + connect \B $xor$ls180.v:5084$946_Y + connect \Y $xor$ls180.v:5084$947_Y end - attribute \src "ls180.v:5089.879-5089.961" - cell $xor $xor$ls180.v:5089$949 + attribute \src "ls180.v:5085.879-5085.961" + cell $xor $xor$ls180.v:5085$948 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -109932,10 +109917,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_val [0] connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:5089$949_Y + connect \Y $xor$ls180.v:5085$948_Y end - attribute \src "ls180.v:5089.620-5089.702" - cell $xor $xor$ls180.v:5089$950 + attribute \src "ls180.v:5085.620-5085.702" + cell $xor $xor$ls180.v:5085$949 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -109943,21 +109928,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_val [0] connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:5089$950_Y + connect \Y $xor$ls180.v:5085$949_Y end - attribute \src "ls180.v:5089.575-5089.703" - cell $xor $xor$ls180.v:5089$951 + attribute \src "ls180.v:5085.575-5085.703" + cell $xor $xor$ls180.v:5085$950 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_crcreg1 [4] - connect \B $xor$ls180.v:5089$950_Y - connect \Y $xor$ls180.v:5089$951_Y + connect \B $xor$ls180.v:5085$949_Y + connect \Y $xor$ls180.v:5085$950_Y end - attribute \src "ls180.v:5089.229-5089.311" - cell $xor $xor$ls180.v:5089$952 + attribute \src "ls180.v:5085.229-5085.311" + cell $xor $xor$ls180.v:5085$951 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -109965,21 +109950,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_val [0] connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:5089$952_Y + connect \Y $xor$ls180.v:5085$951_Y end - attribute \src "ls180.v:5089.183-5089.312" - cell $xor $xor$ls180.v:5089$953 + attribute \src "ls180.v:5085.183-5085.312" + cell $xor $xor$ls180.v:5085$952 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_crcreg1 [11] - connect \B $xor$ls180.v:5089$952_Y - connect \Y $xor$ls180.v:5089$953_Y + connect \B $xor$ls180.v:5085$951_Y + connect \Y $xor$ls180.v:5085$952_Y end attribute \module_not_derived 1 - attribute \src "ls180.v:10117.13-10284.2" + attribute \src "ls180.v:10113.13-10280.2" cell \test_issuer \test_issuer connect \TAP_bus__tck \main_libresocsim_libresoc_jtag_tck connect \TAP_bus__tdi \main_libresocsim_libresoc_jtag_tdi @@ -110142,765 +110127,740 @@ module \ls180 connect \pc_i 1'0 connect \pc_i_ok 1'0 connect \pc_o \main_libresocsim_libresoc2 - connect \rst $or$ls180.v:10199$2754_Y + connect \rst $or$ls180.v:10195$2752_Y connect \uart_rx__core__i \main_libresocsim_libresoc_constraintmanager0_uart0_rx connect \uart_rx__pad__i \main_libresocsim_libresoc_constraintmanager1_uart0_rx connect \uart_tx__core__o \main_libresocsim_libresoc_constraintmanager0_uart0_tx connect \uart_tx__pad__o \main_libresocsim_libresoc_constraintmanager1_uart0_tx end attribute \src "ls180.v:0.0-0.0" - process $proc$ls180.v:0$3704 + process $proc$ls180.v:0$3701 sync always sync init end - attribute \src "ls180.v:10001.1-10005.4" - process $proc$ls180.v:10001$2698 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\storage$ls180.v:10003$5_ADDR[2:0]$2699 3'xxx - assign $0$memwr$\storage$ls180.v:10003$5_DATA[24:0]$2700 25'xxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\storage$ls180.v:10003$5_EN[24:0]$2701 25'0000000000000000000000000 - assign $0\memdat[24:0] $memrd$\storage$ls180.v:10004$2702_DATA - attribute \src "ls180.v:10002.2-10003.129" - switch \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:10002.6-10002.60" - case 1'1 - assign $0$memwr$\storage$ls180.v:10003$5_ADDR[2:0]$2699 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr - assign $0$memwr$\storage$ls180.v:10003$5_DATA[24:0]$2700 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w - assign $0$memwr$\storage$ls180.v:10003$5_EN[24:0]$2701 25'1111111111111111111111111 - case - end + attribute \src "ls180.v:10003.1-10004.4" + process $proc$ls180.v:10003$2701 sync posedge \sys_clk_1 - update \memdat $0\memdat[24:0] - update $memwr$\storage$ls180.v:10003$5_ADDR $0$memwr$\storage$ls180.v:10003$5_ADDR[2:0]$2699 - update $memwr$\storage$ls180.v:10003$5_DATA $0$memwr$\storage$ls180.v:10003$5_DATA[24:0]$2700 - update $memwr$\storage$ls180.v:10003$5_EN $0$memwr$\storage$ls180.v:10003$5_EN[24:0]$2701 end - attribute \src "ls180.v:10007.1-10008.4" - process $proc$ls180.v:10007$2703 - sync posedge \sys_clk_1 + attribute \src "ls180.v:1001.12-1001.37" + process $proc$ls180.v:1001$3150 + assign { } { } + assign $1\main_pwm0_counter[31:0] 0 + sync always + sync init + update \main_pwm0_counter $1\main_pwm0_counter[31:0] end - attribute \src "ls180.v:10015.1-10019.4" - process $proc$ls180.v:10015$2705 + attribute \src "ls180.v:10011.1-10015.4" + process $proc$ls180.v:10011$2703 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage_1$ls180.v:10017$6_ADDR[2:0]$2706 3'xxx - assign $0$memwr$\storage_1$ls180.v:10017$6_DATA[24:0]$2707 25'xxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\storage_1$ls180.v:10017$6_EN[24:0]$2708 25'0000000000000000000000000 - assign $0\memdat_1[24:0] $memrd$\storage_1$ls180.v:10018$2709_DATA - attribute \src "ls180.v:10016.2-10017.131" + assign $0$memwr$\storage_1$ls180.v:10013$6_ADDR[2:0]$2704 3'xxx + assign $0$memwr$\storage_1$ls180.v:10013$6_DATA[24:0]$2705 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage_1$ls180.v:10013$6_EN[24:0]$2706 25'0000000000000000000000000 + assign $0\memdat_1[24:0] $memrd$\storage_1$ls180.v:10014$2707_DATA + attribute \src "ls180.v:10012.2-10013.131" switch \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:10016.6-10016.60" + attribute \src "ls180.v:10012.6-10012.60" case 1'1 - assign $0$memwr$\storage_1$ls180.v:10017$6_ADDR[2:0]$2706 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr - assign $0$memwr$\storage_1$ls180.v:10017$6_DATA[24:0]$2707 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w - assign $0$memwr$\storage_1$ls180.v:10017$6_EN[24:0]$2708 25'1111111111111111111111111 + assign $0$memwr$\storage_1$ls180.v:10013$6_ADDR[2:0]$2704 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage_1$ls180.v:10013$6_DATA[24:0]$2705 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage_1$ls180.v:10013$6_EN[24:0]$2706 25'1111111111111111111111111 case end sync posedge \sys_clk_1 update \memdat_1 $0\memdat_1[24:0] - update $memwr$\storage_1$ls180.v:10017$6_ADDR $0$memwr$\storage_1$ls180.v:10017$6_ADDR[2:0]$2706 - update $memwr$\storage_1$ls180.v:10017$6_DATA $0$memwr$\storage_1$ls180.v:10017$6_DATA[24:0]$2707 - update $memwr$\storage_1$ls180.v:10017$6_EN $0$memwr$\storage_1$ls180.v:10017$6_EN[24:0]$2708 + update $memwr$\storage_1$ls180.v:10013$6_ADDR $0$memwr$\storage_1$ls180.v:10013$6_ADDR[2:0]$2704 + update $memwr$\storage_1$ls180.v:10013$6_DATA $0$memwr$\storage_1$ls180.v:10013$6_DATA[24:0]$2705 + update $memwr$\storage_1$ls180.v:10013$6_EN $0$memwr$\storage_1$ls180.v:10013$6_EN[24:0]$2706 + end + attribute \src "ls180.v:10017.1-10018.4" + process $proc$ls180.v:10017$2708 + sync posedge \sys_clk_1 end - attribute \src "ls180.v:1002.12-1002.37" - process $proc$ls180.v:1002$3153 + attribute \src "ls180.v:1002.5-1002.36" + process $proc$ls180.v:1002$3151 assign { } { } - assign $1\main_pwm0_counter[31:0] 0 + assign $1\main_pwm0_enable_storage[0:0] 1'0 sync always sync init - update \main_pwm0_counter $1\main_pwm0_counter[31:0] - end - attribute \src "ls180.v:10021.1-10022.4" - process $proc$ls180.v:10021$2710 - sync posedge \sys_clk_1 + update \main_pwm0_enable_storage $1\main_pwm0_enable_storage[0:0] end - attribute \src "ls180.v:10029.1-10033.4" - process $proc$ls180.v:10029$2712 + attribute \src "ls180.v:10025.1-10029.4" + process $proc$ls180.v:10025$2710 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage_2$ls180.v:10031$7_ADDR[2:0]$2713 3'xxx - assign $0$memwr$\storage_2$ls180.v:10031$7_DATA[24:0]$2714 25'xxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\storage_2$ls180.v:10031$7_EN[24:0]$2715 25'0000000000000000000000000 - assign $0\memdat_2[24:0] $memrd$\storage_2$ls180.v:10032$2716_DATA - attribute \src "ls180.v:10030.2-10031.131" + assign $0$memwr$\storage_2$ls180.v:10027$7_ADDR[2:0]$2711 3'xxx + assign $0$memwr$\storage_2$ls180.v:10027$7_DATA[24:0]$2712 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage_2$ls180.v:10027$7_EN[24:0]$2713 25'0000000000000000000000000 + assign $0\memdat_2[24:0] $memrd$\storage_2$ls180.v:10028$2714_DATA + attribute \src "ls180.v:10026.2-10027.131" switch \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:10030.6-10030.60" + attribute \src "ls180.v:10026.6-10026.60" case 1'1 - assign $0$memwr$\storage_2$ls180.v:10031$7_ADDR[2:0]$2713 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr - assign $0$memwr$\storage_2$ls180.v:10031$7_DATA[24:0]$2714 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w - assign $0$memwr$\storage_2$ls180.v:10031$7_EN[24:0]$2715 25'1111111111111111111111111 + assign $0$memwr$\storage_2$ls180.v:10027$7_ADDR[2:0]$2711 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage_2$ls180.v:10027$7_DATA[24:0]$2712 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage_2$ls180.v:10027$7_EN[24:0]$2713 25'1111111111111111111111111 case end sync posedge \sys_clk_1 update \memdat_2 $0\memdat_2[24:0] - update $memwr$\storage_2$ls180.v:10031$7_ADDR $0$memwr$\storage_2$ls180.v:10031$7_ADDR[2:0]$2713 - update $memwr$\storage_2$ls180.v:10031$7_DATA $0$memwr$\storage_2$ls180.v:10031$7_DATA[24:0]$2714 - update $memwr$\storage_2$ls180.v:10031$7_EN $0$memwr$\storage_2$ls180.v:10031$7_EN[24:0]$2715 - end - attribute \src "ls180.v:1003.5-1003.36" - process $proc$ls180.v:1003$3154 - assign { } { } - assign $1\main_pwm0_enable_storage[0:0] 1'0 - sync always - sync init - update \main_pwm0_enable_storage $1\main_pwm0_enable_storage[0:0] - end - attribute \src "ls180.v:10035.1-10036.4" - process $proc$ls180.v:10035$2717 - sync posedge \sys_clk_1 + update $memwr$\storage_2$ls180.v:10027$7_ADDR $0$memwr$\storage_2$ls180.v:10027$7_ADDR[2:0]$2711 + update $memwr$\storage_2$ls180.v:10027$7_DATA $0$memwr$\storage_2$ls180.v:10027$7_DATA[24:0]$2712 + update $memwr$\storage_2$ls180.v:10027$7_EN $0$memwr$\storage_2$ls180.v:10027$7_EN[24:0]$2713 end - attribute \src "ls180.v:1004.5-1004.31" - process $proc$ls180.v:1004$3155 + attribute \src "ls180.v:1003.5-1003.31" + process $proc$ls180.v:1003$3152 assign { } { } assign $1\main_pwm0_enable_re[0:0] 1'0 sync always sync init update \main_pwm0_enable_re $1\main_pwm0_enable_re[0:0] end - attribute \src "ls180.v:10043.1-10047.4" - process $proc$ls180.v:10043$2719 + attribute \src "ls180.v:10031.1-10032.4" + process $proc$ls180.v:10031$2715 + sync posedge \sys_clk_1 + end + attribute \src "ls180.v:10039.1-10043.4" + process $proc$ls180.v:10039$2717 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage_3$ls180.v:10045$8_ADDR[2:0]$2720 3'xxx - assign $0$memwr$\storage_3$ls180.v:10045$8_DATA[24:0]$2721 25'xxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\storage_3$ls180.v:10045$8_EN[24:0]$2722 25'0000000000000000000000000 - assign $0\memdat_3[24:0] $memrd$\storage_3$ls180.v:10046$2723_DATA - attribute \src "ls180.v:10044.2-10045.131" + assign $0$memwr$\storage_3$ls180.v:10041$8_ADDR[2:0]$2718 3'xxx + assign $0$memwr$\storage_3$ls180.v:10041$8_DATA[24:0]$2719 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage_3$ls180.v:10041$8_EN[24:0]$2720 25'0000000000000000000000000 + assign $0\memdat_3[24:0] $memrd$\storage_3$ls180.v:10042$2721_DATA + attribute \src "ls180.v:10040.2-10041.131" switch \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:10044.6-10044.60" + attribute \src "ls180.v:10040.6-10040.60" case 1'1 - assign $0$memwr$\storage_3$ls180.v:10045$8_ADDR[2:0]$2720 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr - assign $0$memwr$\storage_3$ls180.v:10045$8_DATA[24:0]$2721 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w - assign $0$memwr$\storage_3$ls180.v:10045$8_EN[24:0]$2722 25'1111111111111111111111111 + assign $0$memwr$\storage_3$ls180.v:10041$8_ADDR[2:0]$2718 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage_3$ls180.v:10041$8_DATA[24:0]$2719 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage_3$ls180.v:10041$8_EN[24:0]$2720 25'1111111111111111111111111 case end sync posedge \sys_clk_1 update \memdat_3 $0\memdat_3[24:0] - update $memwr$\storage_3$ls180.v:10045$8_ADDR $0$memwr$\storage_3$ls180.v:10045$8_ADDR[2:0]$2720 - update $memwr$\storage_3$ls180.v:10045$8_DATA $0$memwr$\storage_3$ls180.v:10045$8_DATA[24:0]$2721 - update $memwr$\storage_3$ls180.v:10045$8_EN $0$memwr$\storage_3$ls180.v:10045$8_EN[24:0]$2722 - end - attribute \src "ls180.v:10049.1-10050.4" - process $proc$ls180.v:10049$2724 - sync posedge \sys_clk_1 + update $memwr$\storage_3$ls180.v:10041$8_ADDR $0$memwr$\storage_3$ls180.v:10041$8_ADDR[2:0]$2718 + update $memwr$\storage_3$ls180.v:10041$8_DATA $0$memwr$\storage_3$ls180.v:10041$8_DATA[24:0]$2719 + update $memwr$\storage_3$ls180.v:10041$8_EN $0$memwr$\storage_3$ls180.v:10041$8_EN[24:0]$2720 end - attribute \src "ls180.v:1005.12-1005.43" - process $proc$ls180.v:1005$3156 + attribute \src "ls180.v:1004.12-1004.43" + process $proc$ls180.v:1004$3153 assign { } { } assign $1\main_pwm0_width_storage[31:0] 0 sync always sync init update \main_pwm0_width_storage $1\main_pwm0_width_storage[31:0] end - attribute \src "ls180.v:10058.1-10062.4" - process $proc$ls180.v:10058$2726 + attribute \src "ls180.v:10045.1-10046.4" + process $proc$ls180.v:10045$2722 + sync posedge \sys_clk_1 + end + attribute \src "ls180.v:1005.5-1005.30" + process $proc$ls180.v:1005$3154 + assign { } { } + assign $1\main_pwm0_width_re[0:0] 1'0 + sync always + sync init + update \main_pwm0_width_re $1\main_pwm0_width_re[0:0] + end + attribute \src "ls180.v:10054.1-10058.4" + process $proc$ls180.v:10054$2724 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage_4$ls180.v:10060$9_ADDR[3:0]$2727 4'xxxx - assign $0$memwr$\storage_4$ls180.v:10060$9_DATA[9:0]$2728 10'xxxxxxxxxx - assign $0$memwr$\storage_4$ls180.v:10060$9_EN[9:0]$2729 10'0000000000 - assign $0\memdat_4[9:0] $memrd$\storage_4$ls180.v:10061$2730_DATA - attribute \src "ls180.v:10059.2-10060.77" + assign $0$memwr$\storage_4$ls180.v:10056$9_ADDR[3:0]$2725 4'xxxx + assign $0$memwr$\storage_4$ls180.v:10056$9_DATA[9:0]$2726 10'xxxxxxxxxx + assign $0$memwr$\storage_4$ls180.v:10056$9_EN[9:0]$2727 10'0000000000 + assign $0\memdat_4[9:0] $memrd$\storage_4$ls180.v:10057$2728_DATA + attribute \src "ls180.v:10055.2-10056.77" switch \main_uart_tx_fifo_wrport_we - attribute \src "ls180.v:10059.6-10059.33" + attribute \src "ls180.v:10055.6-10055.33" case 1'1 - assign $0$memwr$\storage_4$ls180.v:10060$9_ADDR[3:0]$2727 \main_uart_tx_fifo_wrport_adr - assign $0$memwr$\storage_4$ls180.v:10060$9_DATA[9:0]$2728 \main_uart_tx_fifo_wrport_dat_w - assign $0$memwr$\storage_4$ls180.v:10060$9_EN[9:0]$2729 10'1111111111 + assign $0$memwr$\storage_4$ls180.v:10056$9_ADDR[3:0]$2725 \main_uart_tx_fifo_wrport_adr + assign $0$memwr$\storage_4$ls180.v:10056$9_DATA[9:0]$2726 \main_uart_tx_fifo_wrport_dat_w + assign $0$memwr$\storage_4$ls180.v:10056$9_EN[9:0]$2727 10'1111111111 case end sync posedge \sys_clk_1 update \memdat_4 $0\memdat_4[9:0] - update $memwr$\storage_4$ls180.v:10060$9_ADDR $0$memwr$\storage_4$ls180.v:10060$9_ADDR[3:0]$2727 - update $memwr$\storage_4$ls180.v:10060$9_DATA $0$memwr$\storage_4$ls180.v:10060$9_DATA[9:0]$2728 - update $memwr$\storage_4$ls180.v:10060$9_EN $0$memwr$\storage_4$ls180.v:10060$9_EN[9:0]$2729 + update $memwr$\storage_4$ls180.v:10056$9_ADDR $0$memwr$\storage_4$ls180.v:10056$9_ADDR[3:0]$2725 + update $memwr$\storage_4$ls180.v:10056$9_DATA $0$memwr$\storage_4$ls180.v:10056$9_DATA[9:0]$2726 + update $memwr$\storage_4$ls180.v:10056$9_EN $0$memwr$\storage_4$ls180.v:10056$9_EN[9:0]$2727 end - attribute \src "ls180.v:1006.5-1006.30" - process $proc$ls180.v:1006$3157 + attribute \src "ls180.v:1006.12-1006.44" + process $proc$ls180.v:1006$3155 assign { } { } - assign $1\main_pwm0_width_re[0:0] 1'0 + assign $1\main_pwm0_period_storage[31:0] 0 sync always sync init - update \main_pwm0_width_re $1\main_pwm0_width_re[0:0] + update \main_pwm0_period_storage $1\main_pwm0_period_storage[31:0] end - attribute \src "ls180.v:10064.1-10067.4" - process $proc$ls180.v:10064$2731 + attribute \src "ls180.v:10060.1-10063.4" + process $proc$ls180.v:10060$2729 assign $0\memdat_5[9:0] \memdat_5 - attribute \src "ls180.v:10065.2-10066.55" + attribute \src "ls180.v:10061.2-10062.55" switch \main_uart_tx_fifo_rdport_re - attribute \src "ls180.v:10065.6-10065.33" + attribute \src "ls180.v:10061.6-10061.33" case 1'1 - assign $0\memdat_5[9:0] $memrd$\storage_4$ls180.v:10066$2732_DATA + assign $0\memdat_5[9:0] $memrd$\storage_4$ls180.v:10062$2730_DATA case end sync posedge \sys_clk_1 update \memdat_5 $0\memdat_5[9:0] end - attribute \src "ls180.v:1007.12-1007.44" - process $proc$ls180.v:1007$3158 + attribute \src "ls180.v:1007.5-1007.31" + process $proc$ls180.v:1007$3156 assign { } { } - assign $1\main_pwm0_period_storage[31:0] 0 + assign $1\main_pwm0_period_re[0:0] 1'0 sync always sync init - update \main_pwm0_period_storage $1\main_pwm0_period_storage[31:0] + update \main_pwm0_period_re $1\main_pwm0_period_re[0:0] end - attribute \src "ls180.v:10075.1-10079.4" - process $proc$ls180.v:10075$2733 + attribute \src "ls180.v:10071.1-10075.4" + process $proc$ls180.v:10071$2731 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage_5$ls180.v:10077$10_ADDR[3:0]$2734 4'xxxx - assign $0$memwr$\storage_5$ls180.v:10077$10_DATA[9:0]$2735 10'xxxxxxxxxx - assign $0$memwr$\storage_5$ls180.v:10077$10_EN[9:0]$2736 10'0000000000 - assign $0\memdat_6[9:0] $memrd$\storage_5$ls180.v:10078$2737_DATA - attribute \src "ls180.v:10076.2-10077.77" + assign $0$memwr$\storage_5$ls180.v:10073$10_ADDR[3:0]$2732 4'xxxx + assign $0$memwr$\storage_5$ls180.v:10073$10_DATA[9:0]$2733 10'xxxxxxxxxx + assign $0$memwr$\storage_5$ls180.v:10073$10_EN[9:0]$2734 10'0000000000 + assign $0\memdat_6[9:0] $memrd$\storage_5$ls180.v:10074$2735_DATA + attribute \src "ls180.v:10072.2-10073.77" switch \main_uart_rx_fifo_wrport_we - attribute \src "ls180.v:10076.6-10076.33" + attribute \src "ls180.v:10072.6-10072.33" case 1'1 - assign $0$memwr$\storage_5$ls180.v:10077$10_ADDR[3:0]$2734 \main_uart_rx_fifo_wrport_adr - assign $0$memwr$\storage_5$ls180.v:10077$10_DATA[9:0]$2735 \main_uart_rx_fifo_wrport_dat_w - assign $0$memwr$\storage_5$ls180.v:10077$10_EN[9:0]$2736 10'1111111111 + assign $0$memwr$\storage_5$ls180.v:10073$10_ADDR[3:0]$2732 \main_uart_rx_fifo_wrport_adr + assign $0$memwr$\storage_5$ls180.v:10073$10_DATA[9:0]$2733 \main_uart_rx_fifo_wrport_dat_w + assign $0$memwr$\storage_5$ls180.v:10073$10_EN[9:0]$2734 10'1111111111 case end sync posedge \sys_clk_1 update \memdat_6 $0\memdat_6[9:0] - update $memwr$\storage_5$ls180.v:10077$10_ADDR $0$memwr$\storage_5$ls180.v:10077$10_ADDR[3:0]$2734 - update $memwr$\storage_5$ls180.v:10077$10_DATA $0$memwr$\storage_5$ls180.v:10077$10_DATA[9:0]$2735 - update $memwr$\storage_5$ls180.v:10077$10_EN $0$memwr$\storage_5$ls180.v:10077$10_EN[9:0]$2736 - end - attribute \src "ls180.v:1008.5-1008.31" - process $proc$ls180.v:1008$3159 - assign { } { } - assign $1\main_pwm0_period_re[0:0] 1'0 - sync always - sync init - update \main_pwm0_period_re $1\main_pwm0_period_re[0:0] + update $memwr$\storage_5$ls180.v:10073$10_ADDR $0$memwr$\storage_5$ls180.v:10073$10_ADDR[3:0]$2732 + update $memwr$\storage_5$ls180.v:10073$10_DATA $0$memwr$\storage_5$ls180.v:10073$10_DATA[9:0]$2733 + update $memwr$\storage_5$ls180.v:10073$10_EN $0$memwr$\storage_5$ls180.v:10073$10_EN[9:0]$2734 end - attribute \src "ls180.v:10081.1-10084.4" - process $proc$ls180.v:10081$2738 + attribute \src "ls180.v:10077.1-10080.4" + process $proc$ls180.v:10077$2736 assign $0\memdat_7[9:0] \memdat_7 - attribute \src "ls180.v:10082.2-10083.55" + attribute \src "ls180.v:10078.2-10079.55" switch \main_uart_rx_fifo_rdport_re - attribute \src "ls180.v:10082.6-10082.33" + attribute \src "ls180.v:10078.6-10078.33" case 1'1 - assign $0\memdat_7[9:0] $memrd$\storage_5$ls180.v:10083$2739_DATA + assign $0\memdat_7[9:0] $memrd$\storage_5$ls180.v:10079$2737_DATA case end sync posedge \sys_clk_1 update \memdat_7 $0\memdat_7[9:0] end - attribute \src "ls180.v:10091.1-10095.4" - process $proc$ls180.v:10091$2740 + attribute \src "ls180.v:10087.1-10091.4" + process $proc$ls180.v:10087$2738 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage_6$ls180.v:10093$11_ADDR[4:0]$2741 5'xxxxx - assign $0$memwr$\storage_6$ls180.v:10093$11_DATA[9:0]$2742 10'xxxxxxxxxx - assign $0$memwr$\storage_6$ls180.v:10093$11_EN[9:0]$2743 10'0000000000 - assign $0\memdat_8[9:0] $memrd$\storage_6$ls180.v:10094$2744_DATA - attribute \src "ls180.v:10092.2-10093.85" + assign $0$memwr$\storage_6$ls180.v:10089$11_ADDR[4:0]$2739 5'xxxxx + assign $0$memwr$\storage_6$ls180.v:10089$11_DATA[9:0]$2740 10'xxxxxxxxxx + assign $0$memwr$\storage_6$ls180.v:10089$11_EN[9:0]$2741 10'0000000000 + assign $0\memdat_8[9:0] $memrd$\storage_6$ls180.v:10090$2742_DATA + attribute \src "ls180.v:10088.2-10089.85" switch \main_sdblock2mem_fifo_wrport_we - attribute \src "ls180.v:10092.6-10092.37" + attribute \src "ls180.v:10088.6-10088.37" case 1'1 - assign $0$memwr$\storage_6$ls180.v:10093$11_ADDR[4:0]$2741 \main_sdblock2mem_fifo_wrport_adr - assign $0$memwr$\storage_6$ls180.v:10093$11_DATA[9:0]$2742 \main_sdblock2mem_fifo_wrport_dat_w - assign $0$memwr$\storage_6$ls180.v:10093$11_EN[9:0]$2743 10'1111111111 + assign $0$memwr$\storage_6$ls180.v:10089$11_ADDR[4:0]$2739 \main_sdblock2mem_fifo_wrport_adr + assign $0$memwr$\storage_6$ls180.v:10089$11_DATA[9:0]$2740 \main_sdblock2mem_fifo_wrport_dat_w + assign $0$memwr$\storage_6$ls180.v:10089$11_EN[9:0]$2741 10'1111111111 case end sync posedge \sys_clk_1 update \memdat_8 $0\memdat_8[9:0] - update $memwr$\storage_6$ls180.v:10093$11_ADDR $0$memwr$\storage_6$ls180.v:10093$11_ADDR[4:0]$2741 - update $memwr$\storage_6$ls180.v:10093$11_DATA $0$memwr$\storage_6$ls180.v:10093$11_DATA[9:0]$2742 - update $memwr$\storage_6$ls180.v:10093$11_EN $0$memwr$\storage_6$ls180.v:10093$11_EN[9:0]$2743 + update $memwr$\storage_6$ls180.v:10089$11_ADDR $0$memwr$\storage_6$ls180.v:10089$11_ADDR[4:0]$2739 + update $memwr$\storage_6$ls180.v:10089$11_DATA $0$memwr$\storage_6$ls180.v:10089$11_DATA[9:0]$2740 + update $memwr$\storage_6$ls180.v:10089$11_EN $0$memwr$\storage_6$ls180.v:10089$11_EN[9:0]$2741 end - attribute \src "ls180.v:10097.1-10098.4" - process $proc$ls180.v:10097$2745 + attribute \src "ls180.v:10093.1-10094.4" + process $proc$ls180.v:10093$2743 sync posedge \sys_clk_1 end - attribute \src "ls180.v:10105.1-10109.4" - process $proc$ls180.v:10105$2747 + attribute \src "ls180.v:10101.1-10105.4" + process $proc$ls180.v:10101$2745 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage_7$ls180.v:10107$12_ADDR[4:0]$2748 5'xxxxx - assign $0$memwr$\storage_7$ls180.v:10107$12_DATA[9:0]$2749 10'xxxxxxxxxx - assign $0$memwr$\storage_7$ls180.v:10107$12_EN[9:0]$2750 10'0000000000 - assign $0\memdat_9[9:0] $memrd$\storage_7$ls180.v:10108$2751_DATA - attribute \src "ls180.v:10106.2-10107.85" + assign $0$memwr$\storage_7$ls180.v:10103$12_ADDR[4:0]$2746 5'xxxxx + assign $0$memwr$\storage_7$ls180.v:10103$12_DATA[9:0]$2747 10'xxxxxxxxxx + assign $0$memwr$\storage_7$ls180.v:10103$12_EN[9:0]$2748 10'0000000000 + assign $0\memdat_9[9:0] $memrd$\storage_7$ls180.v:10104$2749_DATA + attribute \src "ls180.v:10102.2-10103.85" switch \main_sdmem2block_fifo_wrport_we - attribute \src "ls180.v:10106.6-10106.37" + attribute \src "ls180.v:10102.6-10102.37" case 1'1 - assign $0$memwr$\storage_7$ls180.v:10107$12_ADDR[4:0]$2748 \main_sdmem2block_fifo_wrport_adr - assign $0$memwr$\storage_7$ls180.v:10107$12_DATA[9:0]$2749 \main_sdmem2block_fifo_wrport_dat_w - assign $0$memwr$\storage_7$ls180.v:10107$12_EN[9:0]$2750 10'1111111111 + assign $0$memwr$\storage_7$ls180.v:10103$12_ADDR[4:0]$2746 \main_sdmem2block_fifo_wrport_adr + assign $0$memwr$\storage_7$ls180.v:10103$12_DATA[9:0]$2747 \main_sdmem2block_fifo_wrport_dat_w + assign $0$memwr$\storage_7$ls180.v:10103$12_EN[9:0]$2748 10'1111111111 case end sync posedge \sys_clk_1 update \memdat_9 $0\memdat_9[9:0] - update $memwr$\storage_7$ls180.v:10107$12_ADDR $0$memwr$\storage_7$ls180.v:10107$12_ADDR[4:0]$2748 - update $memwr$\storage_7$ls180.v:10107$12_DATA $0$memwr$\storage_7$ls180.v:10107$12_DATA[9:0]$2749 - update $memwr$\storage_7$ls180.v:10107$12_EN $0$memwr$\storage_7$ls180.v:10107$12_EN[9:0]$2750 + update $memwr$\storage_7$ls180.v:10103$12_ADDR $0$memwr$\storage_7$ls180.v:10103$12_ADDR[4:0]$2746 + update $memwr$\storage_7$ls180.v:10103$12_DATA $0$memwr$\storage_7$ls180.v:10103$12_DATA[9:0]$2747 + update $memwr$\storage_7$ls180.v:10103$12_EN $0$memwr$\storage_7$ls180.v:10103$12_EN[9:0]$2748 end - attribute \src "ls180.v:10111.1-10112.4" - process $proc$ls180.v:10111$2752 + attribute \src "ls180.v:10107.1-10108.4" + process $proc$ls180.v:10107$2750 sync posedge \sys_clk_1 end - attribute \src "ls180.v:1012.12-1012.37" - process $proc$ls180.v:1012$3160 + attribute \src "ls180.v:1011.12-1011.37" + process $proc$ls180.v:1011$3157 assign { } { } assign $1\main_pwm1_counter[31:0] 0 sync always sync init update \main_pwm1_counter $1\main_pwm1_counter[31:0] end - attribute \src "ls180.v:1013.5-1013.36" - process $proc$ls180.v:1013$3161 + attribute \src "ls180.v:1012.5-1012.36" + process $proc$ls180.v:1012$3158 assign { } { } assign $1\main_pwm1_enable_storage[0:0] 1'0 sync always sync init update \main_pwm1_enable_storage $1\main_pwm1_enable_storage[0:0] end - attribute \src "ls180.v:1014.5-1014.31" - process $proc$ls180.v:1014$3162 + attribute \src "ls180.v:1013.5-1013.31" + process $proc$ls180.v:1013$3159 assign { } { } assign $1\main_pwm1_enable_re[0:0] 1'0 sync always sync init update \main_pwm1_enable_re $1\main_pwm1_enable_re[0:0] end - attribute \src "ls180.v:1015.12-1015.43" - process $proc$ls180.v:1015$3163 + attribute \src "ls180.v:1014.12-1014.43" + process $proc$ls180.v:1014$3160 assign { } { } assign $1\main_pwm1_width_storage[31:0] 0 sync always sync init update \main_pwm1_width_storage $1\main_pwm1_width_storage[31:0] end - attribute \src "ls180.v:1016.5-1016.30" - process $proc$ls180.v:1016$3164 + attribute \src "ls180.v:1015.5-1015.30" + process $proc$ls180.v:1015$3161 assign { } { } assign $1\main_pwm1_width_re[0:0] 1'0 sync always sync init update \main_pwm1_width_re $1\main_pwm1_width_re[0:0] end - attribute \src "ls180.v:1017.12-1017.44" - process $proc$ls180.v:1017$3165 + attribute \src "ls180.v:1016.12-1016.44" + process $proc$ls180.v:1016$3162 assign { } { } assign $1\main_pwm1_period_storage[31:0] 0 sync always sync init update \main_pwm1_period_storage $1\main_pwm1_period_storage[31:0] end - attribute \src "ls180.v:1018.5-1018.31" - process $proc$ls180.v:1018$3166 + attribute \src "ls180.v:1017.5-1017.31" + process $proc$ls180.v:1017$3163 assign { } { } assign $1\main_pwm1_period_re[0:0] 1'0 sync always sync init update \main_pwm1_period_re $1\main_pwm1_period_re[0:0] end - attribute \src "ls180.v:1021.11-1021.46" - process $proc$ls180.v:1021$3167 + attribute \src "ls180.v:1020.11-1020.46" + process $proc$ls180.v:1020$3164 assign { } { } assign $1\main_sdphy_clocker_storage[8:0] 9'100000000 sync always sync init update \main_sdphy_clocker_storage $1\main_sdphy_clocker_storage[8:0] end - attribute \src "ls180.v:1022.5-1022.33" - process $proc$ls180.v:1022$3168 + attribute \src "ls180.v:1021.5-1021.33" + process $proc$ls180.v:1021$3165 assign { } { } assign $1\main_sdphy_clocker_re[0:0] 1'0 sync always sync init update \main_sdphy_clocker_re $1\main_sdphy_clocker_re[0:0] end - attribute \src "ls180.v:1024.5-1024.35" - process $proc$ls180.v:1024$3169 + attribute \src "ls180.v:1023.5-1023.35" + process $proc$ls180.v:1023$3166 assign { } { } assign $1\main_sdphy_clocker_clk0[0:0] 1'0 sync always sync init update \main_sdphy_clocker_clk0 $1\main_sdphy_clocker_clk0[0:0] end - attribute \src "ls180.v:1026.11-1026.41" - process $proc$ls180.v:1026$3170 + attribute \src "ls180.v:1025.11-1025.41" + process $proc$ls180.v:1025$3167 assign { } { } assign $1\main_sdphy_clocker_clks[8:0] 9'000000000 sync always sync init update \main_sdphy_clocker_clks $1\main_sdphy_clocker_clks[8:0] end - attribute \src "ls180.v:1027.5-1027.35" - process $proc$ls180.v:1027$3171 + attribute \src "ls180.v:1026.5-1026.35" + process $proc$ls180.v:1026$3168 assign { } { } assign $1\main_sdphy_clocker_clk1[0:0] 1'0 sync always sync init update \main_sdphy_clocker_clk1 $1\main_sdphy_clocker_clk1[0:0] end - attribute \src "ls180.v:1028.5-1028.36" - process $proc$ls180.v:1028$3172 + attribute \src "ls180.v:1027.5-1027.36" + process $proc$ls180.v:1027$3169 assign { } { } assign $1\main_sdphy_clocker_clk_d[0:0] 1'0 sync always sync init update \main_sdphy_clocker_clk_d $1\main_sdphy_clocker_clk_d[0:0] end - attribute \src "ls180.v:1032.5-1032.40" - process $proc$ls180.v:1032$3173 + attribute \src "ls180.v:1031.5-1031.40" + process $proc$ls180.v:1031$3170 assign { } { } assign $0\main_sdphy_init_initialize_w[0:0] 1'0 sync always update \main_sdphy_init_initialize_w $0\main_sdphy_init_initialize_w[0:0] sync init end - attribute \src "ls180.v:1037.5-1037.48" - process $proc$ls180.v:1037$3174 + attribute \src "ls180.v:1036.5-1036.48" + process $proc$ls180.v:1036$3171 assign { } { } assign $1\main_sdphy_init_pads_out_payload_clk[0:0] 1'0 sync always sync init update \main_sdphy_init_pads_out_payload_clk $1\main_sdphy_init_pads_out_payload_clk[0:0] end - attribute \src "ls180.v:1038.5-1038.50" - process $proc$ls180.v:1038$3175 + attribute \src "ls180.v:1037.5-1037.50" + process $proc$ls180.v:1037$3172 assign { } { } assign $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'0 sync always sync init update \main_sdphy_init_pads_out_payload_cmd_o $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] end - attribute \src "ls180.v:1039.5-1039.51" - process $proc$ls180.v:1039$3176 + attribute \src "ls180.v:1038.5-1038.51" + process $proc$ls180.v:1038$3173 assign { } { } assign $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'0 sync always sync init update \main_sdphy_init_pads_out_payload_cmd_oe $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] end - attribute \src "ls180.v:1040.11-1040.57" - process $proc$ls180.v:1040$3177 + attribute \src "ls180.v:1039.11-1039.57" + process $proc$ls180.v:1039$3174 assign { } { } assign $1\main_sdphy_init_pads_out_payload_data_o[3:0] 4'0000 sync always sync init update \main_sdphy_init_pads_out_payload_data_o $1\main_sdphy_init_pads_out_payload_data_o[3:0] end - attribute \src "ls180.v:1041.5-1041.52" - process $proc$ls180.v:1041$3178 + attribute \src "ls180.v:1040.5-1040.52" + process $proc$ls180.v:1040$3175 assign { } { } assign $1\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'0 sync always sync init update \main_sdphy_init_pads_out_payload_data_oe $1\main_sdphy_init_pads_out_payload_data_oe[0:0] end - attribute \src "ls180.v:1042.11-1042.39" - process $proc$ls180.v:1042$3179 + attribute \src "ls180.v:1041.11-1041.39" + process $proc$ls180.v:1041$3176 assign { } { } assign $1\main_sdphy_init_count[7:0] 8'00000000 sync always sync init update \main_sdphy_init_count $1\main_sdphy_init_count[7:0] end - attribute \src "ls180.v:1047.5-1047.48" - process $proc$ls180.v:1047$3180 + attribute \src "ls180.v:1046.5-1046.48" + process $proc$ls180.v:1046$3177 assign { } { } assign $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'0 sync always sync init update \main_sdphy_cmdw_pads_out_payload_clk $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] end - attribute \src "ls180.v:1048.5-1048.50" - process $proc$ls180.v:1048$3181 + attribute \src "ls180.v:1047.5-1047.50" + process $proc$ls180.v:1047$3178 assign { } { } assign $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'0 sync always sync init update \main_sdphy_cmdw_pads_out_payload_cmd_o $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] end - attribute \src "ls180.v:1049.5-1049.51" - process $proc$ls180.v:1049$3182 + attribute \src "ls180.v:1048.5-1048.51" + process $proc$ls180.v:1048$3179 assign { } { } assign $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'0 sync always sync init update \main_sdphy_cmdw_pads_out_payload_cmd_oe $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] end - attribute \src "ls180.v:1050.11-1050.57" - process $proc$ls180.v:1050$3183 + attribute \src "ls180.v:1049.11-1049.57" + process $proc$ls180.v:1049$3180 assign { } { } assign $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] 4'0000 sync always update \main_sdphy_cmdw_pads_out_payload_data_o $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] sync init end - attribute \src "ls180.v:1051.5-1051.52" - process $proc$ls180.v:1051$3184 + attribute \src "ls180.v:1050.5-1050.52" + process $proc$ls180.v:1050$3181 assign { } { } assign $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] 1'0 sync always update \main_sdphy_cmdw_pads_out_payload_data_oe $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] sync init end - attribute \src "ls180.v:1052.5-1052.38" - process $proc$ls180.v:1052$3185 + attribute \src "ls180.v:1051.5-1051.38" + process $proc$ls180.v:1051$3182 assign { } { } assign $1\main_sdphy_cmdw_sink_valid[0:0] 1'0 sync always sync init update \main_sdphy_cmdw_sink_valid $1\main_sdphy_cmdw_sink_valid[0:0] end - attribute \src "ls180.v:1053.5-1053.38" - process $proc$ls180.v:1053$3186 + attribute \src "ls180.v:1052.5-1052.38" + process $proc$ls180.v:1052$3183 assign { } { } assign $1\main_sdphy_cmdw_sink_ready[0:0] 1'0 sync always sync init update \main_sdphy_cmdw_sink_ready $1\main_sdphy_cmdw_sink_ready[0:0] end - attribute \src "ls180.v:1054.5-1054.37" - process $proc$ls180.v:1054$3187 + attribute \src "ls180.v:1053.5-1053.37" + process $proc$ls180.v:1053$3184 assign { } { } assign $1\main_sdphy_cmdw_sink_last[0:0] 1'0 sync always sync init update \main_sdphy_cmdw_sink_last $1\main_sdphy_cmdw_sink_last[0:0] end - attribute \src "ls180.v:1055.11-1055.51" - process $proc$ls180.v:1055$3188 + attribute \src "ls180.v:1054.11-1054.51" + process $proc$ls180.v:1054$3185 assign { } { } assign $1\main_sdphy_cmdw_sink_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_cmdw_sink_payload_data $1\main_sdphy_cmdw_sink_payload_data[7:0] end - attribute \src "ls180.v:1056.5-1056.32" - process $proc$ls180.v:1056$3189 + attribute \src "ls180.v:1055.5-1055.32" + process $proc$ls180.v:1055$3186 assign { } { } assign $1\main_sdphy_cmdw_done[0:0] 1'0 sync always sync init update \main_sdphy_cmdw_done $1\main_sdphy_cmdw_done[0:0] end - attribute \src "ls180.v:1057.11-1057.39" - process $proc$ls180.v:1057$3190 + attribute \src "ls180.v:1056.11-1056.39" + process $proc$ls180.v:1056$3187 assign { } { } assign $1\main_sdphy_cmdw_count[7:0] 8'00000000 sync always sync init update \main_sdphy_cmdw_count $1\main_sdphy_cmdw_count[7:0] end - attribute \src "ls180.v:1060.5-1060.49" - process $proc$ls180.v:1060$3191 + attribute \src "ls180.v:1059.5-1059.49" + process $proc$ls180.v:1059$3188 assign { } { } assign $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] 1'0 sync always update \main_sdphy_cmdr_pads_in_pads_in_first $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] sync init end - attribute \src "ls180.v:1061.5-1061.48" - process $proc$ls180.v:1061$3192 + attribute \src "ls180.v:1060.5-1060.48" + process $proc$ls180.v:1060$3189 assign { } { } assign $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] 1'0 sync always update \main_sdphy_cmdr_pads_in_pads_in_last $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] sync init end - attribute \src "ls180.v:1062.5-1062.55" - process $proc$ls180.v:1062$3193 + attribute \src "ls180.v:1061.5-1061.55" + process $proc$ls180.v:1061$3190 assign { } { } assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] 1'0 sync always update \main_sdphy_cmdr_pads_in_pads_in_payload_clk $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] sync init end - attribute \src "ls180.v:1064.5-1064.57" - process $proc$ls180.v:1064$3194 + attribute \src "ls180.v:1063.5-1063.57" + process $proc$ls180.v:1063$3191 assign { } { } assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] 1'0 sync always update \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] sync init end - attribute \src "ls180.v:1065.5-1065.58" - process $proc$ls180.v:1065$3195 + attribute \src "ls180.v:1064.5-1064.58" + process $proc$ls180.v:1064$3192 assign { } { } assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 sync always update \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] sync init end - attribute \src "ls180.v:1067.11-1067.64" - process $proc$ls180.v:1067$3196 + attribute \src "ls180.v:1066.11-1066.64" + process $proc$ls180.v:1066$3193 assign { } { } assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] 4'0000 sync always update \main_sdphy_cmdr_pads_in_pads_in_payload_data_o $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] sync init end - attribute \src "ls180.v:1068.5-1068.59" - process $proc$ls180.v:1068$3197 + attribute \src "ls180.v:1067.5-1067.59" + process $proc$ls180.v:1067$3194 assign { } { } assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] 1'0 sync always update \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] sync init end - attribute \src "ls180.v:1070.5-1070.48" - process $proc$ls180.v:1070$3198 + attribute \src "ls180.v:1069.5-1069.48" + process $proc$ls180.v:1069$3195 assign { } { } assign $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_pads_out_payload_clk $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] end - attribute \src "ls180.v:1071.5-1071.50" - process $proc$ls180.v:1071$3199 + attribute \src "ls180.v:1070.5-1070.50" + process $proc$ls180.v:1070$3196 assign { } { } assign $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_pads_out_payload_cmd_o $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] end - attribute \src "ls180.v:1072.5-1072.51" - process $proc$ls180.v:1072$3200 + attribute \src "ls180.v:1071.5-1071.51" + process $proc$ls180.v:1071$3197 assign { } { } assign $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_pads_out_payload_cmd_oe $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] end - attribute \src "ls180.v:1073.11-1073.57" - process $proc$ls180.v:1073$3201 + attribute \src "ls180.v:1072.11-1072.57" + process $proc$ls180.v:1072$3198 assign { } { } assign $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] 4'0000 sync always update \main_sdphy_cmdr_pads_out_payload_data_o $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] sync init end - attribute \src "ls180.v:1074.5-1074.52" - process $proc$ls180.v:1074$3202 + attribute \src "ls180.v:1073.5-1073.52" + process $proc$ls180.v:1073$3199 assign { } { } assign $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] 1'0 sync always update \main_sdphy_cmdr_pads_out_payload_data_oe $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] sync init end - attribute \src "ls180.v:1075.5-1075.38" - process $proc$ls180.v:1075$3203 + attribute \src "ls180.v:1074.5-1074.38" + process $proc$ls180.v:1074$3200 assign { } { } assign $1\main_sdphy_cmdr_sink_valid[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_sink_valid $1\main_sdphy_cmdr_sink_valid[0:0] end - attribute \src "ls180.v:1076.5-1076.38" - process $proc$ls180.v:1076$3204 + attribute \src "ls180.v:1075.5-1075.38" + process $proc$ls180.v:1075$3201 assign { } { } assign $1\main_sdphy_cmdr_sink_ready[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_sink_ready $1\main_sdphy_cmdr_sink_ready[0:0] end - attribute \src "ls180.v:1077.5-1077.37" - process $proc$ls180.v:1077$3205 + attribute \src "ls180.v:1076.5-1076.37" + process $proc$ls180.v:1076$3202 assign { } { } assign $1\main_sdphy_cmdr_sink_last[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_sink_last $1\main_sdphy_cmdr_sink_last[0:0] end - attribute \src "ls180.v:1078.11-1078.53" - process $proc$ls180.v:1078$3206 + attribute \src "ls180.v:1077.11-1077.53" + process $proc$ls180.v:1077$3203 assign { } { } assign $1\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000000 sync always sync init update \main_sdphy_cmdr_sink_payload_length $1\main_sdphy_cmdr_sink_payload_length[7:0] end - attribute \src "ls180.v:1079.5-1079.40" - process $proc$ls180.v:1079$3207 + attribute \src "ls180.v:1078.5-1078.40" + process $proc$ls180.v:1078$3204 assign { } { } assign $1\main_sdphy_cmdr_source_valid[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_source_valid $1\main_sdphy_cmdr_source_valid[0:0] end - attribute \src "ls180.v:1080.5-1080.40" - process $proc$ls180.v:1080$3208 + attribute \src "ls180.v:1079.5-1079.40" + process $proc$ls180.v:1079$3205 assign { } { } assign $1\main_sdphy_cmdr_source_ready[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_source_ready $1\main_sdphy_cmdr_source_ready[0:0] end - attribute \src "ls180.v:1081.5-1081.39" - process $proc$ls180.v:1081$3209 + attribute \src "ls180.v:1080.5-1080.39" + process $proc$ls180.v:1080$3206 assign { } { } assign $1\main_sdphy_cmdr_source_last[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_source_last $1\main_sdphy_cmdr_source_last[0:0] end - attribute \src "ls180.v:1082.11-1082.53" - process $proc$ls180.v:1082$3210 + attribute \src "ls180.v:1081.11-1081.53" + process $proc$ls180.v:1081$3207 assign { } { } assign $1\main_sdphy_cmdr_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_cmdr_source_payload_data $1\main_sdphy_cmdr_source_payload_data[7:0] end - attribute \src "ls180.v:1083.11-1083.55" - process $proc$ls180.v:1083$3211 + attribute \src "ls180.v:1082.11-1082.55" + process $proc$ls180.v:1082$3208 assign { } { } assign $1\main_sdphy_cmdr_source_payload_status[2:0] 3'000 sync always sync init update \main_sdphy_cmdr_source_payload_status $1\main_sdphy_cmdr_source_payload_status[2:0] end - attribute \src "ls180.v:1084.12-1084.48" - process $proc$ls180.v:1084$3212 + attribute \src "ls180.v:1083.12-1083.48" + process $proc$ls180.v:1083$3209 assign { } { } assign $1\main_sdphy_cmdr_timeout[31:0] 500000 sync always sync init update \main_sdphy_cmdr_timeout $1\main_sdphy_cmdr_timeout[31:0] end - attribute \src "ls180.v:1085.11-1085.39" - process $proc$ls180.v:1085$3213 + attribute \src "ls180.v:1084.11-1084.39" + process $proc$ls180.v:1084$3210 assign { } { } assign $1\main_sdphy_cmdr_count[7:0] 8'00000000 sync always sync init update \main_sdphy_cmdr_count $1\main_sdphy_cmdr_count[7:0] end - attribute \src "ls180.v:1087.5-1087.46" - process $proc$ls180.v:1087$3214 + attribute \src "ls180.v:1086.5-1086.46" + process $proc$ls180.v:1086$3211 assign { } { } assign $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] 1'0 sync always update \main_sdphy_cmdr_cmdr_pads_in_ready $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] sync init end - attribute \src "ls180.v:1098.5-1098.53" - process $proc$ls180.v:1098$3215 + attribute \src "ls180.v:1097.5-1097.53" + process $proc$ls180.v:1097$3212 assign { } { } assign $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'0 sync always @@ -110908,79 +110868,79 @@ module \ls180 update \main_sdphy_cmdr_cmdr_source_source_ready0 $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] end attribute \src "ls180.v:110.5-110.49" - process $proc$ls180.v:110$2777 + process $proc$ls180.v:110$2775 assign { } { } assign $1\main_libresocsim_libresoc_jtag_wb_ack[0:0] 1'0 sync always sync init update \main_libresocsim_libresoc_jtag_wb_ack $1\main_libresocsim_libresoc_jtag_wb_ack[0:0] end - attribute \src "ls180.v:1103.5-1103.36" - process $proc$ls180.v:1103$3216 + attribute \src "ls180.v:1102.5-1102.36" + process $proc$ls180.v:1102$3213 assign { } { } assign $1\main_sdphy_cmdr_cmdr_run[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_run $1\main_sdphy_cmdr_cmdr_run[0:0] end - attribute \src "ls180.v:1106.5-1106.53" - process $proc$ls180.v:1106$3217 + attribute \src "ls180.v:1105.5-1105.53" + process $proc$ls180.v:1105$3214 assign { } { } assign $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] 1'0 sync always update \main_sdphy_cmdr_cmdr_converter_sink_first $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] sync init end - attribute \src "ls180.v:1107.5-1107.52" - process $proc$ls180.v:1107$3218 + attribute \src "ls180.v:1106.5-1106.52" + process $proc$ls180.v:1106$3215 assign { } { } assign $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] 1'0 sync always update \main_sdphy_cmdr_cmdr_converter_sink_last $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] sync init end - attribute \src "ls180.v:1111.5-1111.55" - process $proc$ls180.v:1111$3219 + attribute \src "ls180.v:1110.5-1110.55" + process $proc$ls180.v:1110$3216 assign { } { } assign $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_converter_source_first $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] end - attribute \src "ls180.v:1112.5-1112.54" - process $proc$ls180.v:1112$3220 + attribute \src "ls180.v:1111.5-1111.54" + process $proc$ls180.v:1111$3217 assign { } { } assign $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_converter_source_last $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] end - attribute \src "ls180.v:1113.11-1113.68" - process $proc$ls180.v:1113$3221 + attribute \src "ls180.v:1112.11-1112.68" + process $proc$ls180.v:1112$3218 assign { } { } assign $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_cmdr_cmdr_converter_source_payload_data $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] end - attribute \src "ls180.v:1114.11-1114.81" - process $proc$ls180.v:1114$3222 + attribute \src "ls180.v:1113.11-1113.81" + process $proc$ls180.v:1113$3219 assign { } { } assign $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] 4'0000 sync always sync init update \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] end - attribute \src "ls180.v:1115.11-1115.54" - process $proc$ls180.v:1115$3223 + attribute \src "ls180.v:1114.11-1114.54" + process $proc$ls180.v:1114$3220 assign { } { } assign $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 sync always sync init update \main_sdphy_cmdr_cmdr_converter_demux $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] end - attribute \src "ls180.v:1117.5-1117.53" - process $proc$ls180.v:1117$3224 + attribute \src "ls180.v:1116.5-1116.53" + process $proc$ls180.v:1116$3221 assign { } { } assign $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 sync always @@ -110988,335 +110948,335 @@ module \ls180 update \main_sdphy_cmdr_cmdr_converter_strobe_all $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] end attribute \src "ls180.v:112.5-112.49" - process $proc$ls180.v:112$2778 + process $proc$ls180.v:112$2776 assign { } { } assign $0\main_libresocsim_libresoc_jtag_wb_err[0:0] 1'0 sync always update \main_libresocsim_libresoc_jtag_wb_err $0\main_libresocsim_libresoc_jtag_wb_err[0:0] sync init end - attribute \src "ls180.v:1128.5-1128.49" - process $proc$ls180.v:1128$3225 + attribute \src "ls180.v:1127.5-1127.49" + process $proc$ls180.v:1127$3222 assign { } { } assign $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_buf_source_valid $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] end - attribute \src "ls180.v:1130.5-1130.49" - process $proc$ls180.v:1130$3226 + attribute \src "ls180.v:1129.5-1129.49" + process $proc$ls180.v:1129$3223 assign { } { } assign $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_buf_source_first $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] end - attribute \src "ls180.v:1131.5-1131.48" - process $proc$ls180.v:1131$3227 + attribute \src "ls180.v:1130.5-1130.48" + process $proc$ls180.v:1130$3224 assign { } { } assign $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_buf_source_last $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] end - attribute \src "ls180.v:1132.11-1132.62" - process $proc$ls180.v:1132$3228 + attribute \src "ls180.v:1131.11-1131.62" + process $proc$ls180.v:1131$3225 assign { } { } assign $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_cmdr_cmdr_buf_source_payload_data $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] end - attribute \src "ls180.v:1133.5-1133.38" - process $proc$ls180.v:1133$3229 + attribute \src "ls180.v:1132.5-1132.38" + process $proc$ls180.v:1132$3226 assign { } { } assign $1\main_sdphy_cmdr_cmdr_reset[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_reset $1\main_sdphy_cmdr_cmdr_reset[0:0] end - attribute \src "ls180.v:1138.5-1138.49" - process $proc$ls180.v:1138$3230 + attribute \src "ls180.v:1137.5-1137.49" + process $proc$ls180.v:1137$3227 assign { } { } assign $1\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'0 sync always sync init update \main_sdphy_dataw_pads_out_payload_clk $1\main_sdphy_dataw_pads_out_payload_clk[0:0] end - attribute \src "ls180.v:1139.5-1139.51" - process $proc$ls180.v:1139$3231 + attribute \src "ls180.v:1138.5-1138.51" + process $proc$ls180.v:1138$3228 assign { } { } assign $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] 1'0 sync always update \main_sdphy_dataw_pads_out_payload_cmd_o $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] sync init end - attribute \src "ls180.v:1140.5-1140.52" - process $proc$ls180.v:1140$3232 + attribute \src "ls180.v:1139.5-1139.52" + process $proc$ls180.v:1139$3229 assign { } { } assign $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] 1'0 sync always update \main_sdphy_dataw_pads_out_payload_cmd_oe $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] sync init end - attribute \src "ls180.v:1141.11-1141.58" - process $proc$ls180.v:1141$3233 + attribute \src "ls180.v:1140.11-1140.58" + process $proc$ls180.v:1140$3230 assign { } { } assign $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 sync always sync init update \main_sdphy_dataw_pads_out_payload_data_o $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] end - attribute \src "ls180.v:1142.5-1142.53" - process $proc$ls180.v:1142$3234 + attribute \src "ls180.v:1141.5-1141.53" + process $proc$ls180.v:1141$3231 assign { } { } assign $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'0 sync always sync init update \main_sdphy_dataw_pads_out_payload_data_oe $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] end - attribute \src "ls180.v:1143.5-1143.39" - process $proc$ls180.v:1143$3235 + attribute \src "ls180.v:1142.5-1142.39" + process $proc$ls180.v:1142$3232 assign { } { } assign $1\main_sdphy_dataw_sink_valid[0:0] 1'0 sync always sync init update \main_sdphy_dataw_sink_valid $1\main_sdphy_dataw_sink_valid[0:0] end - attribute \src "ls180.v:1144.5-1144.39" - process $proc$ls180.v:1144$3236 + attribute \src "ls180.v:1143.5-1143.39" + process $proc$ls180.v:1143$3233 assign { } { } assign $1\main_sdphy_dataw_sink_ready[0:0] 1'0 sync always sync init update \main_sdphy_dataw_sink_ready $1\main_sdphy_dataw_sink_ready[0:0] end - attribute \src "ls180.v:1145.5-1145.39" - process $proc$ls180.v:1145$3237 + attribute \src "ls180.v:1144.5-1144.39" + process $proc$ls180.v:1144$3234 assign { } { } assign $1\main_sdphy_dataw_sink_first[0:0] 1'0 sync always sync init update \main_sdphy_dataw_sink_first $1\main_sdphy_dataw_sink_first[0:0] end - attribute \src "ls180.v:1146.5-1146.38" - process $proc$ls180.v:1146$3238 + attribute \src "ls180.v:1145.5-1145.38" + process $proc$ls180.v:1145$3235 assign { } { } assign $1\main_sdphy_dataw_sink_last[0:0] 1'0 sync always sync init update \main_sdphy_dataw_sink_last $1\main_sdphy_dataw_sink_last[0:0] end - attribute \src "ls180.v:1147.11-1147.52" - process $proc$ls180.v:1147$3239 + attribute \src "ls180.v:1146.11-1146.52" + process $proc$ls180.v:1146$3236 assign { } { } assign $1\main_sdphy_dataw_sink_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_dataw_sink_payload_data $1\main_sdphy_dataw_sink_payload_data[7:0] end - attribute \src "ls180.v:1148.5-1148.33" - process $proc$ls180.v:1148$3240 + attribute \src "ls180.v:1147.5-1147.33" + process $proc$ls180.v:1147$3237 assign { } { } assign $1\main_sdphy_dataw_stop[0:0] 1'0 sync always sync init update \main_sdphy_dataw_stop $1\main_sdphy_dataw_stop[0:0] end - attribute \src "ls180.v:1149.11-1149.40" - process $proc$ls180.v:1149$3241 + attribute \src "ls180.v:1148.11-1148.40" + process $proc$ls180.v:1148$3238 assign { } { } assign $1\main_sdphy_dataw_count[7:0] 8'00000000 sync always sync init update \main_sdphy_dataw_count $1\main_sdphy_dataw_count[7:0] end - attribute \src "ls180.v:1150.5-1150.50" - process $proc$ls180.v:1150$3242 + attribute \src "ls180.v:1149.5-1149.50" + process $proc$ls180.v:1149$3239 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] 1'0 sync always update \main_sdphy_dataw_pads_in_pads_in_valid $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] sync init end - attribute \src "ls180.v:1152.5-1152.50" - process $proc$ls180.v:1152$3243 + attribute \src "ls180.v:1151.5-1151.50" + process $proc$ls180.v:1151$3240 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] 1'0 sync always update \main_sdphy_dataw_pads_in_pads_in_first $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] sync init end - attribute \src "ls180.v:1153.5-1153.49" - process $proc$ls180.v:1153$3244 + attribute \src "ls180.v:1152.5-1152.49" + process $proc$ls180.v:1152$3241 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] 1'0 sync always update \main_sdphy_dataw_pads_in_pads_in_last $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] sync init end - attribute \src "ls180.v:1154.5-1154.56" - process $proc$ls180.v:1154$3245 + attribute \src "ls180.v:1153.5-1153.56" + process $proc$ls180.v:1153$3242 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] 1'0 sync always update \main_sdphy_dataw_pads_in_pads_in_payload_clk $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] sync init end - attribute \src "ls180.v:1155.5-1155.58" - process $proc$ls180.v:1155$3246 + attribute \src "ls180.v:1154.5-1154.58" + process $proc$ls180.v:1154$3243 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] 1'0 sync always update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_i $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] sync init end - attribute \src "ls180.v:1156.5-1156.58" - process $proc$ls180.v:1156$3247 + attribute \src "ls180.v:1155.5-1155.58" + process $proc$ls180.v:1155$3244 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] 1'0 sync always update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_o $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] sync init end - attribute \src "ls180.v:1157.5-1157.59" - process $proc$ls180.v:1157$3248 + attribute \src "ls180.v:1156.5-1156.59" + process $proc$ls180.v:1156$3245 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 sync always update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] sync init end - attribute \src "ls180.v:1158.11-1158.65" - process $proc$ls180.v:1158$3249 + attribute \src "ls180.v:1157.11-1157.65" + process $proc$ls180.v:1157$3246 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] 4'0000 sync always update \main_sdphy_dataw_pads_in_pads_in_payload_data_i $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] sync init end - attribute \src "ls180.v:1159.11-1159.65" - process $proc$ls180.v:1159$3250 + attribute \src "ls180.v:1158.11-1158.65" + process $proc$ls180.v:1158$3247 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] 4'0000 sync always update \main_sdphy_dataw_pads_in_pads_in_payload_data_o $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] sync init end - attribute \src "ls180.v:1160.5-1160.60" - process $proc$ls180.v:1160$3251 + attribute \src "ls180.v:1159.5-1159.60" + process $proc$ls180.v:1159$3248 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] 1'0 sync always update \main_sdphy_dataw_pads_in_pads_in_payload_data_oe $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] sync init end - attribute \src "ls180.v:1161.5-1161.34" - process $proc$ls180.v:1161$3252 + attribute \src "ls180.v:1160.5-1160.34" + process $proc$ls180.v:1160$3249 assign { } { } assign $1\main_sdphy_dataw_start[0:0] 1'0 sync always sync init update \main_sdphy_dataw_start $1\main_sdphy_dataw_start[0:0] end - attribute \src "ls180.v:1162.5-1162.34" - process $proc$ls180.v:1162$3253 + attribute \src "ls180.v:1161.5-1161.34" + process $proc$ls180.v:1161$3250 assign { } { } assign $1\main_sdphy_dataw_valid[0:0] 1'0 sync always sync init update \main_sdphy_dataw_valid $1\main_sdphy_dataw_valid[0:0] end - attribute \src "ls180.v:1163.5-1163.34" - process $proc$ls180.v:1163$3254 + attribute \src "ls180.v:1162.5-1162.34" + process $proc$ls180.v:1162$3251 assign { } { } assign $1\main_sdphy_dataw_error[0:0] 1'0 sync always sync init update \main_sdphy_dataw_error $1\main_sdphy_dataw_error[0:0] end - attribute \src "ls180.v:1165.5-1165.47" - process $proc$ls180.v:1165$3255 + attribute \src "ls180.v:1164.5-1164.47" + process $proc$ls180.v:1164$3252 assign { } { } assign $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] 1'0 sync always update \main_sdphy_dataw_crcr_pads_in_ready $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] sync init end - attribute \src "ls180.v:1176.5-1176.54" - process $proc$ls180.v:1176$3256 + attribute \src "ls180.v:1175.5-1175.54" + process $proc$ls180.v:1175$3253 assign { } { } assign $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_source_source_ready0 $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] end - attribute \src "ls180.v:1181.5-1181.37" - process $proc$ls180.v:1181$3257 + attribute \src "ls180.v:1180.5-1180.37" + process $proc$ls180.v:1180$3254 assign { } { } assign $1\main_sdphy_dataw_crcr_run[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_run $1\main_sdphy_dataw_crcr_run[0:0] end - attribute \src "ls180.v:1184.5-1184.54" - process $proc$ls180.v:1184$3258 + attribute \src "ls180.v:1183.5-1183.54" + process $proc$ls180.v:1183$3255 assign { } { } assign $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] 1'0 sync always update \main_sdphy_dataw_crcr_converter_sink_first $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] sync init end - attribute \src "ls180.v:1185.5-1185.53" - process $proc$ls180.v:1185$3259 + attribute \src "ls180.v:1184.5-1184.53" + process $proc$ls180.v:1184$3256 assign { } { } assign $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] 1'0 sync always update \main_sdphy_dataw_crcr_converter_sink_last $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] sync init end - attribute \src "ls180.v:1189.5-1189.56" - process $proc$ls180.v:1189$3260 + attribute \src "ls180.v:1188.5-1188.56" + process $proc$ls180.v:1188$3257 assign { } { } assign $1\main_sdphy_dataw_crcr_converter_source_first[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_converter_source_first $1\main_sdphy_dataw_crcr_converter_source_first[0:0] end - attribute \src "ls180.v:1190.5-1190.55" - process $proc$ls180.v:1190$3261 + attribute \src "ls180.v:1189.5-1189.55" + process $proc$ls180.v:1189$3258 assign { } { } assign $1\main_sdphy_dataw_crcr_converter_source_last[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_converter_source_last $1\main_sdphy_dataw_crcr_converter_source_last[0:0] end - attribute \src "ls180.v:1191.11-1191.69" - process $proc$ls180.v:1191$3262 + attribute \src "ls180.v:1190.11-1190.69" + process $proc$ls180.v:1190$3259 assign { } { } assign $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_dataw_crcr_converter_source_payload_data $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] end - attribute \src "ls180.v:1192.11-1192.82" - process $proc$ls180.v:1192$3263 + attribute \src "ls180.v:1191.11-1191.82" + process $proc$ls180.v:1191$3260 assign { } { } assign $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] 4'0000 sync always sync init update \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] end - attribute \src "ls180.v:1193.11-1193.55" - process $proc$ls180.v:1193$3264 + attribute \src "ls180.v:1192.11-1192.55" + process $proc$ls180.v:1192$3261 assign { } { } assign $1\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 sync always sync init update \main_sdphy_dataw_crcr_converter_demux $1\main_sdphy_dataw_crcr_converter_demux[2:0] end - attribute \src "ls180.v:1195.5-1195.54" - process $proc$ls180.v:1195$3265 + attribute \src "ls180.v:1194.5-1194.54" + process $proc$ls180.v:1194$3262 assign { } { } assign $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 sync always @@ -111324,391 +111284,391 @@ module \ls180 update \main_sdphy_dataw_crcr_converter_strobe_all $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] end attribute \src "ls180.v:120.5-120.65" - process $proc$ls180.v:120$2779 + process $proc$ls180.v:120$2777 assign { } { } assign $1\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] 1'1 sync always sync init update \main_libresocsim_libresoc_constraintmanager0_uart0_tx $1\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] end - attribute \src "ls180.v:1206.5-1206.50" - process $proc$ls180.v:1206$3266 + attribute \src "ls180.v:1205.5-1205.50" + process $proc$ls180.v:1205$3263 assign { } { } assign $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_buf_source_valid $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] end - attribute \src "ls180.v:1208.5-1208.50" - process $proc$ls180.v:1208$3267 + attribute \src "ls180.v:1207.5-1207.50" + process $proc$ls180.v:1207$3264 assign { } { } assign $1\main_sdphy_dataw_crcr_buf_source_first[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_buf_source_first $1\main_sdphy_dataw_crcr_buf_source_first[0:0] end - attribute \src "ls180.v:1209.5-1209.49" - process $proc$ls180.v:1209$3268 + attribute \src "ls180.v:1208.5-1208.49" + process $proc$ls180.v:1208$3265 assign { } { } assign $1\main_sdphy_dataw_crcr_buf_source_last[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_buf_source_last $1\main_sdphy_dataw_crcr_buf_source_last[0:0] end - attribute \src "ls180.v:1210.11-1210.63" - process $proc$ls180.v:1210$3269 + attribute \src "ls180.v:1209.11-1209.63" + process $proc$ls180.v:1209$3266 assign { } { } assign $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_dataw_crcr_buf_source_payload_data $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] end - attribute \src "ls180.v:1211.5-1211.39" - process $proc$ls180.v:1211$3270 + attribute \src "ls180.v:1210.5-1210.39" + process $proc$ls180.v:1210$3267 assign { } { } assign $1\main_sdphy_dataw_crcr_reset[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_reset $1\main_sdphy_dataw_crcr_reset[0:0] end - attribute \src "ls180.v:1214.5-1214.50" - process $proc$ls180.v:1214$3271 + attribute \src "ls180.v:1213.5-1213.50" + process $proc$ls180.v:1213$3268 assign { } { } assign $0\main_sdphy_datar_pads_in_pads_in_first[0:0] 1'0 sync always update \main_sdphy_datar_pads_in_pads_in_first $0\main_sdphy_datar_pads_in_pads_in_first[0:0] sync init end - attribute \src "ls180.v:1215.5-1215.49" - process $proc$ls180.v:1215$3272 + attribute \src "ls180.v:1214.5-1214.49" + process $proc$ls180.v:1214$3269 assign { } { } assign $0\main_sdphy_datar_pads_in_pads_in_last[0:0] 1'0 sync always update \main_sdphy_datar_pads_in_pads_in_last $0\main_sdphy_datar_pads_in_pads_in_last[0:0] sync init end - attribute \src "ls180.v:1216.5-1216.56" - process $proc$ls180.v:1216$3273 + attribute \src "ls180.v:1215.5-1215.56" + process $proc$ls180.v:1215$3270 assign { } { } assign $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] 1'0 sync always update \main_sdphy_datar_pads_in_pads_in_payload_clk $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] sync init end - attribute \src "ls180.v:1218.5-1218.58" - process $proc$ls180.v:1218$3274 + attribute \src "ls180.v:1217.5-1217.58" + process $proc$ls180.v:1217$3271 assign { } { } assign $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] 1'0 sync always update \main_sdphy_datar_pads_in_pads_in_payload_cmd_o $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] sync init end - attribute \src "ls180.v:1219.5-1219.59" - process $proc$ls180.v:1219$3275 + attribute \src "ls180.v:1218.5-1218.59" + process $proc$ls180.v:1218$3272 assign { } { } assign $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 sync always update \main_sdphy_datar_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] sync init end - attribute \src "ls180.v:1221.11-1221.65" - process $proc$ls180.v:1221$3276 + attribute \src "ls180.v:1220.11-1220.65" + process $proc$ls180.v:1220$3273 assign { } { } assign $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] 4'0000 sync always update \main_sdphy_datar_pads_in_pads_in_payload_data_o $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] sync init end - attribute \src "ls180.v:1222.5-1222.60" - process $proc$ls180.v:1222$3277 + attribute \src "ls180.v:1221.5-1221.60" + process $proc$ls180.v:1221$3274 assign { } { } assign $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] 1'0 sync always update \main_sdphy_datar_pads_in_pads_in_payload_data_oe $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] sync init end - attribute \src "ls180.v:1224.5-1224.49" - process $proc$ls180.v:1224$3278 + attribute \src "ls180.v:1223.5-1223.49" + process $proc$ls180.v:1223$3275 assign { } { } assign $1\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0 sync always sync init update \main_sdphy_datar_pads_out_payload_clk $1\main_sdphy_datar_pads_out_payload_clk[0:0] end - attribute \src "ls180.v:1225.5-1225.51" - process $proc$ls180.v:1225$3279 + attribute \src "ls180.v:1224.5-1224.51" + process $proc$ls180.v:1224$3276 assign { } { } assign $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] 1'0 sync always update \main_sdphy_datar_pads_out_payload_cmd_o $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] sync init end - attribute \src "ls180.v:1226.5-1226.52" - process $proc$ls180.v:1226$3280 + attribute \src "ls180.v:1225.5-1225.52" + process $proc$ls180.v:1225$3277 assign { } { } assign $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] 1'0 sync always update \main_sdphy_datar_pads_out_payload_cmd_oe $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] sync init end - attribute \src "ls180.v:1227.11-1227.58" - process $proc$ls180.v:1227$3281 + attribute \src "ls180.v:1226.11-1226.58" + process $proc$ls180.v:1226$3278 assign { } { } assign $0\main_sdphy_datar_pads_out_payload_data_o[3:0] 4'0000 sync always update \main_sdphy_datar_pads_out_payload_data_o $0\main_sdphy_datar_pads_out_payload_data_o[3:0] sync init end - attribute \src "ls180.v:1228.5-1228.53" - process $proc$ls180.v:1228$3282 + attribute \src "ls180.v:1227.5-1227.53" + process $proc$ls180.v:1227$3279 assign { } { } assign $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] 1'0 sync always update \main_sdphy_datar_pads_out_payload_data_oe $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] sync init end - attribute \src "ls180.v:1229.5-1229.39" - process $proc$ls180.v:1229$3283 + attribute \src "ls180.v:1228.5-1228.39" + process $proc$ls180.v:1228$3280 assign { } { } assign $1\main_sdphy_datar_sink_valid[0:0] 1'0 sync always sync init update \main_sdphy_datar_sink_valid $1\main_sdphy_datar_sink_valid[0:0] end - attribute \src "ls180.v:1230.5-1230.39" - process $proc$ls180.v:1230$3284 + attribute \src "ls180.v:1229.5-1229.39" + process $proc$ls180.v:1229$3281 assign { } { } assign $1\main_sdphy_datar_sink_ready[0:0] 1'0 sync always sync init update \main_sdphy_datar_sink_ready $1\main_sdphy_datar_sink_ready[0:0] end - attribute \src "ls180.v:1231.5-1231.38" - process $proc$ls180.v:1231$3285 + attribute \src "ls180.v:1230.5-1230.38" + process $proc$ls180.v:1230$3282 assign { } { } assign $1\main_sdphy_datar_sink_last[0:0] 1'0 sync always sync init update \main_sdphy_datar_sink_last $1\main_sdphy_datar_sink_last[0:0] end - attribute \src "ls180.v:1232.11-1232.61" - process $proc$ls180.v:1232$3286 + attribute \src "ls180.v:1231.11-1231.61" + process $proc$ls180.v:1231$3283 assign { } { } assign $1\main_sdphy_datar_sink_payload_block_length[9:0] 10'0000000000 sync always sync init update \main_sdphy_datar_sink_payload_block_length $1\main_sdphy_datar_sink_payload_block_length[9:0] end - attribute \src "ls180.v:1233.5-1233.41" - process $proc$ls180.v:1233$3287 + attribute \src "ls180.v:1232.5-1232.41" + process $proc$ls180.v:1232$3284 assign { } { } assign $1\main_sdphy_datar_source_valid[0:0] 1'0 sync always sync init update \main_sdphy_datar_source_valid $1\main_sdphy_datar_source_valid[0:0] end - attribute \src "ls180.v:1234.5-1234.41" - process $proc$ls180.v:1234$3288 + attribute \src "ls180.v:1233.5-1233.41" + process $proc$ls180.v:1233$3285 assign { } { } assign $1\main_sdphy_datar_source_ready[0:0] 1'0 sync always sync init update \main_sdphy_datar_source_ready $1\main_sdphy_datar_source_ready[0:0] end - attribute \src "ls180.v:1235.5-1235.41" - process $proc$ls180.v:1235$3289 + attribute \src "ls180.v:1234.5-1234.41" + process $proc$ls180.v:1234$3286 assign { } { } assign $0\main_sdphy_datar_source_first[0:0] 1'0 sync always update \main_sdphy_datar_source_first $0\main_sdphy_datar_source_first[0:0] sync init end - attribute \src "ls180.v:1236.5-1236.40" - process $proc$ls180.v:1236$3290 + attribute \src "ls180.v:1235.5-1235.40" + process $proc$ls180.v:1235$3287 assign { } { } assign $1\main_sdphy_datar_source_last[0:0] 1'0 sync always sync init update \main_sdphy_datar_source_last $1\main_sdphy_datar_source_last[0:0] end - attribute \src "ls180.v:1237.11-1237.54" - process $proc$ls180.v:1237$3291 + attribute \src "ls180.v:1236.11-1236.54" + process $proc$ls180.v:1236$3288 assign { } { } assign $1\main_sdphy_datar_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_datar_source_payload_data $1\main_sdphy_datar_source_payload_data[7:0] end - attribute \src "ls180.v:1238.11-1238.56" - process $proc$ls180.v:1238$3292 + attribute \src "ls180.v:1237.11-1237.56" + process $proc$ls180.v:1237$3289 assign { } { } assign $1\main_sdphy_datar_source_payload_status[2:0] 3'000 sync always sync init update \main_sdphy_datar_source_payload_status $1\main_sdphy_datar_source_payload_status[2:0] end - attribute \src "ls180.v:1239.5-1239.33" - process $proc$ls180.v:1239$3293 + attribute \src "ls180.v:1238.5-1238.33" + process $proc$ls180.v:1238$3290 assign { } { } assign $1\main_sdphy_datar_stop[0:0] 1'0 sync always sync init update \main_sdphy_datar_stop $1\main_sdphy_datar_stop[0:0] end - attribute \src "ls180.v:1240.12-1240.49" - process $proc$ls180.v:1240$3294 + attribute \src "ls180.v:1239.12-1239.49" + process $proc$ls180.v:1239$3291 assign { } { } assign $1\main_sdphy_datar_timeout[31:0] 500000 sync always sync init update \main_sdphy_datar_timeout $1\main_sdphy_datar_timeout[31:0] end - attribute \src "ls180.v:1241.11-1241.41" - process $proc$ls180.v:1241$3295 + attribute \src "ls180.v:1240.11-1240.41" + process $proc$ls180.v:1240$3292 assign { } { } assign $1\main_sdphy_datar_count[9:0] 10'0000000000 sync always sync init update \main_sdphy_datar_count $1\main_sdphy_datar_count[9:0] end - attribute \src "ls180.v:1243.5-1243.48" - process $proc$ls180.v:1243$3296 + attribute \src "ls180.v:1242.5-1242.48" + process $proc$ls180.v:1242$3293 assign { } { } assign $0\main_sdphy_datar_datar_pads_in_ready[0:0] 1'0 sync always update \main_sdphy_datar_datar_pads_in_ready $0\main_sdphy_datar_datar_pads_in_ready[0:0] sync init end - attribute \src "ls180.v:1254.5-1254.55" - process $proc$ls180.v:1254$3297 + attribute \src "ls180.v:1253.5-1253.55" + process $proc$ls180.v:1253$3294 assign { } { } assign $1\main_sdphy_datar_datar_source_source_ready0[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_source_source_ready0 $1\main_sdphy_datar_datar_source_source_ready0[0:0] end - attribute \src "ls180.v:1259.5-1259.38" - process $proc$ls180.v:1259$3298 + attribute \src "ls180.v:1258.5-1258.38" + process $proc$ls180.v:1258$3295 assign { } { } assign $1\main_sdphy_datar_datar_run[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_run $1\main_sdphy_datar_datar_run[0:0] end - attribute \src "ls180.v:1262.5-1262.55" - process $proc$ls180.v:1262$3299 + attribute \src "ls180.v:1261.5-1261.55" + process $proc$ls180.v:1261$3296 assign { } { } assign $0\main_sdphy_datar_datar_converter_sink_first[0:0] 1'0 sync always update \main_sdphy_datar_datar_converter_sink_first $0\main_sdphy_datar_datar_converter_sink_first[0:0] sync init end - attribute \src "ls180.v:1263.5-1263.54" - process $proc$ls180.v:1263$3300 + attribute \src "ls180.v:1262.5-1262.54" + process $proc$ls180.v:1262$3297 assign { } { } assign $0\main_sdphy_datar_datar_converter_sink_last[0:0] 1'0 sync always update \main_sdphy_datar_datar_converter_sink_last $0\main_sdphy_datar_datar_converter_sink_last[0:0] sync init end - attribute \src "ls180.v:1267.5-1267.57" - process $proc$ls180.v:1267$3301 + attribute \src "ls180.v:1266.5-1266.57" + process $proc$ls180.v:1266$3298 assign { } { } assign $1\main_sdphy_datar_datar_converter_source_first[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_converter_source_first $1\main_sdphy_datar_datar_converter_source_first[0:0] end - attribute \src "ls180.v:1268.5-1268.56" - process $proc$ls180.v:1268$3302 + attribute \src "ls180.v:1267.5-1267.56" + process $proc$ls180.v:1267$3299 assign { } { } assign $1\main_sdphy_datar_datar_converter_source_last[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_converter_source_last $1\main_sdphy_datar_datar_converter_source_last[0:0] end - attribute \src "ls180.v:1269.11-1269.70" - process $proc$ls180.v:1269$3303 + attribute \src "ls180.v:1268.11-1268.70" + process $proc$ls180.v:1268$3300 assign { } { } assign $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_datar_datar_converter_source_payload_data $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] end - attribute \src "ls180.v:1270.11-1270.83" - process $proc$ls180.v:1270$3304 + attribute \src "ls180.v:1269.11-1269.83" + process $proc$ls180.v:1269$3301 assign { } { } assign $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] 2'00 sync always sync init update \main_sdphy_datar_datar_converter_source_payload_valid_token_count $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] end - attribute \src "ls180.v:1271.5-1271.50" - process $proc$ls180.v:1271$3305 + attribute \src "ls180.v:1270.5-1270.50" + process $proc$ls180.v:1270$3302 assign { } { } assign $1\main_sdphy_datar_datar_converter_demux[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_converter_demux $1\main_sdphy_datar_datar_converter_demux[0:0] end - attribute \src "ls180.v:1273.5-1273.55" - process $proc$ls180.v:1273$3306 + attribute \src "ls180.v:1272.5-1272.55" + process $proc$ls180.v:1272$3303 assign { } { } assign $1\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_converter_strobe_all $1\main_sdphy_datar_datar_converter_strobe_all[0:0] end - attribute \src "ls180.v:1284.5-1284.51" - process $proc$ls180.v:1284$3307 + attribute \src "ls180.v:1283.5-1283.51" + process $proc$ls180.v:1283$3304 assign { } { } assign $1\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_buf_source_valid $1\main_sdphy_datar_datar_buf_source_valid[0:0] end - attribute \src "ls180.v:1286.5-1286.51" - process $proc$ls180.v:1286$3308 + attribute \src "ls180.v:1285.5-1285.51" + process $proc$ls180.v:1285$3305 assign { } { } assign $1\main_sdphy_datar_datar_buf_source_first[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_buf_source_first $1\main_sdphy_datar_datar_buf_source_first[0:0] end - attribute \src "ls180.v:1287.5-1287.50" - process $proc$ls180.v:1287$3309 + attribute \src "ls180.v:1286.5-1286.50" + process $proc$ls180.v:1286$3306 assign { } { } assign $1\main_sdphy_datar_datar_buf_source_last[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_buf_source_last $1\main_sdphy_datar_datar_buf_source_last[0:0] end - attribute \src "ls180.v:1288.11-1288.64" - process $proc$ls180.v:1288$3310 + attribute \src "ls180.v:1287.11-1287.64" + process $proc$ls180.v:1287$3307 assign { } { } assign $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_datar_datar_buf_source_payload_data $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] end - attribute \src "ls180.v:1289.5-1289.40" - process $proc$ls180.v:1289$3311 + attribute \src "ls180.v:1288.5-1288.40" + process $proc$ls180.v:1288$3308 assign { } { } assign $1\main_sdphy_datar_datar_reset[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_reset $1\main_sdphy_datar_datar_reset[0:0] end - attribute \src "ls180.v:1291.5-1291.35" - process $proc$ls180.v:1291$3312 + attribute \src "ls180.v:1290.5-1290.35" + process $proc$ls180.v:1290$3309 assign { } { } assign $1\main_sdphy_sdpads_cmd_i[0:0] 1'0 sync always sync init update \main_sdphy_sdpads_cmd_i $1\main_sdphy_sdpads_cmd_i[0:0] end - attribute \src "ls180.v:1294.11-1294.42" - process $proc$ls180.v:1294$3313 + attribute \src "ls180.v:1293.11-1293.42" + process $proc$ls180.v:1293$3310 assign { } { } assign $1\main_sdphy_sdpads_data_i[3:0] 4'0000 sync always @@ -111716,103 +111676,103 @@ module \ls180 update \main_sdphy_sdpads_data_i $1\main_sdphy_sdpads_data_i[3:0] end attribute \src "ls180.v:130.12-130.71" - process $proc$ls180.v:130$2780 + process $proc$ls180.v:130$2778 assign { } { } assign $1\main_libresocsim_interface0_converted_interface_adr[29:0] 30'000000000000000000000000000000 sync always sync init update \main_libresocsim_interface0_converted_interface_adr $1\main_libresocsim_interface0_converted_interface_adr[29:0] end - attribute \src "ls180.v:1307.12-1307.52" - process $proc$ls180.v:1307$3314 + attribute \src "ls180.v:1306.12-1306.52" + process $proc$ls180.v:1306$3311 assign { } { } assign $1\main_sdcore_cmd_argument_storage[31:0] 0 sync always sync init update \main_sdcore_cmd_argument_storage $1\main_sdcore_cmd_argument_storage[31:0] end - attribute \src "ls180.v:1308.5-1308.39" - process $proc$ls180.v:1308$3315 + attribute \src "ls180.v:1307.5-1307.39" + process $proc$ls180.v:1307$3312 assign { } { } assign $1\main_sdcore_cmd_argument_re[0:0] 1'0 sync always sync init update \main_sdcore_cmd_argument_re $1\main_sdcore_cmd_argument_re[0:0] end - attribute \src "ls180.v:1309.12-1309.51" - process $proc$ls180.v:1309$3316 + attribute \src "ls180.v:1308.12-1308.51" + process $proc$ls180.v:1308$3313 assign { } { } assign $1\main_sdcore_cmd_command_storage[31:0] 0 sync always sync init update \main_sdcore_cmd_command_storage $1\main_sdcore_cmd_command_storage[31:0] end - attribute \src "ls180.v:131.12-131.73" - process $proc$ls180.v:131$2781 + attribute \src "ls180.v:1309.5-1309.38" + process $proc$ls180.v:1309$3314 assign { } { } - assign $1\main_libresocsim_interface0_converted_interface_dat_w[31:0] 0 + assign $1\main_sdcore_cmd_command_re[0:0] 1'0 sync always sync init - update \main_libresocsim_interface0_converted_interface_dat_w $1\main_libresocsim_interface0_converted_interface_dat_w[31:0] + update \main_sdcore_cmd_command_re $1\main_sdcore_cmd_command_re[0:0] end - attribute \src "ls180.v:1310.5-1310.38" - process $proc$ls180.v:1310$3317 + attribute \src "ls180.v:131.12-131.73" + process $proc$ls180.v:131$2779 assign { } { } - assign $1\main_sdcore_cmd_command_re[0:0] 1'0 + assign $1\main_libresocsim_interface0_converted_interface_dat_w[31:0] 0 sync always sync init - update \main_sdcore_cmd_command_re $1\main_sdcore_cmd_command_re[0:0] + update \main_libresocsim_interface0_converted_interface_dat_w $1\main_libresocsim_interface0_converted_interface_dat_w[31:0] end - attribute \src "ls180.v:1314.5-1314.34" - process $proc$ls180.v:1314$3318 + attribute \src "ls180.v:1313.5-1313.34" + process $proc$ls180.v:1313$3315 assign { } { } assign $0\main_sdcore_cmd_send_w[0:0] 1'0 sync always update \main_sdcore_cmd_send_w $0\main_sdcore_cmd_send_w[0:0] sync init end - attribute \src "ls180.v:1315.13-1315.53" - process $proc$ls180.v:1315$3319 + attribute \src "ls180.v:1314.13-1314.53" + process $proc$ls180.v:1314$3316 assign { } { } assign $1\main_sdcore_cmd_response_status[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \main_sdcore_cmd_response_status $1\main_sdcore_cmd_response_status[127:0] end - attribute \src "ls180.v:1321.11-1321.51" - process $proc$ls180.v:1321$3320 + attribute \src "ls180.v:1320.11-1320.51" + process $proc$ls180.v:1320$3317 assign { } { } assign $1\main_sdcore_block_length_storage[9:0] 10'0000000000 sync always sync init update \main_sdcore_block_length_storage $1\main_sdcore_block_length_storage[9:0] end - attribute \src "ls180.v:1322.5-1322.39" - process $proc$ls180.v:1322$3321 + attribute \src "ls180.v:1321.5-1321.39" + process $proc$ls180.v:1321$3318 assign { } { } assign $1\main_sdcore_block_length_re[0:0] 1'0 sync always sync init update \main_sdcore_block_length_re $1\main_sdcore_block_length_re[0:0] end - attribute \src "ls180.v:1323.12-1323.51" - process $proc$ls180.v:1323$3322 + attribute \src "ls180.v:1322.12-1322.51" + process $proc$ls180.v:1322$3319 assign { } { } assign $1\main_sdcore_block_count_storage[31:0] 0 sync always sync init update \main_sdcore_block_count_storage $1\main_sdcore_block_count_storage[31:0] end - attribute \src "ls180.v:1324.5-1324.38" - process $proc$ls180.v:1324$3323 + attribute \src "ls180.v:1323.5-1323.38" + process $proc$ls180.v:1323$3320 assign { } { } assign $1\main_sdcore_block_count_re[0:0] 1'0 sync always sync init update \main_sdcore_block_count_re $1\main_sdcore_block_count_re[0:0] end - attribute \src "ls180.v:1325.11-1325.51" - process $proc$ls180.v:1325$3324 + attribute \src "ls180.v:1324.11-1324.51" + process $proc$ls180.v:1324$3321 assign { } { } assign $1\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000 sync always @@ -111820,7 +111780,7 @@ module \ls180 update \main_sdcore_crc7_inserter_crcreg0 $1\main_sdcore_crc7_inserter_crcreg0[6:0] end attribute \src "ls180.v:133.11-133.69" - process $proc$ls180.v:133$2782 + process $proc$ls180.v:133$2780 assign { } { } assign $1\main_libresocsim_interface0_converted_interface_sel[3:0] 4'0000 sync always @@ -111828,7 +111788,7 @@ module \ls180 update \main_libresocsim_interface0_converted_interface_sel $1\main_libresocsim_interface0_converted_interface_sel[3:0] end attribute \src "ls180.v:134.5-134.63" - process $proc$ls180.v:134$2783 + process $proc$ls180.v:134$2781 assign { } { } assign $1\main_libresocsim_interface0_converted_interface_cyc[0:0] 1'0 sync always @@ -111836,15 +111796,15 @@ module \ls180 update \main_libresocsim_interface0_converted_interface_cyc $1\main_libresocsim_interface0_converted_interface_cyc[0:0] end attribute \src "ls180.v:135.5-135.63" - process $proc$ls180.v:135$2784 + process $proc$ls180.v:135$2782 assign { } { } assign $1\main_libresocsim_interface0_converted_interface_stb[0:0] 1'0 sync always sync init update \main_libresocsim_interface0_converted_interface_stb $1\main_libresocsim_interface0_converted_interface_stb[0:0] end - attribute \src "ls180.v:1367.11-1367.47" - process $proc$ls180.v:1367$3325 + attribute \src "ls180.v:1366.11-1366.47" + process $proc$ls180.v:1366$3322 assign { } { } assign $1\main_sdcore_crc7_inserter_crc[6:0] 7'0000000 sync always @@ -111852,95 +111812,95 @@ module \ls180 update \main_sdcore_crc7_inserter_crc $1\main_sdcore_crc7_inserter_crc[6:0] end attribute \src "ls180.v:137.5-137.62" - process $proc$ls180.v:137$2785 + process $proc$ls180.v:137$2783 assign { } { } assign $1\main_libresocsim_interface0_converted_interface_we[0:0] 1'0 sync always sync init update \main_libresocsim_interface0_converted_interface_we $1\main_libresocsim_interface0_converted_interface_we[0:0] end - attribute \src "ls180.v:1371.5-1371.49" - process $proc$ls180.v:1371$3326 + attribute \src "ls180.v:1370.5-1370.49" + process $proc$ls180.v:1370$3323 assign { } { } assign $1\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 sync always sync init update \main_sdcore_crc16_inserter_sink_ready $1\main_sdcore_crc16_inserter_sink_ready[0:0] end - attribute \src "ls180.v:1375.5-1375.51" - process $proc$ls180.v:1375$3327 + attribute \src "ls180.v:1374.5-1374.51" + process $proc$ls180.v:1374$3324 assign { } { } assign $1\main_sdcore_crc16_inserter_source_valid[0:0] 1'0 sync always sync init update \main_sdcore_crc16_inserter_source_valid $1\main_sdcore_crc16_inserter_source_valid[0:0] end - attribute \src "ls180.v:1376.5-1376.51" - process $proc$ls180.v:1376$3328 + attribute \src "ls180.v:1375.5-1375.51" + process $proc$ls180.v:1375$3325 assign { } { } assign $1\main_sdcore_crc16_inserter_source_ready[0:0] 1'0 sync always sync init update \main_sdcore_crc16_inserter_source_ready $1\main_sdcore_crc16_inserter_source_ready[0:0] end - attribute \src "ls180.v:1377.5-1377.51" - process $proc$ls180.v:1377$3329 + attribute \src "ls180.v:1376.5-1376.51" + process $proc$ls180.v:1376$3326 assign { } { } assign $0\main_sdcore_crc16_inserter_source_first[0:0] 1'0 sync always update \main_sdcore_crc16_inserter_source_first $0\main_sdcore_crc16_inserter_source_first[0:0] sync init end - attribute \src "ls180.v:1378.5-1378.50" - process $proc$ls180.v:1378$3330 + attribute \src "ls180.v:1377.5-1377.50" + process $proc$ls180.v:1377$3327 assign { } { } assign $1\main_sdcore_crc16_inserter_source_last[0:0] 1'0 sync always sync init update \main_sdcore_crc16_inserter_source_last $1\main_sdcore_crc16_inserter_source_last[0:0] end - attribute \src "ls180.v:1379.11-1379.64" - process $proc$ls180.v:1379$3331 + attribute \src "ls180.v:1378.11-1378.64" + process $proc$ls180.v:1378$3328 assign { } { } assign $1\main_sdcore_crc16_inserter_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdcore_crc16_inserter_source_payload_data $1\main_sdcore_crc16_inserter_source_payload_data[7:0] end - attribute \src "ls180.v:138.11-138.69" - process $proc$ls180.v:138$2786 + attribute \src "ls180.v:1379.11-1379.48" + process $proc$ls180.v:1379$3329 assign { } { } - assign $0\main_libresocsim_interface0_converted_interface_cti[2:0] 3'000 + assign $1\main_sdcore_crc16_inserter_cnt[2:0] 3'000 sync always - update \main_libresocsim_interface0_converted_interface_cti $0\main_libresocsim_interface0_converted_interface_cti[2:0] sync init + update \main_sdcore_crc16_inserter_cnt $1\main_sdcore_crc16_inserter_cnt[2:0] end - attribute \src "ls180.v:1380.11-1380.48" - process $proc$ls180.v:1380$3332 + attribute \src "ls180.v:138.11-138.69" + process $proc$ls180.v:138$2784 assign { } { } - assign $1\main_sdcore_crc16_inserter_cnt[2:0] 3'000 + assign $0\main_libresocsim_interface0_converted_interface_cti[2:0] 3'000 sync always + update \main_libresocsim_interface0_converted_interface_cti $0\main_libresocsim_interface0_converted_interface_cti[2:0] sync init - update \main_sdcore_crc16_inserter_cnt $1\main_sdcore_crc16_inserter_cnt[2:0] end - attribute \src "ls180.v:1381.12-1381.59" - process $proc$ls180.v:1381$3333 + attribute \src "ls180.v:1380.12-1380.59" + process $proc$ls180.v:1380$3330 assign { } { } assign $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crc0_crcreg0 $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] end - attribute \src "ls180.v:1385.12-1385.55" - process $proc$ls180.v:1385$3334 + attribute \src "ls180.v:1384.12-1384.55" + process $proc$ls180.v:1384$3331 assign { } { } assign $1\main_sdcore_crc16_inserter_crc0_crc[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crc0_crc $1\main_sdcore_crc16_inserter_crc0_crc[15:0] end - attribute \src "ls180.v:1388.12-1388.59" - process $proc$ls180.v:1388$3335 + attribute \src "ls180.v:1387.12-1387.59" + process $proc$ls180.v:1387$3332 assign { } { } assign $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000 sync always @@ -111948,223 +111908,223 @@ module \ls180 update \main_sdcore_crc16_inserter_crc1_crcreg0 $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] end attribute \src "ls180.v:139.11-139.69" - process $proc$ls180.v:139$2787 + process $proc$ls180.v:139$2785 assign { } { } assign $0\main_libresocsim_interface0_converted_interface_bte[1:0] 2'00 sync always update \main_libresocsim_interface0_converted_interface_bte $0\main_libresocsim_interface0_converted_interface_bte[1:0] sync init end - attribute \src "ls180.v:1392.12-1392.55" - process $proc$ls180.v:1392$3336 + attribute \src "ls180.v:1391.12-1391.55" + process $proc$ls180.v:1391$3333 assign { } { } assign $1\main_sdcore_crc16_inserter_crc1_crc[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crc1_crc $1\main_sdcore_crc16_inserter_crc1_crc[15:0] end - attribute \src "ls180.v:1395.12-1395.59" - process $proc$ls180.v:1395$3337 + attribute \src "ls180.v:1394.12-1394.59" + process $proc$ls180.v:1394$3334 assign { } { } assign $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crc2_crcreg0 $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] end - attribute \src "ls180.v:1399.12-1399.55" - process $proc$ls180.v:1399$3338 + attribute \src "ls180.v:1398.12-1398.55" + process $proc$ls180.v:1398$3335 assign { } { } assign $1\main_sdcore_crc16_inserter_crc2_crc[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crc2_crc $1\main_sdcore_crc16_inserter_crc2_crc[15:0] end - attribute \src "ls180.v:1402.12-1402.59" - process $proc$ls180.v:1402$3339 + attribute \src "ls180.v:1401.12-1401.59" + process $proc$ls180.v:1401$3336 assign { } { } assign $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crc3_crcreg0 $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] end - attribute \src "ls180.v:1406.12-1406.55" - process $proc$ls180.v:1406$3340 + attribute \src "ls180.v:1405.12-1405.55" + process $proc$ls180.v:1405$3337 assign { } { } assign $1\main_sdcore_crc16_inserter_crc3_crc[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crc3_crc $1\main_sdcore_crc16_inserter_crc3_crc[15:0] end - attribute \src "ls180.v:1409.12-1409.54" - process $proc$ls180.v:1409$3341 + attribute \src "ls180.v:1408.12-1408.54" + process $proc$ls180.v:1408$3338 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crctmp0 $1\main_sdcore_crc16_inserter_crctmp0[15:0] end - attribute \src "ls180.v:141.5-141.44" - process $proc$ls180.v:141$2788 + attribute \src "ls180.v:1409.12-1409.54" + process $proc$ls180.v:1409$3339 assign { } { } - assign $1\main_libresocsim_converter0_skip[0:0] 1'0 + assign $1\main_sdcore_crc16_inserter_crctmp1[15:0] 16'0000000000000000 sync always sync init - update \main_libresocsim_converter0_skip $1\main_libresocsim_converter0_skip[0:0] + update \main_sdcore_crc16_inserter_crctmp1 $1\main_sdcore_crc16_inserter_crctmp1[15:0] end - attribute \src "ls180.v:1410.12-1410.54" - process $proc$ls180.v:1410$3342 + attribute \src "ls180.v:141.5-141.44" + process $proc$ls180.v:141$2786 assign { } { } - assign $1\main_sdcore_crc16_inserter_crctmp1[15:0] 16'0000000000000000 + assign $1\main_libresocsim_converter0_skip[0:0] 1'0 sync always sync init - update \main_sdcore_crc16_inserter_crctmp1 $1\main_sdcore_crc16_inserter_crctmp1[15:0] + update \main_libresocsim_converter0_skip $1\main_libresocsim_converter0_skip[0:0] end - attribute \src "ls180.v:1411.12-1411.54" - process $proc$ls180.v:1411$3343 + attribute \src "ls180.v:1410.12-1410.54" + process $proc$ls180.v:1410$3340 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp2[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crctmp2 $1\main_sdcore_crc16_inserter_crctmp2[15:0] end - attribute \src "ls180.v:1412.12-1412.54" - process $proc$ls180.v:1412$3344 + attribute \src "ls180.v:1411.12-1411.54" + process $proc$ls180.v:1411$3341 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp3[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crctmp3 $1\main_sdcore_crc16_inserter_crctmp3[15:0] end - attribute \src "ls180.v:1413.5-1413.48" - process $proc$ls180.v:1413$3345 + attribute \src "ls180.v:1412.5-1412.48" + process $proc$ls180.v:1412$3342 assign { } { } assign $1\main_sdcore_crc16_checker_sink_valid[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_sink_valid $1\main_sdcore_crc16_checker_sink_valid[0:0] end - attribute \src "ls180.v:1414.5-1414.48" - process $proc$ls180.v:1414$3346 + attribute \src "ls180.v:1413.5-1413.48" + process $proc$ls180.v:1413$3343 assign { } { } assign $1\main_sdcore_crc16_checker_sink_ready[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_sink_ready $1\main_sdcore_crc16_checker_sink_ready[0:0] end - attribute \src "ls180.v:1415.5-1415.48" - process $proc$ls180.v:1415$3347 + attribute \src "ls180.v:1414.5-1414.48" + process $proc$ls180.v:1414$3344 assign { } { } assign $1\main_sdcore_crc16_checker_sink_first[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_sink_first $1\main_sdcore_crc16_checker_sink_first[0:0] end - attribute \src "ls180.v:1416.5-1416.47" - process $proc$ls180.v:1416$3348 + attribute \src "ls180.v:1415.5-1415.47" + process $proc$ls180.v:1415$3345 assign { } { } assign $1\main_sdcore_crc16_checker_sink_last[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_sink_last $1\main_sdcore_crc16_checker_sink_last[0:0] end - attribute \src "ls180.v:1417.11-1417.61" - process $proc$ls180.v:1417$3349 + attribute \src "ls180.v:1416.11-1416.61" + process $proc$ls180.v:1416$3346 assign { } { } assign $1\main_sdcore_crc16_checker_sink_payload_data[7:0] 8'00000000 sync always sync init update \main_sdcore_crc16_checker_sink_payload_data $1\main_sdcore_crc16_checker_sink_payload_data[7:0] end - attribute \src "ls180.v:1418.5-1418.50" - process $proc$ls180.v:1418$3350 + attribute \src "ls180.v:1417.5-1417.50" + process $proc$ls180.v:1417$3347 assign { } { } assign $1\main_sdcore_crc16_checker_source_valid[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_source_valid $1\main_sdcore_crc16_checker_source_valid[0:0] end - attribute \src "ls180.v:142.5-142.47" - process $proc$ls180.v:142$2789 + attribute \src "ls180.v:1419.5-1419.50" + process $proc$ls180.v:1419$3348 assign { } { } - assign $1\main_libresocsim_converter0_counter[0:0] 1'0 + assign $0\main_sdcore_crc16_checker_source_first[0:0] 1'0 sync always + update \main_sdcore_crc16_checker_source_first $0\main_sdcore_crc16_checker_source_first[0:0] sync init - update \main_libresocsim_converter0_counter $1\main_libresocsim_converter0_counter[0:0] end - attribute \src "ls180.v:1420.5-1420.50" - process $proc$ls180.v:1420$3351 + attribute \src "ls180.v:142.5-142.47" + process $proc$ls180.v:142$2787 assign { } { } - assign $0\main_sdcore_crc16_checker_source_first[0:0] 1'0 + assign $1\main_libresocsim_converter0_counter[0:0] 1'0 sync always - update \main_sdcore_crc16_checker_source_first $0\main_sdcore_crc16_checker_source_first[0:0] sync init + update \main_libresocsim_converter0_counter $1\main_libresocsim_converter0_counter[0:0] end - attribute \src "ls180.v:1423.11-1423.47" - process $proc$ls180.v:1423$3352 + attribute \src "ls180.v:1422.11-1422.47" + process $proc$ls180.v:1422$3349 assign { } { } assign $1\main_sdcore_crc16_checker_val[7:0] 8'00000000 sync always sync init update \main_sdcore_crc16_checker_val $1\main_sdcore_crc16_checker_val[7:0] end - attribute \src "ls180.v:1424.11-1424.47" - process $proc$ls180.v:1424$3353 + attribute \src "ls180.v:1423.11-1423.47" + process $proc$ls180.v:1423$3350 assign { } { } assign $1\main_sdcore_crc16_checker_cnt[3:0] 4'0000 sync always sync init update \main_sdcore_crc16_checker_cnt $1\main_sdcore_crc16_checker_cnt[3:0] end - attribute \src "ls180.v:1425.12-1425.58" - process $proc$ls180.v:1425$3354 + attribute \src "ls180.v:1424.12-1424.58" + process $proc$ls180.v:1424$3351 assign { } { } assign $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crc0_crcreg0 $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] end - attribute \src "ls180.v:1429.12-1429.54" - process $proc$ls180.v:1429$3355 + attribute \src "ls180.v:1428.12-1428.54" + process $proc$ls180.v:1428$3352 assign { } { } assign $1\main_sdcore_crc16_checker_crc0_crc[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crc0_crc $1\main_sdcore_crc16_checker_crc0_crc[15:0] end - attribute \src "ls180.v:1430.5-1430.46" - process $proc$ls180.v:1430$3356 + attribute \src "ls180.v:1429.5-1429.46" + process $proc$ls180.v:1429$3353 assign { } { } assign $1\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_crc0_clr $1\main_sdcore_crc16_checker_crc0_clr[0:0] end - attribute \src "ls180.v:1432.12-1432.58" - process $proc$ls180.v:1432$3357 + attribute \src "ls180.v:1431.12-1431.58" + process $proc$ls180.v:1431$3354 assign { } { } assign $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crc1_crcreg0 $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] end - attribute \src "ls180.v:1436.12-1436.54" - process $proc$ls180.v:1436$3358 + attribute \src "ls180.v:1435.12-1435.54" + process $proc$ls180.v:1435$3355 assign { } { } assign $1\main_sdcore_crc16_checker_crc1_crc[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crc1_crc $1\main_sdcore_crc16_checker_crc1_crc[15:0] end - attribute \src "ls180.v:1437.5-1437.46" - process $proc$ls180.v:1437$3359 + attribute \src "ls180.v:1436.5-1436.46" + process $proc$ls180.v:1436$3356 assign { } { } assign $1\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_crc1_clr $1\main_sdcore_crc16_checker_crc1_clr[0:0] end - attribute \src "ls180.v:1439.12-1439.58" - process $proc$ls180.v:1439$3360 + attribute \src "ls180.v:1438.12-1438.58" + process $proc$ls180.v:1438$3357 assign { } { } assign $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000 sync always @@ -112172,223 +112132,223 @@ module \ls180 update \main_sdcore_crc16_checker_crc2_crcreg0 $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] end attribute \src "ls180.v:144.12-144.53" - process $proc$ls180.v:144$2790 + process $proc$ls180.v:144$2788 assign { } { } assign $1\main_libresocsim_converter0_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \main_libresocsim_converter0_dat_r $1\main_libresocsim_converter0_dat_r[63:0] end - attribute \src "ls180.v:1443.12-1443.54" - process $proc$ls180.v:1443$3361 + attribute \src "ls180.v:1442.12-1442.54" + process $proc$ls180.v:1442$3358 assign { } { } assign $1\main_sdcore_crc16_checker_crc2_crc[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crc2_crc $1\main_sdcore_crc16_checker_crc2_crc[15:0] end - attribute \src "ls180.v:1444.5-1444.46" - process $proc$ls180.v:1444$3362 + attribute \src "ls180.v:1443.5-1443.46" + process $proc$ls180.v:1443$3359 assign { } { } assign $1\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_crc2_clr $1\main_sdcore_crc16_checker_crc2_clr[0:0] end - attribute \src "ls180.v:1446.12-1446.58" - process $proc$ls180.v:1446$3363 + attribute \src "ls180.v:1445.12-1445.58" + process $proc$ls180.v:1445$3360 assign { } { } assign $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crc3_crcreg0 $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] end - attribute \src "ls180.v:145.12-145.71" - process $proc$ls180.v:145$2791 + attribute \src "ls180.v:1449.12-1449.54" + process $proc$ls180.v:1449$3361 assign { } { } - assign $1\main_libresocsim_interface1_converted_interface_adr[29:0] 30'000000000000000000000000000000 + assign $1\main_sdcore_crc16_checker_crc3_crc[15:0] 16'0000000000000000 sync always sync init - update \main_libresocsim_interface1_converted_interface_adr $1\main_libresocsim_interface1_converted_interface_adr[29:0] + update \main_sdcore_crc16_checker_crc3_crc $1\main_sdcore_crc16_checker_crc3_crc[15:0] end - attribute \src "ls180.v:1450.12-1450.54" - process $proc$ls180.v:1450$3364 + attribute \src "ls180.v:145.12-145.71" + process $proc$ls180.v:145$2789 assign { } { } - assign $1\main_sdcore_crc16_checker_crc3_crc[15:0] 16'0000000000000000 + assign $1\main_libresocsim_interface1_converted_interface_adr[29:0] 30'000000000000000000000000000000 sync always sync init - update \main_sdcore_crc16_checker_crc3_crc $1\main_sdcore_crc16_checker_crc3_crc[15:0] + update \main_libresocsim_interface1_converted_interface_adr $1\main_libresocsim_interface1_converted_interface_adr[29:0] end - attribute \src "ls180.v:1451.5-1451.46" - process $proc$ls180.v:1451$3365 + attribute \src "ls180.v:1450.5-1450.46" + process $proc$ls180.v:1450$3362 assign { } { } assign $1\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_crc3_clr $1\main_sdcore_crc16_checker_crc3_clr[0:0] end - attribute \src "ls180.v:1453.12-1453.53" - process $proc$ls180.v:1453$3366 + attribute \src "ls180.v:1452.12-1452.53" + process $proc$ls180.v:1452$3363 assign { } { } assign $1\main_sdcore_crc16_checker_crctmp0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crctmp0 $1\main_sdcore_crc16_checker_crctmp0[15:0] end - attribute \src "ls180.v:1454.12-1454.53" - process $proc$ls180.v:1454$3367 + attribute \src "ls180.v:1453.12-1453.53" + process $proc$ls180.v:1453$3364 assign { } { } assign $1\main_sdcore_crc16_checker_crctmp1[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crctmp1 $1\main_sdcore_crc16_checker_crctmp1[15:0] end - attribute \src "ls180.v:1455.12-1455.53" - process $proc$ls180.v:1455$3368 + attribute \src "ls180.v:1454.12-1454.53" + process $proc$ls180.v:1454$3365 assign { } { } assign $1\main_sdcore_crc16_checker_crctmp2[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crctmp2 $1\main_sdcore_crc16_checker_crctmp2[15:0] end - attribute \src "ls180.v:1456.12-1456.53" - process $proc$ls180.v:1456$3369 + attribute \src "ls180.v:1455.12-1455.53" + process $proc$ls180.v:1455$3366 assign { } { } assign $1\main_sdcore_crc16_checker_crctmp3[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crctmp3 $1\main_sdcore_crc16_checker_crctmp3[15:0] end - attribute \src "ls180.v:1457.5-1457.43" - process $proc$ls180.v:1457$3370 + attribute \src "ls180.v:1456.5-1456.43" + process $proc$ls180.v:1456$3367 assign { } { } assign $1\main_sdcore_crc16_checker_valid[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_valid $1\main_sdcore_crc16_checker_valid[0:0] end - attribute \src "ls180.v:1458.12-1458.51" - process $proc$ls180.v:1458$3371 + attribute \src "ls180.v:1457.12-1457.51" + process $proc$ls180.v:1457$3368 assign { } { } assign $1\main_sdcore_crc16_checker_fifo0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_fifo0 $1\main_sdcore_crc16_checker_fifo0[15:0] end - attribute \src "ls180.v:1459.12-1459.51" - process $proc$ls180.v:1459$3372 + attribute \src "ls180.v:1458.12-1458.51" + process $proc$ls180.v:1458$3369 assign { } { } assign $1\main_sdcore_crc16_checker_fifo1[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_fifo1 $1\main_sdcore_crc16_checker_fifo1[15:0] end - attribute \src "ls180.v:146.12-146.73" - process $proc$ls180.v:146$2792 + attribute \src "ls180.v:1459.12-1459.51" + process $proc$ls180.v:1459$3370 assign { } { } - assign $1\main_libresocsim_interface1_converted_interface_dat_w[31:0] 0 + assign $1\main_sdcore_crc16_checker_fifo2[15:0] 16'0000000000000000 sync always sync init - update \main_libresocsim_interface1_converted_interface_dat_w $1\main_libresocsim_interface1_converted_interface_dat_w[31:0] + update \main_sdcore_crc16_checker_fifo2 $1\main_sdcore_crc16_checker_fifo2[15:0] end - attribute \src "ls180.v:1460.12-1460.51" - process $proc$ls180.v:1460$3373 + attribute \src "ls180.v:146.12-146.73" + process $proc$ls180.v:146$2790 assign { } { } - assign $1\main_sdcore_crc16_checker_fifo2[15:0] 16'0000000000000000 + assign $1\main_libresocsim_interface1_converted_interface_dat_w[31:0] 0 sync always sync init - update \main_sdcore_crc16_checker_fifo2 $1\main_sdcore_crc16_checker_fifo2[15:0] + update \main_libresocsim_interface1_converted_interface_dat_w $1\main_libresocsim_interface1_converted_interface_dat_w[31:0] end - attribute \src "ls180.v:1461.12-1461.51" - process $proc$ls180.v:1461$3374 + attribute \src "ls180.v:1460.12-1460.51" + process $proc$ls180.v:1460$3371 assign { } { } assign $1\main_sdcore_crc16_checker_fifo3[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_fifo3 $1\main_sdcore_crc16_checker_fifo3[15:0] end - attribute \src "ls180.v:1463.11-1463.39" - process $proc$ls180.v:1463$3375 + attribute \src "ls180.v:1462.11-1462.39" + process $proc$ls180.v:1462$3372 assign { } { } assign $1\main_sdcore_cmd_count[2:0] 3'000 sync always sync init update \main_sdcore_cmd_count $1\main_sdcore_cmd_count[2:0] end - attribute \src "ls180.v:1464.5-1464.32" - process $proc$ls180.v:1464$3376 + attribute \src "ls180.v:1463.5-1463.32" + process $proc$ls180.v:1463$3373 assign { } { } assign $1\main_sdcore_cmd_done[0:0] 1'0 sync always sync init update \main_sdcore_cmd_done $1\main_sdcore_cmd_done[0:0] end - attribute \src "ls180.v:1465.5-1465.33" - process $proc$ls180.v:1465$3377 + attribute \src "ls180.v:1464.5-1464.33" + process $proc$ls180.v:1464$3374 assign { } { } assign $1\main_sdcore_cmd_error[0:0] 1'0 sync always sync init update \main_sdcore_cmd_error $1\main_sdcore_cmd_error[0:0] end - attribute \src "ls180.v:1466.5-1466.35" - process $proc$ls180.v:1466$3378 + attribute \src "ls180.v:1465.5-1465.35" + process $proc$ls180.v:1465$3375 assign { } { } assign $1\main_sdcore_cmd_timeout[0:0] 1'0 sync always sync init update \main_sdcore_cmd_timeout $1\main_sdcore_cmd_timeout[0:0] end - attribute \src "ls180.v:1468.12-1468.42" - process $proc$ls180.v:1468$3379 + attribute \src "ls180.v:1467.12-1467.42" + process $proc$ls180.v:1467$3376 assign { } { } assign $1\main_sdcore_data_count[31:0] 0 sync always sync init update \main_sdcore_data_count $1\main_sdcore_data_count[31:0] end - attribute \src "ls180.v:1469.5-1469.33" - process $proc$ls180.v:1469$3380 + attribute \src "ls180.v:1468.5-1468.33" + process $proc$ls180.v:1468$3377 assign { } { } assign $1\main_sdcore_data_done[0:0] 1'0 sync always sync init update \main_sdcore_data_done $1\main_sdcore_data_done[0:0] end - attribute \src "ls180.v:1470.5-1470.34" - process $proc$ls180.v:1470$3381 + attribute \src "ls180.v:1469.5-1469.34" + process $proc$ls180.v:1469$3378 assign { } { } assign $1\main_sdcore_data_error[0:0] 1'0 sync always sync init update \main_sdcore_data_error $1\main_sdcore_data_error[0:0] end - attribute \src "ls180.v:1471.5-1471.36" - process $proc$ls180.v:1471$3382 + attribute \src "ls180.v:1470.5-1470.36" + process $proc$ls180.v:1470$3379 assign { } { } assign $1\main_sdcore_data_timeout[0:0] 1'0 sync always sync init update \main_sdcore_data_timeout $1\main_sdcore_data_timeout[0:0] end - attribute \src "ls180.v:148.11-148.69" - process $proc$ls180.v:148$2793 + attribute \src "ls180.v:1479.11-1479.41" + process $proc$ls180.v:1479$3380 assign { } { } - assign $1\main_libresocsim_interface1_converted_interface_sel[3:0] 4'0000 + assign $0\main_interface0_bus_cti[2:0] 3'000 sync always + update \main_interface0_bus_cti $0\main_interface0_bus_cti[2:0] sync init - update \main_libresocsim_interface1_converted_interface_sel $1\main_libresocsim_interface1_converted_interface_sel[3:0] end - attribute \src "ls180.v:1480.11-1480.41" - process $proc$ls180.v:1480$3383 + attribute \src "ls180.v:148.11-148.69" + process $proc$ls180.v:148$2791 assign { } { } - assign $0\main_interface0_bus_cti[2:0] 3'000 + assign $1\main_libresocsim_interface1_converted_interface_sel[3:0] 4'0000 sync always - update \main_interface0_bus_cti $0\main_interface0_bus_cti[2:0] sync init + update \main_libresocsim_interface1_converted_interface_sel $1\main_libresocsim_interface1_converted_interface_sel[3:0] end - attribute \src "ls180.v:1481.11-1481.41" - process $proc$ls180.v:1481$3384 + attribute \src "ls180.v:1480.11-1480.41" + process $proc$ls180.v:1480$3381 assign { } { } assign $0\main_interface0_bus_bte[1:0] 2'00 sync always @@ -112396,7 +112356,7 @@ module \ls180 sync init end attribute \src "ls180.v:149.5-149.63" - process $proc$ls180.v:149$2794 + process $proc$ls180.v:149$2792 assign { } { } assign $1\main_libresocsim_interface1_converted_interface_cyc[0:0] 1'0 sync always @@ -112404,47 +112364,47 @@ module \ls180 update \main_libresocsim_interface1_converted_interface_cyc $1\main_libresocsim_interface1_converted_interface_cyc[0:0] end attribute \src "ls180.v:150.5-150.63" - process $proc$ls180.v:150$2795 + process $proc$ls180.v:150$2793 assign { } { } assign $1\main_libresocsim_interface1_converted_interface_stb[0:0] 1'0 sync always sync init update \main_libresocsim_interface1_converted_interface_stb $1\main_libresocsim_interface1_converted_interface_stb[0:0] end - attribute \src "ls180.v:1504.11-1504.45" - process $proc$ls180.v:1504$3385 + attribute \src "ls180.v:1503.11-1503.45" + process $proc$ls180.v:1503$3382 assign { } { } assign $1\main_sdblock2mem_fifo_level[5:0] 6'000000 sync always sync init update \main_sdblock2mem_fifo_level $1\main_sdblock2mem_fifo_level[5:0] end - attribute \src "ls180.v:1505.5-1505.41" - process $proc$ls180.v:1505$3386 + attribute \src "ls180.v:1504.5-1504.41" + process $proc$ls180.v:1504$3383 assign { } { } assign $0\main_sdblock2mem_fifo_replace[0:0] 1'0 sync always update \main_sdblock2mem_fifo_replace $0\main_sdblock2mem_fifo_replace[0:0] sync init end - attribute \src "ls180.v:1506.11-1506.47" - process $proc$ls180.v:1506$3387 + attribute \src "ls180.v:1505.11-1505.47" + process $proc$ls180.v:1505$3384 assign { } { } assign $1\main_sdblock2mem_fifo_produce[4:0] 5'00000 sync always sync init update \main_sdblock2mem_fifo_produce $1\main_sdblock2mem_fifo_produce[4:0] end - attribute \src "ls180.v:1507.11-1507.47" - process $proc$ls180.v:1507$3388 + attribute \src "ls180.v:1506.11-1506.47" + process $proc$ls180.v:1506$3385 assign { } { } assign $1\main_sdblock2mem_fifo_consume[4:0] 5'00000 sync always sync init update \main_sdblock2mem_fifo_consume $1\main_sdblock2mem_fifo_consume[4:0] end - attribute \src "ls180.v:1508.11-1508.50" - process $proc$ls180.v:1508$3389 + attribute \src "ls180.v:1507.11-1507.50" + process $proc$ls180.v:1507$3386 assign { } { } assign $1\main_sdblock2mem_fifo_wrport_adr[4:0] 5'00000 sync always @@ -112452,415 +112412,415 @@ module \ls180 update \main_sdblock2mem_fifo_wrport_adr $1\main_sdblock2mem_fifo_wrport_adr[4:0] end attribute \src "ls180.v:152.5-152.62" - process $proc$ls180.v:152$2796 + process $proc$ls180.v:152$2794 assign { } { } assign $1\main_libresocsim_interface1_converted_interface_we[0:0] 1'0 sync always sync init update \main_libresocsim_interface1_converted_interface_we $1\main_libresocsim_interface1_converted_interface_we[0:0] end - attribute \src "ls180.v:1528.5-1528.51" - process $proc$ls180.v:1528$3390 + attribute \src "ls180.v:1527.5-1527.51" + process $proc$ls180.v:1527$3387 assign { } { } assign $1\main_sdblock2mem_converter_source_first[0:0] 1'0 sync always sync init update \main_sdblock2mem_converter_source_first $1\main_sdblock2mem_converter_source_first[0:0] end - attribute \src "ls180.v:1529.5-1529.50" - process $proc$ls180.v:1529$3391 + attribute \src "ls180.v:1528.5-1528.50" + process $proc$ls180.v:1528$3388 assign { } { } assign $1\main_sdblock2mem_converter_source_last[0:0] 1'0 sync always sync init update \main_sdblock2mem_converter_source_last $1\main_sdblock2mem_converter_source_last[0:0] end - attribute \src "ls180.v:153.11-153.69" - process $proc$ls180.v:153$2797 + attribute \src "ls180.v:1529.12-1529.66" + process $proc$ls180.v:1529$3389 assign { } { } - assign $0\main_libresocsim_interface1_converted_interface_cti[2:0] 3'000 + assign $1\main_sdblock2mem_converter_source_payload_data[31:0] 0 sync always - update \main_libresocsim_interface1_converted_interface_cti $0\main_libresocsim_interface1_converted_interface_cti[2:0] sync init + update \main_sdblock2mem_converter_source_payload_data $1\main_sdblock2mem_converter_source_payload_data[31:0] end - attribute \src "ls180.v:1530.12-1530.66" - process $proc$ls180.v:1530$3392 + attribute \src "ls180.v:153.11-153.69" + process $proc$ls180.v:153$2795 assign { } { } - assign $1\main_sdblock2mem_converter_source_payload_data[31:0] 0 + assign $0\main_libresocsim_interface1_converted_interface_cti[2:0] 3'000 sync always + update \main_libresocsim_interface1_converted_interface_cti $0\main_libresocsim_interface1_converted_interface_cti[2:0] sync init - update \main_sdblock2mem_converter_source_payload_data $1\main_sdblock2mem_converter_source_payload_data[31:0] end - attribute \src "ls180.v:1531.11-1531.77" - process $proc$ls180.v:1531$3393 + attribute \src "ls180.v:1530.11-1530.77" + process $proc$ls180.v:1530$3390 assign { } { } assign $1\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] 3'000 sync always sync init update \main_sdblock2mem_converter_source_payload_valid_token_count $1\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] end - attribute \src "ls180.v:1532.11-1532.50" - process $proc$ls180.v:1532$3394 + attribute \src "ls180.v:1531.11-1531.50" + process $proc$ls180.v:1531$3391 assign { } { } assign $1\main_sdblock2mem_converter_demux[1:0] 2'00 sync always sync init update \main_sdblock2mem_converter_demux $1\main_sdblock2mem_converter_demux[1:0] end - attribute \src "ls180.v:1534.5-1534.49" - process $proc$ls180.v:1534$3395 + attribute \src "ls180.v:1533.5-1533.49" + process $proc$ls180.v:1533$3392 assign { } { } assign $1\main_sdblock2mem_converter_strobe_all[0:0] 1'0 sync always sync init update \main_sdblock2mem_converter_strobe_all $1\main_sdblock2mem_converter_strobe_all[0:0] end - attribute \src "ls180.v:154.11-154.69" - process $proc$ls180.v:154$2798 + attribute \src "ls180.v:1539.5-1539.45" + process $proc$ls180.v:1539$3393 assign { } { } - assign $0\main_libresocsim_interface1_converted_interface_bte[1:0] 2'00 + assign $1\main_sdblock2mem_sink_sink_valid1[0:0] 1'0 sync always - update \main_libresocsim_interface1_converted_interface_bte $0\main_libresocsim_interface1_converted_interface_bte[1:0] sync init + update \main_sdblock2mem_sink_sink_valid1 $1\main_sdblock2mem_sink_sink_valid1[0:0] end - attribute \src "ls180.v:1540.5-1540.45" - process $proc$ls180.v:1540$3396 + attribute \src "ls180.v:154.11-154.69" + process $proc$ls180.v:154$2796 assign { } { } - assign $1\main_sdblock2mem_sink_sink_valid1[0:0] 1'0 + assign $0\main_libresocsim_interface1_converted_interface_bte[1:0] 2'00 sync always + update \main_libresocsim_interface1_converted_interface_bte $0\main_libresocsim_interface1_converted_interface_bte[1:0] sync init - update \main_sdblock2mem_sink_sink_valid1 $1\main_sdblock2mem_sink_sink_valid1[0:0] end - attribute \src "ls180.v:1542.12-1542.62" - process $proc$ls180.v:1542$3397 + attribute \src "ls180.v:1541.12-1541.62" + process $proc$ls180.v:1541$3394 assign { } { } assign $1\main_sdblock2mem_sink_sink_payload_address[31:0] 0 sync always sync init update \main_sdblock2mem_sink_sink_payload_address $1\main_sdblock2mem_sink_sink_payload_address[31:0] end - attribute \src "ls180.v:1543.12-1543.60" - process $proc$ls180.v:1543$3398 + attribute \src "ls180.v:1542.12-1542.60" + process $proc$ls180.v:1542$3395 assign { } { } assign $1\main_sdblock2mem_sink_sink_payload_data1[31:0] 0 sync always sync init update \main_sdblock2mem_sink_sink_payload_data1 $1\main_sdblock2mem_sink_sink_payload_data1[31:0] end - attribute \src "ls180.v:1545.5-1545.57" - process $proc$ls180.v:1545$3399 + attribute \src "ls180.v:1544.5-1544.57" + process $proc$ls180.v:1544$3396 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_sink_ready $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] end - attribute \src "ls180.v:1549.12-1549.67" - process $proc$ls180.v:1549$3400 + attribute \src "ls180.v:1548.12-1548.67" + process $proc$ls180.v:1548$3397 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \main_sdblock2mem_wishbonedmawriter_base_storage $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] end - attribute \src "ls180.v:1550.5-1550.54" - process $proc$ls180.v:1550$3401 + attribute \src "ls180.v:1549.5-1549.54" + process $proc$ls180.v:1549$3398 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] 1'0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_base_re $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] end - attribute \src "ls180.v:1551.12-1551.69" - process $proc$ls180.v:1551$3402 + attribute \src "ls180.v:1550.12-1550.69" + process $proc$ls180.v:1550$3399 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] 0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_length_storage $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] end - attribute \src "ls180.v:1552.5-1552.56" - process $proc$ls180.v:1552$3403 + attribute \src "ls180.v:1551.5-1551.56" + process $proc$ls180.v:1551$3400 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] 1'0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_length_re $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] end - attribute \src "ls180.v:1553.5-1553.61" - process $proc$ls180.v:1553$3404 + attribute \src "ls180.v:1552.5-1552.61" + process $proc$ls180.v:1552$3401 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] 1'0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_enable_storage $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] end - attribute \src "ls180.v:1554.5-1554.56" - process $proc$ls180.v:1554$3405 + attribute \src "ls180.v:1553.5-1553.56" + process $proc$ls180.v:1553$3402 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] 1'0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_enable_re $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] end - attribute \src "ls180.v:1555.5-1555.53" - process $proc$ls180.v:1555$3406 + attribute \src "ls180.v:1554.5-1554.53" + process $proc$ls180.v:1554$3403 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_status $1\main_sdblock2mem_wishbonedmawriter_status[0:0] end - attribute \src "ls180.v:1557.5-1557.59" - process $proc$ls180.v:1557$3407 + attribute \src "ls180.v:1556.5-1556.59" + process $proc$ls180.v:1556$3404 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] 1'0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_loop_storage $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] end - attribute \src "ls180.v:1558.5-1558.54" - process $proc$ls180.v:1558$3408 + attribute \src "ls180.v:1557.5-1557.54" + process $proc$ls180.v:1557$3405 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] 1'0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_loop_re $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] end - attribute \src "ls180.v:156.5-156.44" - process $proc$ls180.v:156$2799 + attribute \src "ls180.v:1559.12-1559.61" + process $proc$ls180.v:1559$3406 assign { } { } - assign $1\main_libresocsim_converter1_skip[0:0] 1'0 + assign $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0 sync always sync init - update \main_libresocsim_converter1_skip $1\main_libresocsim_converter1_skip[0:0] + update \main_sdblock2mem_wishbonedmawriter_offset $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] end - attribute \src "ls180.v:1560.12-1560.61" - process $proc$ls180.v:1560$3409 + attribute \src "ls180.v:156.5-156.44" + process $proc$ls180.v:156$2797 assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0 + assign $1\main_libresocsim_converter1_skip[0:0] 1'0 sync always sync init - update \main_sdblock2mem_wishbonedmawriter_offset $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] + update \main_libresocsim_converter1_skip $1\main_libresocsim_converter1_skip[0:0] end - attribute \src "ls180.v:1563.12-1563.43" - process $proc$ls180.v:1563$3410 + attribute \src "ls180.v:1562.12-1562.43" + process $proc$ls180.v:1562$3407 assign { } { } assign $1\main_interface1_bus_adr[31:0] 0 sync always sync init update \main_interface1_bus_adr $1\main_interface1_bus_adr[31:0] end - attribute \src "ls180.v:1564.12-1564.45" - process $proc$ls180.v:1564$3411 + attribute \src "ls180.v:1563.12-1563.45" + process $proc$ls180.v:1563$3408 assign { } { } assign $0\main_interface1_bus_dat_w[31:0] 0 sync always update \main_interface1_bus_dat_w $0\main_interface1_bus_dat_w[31:0] sync init end - attribute \src "ls180.v:1566.11-1566.41" - process $proc$ls180.v:1566$3412 + attribute \src "ls180.v:1565.11-1565.41" + process $proc$ls180.v:1565$3409 assign { } { } assign $1\main_interface1_bus_sel[3:0] 4'0000 sync always sync init update \main_interface1_bus_sel $1\main_interface1_bus_sel[3:0] end - attribute \src "ls180.v:1567.5-1567.35" - process $proc$ls180.v:1567$3413 + attribute \src "ls180.v:1566.5-1566.35" + process $proc$ls180.v:1566$3410 assign { } { } assign $1\main_interface1_bus_cyc[0:0] 1'0 sync always sync init update \main_interface1_bus_cyc $1\main_interface1_bus_cyc[0:0] end - attribute \src "ls180.v:1568.5-1568.35" - process $proc$ls180.v:1568$3414 + attribute \src "ls180.v:1567.5-1567.35" + process $proc$ls180.v:1567$3411 assign { } { } assign $1\main_interface1_bus_stb[0:0] 1'0 sync always sync init update \main_interface1_bus_stb $1\main_interface1_bus_stb[0:0] end - attribute \src "ls180.v:157.5-157.47" - process $proc$ls180.v:157$2800 + attribute \src "ls180.v:1569.5-1569.34" + process $proc$ls180.v:1569$3412 assign { } { } - assign $1\main_libresocsim_converter1_counter[0:0] 1'0 + assign $1\main_interface1_bus_we[0:0] 1'0 sync always sync init - update \main_libresocsim_converter1_counter $1\main_libresocsim_converter1_counter[0:0] + update \main_interface1_bus_we $1\main_interface1_bus_we[0:0] end - attribute \src "ls180.v:1570.5-1570.34" - process $proc$ls180.v:1570$3415 + attribute \src "ls180.v:157.5-157.47" + process $proc$ls180.v:157$2798 assign { } { } - assign $1\main_interface1_bus_we[0:0] 1'0 + assign $1\main_libresocsim_converter1_counter[0:0] 1'0 sync always sync init - update \main_interface1_bus_we $1\main_interface1_bus_we[0:0] + update \main_libresocsim_converter1_counter $1\main_libresocsim_converter1_counter[0:0] end - attribute \src "ls180.v:1571.11-1571.41" - process $proc$ls180.v:1571$3416 + attribute \src "ls180.v:1570.11-1570.41" + process $proc$ls180.v:1570$3413 assign { } { } assign $0\main_interface1_bus_cti[2:0] 3'000 sync always update \main_interface1_bus_cti $0\main_interface1_bus_cti[2:0] sync init end - attribute \src "ls180.v:1572.11-1572.41" - process $proc$ls180.v:1572$3417 + attribute \src "ls180.v:1571.11-1571.41" + process $proc$ls180.v:1571$3414 assign { } { } assign $0\main_interface1_bus_bte[1:0] 2'00 sync always update \main_interface1_bus_bte $0\main_interface1_bus_bte[1:0] sync init end - attribute \src "ls180.v:1579.5-1579.43" - process $proc$ls180.v:1579$3418 + attribute \src "ls180.v:1578.5-1578.43" + process $proc$ls180.v:1578$3415 assign { } { } assign $1\main_sdmem2block_dma_sink_valid[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_sink_valid $1\main_sdmem2block_dma_sink_valid[0:0] end - attribute \src "ls180.v:1580.5-1580.43" - process $proc$ls180.v:1580$3419 + attribute \src "ls180.v:1579.5-1579.43" + process $proc$ls180.v:1579$3416 assign { } { } assign $1\main_sdmem2block_dma_sink_ready[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_sink_ready $1\main_sdmem2block_dma_sink_ready[0:0] end - attribute \src "ls180.v:1581.5-1581.42" - process $proc$ls180.v:1581$3420 + attribute \src "ls180.v:1580.5-1580.42" + process $proc$ls180.v:1580$3417 assign { } { } assign $1\main_sdmem2block_dma_sink_last[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_sink_last $1\main_sdmem2block_dma_sink_last[0:0] end - attribute \src "ls180.v:1582.12-1582.61" - process $proc$ls180.v:1582$3421 + attribute \src "ls180.v:1581.12-1581.61" + process $proc$ls180.v:1581$3418 assign { } { } assign $1\main_sdmem2block_dma_sink_payload_address[31:0] 0 sync always sync init update \main_sdmem2block_dma_sink_payload_address $1\main_sdmem2block_dma_sink_payload_address[31:0] end - attribute \src "ls180.v:1583.5-1583.45" - process $proc$ls180.v:1583$3422 + attribute \src "ls180.v:1582.5-1582.45" + process $proc$ls180.v:1582$3419 assign { } { } assign $1\main_sdmem2block_dma_source_valid[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_source_valid $1\main_sdmem2block_dma_source_valid[0:0] end - attribute \src "ls180.v:1585.5-1585.45" - process $proc$ls180.v:1585$3423 + attribute \src "ls180.v:1584.5-1584.45" + process $proc$ls180.v:1584$3420 assign { } { } assign $0\main_sdmem2block_dma_source_first[0:0] 1'0 sync always update \main_sdmem2block_dma_source_first $0\main_sdmem2block_dma_source_first[0:0] sync init end - attribute \src "ls180.v:1586.5-1586.44" - process $proc$ls180.v:1586$3424 + attribute \src "ls180.v:1585.5-1585.44" + process $proc$ls180.v:1585$3421 assign { } { } assign $1\main_sdmem2block_dma_source_last[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_source_last $1\main_sdmem2block_dma_source_last[0:0] end - attribute \src "ls180.v:1587.12-1587.60" - process $proc$ls180.v:1587$3425 + attribute \src "ls180.v:1586.12-1586.60" + process $proc$ls180.v:1586$3422 assign { } { } assign $1\main_sdmem2block_dma_source_payload_data[31:0] 0 sync always sync init update \main_sdmem2block_dma_source_payload_data $1\main_sdmem2block_dma_source_payload_data[31:0] end - attribute \src "ls180.v:1588.12-1588.45" - process $proc$ls180.v:1588$3426 + attribute \src "ls180.v:1587.12-1587.45" + process $proc$ls180.v:1587$3423 assign { } { } assign $1\main_sdmem2block_dma_data[31:0] 0 sync always sync init update \main_sdmem2block_dma_data $1\main_sdmem2block_dma_data[31:0] end - attribute \src "ls180.v:1589.12-1589.53" - process $proc$ls180.v:1589$3427 + attribute \src "ls180.v:1588.12-1588.53" + process $proc$ls180.v:1588$3424 assign { } { } assign $1\main_sdmem2block_dma_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \main_sdmem2block_dma_base_storage $1\main_sdmem2block_dma_base_storage[63:0] end - attribute \src "ls180.v:159.12-159.53" - process $proc$ls180.v:159$2801 + attribute \src "ls180.v:1589.5-1589.40" + process $proc$ls180.v:1589$3425 assign { } { } - assign $1\main_libresocsim_converter1_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\main_sdmem2block_dma_base_re[0:0] 1'0 sync always sync init - update \main_libresocsim_converter1_dat_r $1\main_libresocsim_converter1_dat_r[63:0] + update \main_sdmem2block_dma_base_re $1\main_sdmem2block_dma_base_re[0:0] end - attribute \src "ls180.v:1590.5-1590.40" - process $proc$ls180.v:1590$3428 + attribute \src "ls180.v:159.12-159.53" + process $proc$ls180.v:159$2799 assign { } { } - assign $1\main_sdmem2block_dma_base_re[0:0] 1'0 + assign $1\main_libresocsim_converter1_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \main_sdmem2block_dma_base_re $1\main_sdmem2block_dma_base_re[0:0] + update \main_libresocsim_converter1_dat_r $1\main_libresocsim_converter1_dat_r[63:0] end - attribute \src "ls180.v:1591.12-1591.55" - process $proc$ls180.v:1591$3429 + attribute \src "ls180.v:1590.12-1590.55" + process $proc$ls180.v:1590$3426 assign { } { } assign $1\main_sdmem2block_dma_length_storage[31:0] 0 sync always sync init update \main_sdmem2block_dma_length_storage $1\main_sdmem2block_dma_length_storage[31:0] end - attribute \src "ls180.v:1592.5-1592.42" - process $proc$ls180.v:1592$3430 + attribute \src "ls180.v:1591.5-1591.42" + process $proc$ls180.v:1591$3427 assign { } { } assign $1\main_sdmem2block_dma_length_re[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_length_re $1\main_sdmem2block_dma_length_re[0:0] end - attribute \src "ls180.v:1593.5-1593.47" - process $proc$ls180.v:1593$3431 + attribute \src "ls180.v:1592.5-1592.47" + process $proc$ls180.v:1592$3428 assign { } { } assign $1\main_sdmem2block_dma_enable_storage[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_enable_storage $1\main_sdmem2block_dma_enable_storage[0:0] end - attribute \src "ls180.v:1594.5-1594.42" - process $proc$ls180.v:1594$3432 + attribute \src "ls180.v:1593.5-1593.42" + process $proc$ls180.v:1593$3429 assign { } { } assign $1\main_sdmem2block_dma_enable_re[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_enable_re $1\main_sdmem2block_dma_enable_re[0:0] end - attribute \src "ls180.v:1595.5-1595.44" - process $proc$ls180.v:1595$3433 + attribute \src "ls180.v:1594.5-1594.44" + process $proc$ls180.v:1594$3430 assign { } { } assign $1\main_sdmem2block_dma_done_status[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_done_status $1\main_sdmem2block_dma_done_status[0:0] end - attribute \src "ls180.v:1597.5-1597.45" - process $proc$ls180.v:1597$3434 + attribute \src "ls180.v:1596.5-1596.45" + process $proc$ls180.v:1596$3431 assign { } { } assign $1\main_sdmem2block_dma_loop_storage[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_loop_storage $1\main_sdmem2block_dma_loop_storage[0:0] end - attribute \src "ls180.v:1598.5-1598.40" - process $proc$ls180.v:1598$3435 + attribute \src "ls180.v:1597.5-1597.40" + process $proc$ls180.v:1597$3432 assign { } { } assign $1\main_sdmem2block_dma_loop_re[0:0] 1'0 sync always @@ -112868,15 +112828,15 @@ module \ls180 update \main_sdmem2block_dma_loop_re $1\main_sdmem2block_dma_loop_re[0:0] end attribute \src "ls180.v:160.12-160.71" - process $proc$ls180.v:160$2802 + process $proc$ls180.v:160$2800 assign { } { } assign $1\main_libresocsim_interface2_converted_interface_adr[29:0] 30'000000000000000000000000000000 sync always sync init update \main_libresocsim_interface2_converted_interface_adr $1\main_libresocsim_interface2_converted_interface_adr[29:0] end - attribute \src "ls180.v:1602.12-1602.47" - process $proc$ls180.v:1602$3436 + attribute \src "ls180.v:1601.12-1601.47" + process $proc$ls180.v:1601$3433 assign { } { } assign $1\main_sdmem2block_dma_offset[31:0] 0 sync always @@ -112884,23 +112844,23 @@ module \ls180 update \main_sdmem2block_dma_offset $1\main_sdmem2block_dma_offset[31:0] end attribute \src "ls180.v:161.12-161.73" - process $proc$ls180.v:161$2803 + process $proc$ls180.v:161$2801 assign { } { } assign $1\main_libresocsim_interface2_converted_interface_dat_w[31:0] 0 sync always sync init update \main_libresocsim_interface2_converted_interface_dat_w $1\main_libresocsim_interface2_converted_interface_dat_w[31:0] end - attribute \src "ls180.v:1614.11-1614.64" - process $proc$ls180.v:1614$3437 + attribute \src "ls180.v:1613.11-1613.64" + process $proc$ls180.v:1613$3434 assign { } { } assign $1\main_sdmem2block_converter_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdmem2block_converter_source_payload_data $1\main_sdmem2block_converter_source_payload_data[7:0] end - attribute \src "ls180.v:1616.11-1616.48" - process $proc$ls180.v:1616$3438 + attribute \src "ls180.v:1615.11-1615.48" + process $proc$ls180.v:1615$3435 assign { } { } assign $1\main_sdmem2block_converter_mux[1:0] 2'00 sync always @@ -112908,55 +112868,55 @@ module \ls180 update \main_sdmem2block_converter_mux $1\main_sdmem2block_converter_mux[1:0] end attribute \src "ls180.v:163.11-163.69" - process $proc$ls180.v:163$2804 + process $proc$ls180.v:163$2802 assign { } { } assign $1\main_libresocsim_interface2_converted_interface_sel[3:0] 4'0000 sync always sync init update \main_libresocsim_interface2_converted_interface_sel $1\main_libresocsim_interface2_converted_interface_sel[3:0] end - attribute \src "ls180.v:164.5-164.63" - process $proc$ls180.v:164$2805 + attribute \src "ls180.v:1639.11-1639.45" + process $proc$ls180.v:1639$3436 assign { } { } - assign $1\main_libresocsim_interface2_converted_interface_cyc[0:0] 1'0 + assign $1\main_sdmem2block_fifo_level[5:0] 6'000000 sync always sync init - update \main_libresocsim_interface2_converted_interface_cyc $1\main_libresocsim_interface2_converted_interface_cyc[0:0] + update \main_sdmem2block_fifo_level $1\main_sdmem2block_fifo_level[5:0] end - attribute \src "ls180.v:1640.11-1640.45" - process $proc$ls180.v:1640$3439 + attribute \src "ls180.v:164.5-164.63" + process $proc$ls180.v:164$2803 assign { } { } - assign $1\main_sdmem2block_fifo_level[5:0] 6'000000 + assign $1\main_libresocsim_interface2_converted_interface_cyc[0:0] 1'0 sync always sync init - update \main_sdmem2block_fifo_level $1\main_sdmem2block_fifo_level[5:0] + update \main_libresocsim_interface2_converted_interface_cyc $1\main_libresocsim_interface2_converted_interface_cyc[0:0] end - attribute \src "ls180.v:1641.5-1641.41" - process $proc$ls180.v:1641$3440 + attribute \src "ls180.v:1640.5-1640.41" + process $proc$ls180.v:1640$3437 assign { } { } assign $0\main_sdmem2block_fifo_replace[0:0] 1'0 sync always update \main_sdmem2block_fifo_replace $0\main_sdmem2block_fifo_replace[0:0] sync init end - attribute \src "ls180.v:1642.11-1642.47" - process $proc$ls180.v:1642$3441 + attribute \src "ls180.v:1641.11-1641.47" + process $proc$ls180.v:1641$3438 assign { } { } assign $1\main_sdmem2block_fifo_produce[4:0] 5'00000 sync always sync init update \main_sdmem2block_fifo_produce $1\main_sdmem2block_fifo_produce[4:0] end - attribute \src "ls180.v:1643.11-1643.47" - process $proc$ls180.v:1643$3442 + attribute \src "ls180.v:1642.11-1642.47" + process $proc$ls180.v:1642$3439 assign { } { } assign $1\main_sdmem2block_fifo_consume[4:0] 5'00000 sync always sync init update \main_sdmem2block_fifo_consume $1\main_sdmem2block_fifo_consume[4:0] end - attribute \src "ls180.v:1644.11-1644.50" - process $proc$ls180.v:1644$3443 + attribute \src "ls180.v:1643.11-1643.50" + process $proc$ls180.v:1643$3440 assign { } { } assign $1\main_sdmem2block_fifo_wrport_adr[4:0] 5'00000 sync always @@ -112964,55 +112924,55 @@ module \ls180 update \main_sdmem2block_fifo_wrport_adr $1\main_sdmem2block_fifo_wrport_adr[4:0] end attribute \src "ls180.v:165.5-165.63" - process $proc$ls180.v:165$2806 + process $proc$ls180.v:165$2804 assign { } { } assign $1\main_libresocsim_interface2_converted_interface_stb[0:0] 1'0 sync always sync init update \main_libresocsim_interface2_converted_interface_stb $1\main_libresocsim_interface2_converted_interface_stb[0:0] end - attribute \src "ls180.v:1659.5-1659.29" - process $proc$ls180.v:1659$3444 + attribute \src "ls180.v:1658.5-1658.29" + process $proc$ls180.v:1658$3441 assign { } { } assign $1\libresocsim_done0[0:0] 1'0 sync always sync init update \libresocsim_done0 $1\libresocsim_done0[0:0] end - attribute \src "ls180.v:1660.5-1660.27" - process $proc$ls180.v:1660$3445 + attribute \src "ls180.v:1659.5-1659.27" + process $proc$ls180.v:1659$3442 assign { } { } assign $1\libresocsim_irq[0:0] 1'0 sync always sync init update \libresocsim_irq $1\libresocsim_irq[0:0] end - attribute \src "ls180.v:1662.11-1662.34" - process $proc$ls180.v:1662$3446 + attribute \src "ls180.v:1661.11-1661.34" + process $proc$ls180.v:1661$3443 assign { } { } assign $1\libresocsim_miso[7:0] 8'00000000 sync always sync init update \libresocsim_miso $1\libresocsim_miso[7:0] end - attribute \src "ls180.v:1666.5-1666.30" - process $proc$ls180.v:1666$3447 + attribute \src "ls180.v:1665.5-1665.30" + process $proc$ls180.v:1665$3444 assign { } { } assign $1\libresocsim_start1[0:0] 1'0 sync always sync init update \libresocsim_start1 $1\libresocsim_start1[0:0] end - attribute \src "ls180.v:1668.12-1668.47" - process $proc$ls180.v:1668$3448 + attribute \src "ls180.v:1667.12-1667.47" + process $proc$ls180.v:1667$3445 assign { } { } assign $1\libresocsim_control_storage[15:0] 16'0000000000000000 sync always sync init update \libresocsim_control_storage $1\libresocsim_control_storage[15:0] end - attribute \src "ls180.v:1669.5-1669.34" - process $proc$ls180.v:1669$3449 + attribute \src "ls180.v:1668.5-1668.34" + process $proc$ls180.v:1668$3446 assign { } { } assign $1\libresocsim_control_re[0:0] 1'0 sync always @@ -113020,359 +112980,359 @@ module \ls180 update \libresocsim_control_re $1\libresocsim_control_re[0:0] end attribute \src "ls180.v:167.5-167.62" - process $proc$ls180.v:167$2807 + process $proc$ls180.v:167$2805 assign { } { } assign $1\main_libresocsim_interface2_converted_interface_we[0:0] 1'0 sync always sync init update \main_libresocsim_interface2_converted_interface_we $1\main_libresocsim_interface2_converted_interface_we[0:0] end - attribute \src "ls180.v:1673.11-1673.42" - process $proc$ls180.v:1673$3450 + attribute \src "ls180.v:1672.11-1672.42" + process $proc$ls180.v:1672$3447 assign { } { } assign $1\libresocsim_mosi_storage[7:0] 8'00000000 sync always sync init update \libresocsim_mosi_storage $1\libresocsim_mosi_storage[7:0] end - attribute \src "ls180.v:1674.5-1674.31" - process $proc$ls180.v:1674$3451 + attribute \src "ls180.v:1673.5-1673.31" + process $proc$ls180.v:1673$3448 assign { } { } assign $1\libresocsim_mosi_re[0:0] 1'0 sync always sync init update \libresocsim_mosi_re $1\libresocsim_mosi_re[0:0] end - attribute \src "ls180.v:1678.5-1678.34" - process $proc$ls180.v:1678$3452 + attribute \src "ls180.v:1677.5-1677.34" + process $proc$ls180.v:1677$3449 assign { } { } assign $1\libresocsim_cs_storage[0:0] 1'1 sync always sync init update \libresocsim_cs_storage $1\libresocsim_cs_storage[0:0] end - attribute \src "ls180.v:1679.5-1679.29" - process $proc$ls180.v:1679$3453 + attribute \src "ls180.v:1678.5-1678.29" + process $proc$ls180.v:1678$3450 assign { } { } assign $1\libresocsim_cs_re[0:0] 1'0 sync always sync init update \libresocsim_cs_re $1\libresocsim_cs_re[0:0] end - attribute \src "ls180.v:168.11-168.69" - process $proc$ls180.v:168$2808 + attribute \src "ls180.v:1679.5-1679.40" + process $proc$ls180.v:1679$3451 assign { } { } - assign $0\main_libresocsim_interface2_converted_interface_cti[2:0] 3'000 + assign $1\libresocsim_loopback_storage[0:0] 1'0 sync always - update \main_libresocsim_interface2_converted_interface_cti $0\main_libresocsim_interface2_converted_interface_cti[2:0] sync init + update \libresocsim_loopback_storage $1\libresocsim_loopback_storage[0:0] end - attribute \src "ls180.v:1680.5-1680.40" - process $proc$ls180.v:1680$3454 + attribute \src "ls180.v:168.11-168.69" + process $proc$ls180.v:168$2806 assign { } { } - assign $1\libresocsim_loopback_storage[0:0] 1'0 + assign $0\main_libresocsim_interface2_converted_interface_cti[2:0] 3'000 sync always + update \main_libresocsim_interface2_converted_interface_cti $0\main_libresocsim_interface2_converted_interface_cti[2:0] sync init - update \libresocsim_loopback_storage $1\libresocsim_loopback_storage[0:0] end - attribute \src "ls180.v:1681.5-1681.35" - process $proc$ls180.v:1681$3455 + attribute \src "ls180.v:1680.5-1680.35" + process $proc$ls180.v:1680$3452 assign { } { } assign $1\libresocsim_loopback_re[0:0] 1'0 sync always sync init update \libresocsim_loopback_re $1\libresocsim_loopback_re[0:0] end - attribute \src "ls180.v:1682.5-1682.34" - process $proc$ls180.v:1682$3456 + attribute \src "ls180.v:1681.5-1681.34" + process $proc$ls180.v:1681$3453 assign { } { } assign $1\libresocsim_clk_enable[0:0] 1'0 sync always sync init update \libresocsim_clk_enable $1\libresocsim_clk_enable[0:0] end - attribute \src "ls180.v:1683.5-1683.33" - process $proc$ls180.v:1683$3457 + attribute \src "ls180.v:1682.5-1682.33" + process $proc$ls180.v:1682$3454 assign { } { } assign $1\libresocsim_cs_enable[0:0] 1'0 sync always sync init update \libresocsim_cs_enable $1\libresocsim_cs_enable[0:0] end - attribute \src "ls180.v:1684.11-1684.35" - process $proc$ls180.v:1684$3458 + attribute \src "ls180.v:1683.11-1683.35" + process $proc$ls180.v:1683$3455 assign { } { } assign $1\libresocsim_count[2:0] 3'000 sync always sync init update \libresocsim_count $1\libresocsim_count[2:0] end - attribute \src "ls180.v:1685.5-1685.34" - process $proc$ls180.v:1685$3459 + attribute \src "ls180.v:1684.5-1684.34" + process $proc$ls180.v:1684$3456 assign { } { } assign $1\libresocsim_mosi_latch[0:0] 1'0 sync always sync init update \libresocsim_mosi_latch $1\libresocsim_mosi_latch[0:0] end - attribute \src "ls180.v:1686.5-1686.34" - process $proc$ls180.v:1686$3460 + attribute \src "ls180.v:1685.5-1685.34" + process $proc$ls180.v:1685$3457 assign { } { } assign $1\libresocsim_miso_latch[0:0] 1'0 sync always sync init update \libresocsim_miso_latch $1\libresocsim_miso_latch[0:0] end - attribute \src "ls180.v:1687.12-1687.44" - process $proc$ls180.v:1687$3461 + attribute \src "ls180.v:1686.12-1686.44" + process $proc$ls180.v:1686$3458 assign { } { } assign $1\libresocsim_clk_divider1[15:0] 16'0000000000000000 sync always sync init update \libresocsim_clk_divider1 $1\libresocsim_clk_divider1[15:0] end - attribute \src "ls180.v:169.11-169.69" - process $proc$ls180.v:169$2809 + attribute \src "ls180.v:1689.11-1689.39" + process $proc$ls180.v:1689$3459 assign { } { } - assign $0\main_libresocsim_interface2_converted_interface_bte[1:0] 2'00 + assign $1\libresocsim_mosi_data[7:0] 8'00000000 sync always - update \main_libresocsim_interface2_converted_interface_bte $0\main_libresocsim_interface2_converted_interface_bte[1:0] sync init + update \libresocsim_mosi_data $1\libresocsim_mosi_data[7:0] end - attribute \src "ls180.v:1690.11-1690.39" - process $proc$ls180.v:1690$3462 + attribute \src "ls180.v:169.11-169.69" + process $proc$ls180.v:169$2807 assign { } { } - assign $1\libresocsim_mosi_data[7:0] 8'00000000 + assign $0\main_libresocsim_interface2_converted_interface_bte[1:0] 2'00 sync always + update \main_libresocsim_interface2_converted_interface_bte $0\main_libresocsim_interface2_converted_interface_bte[1:0] sync init - update \libresocsim_mosi_data $1\libresocsim_mosi_data[7:0] end - attribute \src "ls180.v:1691.11-1691.38" - process $proc$ls180.v:1691$3463 + attribute \src "ls180.v:1690.11-1690.38" + process $proc$ls180.v:1690$3460 assign { } { } assign $1\libresocsim_mosi_sel[2:0] 3'000 sync always sync init update \libresocsim_mosi_sel $1\libresocsim_mosi_sel[2:0] end - attribute \src "ls180.v:1692.11-1692.39" - process $proc$ls180.v:1692$3464 + attribute \src "ls180.v:1691.11-1691.39" + process $proc$ls180.v:1691$3461 assign { } { } assign $1\libresocsim_miso_data[7:0] 8'00000000 sync always sync init update \libresocsim_miso_data $1\libresocsim_miso_data[7:0] end - attribute \src "ls180.v:1693.12-1693.41" - process $proc$ls180.v:1693$3465 + attribute \src "ls180.v:1692.12-1692.41" + process $proc$ls180.v:1692$3462 assign { } { } assign $1\libresocsim_storage[15:0] 16'0000000001111101 sync always sync init update \libresocsim_storage $1\libresocsim_storage[15:0] end - attribute \src "ls180.v:1694.5-1694.26" - process $proc$ls180.v:1694$3466 + attribute \src "ls180.v:1693.5-1693.26" + process $proc$ls180.v:1693$3463 assign { } { } assign $1\libresocsim_re[0:0] 1'0 sync always sync init update \libresocsim_re $1\libresocsim_re[0:0] end - attribute \src "ls180.v:1695.5-1695.36" - process $proc$ls180.v:1695$3467 + attribute \src "ls180.v:1694.5-1694.36" + process $proc$ls180.v:1694$3464 assign { } { } assign $1\builder_converter0_state[0:0] 1'0 sync always sync init update \builder_converter0_state $1\builder_converter0_state[0:0] end - attribute \src "ls180.v:1696.5-1696.41" - process $proc$ls180.v:1696$3468 + attribute \src "ls180.v:1695.5-1695.41" + process $proc$ls180.v:1695$3465 assign { } { } assign $1\builder_converter0_next_state[0:0] 1'0 sync always sync init update \builder_converter0_next_state $1\builder_converter0_next_state[0:0] end - attribute \src "ls180.v:1697.5-1697.69" - process $proc$ls180.v:1697$3469 + attribute \src "ls180.v:1696.5-1696.69" + process $proc$ls180.v:1696$3466 assign { } { } assign $1\main_libresocsim_converter0_counter_converter0_next_value[0:0] 1'0 sync always sync init update \main_libresocsim_converter0_counter_converter0_next_value $1\main_libresocsim_converter0_counter_converter0_next_value[0:0] end - attribute \src "ls180.v:1698.5-1698.72" - process $proc$ls180.v:1698$3470 + attribute \src "ls180.v:1697.5-1697.72" + process $proc$ls180.v:1697$3467 assign { } { } assign $1\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'0 sync always sync init update \main_libresocsim_converter0_counter_converter0_next_value_ce $1\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] end - attribute \src "ls180.v:1699.5-1699.36" - process $proc$ls180.v:1699$3471 + attribute \src "ls180.v:1698.5-1698.36" + process $proc$ls180.v:1698$3468 assign { } { } assign $1\builder_converter1_state[0:0] 1'0 sync always sync init update \builder_converter1_state $1\builder_converter1_state[0:0] end - attribute \src "ls180.v:1700.5-1700.41" - process $proc$ls180.v:1700$3472 + attribute \src "ls180.v:1699.5-1699.41" + process $proc$ls180.v:1699$3469 assign { } { } assign $1\builder_converter1_next_state[0:0] 1'0 sync always sync init update \builder_converter1_next_state $1\builder_converter1_next_state[0:0] end - attribute \src "ls180.v:1701.5-1701.69" - process $proc$ls180.v:1701$3473 + attribute \src "ls180.v:1700.5-1700.69" + process $proc$ls180.v:1700$3470 assign { } { } assign $1\main_libresocsim_converter1_counter_converter1_next_value[0:0] 1'0 sync always sync init update \main_libresocsim_converter1_counter_converter1_next_value $1\main_libresocsim_converter1_counter_converter1_next_value[0:0] end - attribute \src "ls180.v:1702.5-1702.72" - process $proc$ls180.v:1702$3474 + attribute \src "ls180.v:1701.5-1701.72" + process $proc$ls180.v:1701$3471 assign { } { } assign $1\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'0 sync always sync init update \main_libresocsim_converter1_counter_converter1_next_value_ce $1\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] end - attribute \src "ls180.v:1703.5-1703.36" - process $proc$ls180.v:1703$3475 + attribute \src "ls180.v:1702.5-1702.36" + process $proc$ls180.v:1702$3472 assign { } { } assign $1\builder_converter2_state[0:0] 1'0 sync always sync init update \builder_converter2_state $1\builder_converter2_state[0:0] end - attribute \src "ls180.v:1704.5-1704.41" - process $proc$ls180.v:1704$3476 + attribute \src "ls180.v:1703.5-1703.41" + process $proc$ls180.v:1703$3473 assign { } { } assign $1\builder_converter2_next_state[0:0] 1'0 sync always sync init update \builder_converter2_next_state $1\builder_converter2_next_state[0:0] end - attribute \src "ls180.v:1705.5-1705.69" - process $proc$ls180.v:1705$3477 + attribute \src "ls180.v:1704.5-1704.69" + process $proc$ls180.v:1704$3474 assign { } { } assign $1\main_libresocsim_converter2_counter_converter2_next_value[0:0] 1'0 sync always sync init update \main_libresocsim_converter2_counter_converter2_next_value $1\main_libresocsim_converter2_counter_converter2_next_value[0:0] end - attribute \src "ls180.v:1706.5-1706.72" - process $proc$ls180.v:1706$3478 + attribute \src "ls180.v:1705.5-1705.72" + process $proc$ls180.v:1705$3475 assign { } { } assign $1\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'0 sync always sync init update \main_libresocsim_converter2_counter_converter2_next_value_ce $1\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] end - attribute \src "ls180.v:1707.11-1707.41" - process $proc$ls180.v:1707$3479 + attribute \src "ls180.v:1706.11-1706.41" + process $proc$ls180.v:1706$3476 assign { } { } assign $1\builder_refresher_state[1:0] 2'00 sync always sync init update \builder_refresher_state $1\builder_refresher_state[1:0] end - attribute \src "ls180.v:1708.11-1708.46" - process $proc$ls180.v:1708$3480 + attribute \src "ls180.v:1707.11-1707.46" + process $proc$ls180.v:1707$3477 assign { } { } assign $1\builder_refresher_next_state[1:0] 2'00 sync always sync init update \builder_refresher_next_state $1\builder_refresher_next_state[1:0] end - attribute \src "ls180.v:1709.11-1709.44" - process $proc$ls180.v:1709$3481 + attribute \src "ls180.v:1708.11-1708.44" + process $proc$ls180.v:1708$3478 assign { } { } assign $1\builder_bankmachine0_state[2:0] 3'000 sync always sync init update \builder_bankmachine0_state $1\builder_bankmachine0_state[2:0] end - attribute \src "ls180.v:171.5-171.44" - process $proc$ls180.v:171$2810 + attribute \src "ls180.v:1709.11-1709.49" + process $proc$ls180.v:1709$3479 assign { } { } - assign $1\main_libresocsim_converter2_skip[0:0] 1'0 + assign $1\builder_bankmachine0_next_state[2:0] 3'000 sync always sync init - update \main_libresocsim_converter2_skip $1\main_libresocsim_converter2_skip[0:0] + update \builder_bankmachine0_next_state $1\builder_bankmachine0_next_state[2:0] end - attribute \src "ls180.v:1710.11-1710.49" - process $proc$ls180.v:1710$3482 + attribute \src "ls180.v:171.5-171.44" + process $proc$ls180.v:171$2808 assign { } { } - assign $1\builder_bankmachine0_next_state[2:0] 3'000 + assign $1\main_libresocsim_converter2_skip[0:0] 1'0 sync always sync init - update \builder_bankmachine0_next_state $1\builder_bankmachine0_next_state[2:0] + update \main_libresocsim_converter2_skip $1\main_libresocsim_converter2_skip[0:0] end - attribute \src "ls180.v:1711.11-1711.44" - process $proc$ls180.v:1711$3483 + attribute \src "ls180.v:1710.11-1710.44" + process $proc$ls180.v:1710$3480 assign { } { } assign $1\builder_bankmachine1_state[2:0] 3'000 sync always sync init update \builder_bankmachine1_state $1\builder_bankmachine1_state[2:0] end - attribute \src "ls180.v:1712.11-1712.49" - process $proc$ls180.v:1712$3484 + attribute \src "ls180.v:1711.11-1711.49" + process $proc$ls180.v:1711$3481 assign { } { } assign $1\builder_bankmachine1_next_state[2:0] 3'000 sync always sync init update \builder_bankmachine1_next_state $1\builder_bankmachine1_next_state[2:0] end - attribute \src "ls180.v:1713.11-1713.44" - process $proc$ls180.v:1713$3485 + attribute \src "ls180.v:1712.11-1712.44" + process $proc$ls180.v:1712$3482 assign { } { } assign $1\builder_bankmachine2_state[2:0] 3'000 sync always sync init update \builder_bankmachine2_state $1\builder_bankmachine2_state[2:0] end - attribute \src "ls180.v:1714.11-1714.49" - process $proc$ls180.v:1714$3486 + attribute \src "ls180.v:1713.11-1713.49" + process $proc$ls180.v:1713$3483 assign { } { } assign $1\builder_bankmachine2_next_state[2:0] 3'000 sync always sync init update \builder_bankmachine2_next_state $1\builder_bankmachine2_next_state[2:0] end - attribute \src "ls180.v:1715.11-1715.44" - process $proc$ls180.v:1715$3487 + attribute \src "ls180.v:1714.11-1714.44" + process $proc$ls180.v:1714$3484 assign { } { } assign $1\builder_bankmachine3_state[2:0] 3'000 sync always sync init update \builder_bankmachine3_state $1\builder_bankmachine3_state[2:0] end - attribute \src "ls180.v:1716.11-1716.49" - process $proc$ls180.v:1716$3488 + attribute \src "ls180.v:1715.11-1715.49" + process $proc$ls180.v:1715$3485 assign { } { } assign $1\builder_bankmachine3_next_state[2:0] 3'000 sync always sync init update \builder_bankmachine3_next_state $1\builder_bankmachine3_next_state[2:0] end - attribute \src "ls180.v:1717.11-1717.43" - process $proc$ls180.v:1717$3489 + attribute \src "ls180.v:1716.11-1716.43" + process $proc$ls180.v:1716$3486 assign { } { } assign $1\builder_multiplexer_state[2:0] 3'000 sync always sync init update \builder_multiplexer_state $1\builder_multiplexer_state[2:0] end - attribute \src "ls180.v:1718.11-1718.48" - process $proc$ls180.v:1718$3490 + attribute \src "ls180.v:1717.11-1717.48" + process $proc$ls180.v:1717$3487 assign { } { } assign $1\builder_multiplexer_next_state[2:0] 3'000 sync always @@ -113380,863 +113340,863 @@ module \ls180 update \builder_multiplexer_next_state $1\builder_multiplexer_next_state[2:0] end attribute \src "ls180.v:172.5-172.47" - process $proc$ls180.v:172$2811 + process $proc$ls180.v:172$2809 assign { } { } assign $1\main_libresocsim_converter2_counter[0:0] 1'0 sync always sync init update \main_libresocsim_converter2_counter $1\main_libresocsim_converter2_counter[0:0] end - attribute \src "ls180.v:1731.5-1731.27" - process $proc$ls180.v:1731$3491 + attribute \src "ls180.v:1730.5-1730.27" + process $proc$ls180.v:1730$3488 assign { } { } assign $0\builder_locked0[0:0] 1'0 sync always update \builder_locked0 $0\builder_locked0[0:0] sync init end - attribute \src "ls180.v:1732.5-1732.27" - process $proc$ls180.v:1732$3492 + attribute \src "ls180.v:1731.5-1731.27" + process $proc$ls180.v:1731$3489 assign { } { } assign $0\builder_locked1[0:0] 1'0 sync always update \builder_locked1 $0\builder_locked1[0:0] sync init end - attribute \src "ls180.v:1733.5-1733.27" - process $proc$ls180.v:1733$3493 + attribute \src "ls180.v:1732.5-1732.27" + process $proc$ls180.v:1732$3490 assign { } { } assign $0\builder_locked2[0:0] 1'0 sync always update \builder_locked2 $0\builder_locked2[0:0] sync init end - attribute \src "ls180.v:1734.5-1734.27" - process $proc$ls180.v:1734$3494 + attribute \src "ls180.v:1733.5-1733.27" + process $proc$ls180.v:1733$3491 assign { } { } assign $0\builder_locked3[0:0] 1'0 sync always update \builder_locked3 $0\builder_locked3[0:0] sync init end - attribute \src "ls180.v:1735.5-1735.42" - process $proc$ls180.v:1735$3495 + attribute \src "ls180.v:1734.5-1734.42" + process $proc$ls180.v:1734$3492 assign { } { } assign $1\builder_new_master_wdata_ready[0:0] 1'0 sync always sync init update \builder_new_master_wdata_ready $1\builder_new_master_wdata_ready[0:0] end - attribute \src "ls180.v:1736.5-1736.43" - process $proc$ls180.v:1736$3496 + attribute \src "ls180.v:1735.5-1735.43" + process $proc$ls180.v:1735$3493 assign { } { } assign $1\builder_new_master_rdata_valid0[0:0] 1'0 sync always sync init update \builder_new_master_rdata_valid0 $1\builder_new_master_rdata_valid0[0:0] end - attribute \src "ls180.v:1737.5-1737.43" - process $proc$ls180.v:1737$3497 + attribute \src "ls180.v:1736.5-1736.43" + process $proc$ls180.v:1736$3494 assign { } { } assign $1\builder_new_master_rdata_valid1[0:0] 1'0 sync always sync init update \builder_new_master_rdata_valid1 $1\builder_new_master_rdata_valid1[0:0] end - attribute \src "ls180.v:1738.5-1738.43" - process $proc$ls180.v:1738$3498 + attribute \src "ls180.v:1737.5-1737.43" + process $proc$ls180.v:1737$3495 assign { } { } assign $1\builder_new_master_rdata_valid2[0:0] 1'0 sync always sync init update \builder_new_master_rdata_valid2 $1\builder_new_master_rdata_valid2[0:0] end - attribute \src "ls180.v:1739.5-1739.43" - process $proc$ls180.v:1739$3499 + attribute \src "ls180.v:1738.5-1738.43" + process $proc$ls180.v:1738$3496 assign { } { } assign $1\builder_new_master_rdata_valid3[0:0] 1'0 sync always sync init update \builder_new_master_rdata_valid3 $1\builder_new_master_rdata_valid3[0:0] end - attribute \src "ls180.v:174.12-174.53" - process $proc$ls180.v:174$2812 + attribute \src "ls180.v:1739.5-1739.35" + process $proc$ls180.v:1739$3497 assign { } { } - assign $1\main_libresocsim_converter2_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\builder_converter_state[0:0] 1'0 sync always sync init - update \main_libresocsim_converter2_dat_r $1\main_libresocsim_converter2_dat_r[63:0] + update \builder_converter_state $1\builder_converter_state[0:0] end - attribute \src "ls180.v:1740.5-1740.35" - process $proc$ls180.v:1740$3500 + attribute \src "ls180.v:174.12-174.53" + process $proc$ls180.v:174$2810 assign { } { } - assign $1\builder_converter_state[0:0] 1'0 + assign $1\main_libresocsim_converter2_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \builder_converter_state $1\builder_converter_state[0:0] + update \main_libresocsim_converter2_dat_r $1\main_libresocsim_converter2_dat_r[63:0] end - attribute \src "ls180.v:1741.5-1741.40" - process $proc$ls180.v:1741$3501 + attribute \src "ls180.v:1740.5-1740.40" + process $proc$ls180.v:1740$3498 assign { } { } assign $1\builder_converter_next_state[0:0] 1'0 sync always sync init update \builder_converter_next_state $1\builder_converter_next_state[0:0] end - attribute \src "ls180.v:1742.5-1742.55" - process $proc$ls180.v:1742$3502 + attribute \src "ls180.v:1741.5-1741.55" + process $proc$ls180.v:1741$3499 assign { } { } assign $1\main_converter_counter_converter_next_value[0:0] 1'0 sync always sync init update \main_converter_counter_converter_next_value $1\main_converter_counter_converter_next_value[0:0] end - attribute \src "ls180.v:1743.5-1743.58" - process $proc$ls180.v:1743$3503 + attribute \src "ls180.v:1742.5-1742.58" + process $proc$ls180.v:1742$3500 assign { } { } assign $1\main_converter_counter_converter_next_value_ce[0:0] 1'0 sync always sync init update \main_converter_counter_converter_next_value_ce $1\main_converter_counter_converter_next_value_ce[0:0] end - attribute \src "ls180.v:1744.11-1744.42" - process $proc$ls180.v:1744$3504 + attribute \src "ls180.v:1743.11-1743.42" + process $proc$ls180.v:1743$3501 assign { } { } assign $1\builder_spimaster0_state[1:0] 2'00 sync always sync init update \builder_spimaster0_state $1\builder_spimaster0_state[1:0] end - attribute \src "ls180.v:1745.11-1745.47" - process $proc$ls180.v:1745$3505 + attribute \src "ls180.v:1744.11-1744.47" + process $proc$ls180.v:1744$3502 assign { } { } assign $1\builder_spimaster0_next_state[1:0] 2'00 sync always sync init update \builder_spimaster0_next_state $1\builder_spimaster0_next_state[1:0] end - attribute \src "ls180.v:1746.11-1746.61" - process $proc$ls180.v:1746$3506 + attribute \src "ls180.v:1745.11-1745.61" + process $proc$ls180.v:1745$3503 assign { } { } assign $1\main_spi_master_count_spimaster0_next_value[2:0] 3'000 sync always sync init update \main_spi_master_count_spimaster0_next_value $1\main_spi_master_count_spimaster0_next_value[2:0] end - attribute \src "ls180.v:1747.5-1747.58" - process $proc$ls180.v:1747$3507 + attribute \src "ls180.v:1746.5-1746.58" + process $proc$ls180.v:1746$3504 assign { } { } assign $1\main_spi_master_count_spimaster0_next_value_ce[0:0] 1'0 sync always sync init update \main_spi_master_count_spimaster0_next_value_ce $1\main_spi_master_count_spimaster0_next_value_ce[0:0] end - attribute \src "ls180.v:1748.5-1748.41" - process $proc$ls180.v:1748$3508 + attribute \src "ls180.v:1747.5-1747.41" + process $proc$ls180.v:1747$3505 assign { } { } assign $1\builder_sdphy_sdphyinit_state[0:0] 1'0 sync always sync init update \builder_sdphy_sdphyinit_state $1\builder_sdphy_sdphyinit_state[0:0] end - attribute \src "ls180.v:1749.5-1749.46" - process $proc$ls180.v:1749$3509 + attribute \src "ls180.v:1748.5-1748.46" + process $proc$ls180.v:1748$3506 assign { } { } assign $1\builder_sdphy_sdphyinit_next_state[0:0] 1'0 sync always sync init update \builder_sdphy_sdphyinit_next_state $1\builder_sdphy_sdphyinit_next_state[0:0] end - attribute \src "ls180.v:1750.11-1750.66" - process $proc$ls180.v:1750$3510 + attribute \src "ls180.v:1749.11-1749.66" + process $proc$ls180.v:1749$3507 assign { } { } assign $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 sync always sync init update \main_sdphy_init_count_sdphy_sdphyinit_next_value $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] end - attribute \src "ls180.v:1751.5-1751.63" - process $proc$ls180.v:1751$3511 + attribute \src "ls180.v:1750.5-1750.63" + process $proc$ls180.v:1750$3508 assign { } { } assign $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'0 sync always sync init update \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] end - attribute \src "ls180.v:1752.11-1752.47" - process $proc$ls180.v:1752$3512 + attribute \src "ls180.v:1751.11-1751.47" + process $proc$ls180.v:1751$3509 assign { } { } assign $1\builder_sdphy_sdphycmdw_state[1:0] 2'00 sync always sync init update \builder_sdphy_sdphycmdw_state $1\builder_sdphy_sdphycmdw_state[1:0] end - attribute \src "ls180.v:1753.11-1753.52" - process $proc$ls180.v:1753$3513 + attribute \src "ls180.v:1752.11-1752.52" + process $proc$ls180.v:1752$3510 assign { } { } assign $1\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 sync always sync init update \builder_sdphy_sdphycmdw_next_state $1\builder_sdphy_sdphycmdw_next_state[1:0] end - attribute \src "ls180.v:1754.11-1754.66" - process $proc$ls180.v:1754$3514 + attribute \src "ls180.v:1753.11-1753.66" + process $proc$ls180.v:1753$3511 assign { } { } assign $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 sync always sync init update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] end - attribute \src "ls180.v:1755.5-1755.63" - process $proc$ls180.v:1755$3515 + attribute \src "ls180.v:1754.5-1754.63" + process $proc$ls180.v:1754$3512 assign { } { } assign $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'0 sync always sync init update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] end - attribute \src "ls180.v:1756.11-1756.47" - process $proc$ls180.v:1756$3516 + attribute \src "ls180.v:1755.11-1755.47" + process $proc$ls180.v:1755$3513 assign { } { } assign $1\builder_sdphy_sdphycmdr_state[2:0] 3'000 sync always sync init update \builder_sdphy_sdphycmdr_state $1\builder_sdphy_sdphycmdr_state[2:0] end - attribute \src "ls180.v:1757.11-1757.52" - process $proc$ls180.v:1757$3517 + attribute \src "ls180.v:1756.11-1756.52" + process $proc$ls180.v:1756$3514 assign { } { } assign $1\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 sync always sync init update \builder_sdphy_sdphycmdr_next_state $1\builder_sdphy_sdphycmdr_next_state[2:0] end - attribute \src "ls180.v:1758.11-1758.67" - process $proc$ls180.v:1758$3518 + attribute \src "ls180.v:1757.11-1757.67" + process $proc$ls180.v:1757$3515 assign { } { } assign $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 sync always sync init update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] end - attribute \src "ls180.v:1759.5-1759.64" - process $proc$ls180.v:1759$3519 + attribute \src "ls180.v:1758.5-1758.64" + process $proc$ls180.v:1758$3516 assign { } { } assign $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] end - attribute \src "ls180.v:1760.12-1760.71" - process $proc$ls180.v:1760$3520 + attribute \src "ls180.v:1759.12-1759.71" + process $proc$ls180.v:1759$3517 assign { } { } assign $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 0 sync always sync init update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] end - attribute \src "ls180.v:1761.5-1761.66" - process $proc$ls180.v:1761$3521 + attribute \src "ls180.v:1760.5-1760.66" + process $proc$ls180.v:1760$3518 assign { } { } assign $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] end - attribute \src "ls180.v:1762.5-1762.66" - process $proc$ls180.v:1762$3522 + attribute \src "ls180.v:1761.5-1761.66" + process $proc$ls180.v:1761$3519 assign { } { } assign $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] end - attribute \src "ls180.v:1763.5-1763.69" - process $proc$ls180.v:1763$3523 + attribute \src "ls180.v:1762.5-1762.69" + process $proc$ls180.v:1762$3520 assign { } { } assign $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] end - attribute \src "ls180.v:1764.5-1764.41" - process $proc$ls180.v:1764$3524 + attribute \src "ls180.v:1763.5-1763.41" + process $proc$ls180.v:1763$3521 assign { } { } assign $1\builder_sdphy_sdphycrcr_state[0:0] 1'0 sync always sync init update \builder_sdphy_sdphycrcr_state $1\builder_sdphy_sdphycrcr_state[0:0] end - attribute \src "ls180.v:1765.5-1765.46" - process $proc$ls180.v:1765$3525 + attribute \src "ls180.v:1764.5-1764.46" + process $proc$ls180.v:1764$3522 assign { } { } assign $1\builder_sdphy_sdphycrcr_next_state[0:0] 1'0 sync always sync init update \builder_sdphy_sdphycrcr_next_state $1\builder_sdphy_sdphycrcr_next_state[0:0] end - attribute \src "ls180.v:1766.5-1766.66" - process $proc$ls180.v:1766$3526 + attribute \src "ls180.v:1765.5-1765.66" + process $proc$ls180.v:1765$3523 assign { } { } assign $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] end - attribute \src "ls180.v:1767.5-1767.69" - process $proc$ls180.v:1767$3527 + attribute \src "ls180.v:1766.5-1766.69" + process $proc$ls180.v:1766$3524 assign { } { } assign $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] end - attribute \src "ls180.v:1768.11-1768.41" - process $proc$ls180.v:1768$3528 + attribute \src "ls180.v:1767.11-1767.41" + process $proc$ls180.v:1767$3525 assign { } { } assign $1\builder_sdphy_fsm_state[2:0] 3'000 sync always sync init update \builder_sdphy_fsm_state $1\builder_sdphy_fsm_state[2:0] end - attribute \src "ls180.v:1769.11-1769.46" - process $proc$ls180.v:1769$3529 + attribute \src "ls180.v:1768.11-1768.46" + process $proc$ls180.v:1768$3526 assign { } { } assign $1\builder_sdphy_fsm_next_state[2:0] 3'000 sync always sync init update \builder_sdphy_fsm_next_state $1\builder_sdphy_fsm_next_state[2:0] end - attribute \src "ls180.v:1770.11-1770.61" - process $proc$ls180.v:1770$3530 + attribute \src "ls180.v:1769.11-1769.61" + process $proc$ls180.v:1769$3527 assign { } { } assign $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 sync always sync init update \main_sdphy_dataw_count_sdphy_fsm_next_value $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] end - attribute \src "ls180.v:1771.5-1771.58" - process $proc$ls180.v:1771$3531 + attribute \src "ls180.v:1770.5-1770.58" + process $proc$ls180.v:1770$3528 assign { } { } assign $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'0 sync always sync init update \main_sdphy_dataw_count_sdphy_fsm_next_value_ce $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] end - attribute \src "ls180.v:1772.11-1772.48" - process $proc$ls180.v:1772$3532 + attribute \src "ls180.v:1771.11-1771.48" + process $proc$ls180.v:1771$3529 assign { } { } assign $1\builder_sdphy_sdphydatar_state[2:0] 3'000 sync always sync init update \builder_sdphy_sdphydatar_state $1\builder_sdphy_sdphydatar_state[2:0] end - attribute \src "ls180.v:1773.11-1773.53" - process $proc$ls180.v:1773$3533 + attribute \src "ls180.v:1772.11-1772.53" + process $proc$ls180.v:1772$3530 assign { } { } assign $1\builder_sdphy_sdphydatar_next_state[2:0] 3'000 sync always sync init update \builder_sdphy_sdphydatar_next_state $1\builder_sdphy_sdphydatar_next_state[2:0] end - attribute \src "ls180.v:1774.11-1774.70" - process $proc$ls180.v:1774$3534 + attribute \src "ls180.v:1773.11-1773.70" + process $proc$ls180.v:1773$3531 assign { } { } assign $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 sync always sync init update \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] end - attribute \src "ls180.v:1775.5-1775.66" - process $proc$ls180.v:1775$3535 + attribute \src "ls180.v:1774.5-1774.66" + process $proc$ls180.v:1774$3532 assign { } { } assign $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'0 sync always sync init update \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] end - attribute \src "ls180.v:1776.12-1776.73" - process $proc$ls180.v:1776$3536 + attribute \src "ls180.v:1775.12-1775.73" + process $proc$ls180.v:1775$3533 assign { } { } assign $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 0 sync always sync init update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] end - attribute \src "ls180.v:1777.5-1777.68" - process $proc$ls180.v:1777$3537 + attribute \src "ls180.v:1776.5-1776.68" + process $proc$ls180.v:1776$3534 assign { } { } assign $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'0 sync always sync init update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] end - attribute \src "ls180.v:1778.5-1778.69" - process $proc$ls180.v:1778$3538 + attribute \src "ls180.v:1777.5-1777.69" + process $proc$ls180.v:1777$3535 assign { } { } assign $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] end - attribute \src "ls180.v:1779.5-1779.72" - process $proc$ls180.v:1779$3539 + attribute \src "ls180.v:1778.5-1778.72" + process $proc$ls180.v:1778$3536 assign { } { } assign $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] end - attribute \src "ls180.v:1780.5-1780.52" - process $proc$ls180.v:1780$3540 + attribute \src "ls180.v:1779.5-1779.52" + process $proc$ls180.v:1779$3537 assign { } { } assign $1\builder_sdcore_crcupstreaminserter_state[0:0] 1'0 sync always sync init update \builder_sdcore_crcupstreaminserter_state $1\builder_sdcore_crcupstreaminserter_state[0:0] end - attribute \src "ls180.v:1781.5-1781.57" - process $proc$ls180.v:1781$3541 + attribute \src "ls180.v:1780.5-1780.57" + process $proc$ls180.v:1780$3538 assign { } { } assign $1\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'0 sync always sync init update \builder_sdcore_crcupstreaminserter_next_state $1\builder_sdcore_crcupstreaminserter_next_state[0:0] end - attribute \src "ls180.v:1782.12-1782.93" - process $proc$ls180.v:1782$3542 + attribute \src "ls180.v:1781.12-1781.93" + process $proc$ls180.v:1781$3539 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] end - attribute \src "ls180.v:1783.5-1783.88" - process $proc$ls180.v:1783$3543 + attribute \src "ls180.v:1782.5-1782.88" + process $proc$ls180.v:1782$3540 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'0 sync always sync init update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] end - attribute \src "ls180.v:1784.12-1784.93" - process $proc$ls180.v:1784$3544 + attribute \src "ls180.v:1783.12-1783.93" + process $proc$ls180.v:1783$3541 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] end - attribute \src "ls180.v:1785.5-1785.88" - process $proc$ls180.v:1785$3545 + attribute \src "ls180.v:1784.5-1784.88" + process $proc$ls180.v:1784$3542 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'0 sync always sync init update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] end - attribute \src "ls180.v:1786.12-1786.93" - process $proc$ls180.v:1786$3546 + attribute \src "ls180.v:1785.12-1785.93" + process $proc$ls180.v:1785$3543 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] end - attribute \src "ls180.v:1787.5-1787.88" - process $proc$ls180.v:1787$3547 + attribute \src "ls180.v:1786.5-1786.88" + process $proc$ls180.v:1786$3544 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'0 sync always sync init update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] end - attribute \src "ls180.v:1788.12-1788.93" - process $proc$ls180.v:1788$3548 + attribute \src "ls180.v:1787.12-1787.93" + process $proc$ls180.v:1787$3545 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] end - attribute \src "ls180.v:1789.5-1789.88" - process $proc$ls180.v:1789$3549 + attribute \src "ls180.v:1788.5-1788.88" + process $proc$ls180.v:1788$3546 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0 sync always sync init update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] end - attribute \src "ls180.v:1790.11-1790.87" - process $proc$ls180.v:1790$3550 + attribute \src "ls180.v:1789.11-1789.87" + process $proc$ls180.v:1789$3547 assign { } { } assign $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 sync always sync init update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] end - attribute \src "ls180.v:1791.5-1791.84" - process $proc$ls180.v:1791$3551 + attribute \src "ls180.v:1790.5-1790.84" + process $proc$ls180.v:1790$3548 assign { } { } assign $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0 sync always sync init update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] end - attribute \src "ls180.v:1792.11-1792.42" - process $proc$ls180.v:1792$3552 + attribute \src "ls180.v:1791.11-1791.42" + process $proc$ls180.v:1791$3549 assign { } { } assign $1\builder_sdcore_fsm_state[2:0] 3'000 sync always sync init update \builder_sdcore_fsm_state $1\builder_sdcore_fsm_state[2:0] end - attribute \src "ls180.v:1793.11-1793.47" - process $proc$ls180.v:1793$3553 + attribute \src "ls180.v:1792.11-1792.47" + process $proc$ls180.v:1792$3550 assign { } { } assign $1\builder_sdcore_fsm_next_state[2:0] 3'000 sync always sync init update \builder_sdcore_fsm_next_state $1\builder_sdcore_fsm_next_state[2:0] end - attribute \src "ls180.v:1794.5-1794.55" - process $proc$ls180.v:1794$3554 + attribute \src "ls180.v:1793.5-1793.55" + process $proc$ls180.v:1793$3551 assign { } { } assign $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 sync always sync init update \main_sdcore_cmd_done_sdcore_fsm_next_value0 $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] end - attribute \src "ls180.v:1795.5-1795.58" - process $proc$ls180.v:1795$3555 + attribute \src "ls180.v:1794.5-1794.58" + process $proc$ls180.v:1794$3552 assign { } { } assign $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'0 sync always sync init update \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] end - attribute \src "ls180.v:1796.5-1796.56" - process $proc$ls180.v:1796$3556 + attribute \src "ls180.v:1795.5-1795.56" + process $proc$ls180.v:1795$3553 assign { } { } assign $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0 sync always sync init update \main_sdcore_data_done_sdcore_fsm_next_value1 $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] end - attribute \src "ls180.v:1797.5-1797.59" - process $proc$ls180.v:1797$3557 + attribute \src "ls180.v:1796.5-1796.59" + process $proc$ls180.v:1796$3554 assign { } { } assign $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'0 sync always sync init update \main_sdcore_data_done_sdcore_fsm_next_value_ce1 $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] end - attribute \src "ls180.v:1798.11-1798.62" - process $proc$ls180.v:1798$3558 + attribute \src "ls180.v:1797.11-1797.62" + process $proc$ls180.v:1797$3555 assign { } { } assign $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000 sync always sync init update \main_sdcore_cmd_count_sdcore_fsm_next_value2 $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] end - attribute \src "ls180.v:1799.5-1799.59" - process $proc$ls180.v:1799$3559 + attribute \src "ls180.v:1798.5-1798.59" + process $proc$ls180.v:1798$3556 assign { } { } assign $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'0 sync always sync init update \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] end - attribute \src "ls180.v:1800.12-1800.65" - process $proc$ls180.v:1800$3560 + attribute \src "ls180.v:1799.12-1799.65" + process $proc$ls180.v:1799$3557 assign { } { } assign $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 sync always sync init update \main_sdcore_data_count_sdcore_fsm_next_value3 $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] end - attribute \src "ls180.v:1801.5-1801.60" - process $proc$ls180.v:1801$3561 + attribute \src "ls180.v:1800.5-1800.60" + process $proc$ls180.v:1800$3558 assign { } { } assign $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'0 sync always sync init update \main_sdcore_data_count_sdcore_fsm_next_value_ce3 $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] end - attribute \src "ls180.v:1802.5-1802.56" - process $proc$ls180.v:1802$3562 + attribute \src "ls180.v:1801.5-1801.56" + process $proc$ls180.v:1801$3559 assign { } { } assign $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0 sync always sync init update \main_sdcore_cmd_error_sdcore_fsm_next_value4 $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] end - attribute \src "ls180.v:1803.5-1803.59" - process $proc$ls180.v:1803$3563 + attribute \src "ls180.v:1802.5-1802.59" + process $proc$ls180.v:1802$3560 assign { } { } assign $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'0 sync always sync init update \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] end - attribute \src "ls180.v:1804.5-1804.58" - process $proc$ls180.v:1804$3564 + attribute \src "ls180.v:1803.5-1803.58" + process $proc$ls180.v:1803$3561 assign { } { } assign $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0 sync always sync init update \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] end - attribute \src "ls180.v:1805.5-1805.61" - process $proc$ls180.v:1805$3565 + attribute \src "ls180.v:1804.5-1804.61" + process $proc$ls180.v:1804$3562 assign { } { } assign $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'0 sync always sync init update \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] end - attribute \src "ls180.v:1806.5-1806.57" - process $proc$ls180.v:1806$3566 + attribute \src "ls180.v:1805.5-1805.57" + process $proc$ls180.v:1805$3563 assign { } { } assign $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0 sync always sync init update \main_sdcore_data_error_sdcore_fsm_next_value6 $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] end - attribute \src "ls180.v:1807.5-1807.60" - process $proc$ls180.v:1807$3567 + attribute \src "ls180.v:1806.5-1806.60" + process $proc$ls180.v:1806$3564 assign { } { } assign $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'0 sync always sync init update \main_sdcore_data_error_sdcore_fsm_next_value_ce6 $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] end - attribute \src "ls180.v:1808.5-1808.59" - process $proc$ls180.v:1808$3568 + attribute \src "ls180.v:1807.5-1807.59" + process $proc$ls180.v:1807$3565 assign { } { } assign $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0 sync always sync init update \main_sdcore_data_timeout_sdcore_fsm_next_value7 $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] end - attribute \src "ls180.v:1809.5-1809.62" - process $proc$ls180.v:1809$3569 + attribute \src "ls180.v:1808.5-1808.62" + process $proc$ls180.v:1808$3566 assign { } { } assign $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'0 sync always sync init update \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] end - attribute \src "ls180.v:181.5-181.40" - process $proc$ls180.v:181$2813 + attribute \src "ls180.v:1809.13-1809.76" + process $proc$ls180.v:1809$3567 assign { } { } - assign $1\main_libresocsim_ram_bus_ack[0:0] 1'0 + assign $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \main_libresocsim_ram_bus_ack $1\main_libresocsim_ram_bus_ack[0:0] + update \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] end - attribute \src "ls180.v:1810.13-1810.76" - process $proc$ls180.v:1810$3570 + attribute \src "ls180.v:181.5-181.40" + process $proc$ls180.v:181$2811 assign { } { } - assign $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $1\main_libresocsim_ram_bus_ack[0:0] 1'0 sync always sync init - update \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] + update \main_libresocsim_ram_bus_ack $1\main_libresocsim_ram_bus_ack[0:0] end - attribute \src "ls180.v:1811.5-1811.69" - process $proc$ls180.v:1811$3571 + attribute \src "ls180.v:1810.5-1810.69" + process $proc$ls180.v:1810$3568 assign { } { } assign $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'0 sync always sync init update \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] end - attribute \src "ls180.v:1812.11-1812.46" - process $proc$ls180.v:1812$3572 + attribute \src "ls180.v:1811.11-1811.46" + process $proc$ls180.v:1811$3569 assign { } { } assign $1\builder_sdblock2memdma_state[1:0] 2'00 sync always sync init update \builder_sdblock2memdma_state $1\builder_sdblock2memdma_state[1:0] end - attribute \src "ls180.v:1813.11-1813.51" - process $proc$ls180.v:1813$3573 + attribute \src "ls180.v:1812.11-1812.51" + process $proc$ls180.v:1812$3570 assign { } { } assign $1\builder_sdblock2memdma_next_state[1:0] 2'00 sync always sync init update \builder_sdblock2memdma_next_state $1\builder_sdblock2memdma_next_state[1:0] end - attribute \src "ls180.v:1814.12-1814.87" - process $proc$ls180.v:1814$3574 + attribute \src "ls180.v:1813.12-1813.87" + process $proc$ls180.v:1813$3571 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] end - attribute \src "ls180.v:1815.5-1815.82" - process $proc$ls180.v:1815$3575 + attribute \src "ls180.v:1814.5-1814.82" + process $proc$ls180.v:1814$3572 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] end - attribute \src "ls180.v:1816.5-1816.44" - process $proc$ls180.v:1816$3576 + attribute \src "ls180.v:1815.5-1815.44" + process $proc$ls180.v:1815$3573 assign { } { } assign $1\builder_sdmem2blockdma_fsm_state[0:0] 1'0 sync always sync init update \builder_sdmem2blockdma_fsm_state $1\builder_sdmem2blockdma_fsm_state[0:0] end - attribute \src "ls180.v:1817.5-1817.49" - process $proc$ls180.v:1817$3577 + attribute \src "ls180.v:1816.5-1816.49" + process $proc$ls180.v:1816$3574 assign { } { } assign $1\builder_sdmem2blockdma_fsm_next_state[0:0] 1'0 sync always sync init update \builder_sdmem2blockdma_fsm_next_state $1\builder_sdmem2blockdma_fsm_next_state[0:0] end - attribute \src "ls180.v:1818.12-1818.75" - process $proc$ls180.v:1818$3578 + attribute \src "ls180.v:1817.12-1817.75" + process $proc$ls180.v:1817$3575 assign { } { } assign $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] 0 sync always sync init update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] end - attribute \src "ls180.v:1819.5-1819.70" - process $proc$ls180.v:1819$3579 + attribute \src "ls180.v:1818.5-1818.70" + process $proc$ls180.v:1818$3576 assign { } { } assign $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] end - attribute \src "ls180.v:1820.11-1820.60" - process $proc$ls180.v:1820$3580 + attribute \src "ls180.v:1819.11-1819.60" + process $proc$ls180.v:1819$3577 assign { } { } assign $1\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00 sync always sync init update \builder_sdmem2blockdma_resetinserter_state $1\builder_sdmem2blockdma_resetinserter_state[1:0] end - attribute \src "ls180.v:1821.11-1821.65" - process $proc$ls180.v:1821$3581 + attribute \src "ls180.v:1820.11-1820.65" + process $proc$ls180.v:1820$3578 assign { } { } assign $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'00 sync always sync init update \builder_sdmem2blockdma_resetinserter_next_state $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] end - attribute \src "ls180.v:1822.12-1822.87" - process $proc$ls180.v:1822$3582 + attribute \src "ls180.v:1821.12-1821.87" + process $proc$ls180.v:1821$3579 assign { } { } assign $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 sync always sync init update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] end - attribute \src "ls180.v:1823.5-1823.82" - process $proc$ls180.v:1823$3583 + attribute \src "ls180.v:1822.5-1822.82" + process $proc$ls180.v:1822$3580 assign { } { } assign $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] end - attribute \src "ls180.v:1824.11-1824.42" - process $proc$ls180.v:1824$3584 + attribute \src "ls180.v:1823.11-1823.42" + process $proc$ls180.v:1823$3581 assign { } { } assign $1\builder_spimaster1_state[1:0] 2'00 sync always sync init update \builder_spimaster1_state $1\builder_spimaster1_state[1:0] end - attribute \src "ls180.v:1825.11-1825.47" - process $proc$ls180.v:1825$3585 + attribute \src "ls180.v:1824.11-1824.47" + process $proc$ls180.v:1824$3582 assign { } { } assign $1\builder_spimaster1_next_state[1:0] 2'00 sync always sync init update \builder_spimaster1_next_state $1\builder_spimaster1_next_state[1:0] end - attribute \src "ls180.v:1826.11-1826.57" - process $proc$ls180.v:1826$3586 + attribute \src "ls180.v:1825.11-1825.57" + process $proc$ls180.v:1825$3583 assign { } { } assign $1\libresocsim_count_spimaster1_next_value[2:0] 3'000 sync always sync init update \libresocsim_count_spimaster1_next_value $1\libresocsim_count_spimaster1_next_value[2:0] end - attribute \src "ls180.v:1827.5-1827.54" - process $proc$ls180.v:1827$3587 + attribute \src "ls180.v:1826.5-1826.54" + process $proc$ls180.v:1826$3584 assign { } { } assign $1\libresocsim_count_spimaster1_next_value_ce[0:0] 1'0 sync always sync init update \libresocsim_count_spimaster1_next_value_ce $1\libresocsim_count_spimaster1_next_value_ce[0:0] end - attribute \src "ls180.v:1828.12-1828.43" - process $proc$ls180.v:1828$3588 + attribute \src "ls180.v:1827.12-1827.43" + process $proc$ls180.v:1827$3585 assign { } { } assign $1\builder_libresocsim_adr[13:0] 14'00000000000000 sync always sync init update \builder_libresocsim_adr $1\builder_libresocsim_adr[13:0] end - attribute \src "ls180.v:1829.5-1829.34" - process $proc$ls180.v:1829$3589 + attribute \src "ls180.v:1828.5-1828.34" + process $proc$ls180.v:1828$3586 assign { } { } assign $1\builder_libresocsim_we[0:0] 1'0 sync always sync init update \builder_libresocsim_we $1\builder_libresocsim_we[0:0] end - attribute \src "ls180.v:1830.11-1830.43" - process $proc$ls180.v:1830$3590 + attribute \src "ls180.v:1829.11-1829.43" + process $proc$ls180.v:1829$3587 assign { } { } assign $1\builder_libresocsim_dat_w[7:0] 8'00000000 sync always sync init update \builder_libresocsim_dat_w $1\builder_libresocsim_dat_w[7:0] end - attribute \src "ls180.v:1834.12-1834.54" - process $proc$ls180.v:1834$3591 + attribute \src "ls180.v:1833.12-1833.54" + process $proc$ls180.v:1833$3588 assign { } { } assign $1\builder_libresocsim_wishbone_dat_r[31:0] 0 sync always sync init update \builder_libresocsim_wishbone_dat_r $1\builder_libresocsim_wishbone_dat_r[31:0] end - attribute \src "ls180.v:1838.5-1838.44" - process $proc$ls180.v:1838$3592 + attribute \src "ls180.v:1837.5-1837.44" + process $proc$ls180.v:1837$3589 assign { } { } assign $1\builder_libresocsim_wishbone_ack[0:0] 1'0 sync always sync init update \builder_libresocsim_wishbone_ack $1\builder_libresocsim_wishbone_ack[0:0] end - attribute \src "ls180.v:1842.5-1842.44" - process $proc$ls180.v:1842$3593 + attribute \src "ls180.v:1841.5-1841.44" + process $proc$ls180.v:1841$3590 assign { } { } assign $0\builder_libresocsim_wishbone_err[0:0] 1'0 sync always update \builder_libresocsim_wishbone_err $0\builder_libresocsim_wishbone_err[0:0] sync init end - attribute \src "ls180.v:1845.12-1845.40" - process $proc$ls180.v:1845$3594 + attribute \src "ls180.v:1844.12-1844.40" + process $proc$ls180.v:1844$3591 assign { } { } assign $1\builder_shared_dat_r[31:0] 0 sync always sync init update \builder_shared_dat_r $1\builder_shared_dat_r[31:0] end - attribute \src "ls180.v:1849.5-1849.30" - process $proc$ls180.v:1849$3595 + attribute \src "ls180.v:1848.5-1848.30" + process $proc$ls180.v:1848$3592 assign { } { } assign $1\builder_shared_ack[0:0] 1'0 sync always @@ -114244,55 +114204,55 @@ module \ls180 update \builder_shared_ack $1\builder_shared_ack[0:0] end attribute \src "ls180.v:185.5-185.40" - process $proc$ls180.v:185$2814 + process $proc$ls180.v:185$2812 assign { } { } assign $0\main_libresocsim_ram_bus_err[0:0] 1'0 sync always update \main_libresocsim_ram_bus_err $0\main_libresocsim_ram_bus_err[0:0] sync init end - attribute \src "ls180.v:1855.11-1855.31" - process $proc$ls180.v:1855$3596 + attribute \src "ls180.v:1854.11-1854.31" + process $proc$ls180.v:1854$3593 assign { } { } assign $1\builder_grant[2:0] 3'000 sync always sync init update \builder_grant $1\builder_grant[2:0] end - attribute \src "ls180.v:1856.11-1856.35" - process $proc$ls180.v:1856$3597 + attribute \src "ls180.v:1855.11-1855.35" + process $proc$ls180.v:1855$3594 assign { } { } assign $1\builder_slave_sel[4:0] 5'00000 sync always sync init update \builder_slave_sel $1\builder_slave_sel[4:0] end - attribute \src "ls180.v:1857.11-1857.37" - process $proc$ls180.v:1857$3598 + attribute \src "ls180.v:1856.11-1856.37" + process $proc$ls180.v:1856$3595 assign { } { } assign $1\builder_slave_sel_r[4:0] 5'00000 sync always sync init update \builder_slave_sel_r $1\builder_slave_sel_r[4:0] end - attribute \src "ls180.v:1858.5-1858.25" - process $proc$ls180.v:1858$3599 + attribute \src "ls180.v:1857.5-1857.25" + process $proc$ls180.v:1857$3596 assign { } { } assign $1\builder_error[0:0] 1'0 sync always sync init update \builder_error $1\builder_error[0:0] end - attribute \src "ls180.v:1861.12-1861.39" - process $proc$ls180.v:1861$3600 + attribute \src "ls180.v:1860.12-1860.39" + process $proc$ls180.v:1860$3597 assign { } { } assign $1\builder_count[19:0] 20'11110100001001000000 sync always sync init update \builder_count $1\builder_count[19:0] end - attribute \src "ls180.v:1865.11-1865.51" - process $proc$ls180.v:1865$3601 + attribute \src "ls180.v:1864.11-1864.51" + process $proc$ls180.v:1864$3598 assign { } { } assign $1\builder_interface0_bank_bus_dat_r[7:0] 8'00000000 sync always @@ -114300,7 +114260,7 @@ module \ls180 update \builder_interface0_bank_bus_dat_r $1\builder_interface0_bank_bus_dat_r[7:0] end attribute \src "ls180.v:188.11-188.37" - process $proc$ls180.v:188$2815 + process $proc$ls180.v:188$2813 assign { } { } assign $1\main_libresocsim_we[3:0] 4'0000 sync always @@ -114308,15 +114268,15 @@ module \ls180 update \main_libresocsim_we $1\main_libresocsim_we[3:0] end attribute \src "ls180.v:190.12-190.49" - process $proc$ls180.v:190$2816 + process $proc$ls180.v:190$2814 assign { } { } assign $1\main_libresocsim_load_storage[31:0] 0 sync always sync init update \main_libresocsim_load_storage $1\main_libresocsim_load_storage[31:0] end - attribute \src "ls180.v:1906.11-1906.51" - process $proc$ls180.v:1906$3602 + attribute \src "ls180.v:1905.11-1905.51" + process $proc$ls180.v:1905$3599 assign { } { } assign $1\builder_interface1_bank_bus_dat_r[7:0] 8'00000000 sync always @@ -114324,7 +114284,7 @@ module \ls180 update \builder_interface1_bank_bus_dat_r $1\builder_interface1_bank_bus_dat_r[7:0] end attribute \src "ls180.v:191.5-191.36" - process $proc$ls180.v:191$2817 + process $proc$ls180.v:191$2815 assign { } { } assign $1\main_libresocsim_load_re[0:0] 1'0 sync always @@ -114332,7 +114292,7 @@ module \ls180 update \main_libresocsim_load_re $1\main_libresocsim_load_re[0:0] end attribute \src "ls180.v:192.12-192.51" - process $proc$ls180.v:192$2818 + process $proc$ls180.v:192$2816 assign { } { } assign $1\main_libresocsim_reload_storage[31:0] 0 sync always @@ -114340,15 +114300,15 @@ module \ls180 update \main_libresocsim_reload_storage $1\main_libresocsim_reload_storage[31:0] end attribute \src "ls180.v:193.5-193.38" - process $proc$ls180.v:193$2819 + process $proc$ls180.v:193$2817 assign { } { } assign $1\main_libresocsim_reload_re[0:0] 1'0 sync always sync init update \main_libresocsim_reload_re $1\main_libresocsim_reload_re[0:0] end - attribute \src "ls180.v:1935.11-1935.51" - process $proc$ls180.v:1935$3603 + attribute \src "ls180.v:1934.11-1934.51" + process $proc$ls180.v:1934$3600 assign { } { } assign $1\builder_interface2_bank_bus_dat_r[7:0] 8'00000000 sync always @@ -114356,7 +114316,7 @@ module \ls180 update \builder_interface2_bank_bus_dat_r $1\builder_interface2_bank_bus_dat_r[7:0] end attribute \src "ls180.v:194.5-194.39" - process $proc$ls180.v:194$2820 + process $proc$ls180.v:194$2818 assign { } { } assign $1\main_libresocsim_en_storage[0:0] 1'0 sync always @@ -114364,7 +114324,7 @@ module \ls180 update \main_libresocsim_en_storage $1\main_libresocsim_en_storage[0:0] end attribute \src "ls180.v:195.5-195.34" - process $proc$ls180.v:195$2821 + process $proc$ls180.v:195$2819 assign { } { } assign $1\main_libresocsim_en_re[0:0] 1'0 sync always @@ -114372,7 +114332,7 @@ module \ls180 update \main_libresocsim_en_re $1\main_libresocsim_en_re[0:0] end attribute \src "ls180.v:196.5-196.49" - process $proc$ls180.v:196$2822 + process $proc$ls180.v:196$2820 assign { } { } assign $1\main_libresocsim_update_value_storage[0:0] 1'0 sync always @@ -114380,15 +114340,15 @@ module \ls180 update \main_libresocsim_update_value_storage $1\main_libresocsim_update_value_storage[0:0] end attribute \src "ls180.v:197.5-197.44" - process $proc$ls180.v:197$2823 + process $proc$ls180.v:197$2821 assign { } { } assign $1\main_libresocsim_update_value_re[0:0] 1'0 sync always sync init update \main_libresocsim_update_value_re $1\main_libresocsim_update_value_re[0:0] end - attribute \src "ls180.v:1976.11-1976.51" - process $proc$ls180.v:1976$3604 + attribute \src "ls180.v:1975.11-1975.51" + process $proc$ls180.v:1975$3601 assign { } { } assign $1\builder_interface3_bank_bus_dat_r[7:0] 8'00000000 sync always @@ -114396,15 +114356,15 @@ module \ls180 update \builder_interface3_bank_bus_dat_r $1\builder_interface3_bank_bus_dat_r[7:0] end attribute \src "ls180.v:198.12-198.49" - process $proc$ls180.v:198$2824 + process $proc$ls180.v:198$2822 assign { } { } assign $1\main_libresocsim_value_status[31:0] 0 sync always sync init update \main_libresocsim_value_status $1\main_libresocsim_value_status[31:0] end - attribute \src "ls180.v:2017.11-2017.51" - process $proc$ls180.v:2017$3605 + attribute \src "ls180.v:2016.11-2016.51" + process $proc$ls180.v:2016$3602 assign { } { } assign $1\builder_interface4_bank_bus_dat_r[7:0] 8'00000000 sync always @@ -114412,7 +114372,7 @@ module \ls180 update \builder_interface4_bank_bus_dat_r $1\builder_interface4_bank_bus_dat_r[7:0] end attribute \src "ls180.v:202.5-202.41" - process $proc$ls180.v:202$2825 + process $proc$ls180.v:202$2823 assign { } { } assign $1\main_libresocsim_zero_pending[0:0] 1'0 sync always @@ -114420,7 +114380,7 @@ module \ls180 update \main_libresocsim_zero_pending $1\main_libresocsim_zero_pending[0:0] end attribute \src "ls180.v:204.5-204.39" - process $proc$ls180.v:204$2826 + process $proc$ls180.v:204$2824 assign { } { } assign $1\main_libresocsim_zero_clear[0:0] 1'0 sync always @@ -114428,15 +114388,15 @@ module \ls180 update \main_libresocsim_zero_clear $1\main_libresocsim_zero_clear[0:0] end attribute \src "ls180.v:205.5-205.45" - process $proc$ls180.v:205$2827 + process $proc$ls180.v:205$2825 assign { } { } assign $1\main_libresocsim_zero_old_trigger[0:0] 1'0 sync always sync init update \main_libresocsim_zero_old_trigger $1\main_libresocsim_zero_old_trigger[0:0] end - attribute \src "ls180.v:2082.11-2082.51" - process $proc$ls180.v:2082$3606 + attribute \src "ls180.v:2081.11-2081.51" + process $proc$ls180.v:2081$3603 assign { } { } assign $1\builder_interface5_bank_bus_dat_r[7:0] 8'00000000 sync always @@ -114444,7 +114404,7 @@ module \ls180 update \builder_interface5_bank_bus_dat_r $1\builder_interface5_bank_bus_dat_r[7:0] end attribute \src "ls180.v:214.5-214.49" - process $proc$ls180.v:214$2828 + process $proc$ls180.v:214$2826 assign { } { } assign $1\main_libresocsim_eventmanager_storage[0:0] 1'0 sync always @@ -114452,7 +114412,7 @@ module \ls180 update \main_libresocsim_eventmanager_storage $1\main_libresocsim_eventmanager_storage[0:0] end attribute \src "ls180.v:215.5-215.44" - process $proc$ls180.v:215$2829 + process $proc$ls180.v:215$2827 assign { } { } assign $1\main_libresocsim_eventmanager_re[0:0] 1'0 sync always @@ -114460,7 +114420,7 @@ module \ls180 update \main_libresocsim_eventmanager_re $1\main_libresocsim_eventmanager_re[0:0] end attribute \src "ls180.v:216.12-216.42" - process $proc$ls180.v:216$2830 + process $proc$ls180.v:216$2828 assign { } { } assign $1\main_libresocsim_value[31:0] 0 sync always @@ -114468,31 +114428,31 @@ module \ls180 update \main_libresocsim_value $1\main_libresocsim_value[31:0] end attribute \src "ls180.v:220.5-220.24" - process $proc$ls180.v:220$2831 + process $proc$ls180.v:220$2829 assign { } { } assign $1\main_int_rst[0:0] 1'1 sync always sync init update \main_int_rst $1\main_int_rst[0:0] end - attribute \src "ls180.v:2215.11-2215.51" - process $proc$ls180.v:2215$3607 + attribute \src "ls180.v:2214.11-2214.51" + process $proc$ls180.v:2214$3604 assign { } { } assign $1\builder_interface6_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \builder_interface6_bank_bus_dat_r $1\builder_interface6_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:2296.11-2296.51" - process $proc$ls180.v:2296$3608 + attribute \src "ls180.v:2295.11-2295.51" + process $proc$ls180.v:2295$3605 assign { } { } assign $1\builder_interface7_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \builder_interface7_bank_bus_dat_r $1\builder_interface7_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:2313.11-2313.51" - process $proc$ls180.v:2313$3609 + attribute \src "ls180.v:2312.11-2312.51" + process $proc$ls180.v:2312$3606 assign { } { } assign $1\builder_interface8_bank_bus_dat_r[7:0] 8'00000000 sync always @@ -114500,15 +114460,15 @@ module \ls180 update \builder_interface8_bank_bus_dat_r $1\builder_interface8_bank_bus_dat_r[7:0] end attribute \src "ls180.v:235.12-235.38" - process $proc$ls180.v:235$2832 + process $proc$ls180.v:235$2830 assign { } { } assign $1\main_dfi_p0_rddata[15:0] 16'0000000000000000 sync always sync init update \main_dfi_p0_rddata $1\main_dfi_p0_rddata[15:0] end - attribute \src "ls180.v:2354.11-2354.51" - process $proc$ls180.v:2354$3610 + attribute \src "ls180.v:2353.11-2353.51" + process $proc$ls180.v:2353$3607 assign { } { } assign $1\builder_interface9_bank_bus_dat_r[7:0] 8'00000000 sync always @@ -114516,855 +114476,863 @@ module \ls180 update \builder_interface9_bank_bus_dat_r $1\builder_interface9_bank_bus_dat_r[7:0] end attribute \src "ls180.v:236.5-236.36" - process $proc$ls180.v:236$2833 + process $proc$ls180.v:236$2831 assign { } { } assign $1\main_dfi_p0_rddata_valid[0:0] 1'0 sync always sync init update \main_dfi_p0_rddata_valid $1\main_dfi_p0_rddata_valid[0:0] end - attribute \src "ls180.v:237.11-237.25" - process $proc$ls180.v:237$2834 - assign { } { } - assign $1\main_dm[1:0] 2'00 - sync always - sync init - update \main_dm $1\main_dm[1:0] - end - attribute \src "ls180.v:238.11-238.32" - process $proc$ls180.v:238$2835 + attribute \src "ls180.v:237.11-237.32" + process $proc$ls180.v:237$2832 assign { } { } assign $1\main_rddata_en[2:0] 3'000 sync always sync init update \main_rddata_en $1\main_rddata_en[2:0] end - attribute \src "ls180.v:2387.11-2387.52" - process $proc$ls180.v:2387$3611 + attribute \src "ls180.v:2386.11-2386.52" + process $proc$ls180.v:2386$3608 assign { } { } assign $1\builder_interface10_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \builder_interface10_bank_bus_dat_r $1\builder_interface10_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:241.5-241.36" - process $proc$ls180.v:241$2836 + attribute \src "ls180.v:240.5-240.36" + process $proc$ls180.v:240$2833 assign { } { } assign $1\main_sdram_inti_p0_cas_n[0:0] 1'1 sync always sync init update \main_sdram_inti_p0_cas_n $1\main_sdram_inti_p0_cas_n[0:0] end - attribute \src "ls180.v:242.5-242.35" - process $proc$ls180.v:242$2837 + attribute \src "ls180.v:241.5-241.35" + process $proc$ls180.v:241$2834 assign { } { } assign $1\main_sdram_inti_p0_cs_n[0:0] 1'1 sync always sync init update \main_sdram_inti_p0_cs_n $1\main_sdram_inti_p0_cs_n[0:0] end - attribute \src "ls180.v:2428.11-2428.52" - process $proc$ls180.v:2428$3612 + attribute \src "ls180.v:242.5-242.36" + process $proc$ls180.v:242$2835 assign { } { } - assign $1\builder_interface11_bank_bus_dat_r[7:0] 8'00000000 + assign $1\main_sdram_inti_p0_ras_n[0:0] 1'1 sync always sync init - update \builder_interface11_bank_bus_dat_r $1\builder_interface11_bank_bus_dat_r[7:0] + update \main_sdram_inti_p0_ras_n $1\main_sdram_inti_p0_ras_n[0:0] end - attribute \src "ls180.v:243.5-243.36" - process $proc$ls180.v:243$2838 + attribute \src "ls180.v:2427.11-2427.52" + process $proc$ls180.v:2427$3609 assign { } { } - assign $1\main_sdram_inti_p0_ras_n[0:0] 1'1 + assign $1\builder_interface11_bank_bus_dat_r[7:0] 8'00000000 sync always sync init - update \main_sdram_inti_p0_ras_n $1\main_sdram_inti_p0_ras_n[0:0] + update \builder_interface11_bank_bus_dat_r $1\builder_interface11_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:244.5-244.35" - process $proc$ls180.v:244$2839 + attribute \src "ls180.v:243.5-243.35" + process $proc$ls180.v:243$2836 assign { } { } assign $1\main_sdram_inti_p0_we_n[0:0] 1'1 sync always sync init update \main_sdram_inti_p0_we_n $1\main_sdram_inti_p0_we_n[0:0] end - attribute \src "ls180.v:248.5-248.36" - process $proc$ls180.v:248$2840 + attribute \src "ls180.v:247.5-247.36" + process $proc$ls180.v:247$2837 assign { } { } assign $0\main_sdram_inti_p0_act_n[0:0] 1'1 sync always update \main_sdram_inti_p0_act_n $0\main_sdram_inti_p0_act_n[0:0] sync init end - attribute \src "ls180.v:2493.11-2493.52" - process $proc$ls180.v:2493$3613 + attribute \src "ls180.v:2492.11-2492.52" + process $proc$ls180.v:2492$3610 assign { } { } assign $1\builder_interface12_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \builder_interface12_bank_bus_dat_r $1\builder_interface12_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:2518.11-2518.52" - process $proc$ls180.v:2518$3614 + attribute \src "ls180.v:2517.11-2517.52" + process $proc$ls180.v:2517$3611 assign { } { } assign $1\builder_interface13_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \builder_interface13_bank_bus_dat_r $1\builder_interface13_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:253.12-253.45" - process $proc$ls180.v:253$2841 + attribute \src "ls180.v:252.12-252.45" + process $proc$ls180.v:252$2838 assign { } { } assign $1\main_sdram_inti_p0_rddata[15:0] 16'0000000000000000 sync always sync init update \main_sdram_inti_p0_rddata $1\main_sdram_inti_p0_rddata[15:0] end - attribute \src "ls180.v:254.5-254.43" - process $proc$ls180.v:254$2842 + attribute \src "ls180.v:253.5-253.43" + process $proc$ls180.v:253$2839 assign { } { } assign $1\main_sdram_inti_p0_rddata_valid[0:0] 1'0 sync always sync init update \main_sdram_inti_p0_rddata_valid $1\main_sdram_inti_p0_rddata_valid[0:0] end - attribute \src "ls180.v:2540.11-2540.31" - process $proc$ls180.v:2540$3615 + attribute \src "ls180.v:2539.11-2539.31" + process $proc$ls180.v:2539$3612 assign { } { } assign $1\builder_state[1:0] 2'00 sync always sync init update \builder_state $1\builder_state[1:0] end - attribute \src "ls180.v:2541.11-2541.36" - process $proc$ls180.v:2541$3616 + attribute \src "ls180.v:2540.11-2540.36" + process $proc$ls180.v:2540$3613 assign { } { } assign $1\builder_next_state[1:0] 2'00 sync always sync init update \builder_next_state $1\builder_next_state[1:0] end - attribute \src "ls180.v:2542.11-2542.55" - process $proc$ls180.v:2542$3617 + attribute \src "ls180.v:2541.11-2541.55" + process $proc$ls180.v:2541$3614 assign { } { } assign $1\builder_libresocsim_dat_w_next_value0[7:0] 8'00000000 sync always sync init update \builder_libresocsim_dat_w_next_value0 $1\builder_libresocsim_dat_w_next_value0[7:0] end - attribute \src "ls180.v:2543.5-2543.52" - process $proc$ls180.v:2543$3618 + attribute \src "ls180.v:2542.5-2542.52" + process $proc$ls180.v:2542$3615 assign { } { } assign $1\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'0 sync always sync init update \builder_libresocsim_dat_w_next_value_ce0 $1\builder_libresocsim_dat_w_next_value_ce0[0:0] end - attribute \src "ls180.v:2544.12-2544.55" - process $proc$ls180.v:2544$3619 + attribute \src "ls180.v:2543.12-2543.55" + process $proc$ls180.v:2543$3616 assign { } { } assign $1\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000 sync always sync init update \builder_libresocsim_adr_next_value1 $1\builder_libresocsim_adr_next_value1[13:0] end - attribute \src "ls180.v:2545.5-2545.50" - process $proc$ls180.v:2545$3620 + attribute \src "ls180.v:2544.5-2544.50" + process $proc$ls180.v:2544$3617 assign { } { } assign $1\builder_libresocsim_adr_next_value_ce1[0:0] 1'0 sync always sync init update \builder_libresocsim_adr_next_value_ce1 $1\builder_libresocsim_adr_next_value_ce1[0:0] end - attribute \src "ls180.v:2546.5-2546.46" - process $proc$ls180.v:2546$3621 + attribute \src "ls180.v:2545.5-2545.46" + process $proc$ls180.v:2545$3618 assign { } { } assign $1\builder_libresocsim_we_next_value2[0:0] 1'0 sync always sync init update \builder_libresocsim_we_next_value2 $1\builder_libresocsim_we_next_value2[0:0] end - attribute \src "ls180.v:2547.5-2547.49" - process $proc$ls180.v:2547$3622 + attribute \src "ls180.v:2546.5-2546.49" + process $proc$ls180.v:2546$3619 assign { } { } assign $1\builder_libresocsim_we_next_value_ce2[0:0] 1'0 sync always sync init update \builder_libresocsim_we_next_value_ce2 $1\builder_libresocsim_we_next_value_ce2[0:0] end - attribute \src "ls180.v:2548.5-2548.41" - process $proc$ls180.v:2548$3623 + attribute \src "ls180.v:2547.5-2547.41" + process $proc$ls180.v:2547$3620 assign { } { } assign $1\builder_comb_rhs_array_muxed0[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed0 $1\builder_comb_rhs_array_muxed0[0:0] end - attribute \src "ls180.v:2549.12-2549.49" - process $proc$ls180.v:2549$3624 + attribute \src "ls180.v:2548.12-2548.49" + process $proc$ls180.v:2548$3621 assign { } { } assign $1\builder_comb_rhs_array_muxed1[12:0] 13'0000000000000 sync always sync init update \builder_comb_rhs_array_muxed1 $1\builder_comb_rhs_array_muxed1[12:0] end - attribute \src "ls180.v:2550.11-2550.47" - process $proc$ls180.v:2550$3625 + attribute \src "ls180.v:2549.11-2549.47" + process $proc$ls180.v:2549$3622 assign { } { } assign $1\builder_comb_rhs_array_muxed2[1:0] 2'00 sync always sync init update \builder_comb_rhs_array_muxed2 $1\builder_comb_rhs_array_muxed2[1:0] end - attribute \src "ls180.v:2551.5-2551.41" - process $proc$ls180.v:2551$3626 + attribute \src "ls180.v:2550.5-2550.41" + process $proc$ls180.v:2550$3623 assign { } { } assign $1\builder_comb_rhs_array_muxed3[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed3 $1\builder_comb_rhs_array_muxed3[0:0] end - attribute \src "ls180.v:2552.5-2552.41" - process $proc$ls180.v:2552$3627 + attribute \src "ls180.v:2551.5-2551.41" + process $proc$ls180.v:2551$3624 assign { } { } assign $1\builder_comb_rhs_array_muxed4[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed4 $1\builder_comb_rhs_array_muxed4[0:0] end - attribute \src "ls180.v:2553.5-2553.41" - process $proc$ls180.v:2553$3628 + attribute \src "ls180.v:2552.5-2552.41" + process $proc$ls180.v:2552$3625 assign { } { } assign $1\builder_comb_rhs_array_muxed5[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed5 $1\builder_comb_rhs_array_muxed5[0:0] end - attribute \src "ls180.v:2554.5-2554.39" - process $proc$ls180.v:2554$3629 + attribute \src "ls180.v:2553.5-2553.39" + process $proc$ls180.v:2553$3626 assign { } { } assign $1\builder_comb_t_array_muxed0[0:0] 1'0 sync always sync init update \builder_comb_t_array_muxed0 $1\builder_comb_t_array_muxed0[0:0] end - attribute \src "ls180.v:2555.5-2555.39" - process $proc$ls180.v:2555$3630 + attribute \src "ls180.v:2554.5-2554.39" + process $proc$ls180.v:2554$3627 assign { } { } assign $1\builder_comb_t_array_muxed1[0:0] 1'0 sync always sync init update \builder_comb_t_array_muxed1 $1\builder_comb_t_array_muxed1[0:0] end - attribute \src "ls180.v:2556.5-2556.39" - process $proc$ls180.v:2556$3631 + attribute \src "ls180.v:2555.5-2555.39" + process $proc$ls180.v:2555$3628 assign { } { } assign $1\builder_comb_t_array_muxed2[0:0] 1'0 sync always sync init update \builder_comb_t_array_muxed2 $1\builder_comb_t_array_muxed2[0:0] end - attribute \src "ls180.v:2557.5-2557.41" - process $proc$ls180.v:2557$3632 + attribute \src "ls180.v:2556.5-2556.41" + process $proc$ls180.v:2556$3629 assign { } { } assign $1\builder_comb_rhs_array_muxed6[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed6 $1\builder_comb_rhs_array_muxed6[0:0] end - attribute \src "ls180.v:2558.12-2558.49" - process $proc$ls180.v:2558$3633 + attribute \src "ls180.v:2557.12-2557.49" + process $proc$ls180.v:2557$3630 assign { } { } assign $1\builder_comb_rhs_array_muxed7[12:0] 13'0000000000000 sync always sync init update \builder_comb_rhs_array_muxed7 $1\builder_comb_rhs_array_muxed7[12:0] end - attribute \src "ls180.v:2559.11-2559.47" - process $proc$ls180.v:2559$3634 + attribute \src "ls180.v:2558.11-2558.47" + process $proc$ls180.v:2558$3631 assign { } { } assign $1\builder_comb_rhs_array_muxed8[1:0] 2'00 sync always sync init update \builder_comb_rhs_array_muxed8 $1\builder_comb_rhs_array_muxed8[1:0] end - attribute \src "ls180.v:2560.5-2560.41" - process $proc$ls180.v:2560$3635 + attribute \src "ls180.v:2559.5-2559.41" + process $proc$ls180.v:2559$3632 assign { } { } assign $1\builder_comb_rhs_array_muxed9[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed9 $1\builder_comb_rhs_array_muxed9[0:0] end - attribute \src "ls180.v:2561.5-2561.42" - process $proc$ls180.v:2561$3636 + attribute \src "ls180.v:2560.5-2560.42" + process $proc$ls180.v:2560$3633 assign { } { } assign $1\builder_comb_rhs_array_muxed10[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed10 $1\builder_comb_rhs_array_muxed10[0:0] end - attribute \src "ls180.v:2562.5-2562.42" - process $proc$ls180.v:2562$3637 + attribute \src "ls180.v:2561.5-2561.42" + process $proc$ls180.v:2561$3634 assign { } { } assign $1\builder_comb_rhs_array_muxed11[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed11 $1\builder_comb_rhs_array_muxed11[0:0] end - attribute \src "ls180.v:2563.5-2563.39" - process $proc$ls180.v:2563$3638 + attribute \src "ls180.v:2562.5-2562.39" + process $proc$ls180.v:2562$3635 assign { } { } assign $1\builder_comb_t_array_muxed3[0:0] 1'0 sync always sync init update \builder_comb_t_array_muxed3 $1\builder_comb_t_array_muxed3[0:0] end - attribute \src "ls180.v:2564.5-2564.39" - process $proc$ls180.v:2564$3639 + attribute \src "ls180.v:2563.5-2563.39" + process $proc$ls180.v:2563$3636 assign { } { } assign $1\builder_comb_t_array_muxed4[0:0] 1'0 sync always sync init update \builder_comb_t_array_muxed4 $1\builder_comb_t_array_muxed4[0:0] end - attribute \src "ls180.v:2565.5-2565.39" - process $proc$ls180.v:2565$3640 + attribute \src "ls180.v:2564.5-2564.39" + process $proc$ls180.v:2564$3637 assign { } { } assign $1\builder_comb_t_array_muxed5[0:0] 1'0 sync always sync init update \builder_comb_t_array_muxed5 $1\builder_comb_t_array_muxed5[0:0] end - attribute \src "ls180.v:2566.12-2566.50" - process $proc$ls180.v:2566$3641 + attribute \src "ls180.v:2565.12-2565.50" + process $proc$ls180.v:2565$3638 assign { } { } assign $1\builder_comb_rhs_array_muxed12[21:0] 22'0000000000000000000000 sync always sync init update \builder_comb_rhs_array_muxed12 $1\builder_comb_rhs_array_muxed12[21:0] end - attribute \src "ls180.v:2567.5-2567.42" - process $proc$ls180.v:2567$3642 + attribute \src "ls180.v:2566.5-2566.42" + process $proc$ls180.v:2566$3639 assign { } { } assign $1\builder_comb_rhs_array_muxed13[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed13 $1\builder_comb_rhs_array_muxed13[0:0] end - attribute \src "ls180.v:2568.5-2568.42" - process $proc$ls180.v:2568$3643 + attribute \src "ls180.v:2567.5-2567.42" + process $proc$ls180.v:2567$3640 assign { } { } assign $1\builder_comb_rhs_array_muxed14[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed14 $1\builder_comb_rhs_array_muxed14[0:0] end - attribute \src "ls180.v:2569.12-2569.50" - process $proc$ls180.v:2569$3644 + attribute \src "ls180.v:2568.12-2568.50" + process $proc$ls180.v:2568$3641 assign { } { } assign $1\builder_comb_rhs_array_muxed15[21:0] 22'0000000000000000000000 sync always sync init update \builder_comb_rhs_array_muxed15 $1\builder_comb_rhs_array_muxed15[21:0] end - attribute \src "ls180.v:2570.5-2570.42" - process $proc$ls180.v:2570$3645 + attribute \src "ls180.v:2569.5-2569.42" + process $proc$ls180.v:2569$3642 assign { } { } assign $1\builder_comb_rhs_array_muxed16[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed16 $1\builder_comb_rhs_array_muxed16[0:0] end - attribute \src "ls180.v:2571.5-2571.42" - process $proc$ls180.v:2571$3646 + attribute \src "ls180.v:2570.5-2570.42" + process $proc$ls180.v:2570$3643 assign { } { } assign $1\builder_comb_rhs_array_muxed17[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed17 $1\builder_comb_rhs_array_muxed17[0:0] end - attribute \src "ls180.v:2572.12-2572.50" - process $proc$ls180.v:2572$3647 + attribute \src "ls180.v:2571.12-2571.50" + process $proc$ls180.v:2571$3644 assign { } { } assign $1\builder_comb_rhs_array_muxed18[21:0] 22'0000000000000000000000 sync always sync init update \builder_comb_rhs_array_muxed18 $1\builder_comb_rhs_array_muxed18[21:0] end - attribute \src "ls180.v:2573.5-2573.42" - process $proc$ls180.v:2573$3648 + attribute \src "ls180.v:2572.5-2572.42" + process $proc$ls180.v:2572$3645 assign { } { } assign $1\builder_comb_rhs_array_muxed19[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed19 $1\builder_comb_rhs_array_muxed19[0:0] end - attribute \src "ls180.v:2574.5-2574.42" - process $proc$ls180.v:2574$3649 + attribute \src "ls180.v:2573.5-2573.42" + process $proc$ls180.v:2573$3646 assign { } { } assign $1\builder_comb_rhs_array_muxed20[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed20 $1\builder_comb_rhs_array_muxed20[0:0] end - attribute \src "ls180.v:2575.12-2575.50" - process $proc$ls180.v:2575$3650 + attribute \src "ls180.v:2574.12-2574.50" + process $proc$ls180.v:2574$3647 assign { } { } assign $1\builder_comb_rhs_array_muxed21[21:0] 22'0000000000000000000000 sync always sync init update \builder_comb_rhs_array_muxed21 $1\builder_comb_rhs_array_muxed21[21:0] end - attribute \src "ls180.v:2576.5-2576.42" - process $proc$ls180.v:2576$3651 + attribute \src "ls180.v:2575.5-2575.42" + process $proc$ls180.v:2575$3648 assign { } { } assign $1\builder_comb_rhs_array_muxed22[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed22 $1\builder_comb_rhs_array_muxed22[0:0] end - attribute \src "ls180.v:2577.5-2577.42" - process $proc$ls180.v:2577$3652 + attribute \src "ls180.v:2576.5-2576.42" + process $proc$ls180.v:2576$3649 assign { } { } assign $1\builder_comb_rhs_array_muxed23[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed23 $1\builder_comb_rhs_array_muxed23[0:0] end - attribute \src "ls180.v:2578.12-2578.50" - process $proc$ls180.v:2578$3653 + attribute \src "ls180.v:2577.12-2577.50" + process $proc$ls180.v:2577$3650 assign { } { } assign $1\builder_comb_rhs_array_muxed24[31:0] 0 sync always sync init update \builder_comb_rhs_array_muxed24 $1\builder_comb_rhs_array_muxed24[31:0] end - attribute \src "ls180.v:2579.12-2579.50" - process $proc$ls180.v:2579$3654 + attribute \src "ls180.v:2578.12-2578.50" + process $proc$ls180.v:2578$3651 assign { } { } assign $1\builder_comb_rhs_array_muxed25[31:0] 0 sync always sync init update \builder_comb_rhs_array_muxed25 $1\builder_comb_rhs_array_muxed25[31:0] end - attribute \src "ls180.v:2580.11-2580.48" - process $proc$ls180.v:2580$3655 + attribute \src "ls180.v:2579.11-2579.48" + process $proc$ls180.v:2579$3652 assign { } { } assign $1\builder_comb_rhs_array_muxed26[3:0] 4'0000 sync always sync init update \builder_comb_rhs_array_muxed26 $1\builder_comb_rhs_array_muxed26[3:0] end - attribute \src "ls180.v:2581.5-2581.42" - process $proc$ls180.v:2581$3656 + attribute \src "ls180.v:2580.5-2580.42" + process $proc$ls180.v:2580$3653 assign { } { } assign $1\builder_comb_rhs_array_muxed27[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed27 $1\builder_comb_rhs_array_muxed27[0:0] end - attribute \src "ls180.v:2582.5-2582.42" - process $proc$ls180.v:2582$3657 + attribute \src "ls180.v:2581.5-2581.42" + process $proc$ls180.v:2581$3654 assign { } { } assign $1\builder_comb_rhs_array_muxed28[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed28 $1\builder_comb_rhs_array_muxed28[0:0] end - attribute \src "ls180.v:2583.5-2583.42" - process $proc$ls180.v:2583$3658 + attribute \src "ls180.v:2582.5-2582.42" + process $proc$ls180.v:2582$3655 assign { } { } assign $1\builder_comb_rhs_array_muxed29[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed29 $1\builder_comb_rhs_array_muxed29[0:0] end - attribute \src "ls180.v:2584.11-2584.48" - process $proc$ls180.v:2584$3659 + attribute \src "ls180.v:2583.11-2583.48" + process $proc$ls180.v:2583$3656 assign { } { } assign $1\builder_comb_rhs_array_muxed30[2:0] 3'000 sync always sync init update \builder_comb_rhs_array_muxed30 $1\builder_comb_rhs_array_muxed30[2:0] end - attribute \src "ls180.v:2585.11-2585.48" - process $proc$ls180.v:2585$3660 + attribute \src "ls180.v:2584.11-2584.48" + process $proc$ls180.v:2584$3657 assign { } { } assign $1\builder_comb_rhs_array_muxed31[1:0] 2'00 sync always sync init update \builder_comb_rhs_array_muxed31 $1\builder_comb_rhs_array_muxed31[1:0] end - attribute \src "ls180.v:2586.11-2586.47" - process $proc$ls180.v:2586$3661 + attribute \src "ls180.v:2585.11-2585.47" + process $proc$ls180.v:2585$3658 assign { } { } assign $1\builder_sync_rhs_array_muxed0[1:0] 2'00 sync always sync init update \builder_sync_rhs_array_muxed0 $1\builder_sync_rhs_array_muxed0[1:0] end - attribute \src "ls180.v:2587.12-2587.49" - process $proc$ls180.v:2587$3662 + attribute \src "ls180.v:2586.12-2586.49" + process $proc$ls180.v:2586$3659 assign { } { } assign $1\builder_sync_rhs_array_muxed1[12:0] 13'0000000000000 sync always sync init update \builder_sync_rhs_array_muxed1 $1\builder_sync_rhs_array_muxed1[12:0] end - attribute \src "ls180.v:2588.5-2588.41" - process $proc$ls180.v:2588$3663 + attribute \src "ls180.v:2587.5-2587.41" + process $proc$ls180.v:2587$3660 assign { } { } assign $1\builder_sync_rhs_array_muxed2[0:0] 1'0 sync always sync init update \builder_sync_rhs_array_muxed2 $1\builder_sync_rhs_array_muxed2[0:0] end - attribute \src "ls180.v:2589.5-2589.41" - process $proc$ls180.v:2589$3664 + attribute \src "ls180.v:2588.5-2588.41" + process $proc$ls180.v:2588$3661 assign { } { } assign $1\builder_sync_rhs_array_muxed3[0:0] 1'0 sync always sync init update \builder_sync_rhs_array_muxed3 $1\builder_sync_rhs_array_muxed3[0:0] end - attribute \src "ls180.v:2590.5-2590.41" - process $proc$ls180.v:2590$3665 + attribute \src "ls180.v:2589.5-2589.41" + process $proc$ls180.v:2589$3662 assign { } { } assign $1\builder_sync_rhs_array_muxed4[0:0] 1'0 sync always sync init update \builder_sync_rhs_array_muxed4 $1\builder_sync_rhs_array_muxed4[0:0] end - attribute \src "ls180.v:2591.5-2591.41" - process $proc$ls180.v:2591$3666 + attribute \src "ls180.v:2590.5-2590.41" + process $proc$ls180.v:2590$3663 assign { } { } assign $1\builder_sync_rhs_array_muxed5[0:0] 1'0 sync always sync init update \builder_sync_rhs_array_muxed5 $1\builder_sync_rhs_array_muxed5[0:0] end - attribute \src "ls180.v:2592.5-2592.41" - process $proc$ls180.v:2592$3667 + attribute \src "ls180.v:2591.5-2591.41" + process $proc$ls180.v:2591$3664 assign { } { } assign $1\builder_sync_rhs_array_muxed6[0:0] 1'0 sync always sync init update \builder_sync_rhs_array_muxed6 $1\builder_sync_rhs_array_muxed6[0:0] end - attribute \src "ls180.v:2593.5-2593.39" - process $proc$ls180.v:2593$3668 + attribute \src "ls180.v:2592.5-2592.39" + process $proc$ls180.v:2592$3665 assign { } { } assign $1\builder_sync_f_array_muxed0[0:0] 1'0 sync always sync init update \builder_sync_f_array_muxed0 $1\builder_sync_f_array_muxed0[0:0] end - attribute \src "ls180.v:2594.5-2594.39" - process $proc$ls180.v:2594$3669 + attribute \src "ls180.v:2593.5-2593.39" + process $proc$ls180.v:2593$3666 assign { } { } assign $1\builder_sync_f_array_muxed1[0:0] 1'0 sync always sync init update \builder_sync_f_array_muxed1 $1\builder_sync_f_array_muxed1[0:0] end - attribute \src "ls180.v:2649.32-2649.66" - process $proc$ls180.v:2649$3670 + attribute \src "ls180.v:2650.32-2650.66" + process $proc$ls180.v:2650$3667 assign { } { } assign $1\builder_multiregimpl0_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl0_regs0 $1\builder_multiregimpl0_regs0[0:0] end - attribute \src "ls180.v:2650.32-2650.66" - process $proc$ls180.v:2650$3671 + attribute \src "ls180.v:2651.32-2651.66" + process $proc$ls180.v:2651$3668 assign { } { } assign $1\builder_multiregimpl0_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl0_regs1 $1\builder_multiregimpl0_regs1[0:0] end - attribute \src "ls180.v:2651.32-2651.66" - process $proc$ls180.v:2651$3672 + attribute \src "ls180.v:2652.32-2652.66" + process $proc$ls180.v:2652$3669 assign { } { } assign $1\builder_multiregimpl1_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl1_regs0 $1\builder_multiregimpl1_regs0[0:0] end - attribute \src "ls180.v:2652.32-2652.66" - process $proc$ls180.v:2652$3673 + attribute \src "ls180.v:2653.32-2653.66" + process $proc$ls180.v:2653$3670 assign { } { } assign $1\builder_multiregimpl1_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl1_regs1 $1\builder_multiregimpl1_regs1[0:0] end - attribute \src "ls180.v:2653.32-2653.66" - process $proc$ls180.v:2653$3674 + attribute \src "ls180.v:2654.32-2654.66" + process $proc$ls180.v:2654$3671 assign { } { } assign $1\builder_multiregimpl2_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl2_regs0 $1\builder_multiregimpl2_regs0[0:0] end - attribute \src "ls180.v:2654.32-2654.66" - process $proc$ls180.v:2654$3675 + attribute \src "ls180.v:2655.32-2655.66" + process $proc$ls180.v:2655$3672 assign { } { } assign $1\builder_multiregimpl2_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl2_regs1 $1\builder_multiregimpl2_regs1[0:0] end - attribute \src "ls180.v:2655.32-2655.66" - process $proc$ls180.v:2655$3676 + attribute \src "ls180.v:2656.32-2656.66" + process $proc$ls180.v:2656$3673 assign { } { } assign $1\builder_multiregimpl3_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl3_regs0 $1\builder_multiregimpl3_regs0[0:0] end - attribute \src "ls180.v:2656.32-2656.66" - process $proc$ls180.v:2656$3677 + attribute \src "ls180.v:2657.32-2657.66" + process $proc$ls180.v:2657$3674 assign { } { } assign $1\builder_multiregimpl3_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl3_regs1 $1\builder_multiregimpl3_regs1[0:0] end - attribute \src "ls180.v:2657.32-2657.66" - process $proc$ls180.v:2657$3678 + attribute \src "ls180.v:2658.32-2658.66" + process $proc$ls180.v:2658$3675 assign { } { } assign $1\builder_multiregimpl4_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl4_regs0 $1\builder_multiregimpl4_regs0[0:0] end - attribute \src "ls180.v:2658.32-2658.66" - process $proc$ls180.v:2658$3679 + attribute \src "ls180.v:2659.32-2659.66" + process $proc$ls180.v:2659$3676 assign { } { } assign $1\builder_multiregimpl4_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl4_regs1 $1\builder_multiregimpl4_regs1[0:0] end - attribute \src "ls180.v:2659.32-2659.66" - process $proc$ls180.v:2659$3680 + attribute \src "ls180.v:2660.32-2660.66" + process $proc$ls180.v:2660$3677 assign { } { } assign $1\builder_multiregimpl5_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl5_regs0 $1\builder_multiregimpl5_regs0[0:0] end - attribute \src "ls180.v:2660.32-2660.66" - process $proc$ls180.v:2660$3681 + attribute \src "ls180.v:2661.32-2661.66" + process $proc$ls180.v:2661$3678 assign { } { } assign $1\builder_multiregimpl5_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl5_regs1 $1\builder_multiregimpl5_regs1[0:0] end - attribute \src "ls180.v:2661.32-2661.66" - process $proc$ls180.v:2661$3682 + attribute \src "ls180.v:2662.32-2662.66" + process $proc$ls180.v:2662$3679 assign { } { } assign $1\builder_multiregimpl6_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl6_regs0 $1\builder_multiregimpl6_regs0[0:0] end - attribute \src "ls180.v:2662.32-2662.66" - process $proc$ls180.v:2662$3683 + attribute \src "ls180.v:2663.32-2663.66" + process $proc$ls180.v:2663$3680 assign { } { } assign $1\builder_multiregimpl6_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl6_regs1 $1\builder_multiregimpl6_regs1[0:0] end - attribute \src "ls180.v:2663.32-2663.66" - process $proc$ls180.v:2663$3684 + attribute \src "ls180.v:2664.32-2664.66" + process $proc$ls180.v:2664$3681 assign { } { } assign $1\builder_multiregimpl7_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl7_regs0 $1\builder_multiregimpl7_regs0[0:0] end - attribute \src "ls180.v:2664.32-2664.66" - process $proc$ls180.v:2664$3685 + attribute \src "ls180.v:2665.32-2665.66" + process $proc$ls180.v:2665$3682 assign { } { } assign $1\builder_multiregimpl7_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl7_regs1 $1\builder_multiregimpl7_regs1[0:0] end - attribute \src "ls180.v:2665.32-2665.66" - process $proc$ls180.v:2665$3686 + attribute \src "ls180.v:2666.32-2666.66" + process $proc$ls180.v:2666$3683 assign { } { } assign $1\builder_multiregimpl8_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl8_regs0 $1\builder_multiregimpl8_regs0[0:0] end - attribute \src "ls180.v:2666.32-2666.66" - process $proc$ls180.v:2666$3687 + attribute \src "ls180.v:2667.32-2667.66" + process $proc$ls180.v:2667$3684 assign { } { } assign $1\builder_multiregimpl8_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl8_regs1 $1\builder_multiregimpl8_regs1[0:0] end - attribute \src "ls180.v:2667.32-2667.66" - process $proc$ls180.v:2667$3688 + attribute \src "ls180.v:2668.32-2668.66" + process $proc$ls180.v:2668$3685 assign { } { } assign $1\builder_multiregimpl9_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl9_regs0 $1\builder_multiregimpl9_regs0[0:0] end - attribute \src "ls180.v:2668.32-2668.66" - process $proc$ls180.v:2668$3689 + attribute \src "ls180.v:2669.32-2669.66" + process $proc$ls180.v:2669$3686 assign { } { } assign $1\builder_multiregimpl9_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl9_regs1 $1\builder_multiregimpl9_regs1[0:0] end - attribute \src "ls180.v:2669.32-2669.67" - process $proc$ls180.v:2669$3690 + attribute \src "ls180.v:2670.32-2670.67" + process $proc$ls180.v:2670$3687 assign { } { } assign $1\builder_multiregimpl10_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl10_regs0 $1\builder_multiregimpl10_regs0[0:0] end - attribute \src "ls180.v:2670.32-2670.67" - process $proc$ls180.v:2670$3691 + attribute \src "ls180.v:2671.32-2671.67" + process $proc$ls180.v:2671$3688 assign { } { } assign $1\builder_multiregimpl10_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl10_regs1 $1\builder_multiregimpl10_regs1[0:0] end - attribute \src "ls180.v:2671.32-2671.67" - process $proc$ls180.v:2671$3692 + attribute \src "ls180.v:2672.32-2672.67" + process $proc$ls180.v:2672$3689 assign { } { } assign $1\builder_multiregimpl11_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl11_regs0 $1\builder_multiregimpl11_regs0[0:0] end - attribute \src "ls180.v:2672.32-2672.67" - process $proc$ls180.v:2672$3693 + attribute \src "ls180.v:2673.32-2673.67" + process $proc$ls180.v:2673$3690 assign { } { } assign $1\builder_multiregimpl11_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl11_regs1 $1\builder_multiregimpl11_regs1[0:0] end - attribute \src "ls180.v:2673.32-2673.67" - process $proc$ls180.v:2673$3694 + attribute \src "ls180.v:2674.32-2674.67" + process $proc$ls180.v:2674$3691 assign { } { } assign $1\builder_multiregimpl12_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl12_regs0 $1\builder_multiregimpl12_regs0[0:0] end - attribute \src "ls180.v:2674.32-2674.67" - process $proc$ls180.v:2674$3695 + attribute \src "ls180.v:2675.32-2675.67" + process $proc$ls180.v:2675$3692 assign { } { } assign $1\builder_multiregimpl12_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl12_regs1 $1\builder_multiregimpl12_regs1[0:0] end - attribute \src "ls180.v:2675.32-2675.67" - process $proc$ls180.v:2675$3696 + attribute \src "ls180.v:2676.32-2676.67" + process $proc$ls180.v:2676$3693 assign { } { } assign $1\builder_multiregimpl13_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl13_regs0 $1\builder_multiregimpl13_regs0[0:0] end - attribute \src "ls180.v:2676.32-2676.67" - process $proc$ls180.v:2676$3697 + attribute \src "ls180.v:2677.32-2677.67" + process $proc$ls180.v:2677$3694 assign { } { } assign $1\builder_multiregimpl13_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl13_regs1 $1\builder_multiregimpl13_regs1[0:0] end - attribute \src "ls180.v:2677.32-2677.67" - process $proc$ls180.v:2677$3698 + attribute \src "ls180.v:2678.32-2678.67" + process $proc$ls180.v:2678$3695 assign { } { } assign $1\builder_multiregimpl14_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl14_regs0 $1\builder_multiregimpl14_regs0[0:0] end - attribute \src "ls180.v:2678.32-2678.67" - process $proc$ls180.v:2678$3699 + attribute \src "ls180.v:2679.32-2679.67" + process $proc$ls180.v:2679$3696 assign { } { } assign $1\builder_multiregimpl14_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl14_regs1 $1\builder_multiregimpl14_regs1[0:0] end - attribute \src "ls180.v:2679.32-2679.67" - process $proc$ls180.v:2679$3700 + attribute \src "ls180.v:268.12-268.46" + process $proc$ls180.v:268$2840 + assign { } { } + assign $1\main_sdram_slave_p0_rddata[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_slave_p0_rddata $1\main_sdram_slave_p0_rddata[15:0] + end + attribute \src "ls180.v:2680.32-2680.67" + process $proc$ls180.v:2680$3697 assign { } { } assign $1\builder_multiregimpl15_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl15_regs0 $1\builder_multiregimpl15_regs0[0:0] end - attribute \src "ls180.v:2680.32-2680.67" - process $proc$ls180.v:2680$3701 + attribute \src "ls180.v:2681.32-2681.67" + process $proc$ls180.v:2681$3698 assign { } { } assign $1\builder_multiregimpl15_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl15_regs1 $1\builder_multiregimpl15_regs1[0:0] end - attribute \src "ls180.v:2681.32-2681.67" - process $proc$ls180.v:2681$3702 + attribute \src "ls180.v:2682.32-2682.67" + process $proc$ls180.v:2682$3699 assign { } { } assign $1\builder_multiregimpl16_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl16_regs0 $1\builder_multiregimpl16_regs0[0:0] end - attribute \src "ls180.v:2682.32-2682.67" - process $proc$ls180.v:2682$3703 + attribute \src "ls180.v:2683.32-2683.67" + process $proc$ls180.v:2683$3700 assign { } { } assign $1\builder_multiregimpl16_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl16_regs1 $1\builder_multiregimpl16_regs1[0:0] end - attribute \src "ls180.v:269.12-269.46" - process $proc$ls180.v:269$2843 - assign { } { } - assign $1\main_sdram_slave_p0_rddata[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdram_slave_p0_rddata $1\main_sdram_slave_p0_rddata[15:0] - end - attribute \src "ls180.v:270.5-270.44" - process $proc$ls180.v:270$2844 + attribute \src "ls180.v:269.5-269.44" + process $proc$ls180.v:269$2841 assign { } { } assign $1\main_sdram_slave_p0_rddata_valid[0:0] 1'0 sync always sync init update \main_sdram_slave_p0_rddata_valid $1\main_sdram_slave_p0_rddata_valid[0:0] end - attribute \src "ls180.v:271.12-271.48" - process $proc$ls180.v:271$2845 + attribute \src "ls180.v:270.12-270.48" + process $proc$ls180.v:270$2842 assign { } { } assign $1\main_sdram_master_p0_address[12:0] 13'0000000000000 sync always sync init update \main_sdram_master_p0_address $1\main_sdram_master_p0_address[12:0] end - attribute \src "ls180.v:2719.1-2724.4" - process $proc$ls180.v:2719$13 + attribute \src "ls180.v:271.11-271.43" + process $proc$ls180.v:271$2843 + assign { } { } + assign $1\main_sdram_master_p0_bank[1:0] 2'00 + sync always + sync init + update \main_sdram_master_p0_bank $1\main_sdram_master_p0_bank[1:0] + end + attribute \src "ls180.v:272.5-272.38" + process $proc$ls180.v:272$2844 + assign { } { } + assign $1\main_sdram_master_p0_cas_n[0:0] 1'1 + sync always + sync init + update \main_sdram_master_p0_cas_n $1\main_sdram_master_p0_cas_n[0:0] + end + attribute \src "ls180.v:2720.1-2725.4" + process $proc$ls180.v:2720$13 assign { } { } assign $0\main_libresocsim_libresoc_interrupt[15:0] [11:2] 10'0000000000 assign $0\main_libresocsim_libresoc_interrupt[15:0] [15:12] { 1'0 \eint } @@ -115373,19 +115341,11 @@ module \ls180 sync always update \main_libresocsim_libresoc_interrupt $0\main_libresocsim_libresoc_interrupt[15:0] end - attribute \src "ls180.v:272.11-272.43" - process $proc$ls180.v:272$2846 - assign { } { } - assign $1\main_sdram_master_p0_bank[1:0] 2'00 - sync always - sync init - update \main_sdram_master_p0_bank $1\main_sdram_master_p0_bank[1:0] - end - attribute \src "ls180.v:2726.1-2736.4" - process $proc$ls180.v:2726$15 + attribute \src "ls180.v:2727.1-2737.4" + process $proc$ls180.v:2727$15 assign { } { } assign $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] 0 - attribute \src "ls180.v:2728.2-2735.9" + attribute \src "ls180.v:2729.2-2736.9" switch \main_libresocsim_converter0_counter attribute \src "ls180.v:0.0-0.0" case 1'0 @@ -115398,16 +115358,16 @@ module \ls180 sync always update \main_libresocsim_interface0_converted_interface_dat_w $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] end - attribute \src "ls180.v:273.5-273.38" - process $proc$ls180.v:273$2847 + attribute \src "ls180.v:273.5-273.37" + process $proc$ls180.v:273$2845 assign { } { } - assign $1\main_sdram_master_p0_cas_n[0:0] 1'1 + assign $1\main_sdram_master_p0_cs_n[0:0] 1'1 sync always sync init - update \main_sdram_master_p0_cas_n $1\main_sdram_master_p0_cas_n[0:0] + update \main_sdram_master_p0_cs_n $1\main_sdram_master_p0_cs_n[0:0] end - attribute \src "ls180.v:2738.1-2784.4" - process $proc$ls180.v:2738$16 + attribute \src "ls180.v:2739.1-2785.4" + process $proc$ls180.v:2739$16 assign { } { } assign { } { } assign { } { } @@ -115418,23 +115378,23 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'0 assign $0\main_libresocsim_interface0_converted_interface_we[0:0] 1'0 assign $0\main_libresocsim_libresoc_ibus_ack[0:0] 1'0 - assign { } { } - assign $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] 1'0 - assign $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'0 assign $0\main_libresocsim_converter0_skip[0:0] 1'0 assign $0\main_libresocsim_interface0_converted_interface_adr[29:0] 30'000000000000000000000000000000 assign $0\main_libresocsim_interface0_converted_interface_sel[3:0] 4'0000 + assign { } { } assign $0\main_libresocsim_interface0_converted_interface_cyc[0:0] 1'0 + assign $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] 1'0 assign $0\main_libresocsim_interface0_converted_interface_stb[0:0] 1'0 assign $0\builder_converter0_next_state[0:0] \builder_converter0_state - attribute \src "ls180.v:2750.2-2783.9" + attribute \src "ls180.v:2751.2-2784.9" switch \builder_converter0_state attribute \src "ls180.v:0.0-0.0" case 1'1 assign $0\main_libresocsim_interface0_converted_interface_adr[29:0] { \main_libresocsim_libresoc_ibus_adr \main_libresocsim_converter0_counter } - attribute \src "ls180.v:2753.4-2760.11" + attribute \src "ls180.v:2754.4-2761.11" switch \main_libresocsim_converter0_counter attribute \src "ls180.v:0.0-0.0" case 1'0 @@ -115444,23 +115404,23 @@ module \ls180 assign $0\main_libresocsim_interface0_converted_interface_sel[3:0] \main_libresocsim_libresoc_ibus_sel [7:4] case end - attribute \src "ls180.v:2761.4-2774.7" - switch $and$ls180.v:2761$17_Y - attribute \src "ls180.v:2761.8-2761.81" + attribute \src "ls180.v:2762.4-2775.7" + switch $and$ls180.v:2762$17_Y + attribute \src "ls180.v:2762.8-2762.81" case 1'1 - assign $0\main_libresocsim_converter0_skip[0:0] $eq$ls180.v:2762$18_Y + assign $0\main_libresocsim_converter0_skip[0:0] $eq$ls180.v:2763$18_Y assign $0\main_libresocsim_interface0_converted_interface_we[0:0] \main_libresocsim_libresoc_ibus_we - assign $0\main_libresocsim_interface0_converted_interface_cyc[0:0] $not$ls180.v:2764$19_Y - assign $0\main_libresocsim_interface0_converted_interface_stb[0:0] $not$ls180.v:2765$20_Y - attribute \src "ls180.v:2766.5-2773.8" - switch $or$ls180.v:2766$21_Y - attribute \src "ls180.v:2766.9-2766.97" + assign $0\main_libresocsim_interface0_converted_interface_cyc[0:0] $not$ls180.v:2765$19_Y + assign $0\main_libresocsim_interface0_converted_interface_stb[0:0] $not$ls180.v:2766$20_Y + attribute \src "ls180.v:2767.5-2774.8" + switch $or$ls180.v:2767$21_Y + attribute \src "ls180.v:2767.9-2767.97" case 1'1 - assign $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] $add$ls180.v:2767$22_Y + assign $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] $add$ls180.v:2768$22_Y assign $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2769.6-2772.9" - switch $eq$ls180.v:2769$23_Y - attribute \src "ls180.v:2769.10-2769.55" + attribute \src "ls180.v:2770.6-2773.9" + switch $eq$ls180.v:2770$23_Y + attribute \src "ls180.v:2770.10-2770.55" case 1'1 assign $0\main_libresocsim_libresoc_ibus_ack[0:0] 1'1 assign $0\builder_converter0_next_state[0:0] 1'0 @@ -115474,9 +115434,9 @@ module \ls180 case assign $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] 1'0 assign $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2779.4-2781.7" - switch $and$ls180.v:2779$24_Y - attribute \src "ls180.v:2779.8-2779.81" + attribute \src "ls180.v:2780.4-2782.7" + switch $and$ls180.v:2780$24_Y + attribute \src "ls180.v:2780.8-2780.81" case 1'1 assign $0\builder_converter0_next_state[0:0] 1'1 case @@ -115494,51 +115454,51 @@ module \ls180 update \main_libresocsim_converter0_counter_converter0_next_value $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] update \main_libresocsim_converter0_counter_converter0_next_value_ce $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] end - attribute \src "ls180.v:274.5-274.37" - process $proc$ls180.v:274$2848 - assign { } { } - assign $1\main_sdram_master_p0_cs_n[0:0] 1'1 - sync always - sync init - update \main_sdram_master_p0_cs_n $1\main_sdram_master_p0_cs_n[0:0] - end - attribute \src "ls180.v:275.5-275.38" - process $proc$ls180.v:275$2849 + attribute \src "ls180.v:274.5-274.38" + process $proc$ls180.v:274$2846 assign { } { } assign $1\main_sdram_master_p0_ras_n[0:0] 1'1 sync always sync init update \main_sdram_master_p0_ras_n $1\main_sdram_master_p0_ras_n[0:0] end - attribute \src "ls180.v:276.5-276.37" - process $proc$ls180.v:276$2850 + attribute \src "ls180.v:275.5-275.37" + process $proc$ls180.v:275$2847 assign { } { } assign $1\main_sdram_master_p0_we_n[0:0] 1'1 sync always sync init update \main_sdram_master_p0_we_n $1\main_sdram_master_p0_we_n[0:0] end - attribute \src "ls180.v:277.5-277.36" - process $proc$ls180.v:277$2851 + attribute \src "ls180.v:276.5-276.36" + process $proc$ls180.v:276$2848 assign { } { } assign $1\main_sdram_master_p0_cke[0:0] 1'0 sync always sync init update \main_sdram_master_p0_cke $1\main_sdram_master_p0_cke[0:0] end - attribute \src "ls180.v:278.5-278.36" - process $proc$ls180.v:278$2852 + attribute \src "ls180.v:277.5-277.36" + process $proc$ls180.v:277$2849 assign { } { } assign $1\main_sdram_master_p0_odt[0:0] 1'0 sync always sync init update \main_sdram_master_p0_odt $1\main_sdram_master_p0_odt[0:0] end - attribute \src "ls180.v:2786.1-2796.4" - process $proc$ls180.v:2786$26 + attribute \src "ls180.v:278.5-278.40" + process $proc$ls180.v:278$2850 + assign { } { } + assign $1\main_sdram_master_p0_reset_n[0:0] 1'0 + sync always + sync init + update \main_sdram_master_p0_reset_n $1\main_sdram_master_p0_reset_n[0:0] + end + attribute \src "ls180.v:2787.1-2797.4" + process $proc$ls180.v:2787$26 assign { } { } assign $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] 0 - attribute \src "ls180.v:2788.2-2795.9" + attribute \src "ls180.v:2789.2-2796.9" switch \main_libresocsim_converter1_counter attribute \src "ls180.v:0.0-0.0" case 1'0 @@ -115551,17 +115511,16 @@ module \ls180 sync always update \main_libresocsim_interface1_converted_interface_dat_w $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] end - attribute \src "ls180.v:279.5-279.40" - process $proc$ls180.v:279$2853 + attribute \src "ls180.v:279.5-279.38" + process $proc$ls180.v:279$2851 assign { } { } - assign $1\main_sdram_master_p0_reset_n[0:0] 1'0 + assign $1\main_sdram_master_p0_act_n[0:0] 1'1 sync always sync init - update \main_sdram_master_p0_reset_n $1\main_sdram_master_p0_reset_n[0:0] + update \main_sdram_master_p0_act_n $1\main_sdram_master_p0_act_n[0:0] end - attribute \src "ls180.v:2798.1-2844.4" - process $proc$ls180.v:2798$27 - assign { } { } + attribute \src "ls180.v:2799.1-2845.4" + process $proc$ls180.v:2799$27 assign { } { } assign { } { } assign { } { } @@ -115573,21 +115532,22 @@ module \ls180 assign { } { } assign { } { } assign $0\main_libresocsim_converter1_skip[0:0] 1'0 - assign $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] 1'0 - assign $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'0 assign $0\main_libresocsim_interface1_converted_interface_adr[29:0] 30'000000000000000000000000000000 + assign $0\main_libresocsim_interface1_converted_interface_we[0:0] 1'0 assign $0\main_libresocsim_libresoc_dbus_ack[0:0] 1'0 assign $0\main_libresocsim_interface1_converted_interface_sel[3:0] 4'0000 assign $0\main_libresocsim_interface1_converted_interface_cyc[0:0] 1'0 assign $0\main_libresocsim_interface1_converted_interface_stb[0:0] 1'0 - assign $0\main_libresocsim_interface1_converted_interface_we[0:0] 1'0 + assign { } { } + assign $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] 1'0 + assign $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'0 assign $0\builder_converter1_next_state[0:0] \builder_converter1_state - attribute \src "ls180.v:2810.2-2843.9" + attribute \src "ls180.v:2811.2-2844.9" switch \builder_converter1_state attribute \src "ls180.v:0.0-0.0" case 1'1 assign $0\main_libresocsim_interface1_converted_interface_adr[29:0] { \main_libresocsim_libresoc_dbus_adr \main_libresocsim_converter1_counter } - attribute \src "ls180.v:2813.4-2820.11" + attribute \src "ls180.v:2814.4-2821.11" switch \main_libresocsim_converter1_counter attribute \src "ls180.v:0.0-0.0" case 1'0 @@ -115597,23 +115557,23 @@ module \ls180 assign $0\main_libresocsim_interface1_converted_interface_sel[3:0] \main_libresocsim_libresoc_dbus_sel [7:4] case end - attribute \src "ls180.v:2821.4-2834.7" - switch $and$ls180.v:2821$28_Y - attribute \src "ls180.v:2821.8-2821.81" + attribute \src "ls180.v:2822.4-2835.7" + switch $and$ls180.v:2822$28_Y + attribute \src "ls180.v:2822.8-2822.81" case 1'1 - assign $0\main_libresocsim_converter1_skip[0:0] $eq$ls180.v:2822$29_Y + assign $0\main_libresocsim_converter1_skip[0:0] $eq$ls180.v:2823$29_Y assign $0\main_libresocsim_interface1_converted_interface_we[0:0] \main_libresocsim_libresoc_dbus_we - assign $0\main_libresocsim_interface1_converted_interface_cyc[0:0] $not$ls180.v:2824$30_Y - assign $0\main_libresocsim_interface1_converted_interface_stb[0:0] $not$ls180.v:2825$31_Y - attribute \src "ls180.v:2826.5-2833.8" - switch $or$ls180.v:2826$32_Y - attribute \src "ls180.v:2826.9-2826.97" + assign $0\main_libresocsim_interface1_converted_interface_cyc[0:0] $not$ls180.v:2825$30_Y + assign $0\main_libresocsim_interface1_converted_interface_stb[0:0] $not$ls180.v:2826$31_Y + attribute \src "ls180.v:2827.5-2834.8" + switch $or$ls180.v:2827$32_Y + attribute \src "ls180.v:2827.9-2827.97" case 1'1 - assign $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] $add$ls180.v:2827$33_Y + assign $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] $add$ls180.v:2828$33_Y assign $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2829.6-2832.9" - switch $eq$ls180.v:2829$34_Y - attribute \src "ls180.v:2829.10-2829.55" + attribute \src "ls180.v:2830.6-2833.9" + switch $eq$ls180.v:2830$34_Y + attribute \src "ls180.v:2830.10-2830.55" case 1'1 assign $0\main_libresocsim_libresoc_dbus_ack[0:0] 1'1 assign $0\builder_converter1_next_state[0:0] 1'0 @@ -115627,9 +115587,9 @@ module \ls180 case assign $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] 1'0 assign $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2839.4-2841.7" - switch $and$ls180.v:2839$35_Y - attribute \src "ls180.v:2839.8-2839.81" + attribute \src "ls180.v:2840.4-2842.7" + switch $and$ls180.v:2840$35_Y + attribute \src "ls180.v:2840.8-2840.81" case 1'1 assign $0\builder_converter1_next_state[0:0] 1'1 case @@ -115647,51 +115607,43 @@ module \ls180 update \main_libresocsim_converter1_counter_converter1_next_value $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] update \main_libresocsim_converter1_counter_converter1_next_value_ce $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] end - attribute \src "ls180.v:280.5-280.38" - process $proc$ls180.v:280$2854 - assign { } { } - assign $1\main_sdram_master_p0_act_n[0:0] 1'1 - sync always - sync init - update \main_sdram_master_p0_act_n $1\main_sdram_master_p0_act_n[0:0] - end - attribute \src "ls180.v:281.12-281.47" - process $proc$ls180.v:281$2855 + attribute \src "ls180.v:280.12-280.47" + process $proc$ls180.v:280$2852 assign { } { } assign $1\main_sdram_master_p0_wrdata[15:0] 16'0000000000000000 sync always sync init update \main_sdram_master_p0_wrdata $1\main_sdram_master_p0_wrdata[15:0] end - attribute \src "ls180.v:282.5-282.42" - process $proc$ls180.v:282$2856 + attribute \src "ls180.v:281.5-281.42" + process $proc$ls180.v:281$2853 assign { } { } assign $1\main_sdram_master_p0_wrdata_en[0:0] 1'0 sync always sync init update \main_sdram_master_p0_wrdata_en $1\main_sdram_master_p0_wrdata_en[0:0] end - attribute \src "ls180.v:283.11-283.50" - process $proc$ls180.v:283$2857 + attribute \src "ls180.v:282.11-282.50" + process $proc$ls180.v:282$2854 assign { } { } assign $1\main_sdram_master_p0_wrdata_mask[1:0] 2'00 sync always sync init update \main_sdram_master_p0_wrdata_mask $1\main_sdram_master_p0_wrdata_mask[1:0] end - attribute \src "ls180.v:284.5-284.42" - process $proc$ls180.v:284$2858 + attribute \src "ls180.v:283.5-283.42" + process $proc$ls180.v:283$2855 assign { } { } assign $1\main_sdram_master_p0_rddata_en[0:0] 1'0 sync always sync init update \main_sdram_master_p0_rddata_en $1\main_sdram_master_p0_rddata_en[0:0] end - attribute \src "ls180.v:2846.1-2856.4" - process $proc$ls180.v:2846$37 + attribute \src "ls180.v:2847.1-2857.4" + process $proc$ls180.v:2847$37 assign { } { } assign $0\main_libresocsim_interface2_converted_interface_dat_w[31:0] 0 - attribute \src "ls180.v:2848.2-2855.9" + attribute \src "ls180.v:2849.2-2856.9" switch \main_libresocsim_converter2_counter attribute \src "ls180.v:0.0-0.0" case 1'0 @@ -115704,8 +115656,8 @@ module \ls180 sync always update \main_libresocsim_interface2_converted_interface_dat_w $0\main_libresocsim_interface2_converted_interface_dat_w[31:0] end - attribute \src "ls180.v:2858.1-2904.4" - process $proc$ls180.v:2858$38 + attribute \src "ls180.v:2859.1-2905.4" + process $proc$ls180.v:2859$38 assign { } { } assign { } { } assign { } { } @@ -115716,23 +115668,23 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] 1'0 - assign $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'0 assign $0\main_libresocsim_interface2_converted_interface_adr[29:0] 30'000000000000000000000000000000 assign $0\main_libresocsim_libresoc_jtag_wb_ack[0:0] 1'0 assign $0\main_libresocsim_interface2_converted_interface_sel[3:0] 4'0000 assign $0\main_libresocsim_interface2_converted_interface_cyc[0:0] 1'0 assign $0\main_libresocsim_interface2_converted_interface_stb[0:0] 1'0 assign $0\main_libresocsim_interface2_converted_interface_we[0:0] 1'0 - assign $0\main_libresocsim_converter2_skip[0:0] 1'0 assign { } { } + assign $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] 1'0 + assign $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'0 + assign $0\main_libresocsim_converter2_skip[0:0] 1'0 assign $0\builder_converter2_next_state[0:0] \builder_converter2_state - attribute \src "ls180.v:2870.2-2903.9" + attribute \src "ls180.v:2871.2-2904.9" switch \builder_converter2_state attribute \src "ls180.v:0.0-0.0" case 1'1 assign $0\main_libresocsim_interface2_converted_interface_adr[29:0] { \main_libresocsim_libresoc_jtag_wb_adr \main_libresocsim_converter2_counter } - attribute \src "ls180.v:2873.4-2880.11" + attribute \src "ls180.v:2874.4-2881.11" switch \main_libresocsim_converter2_counter attribute \src "ls180.v:0.0-0.0" case 1'0 @@ -115742,23 +115694,23 @@ module \ls180 assign $0\main_libresocsim_interface2_converted_interface_sel[3:0] \main_libresocsim_libresoc_jtag_wb_sel [7:4] case end - attribute \src "ls180.v:2881.4-2894.7" - switch $and$ls180.v:2881$39_Y - attribute \src "ls180.v:2881.8-2881.87" + attribute \src "ls180.v:2882.4-2895.7" + switch $and$ls180.v:2882$39_Y + attribute \src "ls180.v:2882.8-2882.87" case 1'1 - assign $0\main_libresocsim_converter2_skip[0:0] $eq$ls180.v:2882$40_Y + assign $0\main_libresocsim_converter2_skip[0:0] $eq$ls180.v:2883$40_Y assign $0\main_libresocsim_interface2_converted_interface_we[0:0] \main_libresocsim_libresoc_jtag_wb_we - assign $0\main_libresocsim_interface2_converted_interface_cyc[0:0] $not$ls180.v:2884$41_Y - assign $0\main_libresocsim_interface2_converted_interface_stb[0:0] $not$ls180.v:2885$42_Y - attribute \src "ls180.v:2886.5-2893.8" - switch $or$ls180.v:2886$43_Y - attribute \src "ls180.v:2886.9-2886.97" + assign $0\main_libresocsim_interface2_converted_interface_cyc[0:0] $not$ls180.v:2885$41_Y + assign $0\main_libresocsim_interface2_converted_interface_stb[0:0] $not$ls180.v:2886$42_Y + attribute \src "ls180.v:2887.5-2894.8" + switch $or$ls180.v:2887$43_Y + attribute \src "ls180.v:2887.9-2887.97" case 1'1 - assign $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] $add$ls180.v:2887$44_Y + assign $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] $add$ls180.v:2888$44_Y assign $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2889.6-2892.9" - switch $eq$ls180.v:2889$45_Y - attribute \src "ls180.v:2889.10-2889.55" + attribute \src "ls180.v:2890.6-2893.9" + switch $eq$ls180.v:2890$45_Y + attribute \src "ls180.v:2890.10-2890.55" case 1'1 assign $0\main_libresocsim_libresoc_jtag_wb_ack[0:0] 1'1 assign $0\builder_converter2_next_state[0:0] 1'0 @@ -115772,9 +115724,9 @@ module \ls180 case assign $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] 1'0 assign $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2899.4-2901.7" - switch $and$ls180.v:2899$46_Y - attribute \src "ls180.v:2899.8-2899.87" + attribute \src "ls180.v:2900.4-2902.7" + switch $and$ls180.v:2900$46_Y + attribute \src "ls180.v:2900.8-2900.87" case 1'1 assign $0\builder_converter2_next_state[0:0] 1'1 case @@ -115792,74 +115744,65 @@ module \ls180 update \main_libresocsim_converter2_counter_converter2_next_value $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] update \main_libresocsim_converter2_counter_converter2_next_value_ce $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] end - attribute \src "ls180.v:2907.1-2913.4" - process $proc$ls180.v:2907$47 - assign { } { } - assign { } { } - assign $0\main_libresocsim_we[3:0] [0] $and$ls180.v:2909$50_Y - assign $0\main_libresocsim_we[3:0] [1] $and$ls180.v:2910$53_Y - assign $0\main_libresocsim_we[3:0] [2] $and$ls180.v:2911$56_Y - assign $0\main_libresocsim_we[3:0] [3] $and$ls180.v:2912$59_Y - sync always - update \main_libresocsim_we $0\main_libresocsim_we[3:0] - end - attribute \src "ls180.v:291.11-291.36" - process $proc$ls180.v:291$2859 + attribute \src "ls180.v:290.11-290.36" + process $proc$ls180.v:290$2856 assign { } { } assign $1\main_sdram_storage[3:0] 4'0001 sync always sync init update \main_sdram_storage $1\main_sdram_storage[3:0] end - attribute \src "ls180.v:2919.1-2924.4" - process $proc$ls180.v:2919$61 + attribute \src "ls180.v:2908.1-2914.4" + process $proc$ls180.v:2908$47 assign { } { } - assign $0\main_libresocsim_zero_clear[0:0] 1'0 - attribute \src "ls180.v:2921.2-2923.5" - switch $and$ls180.v:2921$62_Y - attribute \src "ls180.v:2921.6-2921.90" - case 1'1 - assign $0\main_libresocsim_zero_clear[0:0] 1'1 - case - end + assign { } { } + assign $0\main_libresocsim_we[3:0] [0] $and$ls180.v:2910$50_Y + assign $0\main_libresocsim_we[3:0] [1] $and$ls180.v:2911$53_Y + assign $0\main_libresocsim_we[3:0] [2] $and$ls180.v:2912$56_Y + assign $0\main_libresocsim_we[3:0] [3] $and$ls180.v:2913$59_Y sync always - update \main_libresocsim_zero_clear $0\main_libresocsim_zero_clear[0:0] + update \main_libresocsim_we $0\main_libresocsim_we[3:0] end - attribute \src "ls180.v:292.5-292.25" - process $proc$ls180.v:292$2860 + attribute \src "ls180.v:291.5-291.25" + process $proc$ls180.v:291$2857 assign { } { } assign $1\main_sdram_re[0:0] 1'0 sync always sync init update \main_sdram_re $1\main_sdram_re[0:0] end - attribute \src "ls180.v:293.11-293.44" - process $proc$ls180.v:293$2861 + attribute \src "ls180.v:292.11-292.44" + process $proc$ls180.v:292$2858 assign { } { } assign $1\main_sdram_command_storage[5:0] 6'000000 sync always sync init update \main_sdram_command_storage $1\main_sdram_command_storage[5:0] end - attribute \src "ls180.v:2931.1-2935.4" - process $proc$ls180.v:2931$64 + attribute \src "ls180.v:2920.1-2925.4" + process $proc$ls180.v:2920$61 assign { } { } - assign { } { } - assign $0\main_dm[1:0] [0] 1'1 - assign $0\main_dm[1:0] [1] 1'1 + assign $0\main_libresocsim_zero_clear[0:0] 1'0 + attribute \src "ls180.v:2922.2-2924.5" + switch $and$ls180.v:2922$62_Y + attribute \src "ls180.v:2922.6-2922.90" + case 1'1 + assign $0\main_libresocsim_zero_clear[0:0] 1'1 + case + end sync always - update \main_dm $0\main_dm[1:0] + update \main_libresocsim_zero_clear $0\main_libresocsim_zero_clear[0:0] end - attribute \src "ls180.v:294.5-294.33" - process $proc$ls180.v:294$2862 + attribute \src "ls180.v:293.5-293.33" + process $proc$ls180.v:293$2859 assign { } { } assign $1\main_sdram_command_re[0:0] 1'0 sync always sync init update \main_sdram_command_re $1\main_sdram_command_re[0:0] end - attribute \src "ls180.v:2968.1-3022.4" - process $proc$ls180.v:2968$65 + attribute \src "ls180.v:2964.1-3018.4" + process $proc$ls180.v:2964$64 assign { } { } assign { } { } assign { } { } @@ -115878,7 +115821,6 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdram_master_p0_address[12:0] 13'0000000000000 assign $0\main_sdram_master_p0_bank[1:0] 2'00 assign $0\main_sdram_master_p0_cas_n[0:0] 1'1 assign $0\main_sdram_master_p0_cs_n[0:0] 1'1 @@ -115887,18 +115829,19 @@ module \ls180 assign $0\main_sdram_master_p0_cke[0:0] 1'0 assign $0\main_sdram_master_p0_odt[0:0] 1'0 assign $0\main_sdram_master_p0_reset_n[0:0] 1'0 - assign $0\main_sdram_inti_p0_rddata[15:0] 16'0000000000000000 assign $0\main_sdram_master_p0_act_n[0:0] 1'1 - assign $0\main_sdram_inti_p0_rddata_valid[0:0] 1'0 + assign $0\main_sdram_inti_p0_rddata[15:0] 16'0000000000000000 assign $0\main_sdram_master_p0_wrdata[15:0] 16'0000000000000000 + assign $0\main_sdram_inti_p0_rddata_valid[0:0] 1'0 assign $0\main_sdram_master_p0_wrdata_en[0:0] 1'0 assign $0\main_sdram_master_p0_wrdata_mask[1:0] 2'00 assign $0\main_sdram_master_p0_rddata_en[0:0] 1'0 assign $0\main_sdram_slave_p0_rddata[15:0] 16'0000000000000000 assign $0\main_sdram_slave_p0_rddata_valid[0:0] 1'0 - attribute \src "ls180.v:2987.2-3021.5" + assign $0\main_sdram_master_p0_address[12:0] 13'0000000000000 + attribute \src "ls180.v:2983.2-3017.5" switch \main_sdram_sel - attribute \src "ls180.v:2987.6-2987.20" + attribute \src "ls180.v:2983.6-2983.20" case 1'1 assign $0\main_sdram_master_p0_address[12:0] \main_sdram_slave_p0_address assign $0\main_sdram_master_p0_bank[1:0] \main_sdram_slave_p0_bank @@ -115916,7 +115859,7 @@ module \ls180 assign $0\main_sdram_master_p0_rddata_en[0:0] \main_sdram_slave_p0_rddata_en assign $0\main_sdram_slave_p0_rddata[15:0] \main_sdram_master_p0_rddata assign $0\main_sdram_slave_p0_rddata_valid[0:0] \main_sdram_master_p0_rddata_valid - attribute \src "ls180.v:3004.6-3004.10" + attribute \src "ls180.v:3000.6-3000.10" case assign $0\main_sdram_master_p0_address[12:0] \main_sdram_inti_p0_address assign $0\main_sdram_master_p0_bank[1:0] \main_sdram_inti_p0_bank @@ -115955,65 +115898,73 @@ module \ls180 update \main_sdram_master_p0_wrdata_mask $0\main_sdram_master_p0_wrdata_mask[1:0] update \main_sdram_master_p0_rddata_en $0\main_sdram_master_p0_rddata_en[0:0] end - attribute \src "ls180.v:298.5-298.38" - process $proc$ls180.v:298$2863 + attribute \src "ls180.v:297.5-297.38" + process $proc$ls180.v:297$2860 assign { } { } assign $0\main_sdram_command_issue_w[0:0] 1'0 sync always update \main_sdram_command_issue_w $0\main_sdram_command_issue_w[0:0] sync init end - attribute \src "ls180.v:299.12-299.46" - process $proc$ls180.v:299$2864 + attribute \src "ls180.v:298.12-298.46" + process $proc$ls180.v:298$2861 assign { } { } assign $1\main_sdram_address_storage[12:0] 13'0000000000000 sync always sync init update \main_sdram_address_storage $1\main_sdram_address_storage[12:0] end - attribute \src "ls180.v:300.5-300.33" - process $proc$ls180.v:300$2865 + attribute \src "ls180.v:299.5-299.33" + process $proc$ls180.v:299$2862 assign { } { } assign $1\main_sdram_address_re[0:0] 1'0 sync always sync init update \main_sdram_address_re $1\main_sdram_address_re[0:0] end - attribute \src "ls180.v:301.11-301.45" - process $proc$ls180.v:301$2866 + attribute \src "ls180.v:300.11-300.45" + process $proc$ls180.v:300$2863 assign { } { } assign $1\main_sdram_baddress_storage[1:0] 2'00 sync always sync init update \main_sdram_baddress_storage $1\main_sdram_baddress_storage[1:0] end - attribute \src "ls180.v:302.5-302.34" - process $proc$ls180.v:302$2867 + attribute \src "ls180.v:301.5-301.34" + process $proc$ls180.v:301$2864 assign { } { } assign $1\main_sdram_baddress_re[0:0] 1'0 sync always sync init update \main_sdram_baddress_re $1\main_sdram_baddress_re[0:0] end - attribute \src "ls180.v:3026.1-3042.4" - process $proc$ls180.v:3026$66 + attribute \src "ls180.v:302.12-302.45" + process $proc$ls180.v:302$2865 + assign { } { } + assign $1\main_sdram_wrdata_storage[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_wrdata_storage $1\main_sdram_wrdata_storage[15:0] + end + attribute \src "ls180.v:3022.1-3038.4" + process $proc$ls180.v:3022$65 assign { } { } assign { } { } assign { } { } assign { } { } + assign $0\main_sdram_inti_p0_cas_n[0:0] 1'1 assign $0\main_sdram_inti_p0_cs_n[0:0] 1'1 assign $0\main_sdram_inti_p0_ras_n[0:0] 1'1 assign $0\main_sdram_inti_p0_we_n[0:0] 1'1 - assign $0\main_sdram_inti_p0_cas_n[0:0] 1'1 - attribute \src "ls180.v:3031.2-3041.5" + attribute \src "ls180.v:3027.2-3037.5" switch \main_sdram_command_issue_re - attribute \src "ls180.v:3031.6-3031.33" + attribute \src "ls180.v:3027.6-3027.33" case 1'1 - assign $0\main_sdram_inti_p0_cs_n[0:0] $not$ls180.v:3032$67_Y - assign $0\main_sdram_inti_p0_we_n[0:0] $not$ls180.v:3033$68_Y - assign $0\main_sdram_inti_p0_cas_n[0:0] $not$ls180.v:3034$69_Y - assign $0\main_sdram_inti_p0_ras_n[0:0] $not$ls180.v:3035$70_Y - attribute \src "ls180.v:3036.6-3036.10" + assign $0\main_sdram_inti_p0_cs_n[0:0] $not$ls180.v:3028$66_Y + assign $0\main_sdram_inti_p0_we_n[0:0] $not$ls180.v:3029$67_Y + assign $0\main_sdram_inti_p0_cas_n[0:0] $not$ls180.v:3030$68_Y + assign $0\main_sdram_inti_p0_ras_n[0:0] $not$ls180.v:3031$69_Y + attribute \src "ls180.v:3032.6-3032.10" case assign $0\main_sdram_inti_p0_cs_n[0:0] 1'1 assign $0\main_sdram_inti_p0_we_n[0:0] 1'1 @@ -116026,49 +115977,41 @@ module \ls180 update \main_sdram_inti_p0_ras_n $0\main_sdram_inti_p0_ras_n[0:0] update \main_sdram_inti_p0_we_n $0\main_sdram_inti_p0_we_n[0:0] end - attribute \src "ls180.v:303.12-303.45" - process $proc$ls180.v:303$2868 - assign { } { } - assign $1\main_sdram_wrdata_storage[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdram_wrdata_storage $1\main_sdram_wrdata_storage[15:0] - end - attribute \src "ls180.v:304.5-304.32" - process $proc$ls180.v:304$2869 + attribute \src "ls180.v:303.5-303.32" + process $proc$ls180.v:303$2866 assign { } { } assign $1\main_sdram_wrdata_re[0:0] 1'0 sync always sync init update \main_sdram_wrdata_re $1\main_sdram_wrdata_re[0:0] end - attribute \src "ls180.v:305.12-305.37" - process $proc$ls180.v:305$2870 + attribute \src "ls180.v:304.12-304.37" + process $proc$ls180.v:304$2867 assign { } { } assign $1\main_sdram_status[15:0] 16'0000000000000000 sync always sync init update \main_sdram_status $1\main_sdram_status[15:0] end - attribute \src "ls180.v:3085.1-3115.4" - process $proc$ls180.v:3085$79 + attribute \src "ls180.v:3081.1-3111.4" + process $proc$ls180.v:3081$78 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\main_sdram_cmd_valid[0:0] 1'0 assign { } { } assign $0\main_sdram_cmd_last[0:0] 1'0 assign $0\main_sdram_sequencer_start0[0:0] 1'0 + assign $0\main_sdram_cmd_valid[0:0] 1'0 assign $0\builder_refresher_next_state[1:0] \builder_refresher_state - attribute \src "ls180.v:3091.2-3114.9" + attribute \src "ls180.v:3087.2-3110.9" switch \builder_refresher_state attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\main_sdram_cmd_valid[0:0] 1'1 - attribute \src "ls180.v:3094.4-3097.7" + attribute \src "ls180.v:3090.4-3093.7" switch \main_sdram_cmd_ready - attribute \src "ls180.v:3094.8-3094.28" + attribute \src "ls180.v:3090.8-3090.28" case 1'1 assign $0\main_sdram_sequencer_start0[0:0] 1'1 assign $0\builder_refresher_next_state[1:0] 2'10 @@ -116077,9 +116020,9 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 2'10 assign $0\main_sdram_cmd_valid[0:0] 1'1 - attribute \src "ls180.v:3101.4-3105.7" + attribute \src "ls180.v:3097.4-3101.7" switch \main_sdram_sequencer_done0 - attribute \src "ls180.v:3101.8-3101.34" + attribute \src "ls180.v:3097.8-3097.34" case 1'1 assign $0\main_sdram_cmd_valid[0:0] 1'0 assign $0\main_sdram_cmd_last[0:0] 1'1 @@ -116088,13 +116031,13 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case - attribute \src "ls180.v:3108.4-3112.7" + attribute \src "ls180.v:3104.4-3108.7" switch 1'1 - attribute \src "ls180.v:3108.8-3108.12" + attribute \src "ls180.v:3104.8-3104.12" case 1'1 - attribute \src "ls180.v:3109.5-3111.8" + attribute \src "ls180.v:3105.5-3107.8" switch \main_sdram_wants_refresh - attribute \src "ls180.v:3109.9-3109.33" + attribute \src "ls180.v:3105.9-3105.33" case 1'1 assign $0\builder_refresher_next_state[1:0] 2'01 case @@ -116108,35 +116051,35 @@ module \ls180 update \main_sdram_sequencer_start0 $0\main_sdram_sequencer_start0[0:0] update \builder_refresher_next_state $0\builder_refresher_next_state[1:0] end - attribute \src "ls180.v:3130.1-3137.4" - process $proc$ls180.v:3130$83 + attribute \src "ls180.v:3126.1-3133.4" + process $proc$ls180.v:3126$82 assign { } { } assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000 - attribute \src "ls180.v:3132.2-3136.5" + attribute \src "ls180.v:3128.2-3132.5" switch \main_sdram_bankmachine0_row_col_n_addr_sel - attribute \src "ls180.v:3132.6-3132.48" + attribute \src "ls180.v:3128.6-3128.48" case 1'1 assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] - attribute \src "ls180.v:3134.6-3134.10" + attribute \src "ls180.v:3130.6-3130.10" case - assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] $or$ls180.v:3135$85_Y + assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] $or$ls180.v:3131$84_Y end sync always update \main_sdram_bankmachine0_cmd_payload_a $0\main_sdram_bankmachine0_cmd_payload_a[12:0] end - attribute \src "ls180.v:3141.1-3148.4" - process $proc$ls180.v:3141$92 + attribute \src "ls180.v:3137.1-3144.4" + process $proc$ls180.v:3137$91 assign { } { } assign $0\main_sdram_bankmachine0_auto_precharge[0:0] 1'0 - attribute \src "ls180.v:3143.2-3147.5" - switch $and$ls180.v:3143$93_Y - attribute \src "ls180.v:3143.6-3143.115" + attribute \src "ls180.v:3139.2-3143.5" + switch $and$ls180.v:3139$92_Y + attribute \src "ls180.v:3139.6-3139.115" case 1'1 - attribute \src "ls180.v:3144.3-3146.6" - switch $ne$ls180.v:3144$94_Y - attribute \src "ls180.v:3144.7-3144.143" + attribute \src "ls180.v:3140.3-3142.6" + switch $ne$ls180.v:3140$93_Y + attribute \src "ls180.v:3140.7-3140.143" case 1'1 - assign $0\main_sdram_bankmachine0_auto_precharge[0:0] $eq$ls180.v:3145$95_Y + assign $0\main_sdram_bankmachine0_auto_precharge[0:0] $eq$ls180.v:3141$94_Y case end case @@ -116144,24 +116087,25 @@ module \ls180 sync always update \main_sdram_bankmachine0_auto_precharge $0\main_sdram_bankmachine0_auto_precharge[0:0] end - attribute \src "ls180.v:3163.1-3170.4" - process $proc$ls180.v:3163$96 + attribute \src "ls180.v:3159.1-3166.4" + process $proc$ls180.v:3159$95 assign { } { } assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - attribute \src "ls180.v:3165.2-3169.5" + attribute \src "ls180.v:3161.2-3165.5" switch \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - attribute \src "ls180.v:3165.6-3165.58" + attribute \src "ls180.v:3161.6-3161.58" case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3166$97_Y - attribute \src "ls180.v:3167.6-3167.10" + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3162$96_Y + attribute \src "ls180.v:3163.6-3163.10" case assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_produce end sync always update \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "ls180.v:3179.1-3272.4" - process $proc$ls180.v:3179$105 + attribute \src "ls180.v:3175.1-3268.4" + process $proc$ls180.v:3175$104 + assign { } { } assign { } { } assign { } { } assign { } { } @@ -116176,10 +116120,8 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'0 assign $0\main_sdram_bankmachine0_row_open[0:0] 1'0 assign $0\main_sdram_bankmachine0_row_close[0:0] 1'0 - assign { } { } assign $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0 assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0 assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0 @@ -116190,23 +116132,24 @@ module \ls180 assign $0\main_sdram_bankmachine0_req_wdata_ready[0:0] 1'0 assign $0\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0 assign $0\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'0 assign $0\builder_bankmachine0_next_state[2:0] \builder_bankmachine0_state - attribute \src "ls180.v:3195.2-3271.9" + attribute \src "ls180.v:3191.2-3267.9" switch \builder_bankmachine0_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 - attribute \src "ls180.v:3197.4-3205.7" - switch $and$ls180.v:3197$106_Y - attribute \src "ls180.v:3197.8-3197.87" + attribute \src "ls180.v:3193.4-3201.7" + switch $and$ls180.v:3193$105_Y + attribute \src "ls180.v:3193.8-3193.87" case 1'1 assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'1 assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'1 assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3199.5-3201.8" + attribute \src "ls180.v:3195.5-3197.8" switch \main_sdram_bankmachine0_cmd_ready - attribute \src "ls180.v:3199.9-3199.42" + attribute \src "ls180.v:3195.9-3195.42" case 1'1 assign $0\builder_bankmachine0_next_state[2:0] 3'101 case @@ -116216,27 +116159,27 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'010 assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 - attribute \src "ls180.v:3209.4-3211.7" - switch $and$ls180.v:3209$107_Y - attribute \src "ls180.v:3209.8-3209.87" + attribute \src "ls180.v:3205.4-3207.7" + switch $and$ls180.v:3205$106_Y + attribute \src "ls180.v:3205.8-3205.87" case 1'1 assign $0\builder_bankmachine0_next_state[2:0] 3'101 case end attribute \src "ls180.v:0.0-0.0" case 3'011 - attribute \src "ls180.v:3215.4-3224.7" + attribute \src "ls180.v:3211.4-3220.7" switch \main_sdram_bankmachine0_trccon_ready - attribute \src "ls180.v:3215.8-3215.44" + attribute \src "ls180.v:3211.8-3211.44" case 1'1 assign $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'1 assign $0\main_sdram_bankmachine0_row_open[0:0] 1'1 assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'1 - attribute \src "ls180.v:3220.5-3222.8" + attribute \src "ls180.v:3216.5-3218.8" switch \main_sdram_bankmachine0_cmd_ready - attribute \src "ls180.v:3220.9-3220.42" + attribute \src "ls180.v:3216.9-3216.42" case 1'1 assign $0\builder_bankmachine0_next_state[2:0] 3'110 case @@ -116247,16 +116190,16 @@ module \ls180 case 3'100 assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3227.4-3229.7" + attribute \src "ls180.v:3223.4-3225.7" switch \main_sdram_bankmachine0_twtpcon_ready - attribute \src "ls180.v:3227.8-3227.45" + attribute \src "ls180.v:3223.8-3223.45" case 1'1 assign $0\main_sdram_bankmachine0_refresh_gnt[0:0] 1'1 case end - attribute \src "ls180.v:3232.4-3234.7" - switch $not$ls180.v:3232$108_Y - attribute \src "ls180.v:3232.8-3232.46" + attribute \src "ls180.v:3228.4-3230.7" + switch $not$ls180.v:3228$107_Y + attribute \src "ls180.v:3228.8-3228.46" case 1'1 assign $0\builder_bankmachine0_next_state[2:0] 3'000 case @@ -116269,51 +116212,51 @@ module \ls180 assign $0\builder_bankmachine0_next_state[2:0] 3'000 attribute \src "ls180.v:0.0-0.0" case - attribute \src "ls180.v:3243.4-3269.7" + attribute \src "ls180.v:3239.4-3265.7" switch \main_sdram_bankmachine0_refresh_req - attribute \src "ls180.v:3243.8-3243.43" + attribute \src "ls180.v:3239.8-3239.43" case 1'1 assign $0\builder_bankmachine0_next_state[2:0] 3'100 - attribute \src "ls180.v:3245.8-3245.12" + attribute \src "ls180.v:3241.8-3241.12" case - attribute \src "ls180.v:3246.5-3268.8" + attribute \src "ls180.v:3242.5-3264.8" switch \main_sdram_bankmachine0_cmd_buffer_source_valid - attribute \src "ls180.v:3246.9-3246.56" + attribute \src "ls180.v:3242.9-3242.56" case 1'1 - attribute \src "ls180.v:3247.6-3267.9" + attribute \src "ls180.v:3243.6-3263.9" switch \main_sdram_bankmachine0_row_opened - attribute \src "ls180.v:3247.10-3247.44" + attribute \src "ls180.v:3243.10-3243.44" case 1'1 - attribute \src "ls180.v:3248.7-3264.10" + attribute \src "ls180.v:3244.7-3260.10" switch \main_sdram_bankmachine0_row_hit - attribute \src "ls180.v:3248.11-3248.42" + attribute \src "ls180.v:3244.11-3244.42" case 1'1 assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'1 - attribute \src "ls180.v:3250.8-3257.11" + attribute \src "ls180.v:3246.8-3253.11" switch \main_sdram_bankmachine0_cmd_buffer_source_payload_we - attribute \src "ls180.v:3250.12-3250.64" + attribute \src "ls180.v:3246.12-3246.64" case 1'1 assign $0\main_sdram_bankmachine0_req_wdata_ready[0:0] \main_sdram_bankmachine0_cmd_ready assign $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'1 assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'1 - attribute \src "ls180.v:3254.12-3254.16" + attribute \src "ls180.v:3250.12-3250.16" case assign $0\main_sdram_bankmachine0_req_rdata_valid[0:0] \main_sdram_bankmachine0_cmd_ready assign $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'1 end - attribute \src "ls180.v:3259.8-3261.11" - switch $and$ls180.v:3259$109_Y - attribute \src "ls180.v:3259.12-3259.88" + attribute \src "ls180.v:3255.8-3257.11" + switch $and$ls180.v:3255$108_Y + attribute \src "ls180.v:3255.12-3255.88" case 1'1 assign $0\builder_bankmachine0_next_state[2:0] 3'010 case end - attribute \src "ls180.v:3262.11-3262.15" + attribute \src "ls180.v:3258.11-3258.15" case assign $0\builder_bankmachine0_next_state[2:0] 3'001 end - attribute \src "ls180.v:3265.10-3265.14" + attribute \src "ls180.v:3261.10-3261.14" case assign $0\builder_bankmachine0_next_state[2:0] 3'011 end @@ -116337,35 +116280,35 @@ module \ls180 update \main_sdram_bankmachine0_row_col_n_addr_sel $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] update \builder_bankmachine0_next_state $0\builder_bankmachine0_next_state[2:0] end - attribute \src "ls180.v:3287.1-3294.4" - process $proc$ls180.v:3287$113 + attribute \src "ls180.v:3283.1-3290.4" + process $proc$ls180.v:3283$112 assign { } { } assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000 - attribute \src "ls180.v:3289.2-3293.5" + attribute \src "ls180.v:3285.2-3289.5" switch \main_sdram_bankmachine1_row_col_n_addr_sel - attribute \src "ls180.v:3289.6-3289.48" + attribute \src "ls180.v:3285.6-3285.48" case 1'1 assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] - attribute \src "ls180.v:3291.6-3291.10" + attribute \src "ls180.v:3287.6-3287.10" case - assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] $or$ls180.v:3292$115_Y + assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] $or$ls180.v:3288$114_Y end sync always update \main_sdram_bankmachine1_cmd_payload_a $0\main_sdram_bankmachine1_cmd_payload_a[12:0] end - attribute \src "ls180.v:3298.1-3305.4" - process $proc$ls180.v:3298$122 + attribute \src "ls180.v:3294.1-3301.4" + process $proc$ls180.v:3294$121 assign { } { } assign $0\main_sdram_bankmachine1_auto_precharge[0:0] 1'0 - attribute \src "ls180.v:3300.2-3304.5" - switch $and$ls180.v:3300$123_Y - attribute \src "ls180.v:3300.6-3300.115" + attribute \src "ls180.v:3296.2-3300.5" + switch $and$ls180.v:3296$122_Y + attribute \src "ls180.v:3296.6-3296.115" case 1'1 - attribute \src "ls180.v:3301.3-3303.6" - switch $ne$ls180.v:3301$124_Y - attribute \src "ls180.v:3301.7-3301.143" + attribute \src "ls180.v:3297.3-3299.6" + switch $ne$ls180.v:3297$123_Y + attribute \src "ls180.v:3297.7-3297.143" case 1'1 - assign $0\main_sdram_bankmachine1_auto_precharge[0:0] $eq$ls180.v:3302$125_Y + assign $0\main_sdram_bankmachine1_auto_precharge[0:0] $eq$ls180.v:3298$124_Y case end case @@ -116373,24 +116316,24 @@ module \ls180 sync always update \main_sdram_bankmachine1_auto_precharge $0\main_sdram_bankmachine1_auto_precharge[0:0] end - attribute \src "ls180.v:3320.1-3327.4" - process $proc$ls180.v:3320$126 + attribute \src "ls180.v:3316.1-3323.4" + process $proc$ls180.v:3316$125 assign { } { } assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - attribute \src "ls180.v:3322.2-3326.5" + attribute \src "ls180.v:3318.2-3322.5" switch \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - attribute \src "ls180.v:3322.6-3322.58" + attribute \src "ls180.v:3318.6-3318.58" case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3323$127_Y - attribute \src "ls180.v:3324.6-3324.10" + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3319$126_Y + attribute \src "ls180.v:3320.6-3320.10" case assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_produce end sync always update \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "ls180.v:3336.1-3429.4" - process $proc$ls180.v:3336$135 + attribute \src "ls180.v:3332.1-3425.4" + process $proc$ls180.v:3332$134 assign { } { } assign { } { } assign { } { } @@ -116405,37 +116348,37 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0 assign $0\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0 - assign { } { } assign $0\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0 assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'0 assign $0\main_sdram_bankmachine1_row_open[0:0] 1'0 assign $0\main_sdram_bankmachine1_row_close[0:0] 1'0 - assign $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0 assign $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'0 assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'0 assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'0 + assign $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0 assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0 assign $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0 assign $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0 + assign $0\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0 + assign { } { } assign $0\builder_bankmachine1_next_state[2:0] \builder_bankmachine1_state - attribute \src "ls180.v:3352.2-3428.9" + attribute \src "ls180.v:3348.2-3424.9" switch \builder_bankmachine1_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 - attribute \src "ls180.v:3354.4-3362.7" - switch $and$ls180.v:3354$136_Y - attribute \src "ls180.v:3354.8-3354.87" + attribute \src "ls180.v:3350.4-3358.7" + switch $and$ls180.v:3350$135_Y + attribute \src "ls180.v:3350.8-3350.87" case 1'1 assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'1 assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'1 assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3356.5-3358.8" + attribute \src "ls180.v:3352.5-3354.8" switch \main_sdram_bankmachine1_cmd_ready - attribute \src "ls180.v:3356.9-3356.42" + attribute \src "ls180.v:3352.9-3352.42" case 1'1 assign $0\builder_bankmachine1_next_state[2:0] 3'101 case @@ -116445,27 +116388,27 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'010 assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 - attribute \src "ls180.v:3366.4-3368.7" - switch $and$ls180.v:3366$137_Y - attribute \src "ls180.v:3366.8-3366.87" + attribute \src "ls180.v:3362.4-3364.7" + switch $and$ls180.v:3362$136_Y + attribute \src "ls180.v:3362.8-3362.87" case 1'1 assign $0\builder_bankmachine1_next_state[2:0] 3'101 case end attribute \src "ls180.v:0.0-0.0" case 3'011 - attribute \src "ls180.v:3372.4-3381.7" + attribute \src "ls180.v:3368.4-3377.7" switch \main_sdram_bankmachine1_trccon_ready - attribute \src "ls180.v:3372.8-3372.44" + attribute \src "ls180.v:3368.8-3368.44" case 1'1 assign $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'1 assign $0\main_sdram_bankmachine1_row_open[0:0] 1'1 assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'1 - attribute \src "ls180.v:3377.5-3379.8" + attribute \src "ls180.v:3373.5-3375.8" switch \main_sdram_bankmachine1_cmd_ready - attribute \src "ls180.v:3377.9-3377.42" + attribute \src "ls180.v:3373.9-3373.42" case 1'1 assign $0\builder_bankmachine1_next_state[2:0] 3'110 case @@ -116476,16 +116419,16 @@ module \ls180 case 3'100 assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3384.4-3386.7" + attribute \src "ls180.v:3380.4-3382.7" switch \main_sdram_bankmachine1_twtpcon_ready - attribute \src "ls180.v:3384.8-3384.45" + attribute \src "ls180.v:3380.8-3380.45" case 1'1 assign $0\main_sdram_bankmachine1_refresh_gnt[0:0] 1'1 case end - attribute \src "ls180.v:3389.4-3391.7" - switch $not$ls180.v:3389$138_Y - attribute \src "ls180.v:3389.8-3389.46" + attribute \src "ls180.v:3385.4-3387.7" + switch $not$ls180.v:3385$137_Y + attribute \src "ls180.v:3385.8-3385.46" case 1'1 assign $0\builder_bankmachine1_next_state[2:0] 3'000 case @@ -116498,51 +116441,51 @@ module \ls180 assign $0\builder_bankmachine1_next_state[2:0] 3'000 attribute \src "ls180.v:0.0-0.0" case - attribute \src "ls180.v:3400.4-3426.7" + attribute \src "ls180.v:3396.4-3422.7" switch \main_sdram_bankmachine1_refresh_req - attribute \src "ls180.v:3400.8-3400.43" + attribute \src "ls180.v:3396.8-3396.43" case 1'1 assign $0\builder_bankmachine1_next_state[2:0] 3'100 - attribute \src "ls180.v:3402.8-3402.12" + attribute \src "ls180.v:3398.8-3398.12" case - attribute \src "ls180.v:3403.5-3425.8" + attribute \src "ls180.v:3399.5-3421.8" switch \main_sdram_bankmachine1_cmd_buffer_source_valid - attribute \src "ls180.v:3403.9-3403.56" + attribute \src "ls180.v:3399.9-3399.56" case 1'1 - attribute \src "ls180.v:3404.6-3424.9" + attribute \src "ls180.v:3400.6-3420.9" switch \main_sdram_bankmachine1_row_opened - attribute \src "ls180.v:3404.10-3404.44" + attribute \src "ls180.v:3400.10-3400.44" case 1'1 - attribute \src "ls180.v:3405.7-3421.10" + attribute \src "ls180.v:3401.7-3417.10" switch \main_sdram_bankmachine1_row_hit - attribute \src "ls180.v:3405.11-3405.42" + attribute \src "ls180.v:3401.11-3401.42" case 1'1 assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'1 - attribute \src "ls180.v:3407.8-3414.11" + attribute \src "ls180.v:3403.8-3410.11" switch \main_sdram_bankmachine1_cmd_buffer_source_payload_we - attribute \src "ls180.v:3407.12-3407.64" + attribute \src "ls180.v:3403.12-3403.64" case 1'1 assign $0\main_sdram_bankmachine1_req_wdata_ready[0:0] \main_sdram_bankmachine1_cmd_ready assign $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'1 assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'1 - attribute \src "ls180.v:3411.12-3411.16" + attribute \src "ls180.v:3407.12-3407.16" case assign $0\main_sdram_bankmachine1_req_rdata_valid[0:0] \main_sdram_bankmachine1_cmd_ready assign $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'1 end - attribute \src "ls180.v:3416.8-3418.11" - switch $and$ls180.v:3416$139_Y - attribute \src "ls180.v:3416.12-3416.88" + attribute \src "ls180.v:3412.8-3414.11" + switch $and$ls180.v:3412$138_Y + attribute \src "ls180.v:3412.12-3412.88" case 1'1 assign $0\builder_bankmachine1_next_state[2:0] 3'010 case end - attribute \src "ls180.v:3419.11-3419.15" + attribute \src "ls180.v:3415.11-3415.15" case assign $0\builder_bankmachine1_next_state[2:0] 3'001 end - attribute \src "ls180.v:3422.10-3422.14" + attribute \src "ls180.v:3418.10-3418.14" case assign $0\builder_bankmachine1_next_state[2:0] 3'011 end @@ -116566,99 +116509,99 @@ module \ls180 update \main_sdram_bankmachine1_row_col_n_addr_sel $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] update \builder_bankmachine1_next_state $0\builder_bankmachine1_next_state[2:0] end - attribute \src "ls180.v:335.12-335.46" - process $proc$ls180.v:335$2871 + attribute \src "ls180.v:334.12-334.46" + process $proc$ls180.v:334$2868 assign { } { } assign $1\main_sdram_interface_wdata[15:0] 16'0000000000000000 sync always sync init update \main_sdram_interface_wdata $1\main_sdram_interface_wdata[15:0] end - attribute \src "ls180.v:336.11-336.47" - process $proc$ls180.v:336$2872 + attribute \src "ls180.v:335.11-335.47" + process $proc$ls180.v:335$2869 assign { } { } assign $1\main_sdram_interface_wdata_we[1:0] 2'00 sync always sync init update \main_sdram_interface_wdata_we $1\main_sdram_interface_wdata_we[1:0] end - attribute \src "ls180.v:338.12-338.45" - process $proc$ls180.v:338$2873 + attribute \src "ls180.v:337.12-337.45" + process $proc$ls180.v:337$2870 assign { } { } assign $1\main_sdram_dfi_p0_address[12:0] 13'0000000000000 sync always sync init update \main_sdram_dfi_p0_address $1\main_sdram_dfi_p0_address[12:0] end - attribute \src "ls180.v:339.11-339.40" - process $proc$ls180.v:339$2874 + attribute \src "ls180.v:338.11-338.40" + process $proc$ls180.v:338$2871 assign { } { } assign $1\main_sdram_dfi_p0_bank[1:0] 2'00 sync always sync init update \main_sdram_dfi_p0_bank $1\main_sdram_dfi_p0_bank[1:0] end - attribute \src "ls180.v:340.5-340.35" - process $proc$ls180.v:340$2875 + attribute \src "ls180.v:339.5-339.35" + process $proc$ls180.v:339$2872 assign { } { } assign $1\main_sdram_dfi_p0_cas_n[0:0] 1'1 sync always sync init update \main_sdram_dfi_p0_cas_n $1\main_sdram_dfi_p0_cas_n[0:0] end - attribute \src "ls180.v:341.5-341.34" - process $proc$ls180.v:341$2876 + attribute \src "ls180.v:340.5-340.34" + process $proc$ls180.v:340$2873 assign { } { } assign $1\main_sdram_dfi_p0_cs_n[0:0] 1'1 sync always sync init update \main_sdram_dfi_p0_cs_n $1\main_sdram_dfi_p0_cs_n[0:0] end - attribute \src "ls180.v:342.5-342.35" - process $proc$ls180.v:342$2877 + attribute \src "ls180.v:341.5-341.35" + process $proc$ls180.v:341$2874 assign { } { } assign $1\main_sdram_dfi_p0_ras_n[0:0] 1'1 sync always sync init update \main_sdram_dfi_p0_ras_n $1\main_sdram_dfi_p0_ras_n[0:0] end - attribute \src "ls180.v:343.5-343.34" - process $proc$ls180.v:343$2878 + attribute \src "ls180.v:342.5-342.34" + process $proc$ls180.v:342$2875 assign { } { } assign $1\main_sdram_dfi_p0_we_n[0:0] 1'1 sync always sync init update \main_sdram_dfi_p0_we_n $1\main_sdram_dfi_p0_we_n[0:0] end - attribute \src "ls180.v:3444.1-3451.4" - process $proc$ls180.v:3444$143 + attribute \src "ls180.v:3440.1-3447.4" + process $proc$ls180.v:3440$142 assign { } { } assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000 - attribute \src "ls180.v:3446.2-3450.5" + attribute \src "ls180.v:3442.2-3446.5" switch \main_sdram_bankmachine2_row_col_n_addr_sel - attribute \src "ls180.v:3446.6-3446.48" + attribute \src "ls180.v:3442.6-3442.48" case 1'1 assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] - attribute \src "ls180.v:3448.6-3448.10" + attribute \src "ls180.v:3444.6-3444.10" case - assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] $or$ls180.v:3449$145_Y + assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] $or$ls180.v:3445$144_Y end sync always update \main_sdram_bankmachine2_cmd_payload_a $0\main_sdram_bankmachine2_cmd_payload_a[12:0] end - attribute \src "ls180.v:3455.1-3462.4" - process $proc$ls180.v:3455$152 + attribute \src "ls180.v:3451.1-3458.4" + process $proc$ls180.v:3451$151 assign { } { } assign $0\main_sdram_bankmachine2_auto_precharge[0:0] 1'0 - attribute \src "ls180.v:3457.2-3461.5" - switch $and$ls180.v:3457$153_Y - attribute \src "ls180.v:3457.6-3457.115" + attribute \src "ls180.v:3453.2-3457.5" + switch $and$ls180.v:3453$152_Y + attribute \src "ls180.v:3453.6-3453.115" case 1'1 - attribute \src "ls180.v:3458.3-3460.6" - switch $ne$ls180.v:3458$154_Y - attribute \src "ls180.v:3458.7-3458.143" + attribute \src "ls180.v:3454.3-3456.6" + switch $ne$ls180.v:3454$153_Y + attribute \src "ls180.v:3454.7-3454.143" case 1'1 - assign $0\main_sdram_bankmachine2_auto_precharge[0:0] $eq$ls180.v:3459$155_Y + assign $0\main_sdram_bankmachine2_auto_precharge[0:0] $eq$ls180.v:3455$154_Y case end case @@ -116666,40 +116609,40 @@ module \ls180 sync always update \main_sdram_bankmachine2_auto_precharge $0\main_sdram_bankmachine2_auto_precharge[0:0] end - attribute \src "ls180.v:347.5-347.35" - process $proc$ls180.v:347$2879 + attribute \src "ls180.v:346.5-346.35" + process $proc$ls180.v:346$2876 assign { } { } assign $0\main_sdram_dfi_p0_act_n[0:0] 1'1 sync always update \main_sdram_dfi_p0_act_n $0\main_sdram_dfi_p0_act_n[0:0] sync init end - attribute \src "ls180.v:3477.1-3484.4" - process $proc$ls180.v:3477$156 + attribute \src "ls180.v:3473.1-3480.4" + process $proc$ls180.v:3473$155 assign { } { } assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - attribute \src "ls180.v:3479.2-3483.5" + attribute \src "ls180.v:3475.2-3479.5" switch \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - attribute \src "ls180.v:3479.6-3479.58" + attribute \src "ls180.v:3475.6-3475.58" case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3480$157_Y - attribute \src "ls180.v:3481.6-3481.10" + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3476$156_Y + attribute \src "ls180.v:3477.6-3477.10" case assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_produce end sync always update \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "ls180.v:349.5-349.39" - process $proc$ls180.v:349$2880 + attribute \src "ls180.v:348.5-348.39" + process $proc$ls180.v:348$2877 assign { } { } assign $1\main_sdram_dfi_p0_wrdata_en[0:0] 1'0 sync always sync init update \main_sdram_dfi_p0_wrdata_en $1\main_sdram_dfi_p0_wrdata_en[0:0] end - attribute \src "ls180.v:3493.1-3586.4" - process $proc$ls180.v:3493$165 + attribute \src "ls180.v:3489.1-3582.4" + process $proc$ls180.v:3489$164 assign { } { } assign { } { } assign { } { } @@ -116714,37 +116657,37 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0 - assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 - assign { } { } - assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0 - assign $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 assign $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 assign $0\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 assign $0\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0 assign $0\main_sdram_bankmachine2_refresh_gnt[0:0] 1'0 assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'0 assign $0\main_sdram_bankmachine2_row_open[0:0] 1'0 assign $0\main_sdram_bankmachine2_row_close[0:0] 1'0 - assign $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'0 assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'0 + assign { } { } + assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 assign $0\builder_bankmachine2_next_state[2:0] \builder_bankmachine2_state - attribute \src "ls180.v:3509.2-3585.9" + attribute \src "ls180.v:3505.2-3581.9" switch \builder_bankmachine2_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 - attribute \src "ls180.v:3511.4-3519.7" - switch $and$ls180.v:3511$166_Y - attribute \src "ls180.v:3511.8-3511.87" + attribute \src "ls180.v:3507.4-3515.7" + switch $and$ls180.v:3507$165_Y + attribute \src "ls180.v:3507.8-3507.87" case 1'1 assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'1 assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'1 assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3513.5-3515.8" + attribute \src "ls180.v:3509.5-3511.8" switch \main_sdram_bankmachine2_cmd_ready - attribute \src "ls180.v:3513.9-3513.42" + attribute \src "ls180.v:3509.9-3509.42" case 1'1 assign $0\builder_bankmachine2_next_state[2:0] 3'101 case @@ -116754,27 +116697,27 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'010 assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 - attribute \src "ls180.v:3523.4-3525.7" - switch $and$ls180.v:3523$167_Y - attribute \src "ls180.v:3523.8-3523.87" + attribute \src "ls180.v:3519.4-3521.7" + switch $and$ls180.v:3519$166_Y + attribute \src "ls180.v:3519.8-3519.87" case 1'1 assign $0\builder_bankmachine2_next_state[2:0] 3'101 case end attribute \src "ls180.v:0.0-0.0" case 3'011 - attribute \src "ls180.v:3529.4-3538.7" + attribute \src "ls180.v:3525.4-3534.7" switch \main_sdram_bankmachine2_trccon_ready - attribute \src "ls180.v:3529.8-3529.44" + attribute \src "ls180.v:3525.8-3525.44" case 1'1 assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'1 assign $0\main_sdram_bankmachine2_row_open[0:0] 1'1 assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'1 - attribute \src "ls180.v:3534.5-3536.8" + attribute \src "ls180.v:3530.5-3532.8" switch \main_sdram_bankmachine2_cmd_ready - attribute \src "ls180.v:3534.9-3534.42" + attribute \src "ls180.v:3530.9-3530.42" case 1'1 assign $0\builder_bankmachine2_next_state[2:0] 3'110 case @@ -116785,16 +116728,16 @@ module \ls180 case 3'100 assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3541.4-3543.7" + attribute \src "ls180.v:3537.4-3539.7" switch \main_sdram_bankmachine2_twtpcon_ready - attribute \src "ls180.v:3541.8-3541.45" + attribute \src "ls180.v:3537.8-3537.45" case 1'1 assign $0\main_sdram_bankmachine2_refresh_gnt[0:0] 1'1 case end - attribute \src "ls180.v:3546.4-3548.7" - switch $not$ls180.v:3546$168_Y - attribute \src "ls180.v:3546.8-3546.46" + attribute \src "ls180.v:3542.4-3544.7" + switch $not$ls180.v:3542$167_Y + attribute \src "ls180.v:3542.8-3542.46" case 1'1 assign $0\builder_bankmachine2_next_state[2:0] 3'000 case @@ -116807,51 +116750,51 @@ module \ls180 assign $0\builder_bankmachine2_next_state[2:0] 3'000 attribute \src "ls180.v:0.0-0.0" case - attribute \src "ls180.v:3557.4-3583.7" + attribute \src "ls180.v:3553.4-3579.7" switch \main_sdram_bankmachine2_refresh_req - attribute \src "ls180.v:3557.8-3557.43" + attribute \src "ls180.v:3553.8-3553.43" case 1'1 assign $0\builder_bankmachine2_next_state[2:0] 3'100 - attribute \src "ls180.v:3559.8-3559.12" + attribute \src "ls180.v:3555.8-3555.12" case - attribute \src "ls180.v:3560.5-3582.8" + attribute \src "ls180.v:3556.5-3578.8" switch \main_sdram_bankmachine2_cmd_buffer_source_valid - attribute \src "ls180.v:3560.9-3560.56" + attribute \src "ls180.v:3556.9-3556.56" case 1'1 - attribute \src "ls180.v:3561.6-3581.9" + attribute \src "ls180.v:3557.6-3577.9" switch \main_sdram_bankmachine2_row_opened - attribute \src "ls180.v:3561.10-3561.44" + attribute \src "ls180.v:3557.10-3557.44" case 1'1 - attribute \src "ls180.v:3562.7-3578.10" + attribute \src "ls180.v:3558.7-3574.10" switch \main_sdram_bankmachine2_row_hit - attribute \src "ls180.v:3562.11-3562.42" + attribute \src "ls180.v:3558.11-3558.42" case 1'1 assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'1 - attribute \src "ls180.v:3564.8-3571.11" + attribute \src "ls180.v:3560.8-3567.11" switch \main_sdram_bankmachine2_cmd_buffer_source_payload_we - attribute \src "ls180.v:3564.12-3564.64" + attribute \src "ls180.v:3560.12-3560.64" case 1'1 assign $0\main_sdram_bankmachine2_req_wdata_ready[0:0] \main_sdram_bankmachine2_cmd_ready assign $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'1 assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'1 - attribute \src "ls180.v:3568.12-3568.16" + attribute \src "ls180.v:3564.12-3564.16" case assign $0\main_sdram_bankmachine2_req_rdata_valid[0:0] \main_sdram_bankmachine2_cmd_ready assign $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'1 end - attribute \src "ls180.v:3573.8-3575.11" - switch $and$ls180.v:3573$169_Y - attribute \src "ls180.v:3573.12-3573.88" + attribute \src "ls180.v:3569.8-3571.11" + switch $and$ls180.v:3569$168_Y + attribute \src "ls180.v:3569.12-3569.88" case 1'1 assign $0\builder_bankmachine2_next_state[2:0] 3'010 case end - attribute \src "ls180.v:3576.11-3576.15" + attribute \src "ls180.v:3572.11-3572.15" case assign $0\builder_bankmachine2_next_state[2:0] 3'001 end - attribute \src "ls180.v:3579.10-3579.14" + attribute \src "ls180.v:3575.10-3575.14" case assign $0\builder_bankmachine2_next_state[2:0] 3'011 end @@ -116875,107 +116818,107 @@ module \ls180 update \main_sdram_bankmachine2_row_col_n_addr_sel $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] update \builder_bankmachine2_next_state $0\builder_bankmachine2_next_state[2:0] end - attribute \src "ls180.v:351.5-351.39" - process $proc$ls180.v:351$2881 + attribute \src "ls180.v:350.5-350.39" + process $proc$ls180.v:350$2878 assign { } { } assign $1\main_sdram_dfi_p0_rddata_en[0:0] 1'0 sync always sync init update \main_sdram_dfi_p0_rddata_en $1\main_sdram_dfi_p0_rddata_en[0:0] end - attribute \src "ls180.v:354.5-354.32" - process $proc$ls180.v:354$2882 + attribute \src "ls180.v:353.5-353.32" + process $proc$ls180.v:353$2879 assign { } { } assign $1\main_sdram_cmd_valid[0:0] 1'0 sync always sync init update \main_sdram_cmd_valid $1\main_sdram_cmd_valid[0:0] end - attribute \src "ls180.v:355.5-355.32" - process $proc$ls180.v:355$2883 + attribute \src "ls180.v:354.5-354.32" + process $proc$ls180.v:354$2880 assign { } { } assign $1\main_sdram_cmd_ready[0:0] 1'0 sync always sync init update \main_sdram_cmd_ready $1\main_sdram_cmd_ready[0:0] end - attribute \src "ls180.v:356.5-356.31" - process $proc$ls180.v:356$2884 + attribute \src "ls180.v:355.5-355.31" + process $proc$ls180.v:355$2881 assign { } { } assign $1\main_sdram_cmd_last[0:0] 1'0 sync always sync init update \main_sdram_cmd_last $1\main_sdram_cmd_last[0:0] end - attribute \src "ls180.v:357.12-357.44" - process $proc$ls180.v:357$2885 + attribute \src "ls180.v:356.12-356.44" + process $proc$ls180.v:356$2882 assign { } { } assign $1\main_sdram_cmd_payload_a[12:0] 13'0000000000000 sync always sync init update \main_sdram_cmd_payload_a $1\main_sdram_cmd_payload_a[12:0] end - attribute \src "ls180.v:358.11-358.43" - process $proc$ls180.v:358$2886 + attribute \src "ls180.v:357.11-357.43" + process $proc$ls180.v:357$2883 assign { } { } assign $1\main_sdram_cmd_payload_ba[1:0] 2'00 sync always sync init update \main_sdram_cmd_payload_ba $1\main_sdram_cmd_payload_ba[1:0] end - attribute \src "ls180.v:359.5-359.38" - process $proc$ls180.v:359$2887 + attribute \src "ls180.v:358.5-358.38" + process $proc$ls180.v:358$2884 assign { } { } assign $1\main_sdram_cmd_payload_cas[0:0] 1'0 sync always sync init update \main_sdram_cmd_payload_cas $1\main_sdram_cmd_payload_cas[0:0] end - attribute \src "ls180.v:360.5-360.38" - process $proc$ls180.v:360$2888 + attribute \src "ls180.v:359.5-359.38" + process $proc$ls180.v:359$2885 assign { } { } assign $1\main_sdram_cmd_payload_ras[0:0] 1'0 sync always sync init update \main_sdram_cmd_payload_ras $1\main_sdram_cmd_payload_ras[0:0] end - attribute \src "ls180.v:3601.1-3608.4" - process $proc$ls180.v:3601$173 + attribute \src "ls180.v:3597.1-3604.4" + process $proc$ls180.v:3597$172 assign { } { } assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000 - attribute \src "ls180.v:3603.2-3607.5" + attribute \src "ls180.v:3599.2-3603.5" switch \main_sdram_bankmachine3_row_col_n_addr_sel - attribute \src "ls180.v:3603.6-3603.48" + attribute \src "ls180.v:3599.6-3599.48" case 1'1 assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] - attribute \src "ls180.v:3605.6-3605.10" + attribute \src "ls180.v:3601.6-3601.10" case - assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] $or$ls180.v:3606$175_Y + assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] $or$ls180.v:3602$174_Y end sync always update \main_sdram_bankmachine3_cmd_payload_a $0\main_sdram_bankmachine3_cmd_payload_a[12:0] end - attribute \src "ls180.v:361.5-361.37" - process $proc$ls180.v:361$2889 + attribute \src "ls180.v:360.5-360.37" + process $proc$ls180.v:360$2886 assign { } { } assign $1\main_sdram_cmd_payload_we[0:0] 1'0 sync always sync init update \main_sdram_cmd_payload_we $1\main_sdram_cmd_payload_we[0:0] end - attribute \src "ls180.v:3612.1-3619.4" - process $proc$ls180.v:3612$182 + attribute \src "ls180.v:3608.1-3615.4" + process $proc$ls180.v:3608$181 assign { } { } assign $0\main_sdram_bankmachine3_auto_precharge[0:0] 1'0 - attribute \src "ls180.v:3614.2-3618.5" - switch $and$ls180.v:3614$183_Y - attribute \src "ls180.v:3614.6-3614.115" + attribute \src "ls180.v:3610.2-3614.5" + switch $and$ls180.v:3610$182_Y + attribute \src "ls180.v:3610.6-3610.115" case 1'1 - attribute \src "ls180.v:3615.3-3617.6" - switch $ne$ls180.v:3615$184_Y - attribute \src "ls180.v:3615.7-3615.143" + attribute \src "ls180.v:3611.3-3613.6" + switch $ne$ls180.v:3611$183_Y + attribute \src "ls180.v:3611.7-3611.143" case 1'1 - assign $0\main_sdram_bankmachine3_auto_precharge[0:0] $eq$ls180.v:3616$185_Y + assign $0\main_sdram_bankmachine3_auto_precharge[0:0] $eq$ls180.v:3612$184_Y case end case @@ -116983,40 +116926,40 @@ module \ls180 sync always update \main_sdram_bankmachine3_auto_precharge $0\main_sdram_bankmachine3_auto_precharge[0:0] end - attribute \src "ls180.v:362.5-362.42" - process $proc$ls180.v:362$2890 + attribute \src "ls180.v:361.5-361.42" + process $proc$ls180.v:361$2887 assign { } { } assign $0\main_sdram_cmd_payload_is_read[0:0] 1'0 sync always update \main_sdram_cmd_payload_is_read $0\main_sdram_cmd_payload_is_read[0:0] sync init end - attribute \src "ls180.v:363.5-363.43" - process $proc$ls180.v:363$2891 + attribute \src "ls180.v:362.5-362.43" + process $proc$ls180.v:362$2888 assign { } { } assign $0\main_sdram_cmd_payload_is_write[0:0] 1'0 sync always update \main_sdram_cmd_payload_is_write $0\main_sdram_cmd_payload_is_write[0:0] sync init end - attribute \src "ls180.v:3634.1-3641.4" - process $proc$ls180.v:3634$186 + attribute \src "ls180.v:3630.1-3637.4" + process $proc$ls180.v:3630$185 assign { } { } assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - attribute \src "ls180.v:3636.2-3640.5" + attribute \src "ls180.v:3632.2-3636.5" switch \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - attribute \src "ls180.v:3636.6-3636.58" + attribute \src "ls180.v:3632.6-3632.58" case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3637$187_Y - attribute \src "ls180.v:3638.6-3638.10" + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3633$186_Y + attribute \src "ls180.v:3634.6-3634.10" case assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_produce end sync always update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "ls180.v:3650.1-3743.4" - process $proc$ls180.v:3650$195 + attribute \src "ls180.v:3646.1-3739.4" + process $proc$ls180.v:3646$194 assign { } { } assign { } { } assign { } { } @@ -117031,9 +116974,6 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdram_bankmachine3_row_open[0:0] 1'0 - assign $0\main_sdram_bankmachine3_row_close[0:0] 1'0 - assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0 assign $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 @@ -117045,23 +116985,26 @@ module \ls180 assign $0\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0 assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'0 assign { } { } + assign $0\main_sdram_bankmachine3_row_open[0:0] 1'0 + assign $0\main_sdram_bankmachine3_row_close[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 assign $0\builder_bankmachine3_next_state[2:0] \builder_bankmachine3_state - attribute \src "ls180.v:3666.2-3742.9" + attribute \src "ls180.v:3662.2-3738.9" switch \builder_bankmachine3_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 - attribute \src "ls180.v:3668.4-3676.7" - switch $and$ls180.v:3668$196_Y - attribute \src "ls180.v:3668.8-3668.87" + attribute \src "ls180.v:3664.4-3672.7" + switch $and$ls180.v:3664$195_Y + attribute \src "ls180.v:3664.8-3664.87" case 1'1 assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'1 assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'1 assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3670.5-3672.8" + attribute \src "ls180.v:3666.5-3668.8" switch \main_sdram_bankmachine3_cmd_ready - attribute \src "ls180.v:3670.9-3670.42" + attribute \src "ls180.v:3666.9-3666.42" case 1'1 assign $0\builder_bankmachine3_next_state[2:0] 3'101 case @@ -117071,27 +117014,27 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'010 assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 - attribute \src "ls180.v:3680.4-3682.7" - switch $and$ls180.v:3680$197_Y - attribute \src "ls180.v:3680.8-3680.87" + attribute \src "ls180.v:3676.4-3678.7" + switch $and$ls180.v:3676$196_Y + attribute \src "ls180.v:3676.8-3676.87" case 1'1 assign $0\builder_bankmachine3_next_state[2:0] 3'101 case end attribute \src "ls180.v:0.0-0.0" case 3'011 - attribute \src "ls180.v:3686.4-3695.7" + attribute \src "ls180.v:3682.4-3691.7" switch \main_sdram_bankmachine3_trccon_ready - attribute \src "ls180.v:3686.8-3686.44" + attribute \src "ls180.v:3682.8-3682.44" case 1'1 assign $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'1 assign $0\main_sdram_bankmachine3_row_open[0:0] 1'1 assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'1 - attribute \src "ls180.v:3691.5-3693.8" + attribute \src "ls180.v:3687.5-3689.8" switch \main_sdram_bankmachine3_cmd_ready - attribute \src "ls180.v:3691.9-3691.42" + attribute \src "ls180.v:3687.9-3687.42" case 1'1 assign $0\builder_bankmachine3_next_state[2:0] 3'110 case @@ -117102,16 +117045,16 @@ module \ls180 case 3'100 assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3698.4-3700.7" + attribute \src "ls180.v:3694.4-3696.7" switch \main_sdram_bankmachine3_twtpcon_ready - attribute \src "ls180.v:3698.8-3698.45" + attribute \src "ls180.v:3694.8-3694.45" case 1'1 assign $0\main_sdram_bankmachine3_refresh_gnt[0:0] 1'1 case end - attribute \src "ls180.v:3703.4-3705.7" - switch $not$ls180.v:3703$198_Y - attribute \src "ls180.v:3703.8-3703.46" + attribute \src "ls180.v:3699.4-3701.7" + switch $not$ls180.v:3699$197_Y + attribute \src "ls180.v:3699.8-3699.46" case 1'1 assign $0\builder_bankmachine3_next_state[2:0] 3'000 case @@ -117124,51 +117067,51 @@ module \ls180 assign $0\builder_bankmachine3_next_state[2:0] 3'000 attribute \src "ls180.v:0.0-0.0" case - attribute \src "ls180.v:3714.4-3740.7" + attribute \src "ls180.v:3710.4-3736.7" switch \main_sdram_bankmachine3_refresh_req - attribute \src "ls180.v:3714.8-3714.43" + attribute \src "ls180.v:3710.8-3710.43" case 1'1 assign $0\builder_bankmachine3_next_state[2:0] 3'100 - attribute \src "ls180.v:3716.8-3716.12" + attribute \src "ls180.v:3712.8-3712.12" case - attribute \src "ls180.v:3717.5-3739.8" + attribute \src "ls180.v:3713.5-3735.8" switch \main_sdram_bankmachine3_cmd_buffer_source_valid - attribute \src "ls180.v:3717.9-3717.56" + attribute \src "ls180.v:3713.9-3713.56" case 1'1 - attribute \src "ls180.v:3718.6-3738.9" + attribute \src "ls180.v:3714.6-3734.9" switch \main_sdram_bankmachine3_row_opened - attribute \src "ls180.v:3718.10-3718.44" + attribute \src "ls180.v:3714.10-3714.44" case 1'1 - attribute \src "ls180.v:3719.7-3735.10" + attribute \src "ls180.v:3715.7-3731.10" switch \main_sdram_bankmachine3_row_hit - attribute \src "ls180.v:3719.11-3719.42" + attribute \src "ls180.v:3715.11-3715.42" case 1'1 assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'1 - attribute \src "ls180.v:3721.8-3728.11" + attribute \src "ls180.v:3717.8-3724.11" switch \main_sdram_bankmachine3_cmd_buffer_source_payload_we - attribute \src "ls180.v:3721.12-3721.64" + attribute \src "ls180.v:3717.12-3717.64" case 1'1 assign $0\main_sdram_bankmachine3_req_wdata_ready[0:0] \main_sdram_bankmachine3_cmd_ready assign $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'1 assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'1 - attribute \src "ls180.v:3725.12-3725.16" + attribute \src "ls180.v:3721.12-3721.16" case assign $0\main_sdram_bankmachine3_req_rdata_valid[0:0] \main_sdram_bankmachine3_cmd_ready assign $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'1 end - attribute \src "ls180.v:3730.8-3732.11" - switch $and$ls180.v:3730$199_Y - attribute \src "ls180.v:3730.12-3730.88" + attribute \src "ls180.v:3726.8-3728.11" + switch $and$ls180.v:3726$198_Y + attribute \src "ls180.v:3726.12-3726.88" case 1'1 assign $0\builder_bankmachine3_next_state[2:0] 3'010 case end - attribute \src "ls180.v:3733.11-3733.15" + attribute \src "ls180.v:3729.11-3729.15" case assign $0\builder_bankmachine3_next_state[2:0] 3'001 end - attribute \src "ls180.v:3736.10-3736.14" + attribute \src "ls180.v:3732.10-3732.14" case assign $0\builder_bankmachine3_next_state[2:0] 3'011 end @@ -117192,72 +117135,80 @@ module \ls180 update \main_sdram_bankmachine3_row_col_n_addr_sel $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] update \builder_bankmachine3_next_state $0\builder_bankmachine3_next_state[2:0] end - attribute \src "ls180.v:369.11-369.44" - process $proc$ls180.v:369$2892 + attribute \src "ls180.v:368.11-368.44" + process $proc$ls180.v:368$2889 assign { } { } assign $1\main_sdram_timer_count1[9:0] 10'1100001101 sync always sync init update \main_sdram_timer_count1 $1\main_sdram_timer_count1[9:0] end - attribute \src "ls180.v:371.5-371.38" - process $proc$ls180.v:371$2893 + attribute \src "ls180.v:370.5-370.38" + process $proc$ls180.v:370$2890 assign { } { } assign $1\main_sdram_postponer_req_o[0:0] 1'0 sync always sync init update \main_sdram_postponer_req_o $1\main_sdram_postponer_req_o[0:0] end - attribute \src "ls180.v:372.5-372.38" - process $proc$ls180.v:372$2894 + attribute \src "ls180.v:371.5-371.38" + process $proc$ls180.v:371$2891 assign { } { } assign $1\main_sdram_postponer_count[0:0] 1'0 sync always sync init update \main_sdram_postponer_count $1\main_sdram_postponer_count[0:0] end - attribute \src "ls180.v:373.5-373.39" - process $proc$ls180.v:373$2895 + attribute \src "ls180.v:372.5-372.39" + process $proc$ls180.v:372$2892 assign { } { } assign $1\main_sdram_sequencer_start0[0:0] 1'0 sync always sync init update \main_sdram_sequencer_start0 $1\main_sdram_sequencer_start0[0:0] end - attribute \src "ls180.v:376.5-376.38" - process $proc$ls180.v:376$2896 + attribute \src "ls180.v:375.5-375.38" + process $proc$ls180.v:375$2893 assign { } { } assign $1\main_sdram_sequencer_done1[0:0] 1'0 sync always sync init update \main_sdram_sequencer_done1 $1\main_sdram_sequencer_done1[0:0] end - attribute \src "ls180.v:3763.1-3769.4" - process $proc$ls180.v:3763$238 + attribute \src "ls180.v:3759.1-3765.4" + process $proc$ls180.v:3759$237 assign { } { } assign { } { } - assign $0\main_sdram_choose_cmd_valids[3:0] [0] $and$ls180.v:3765$251_Y - assign $0\main_sdram_choose_cmd_valids[3:0] [1] $and$ls180.v:3766$264_Y - assign $0\main_sdram_choose_cmd_valids[3:0] [2] $and$ls180.v:3767$277_Y - assign $0\main_sdram_choose_cmd_valids[3:0] [3] $and$ls180.v:3768$290_Y + assign $0\main_sdram_choose_cmd_valids[3:0] [0] $and$ls180.v:3761$250_Y + assign $0\main_sdram_choose_cmd_valids[3:0] [1] $and$ls180.v:3762$263_Y + assign $0\main_sdram_choose_cmd_valids[3:0] [2] $and$ls180.v:3763$276_Y + assign $0\main_sdram_choose_cmd_valids[3:0] [3] $and$ls180.v:3764$289_Y sync always update \main_sdram_choose_cmd_valids $0\main_sdram_choose_cmd_valids[3:0] end - attribute \src "ls180.v:377.11-377.46" - process $proc$ls180.v:377$2897 + attribute \src "ls180.v:376.11-376.46" + process $proc$ls180.v:376$2894 assign { } { } assign $1\main_sdram_sequencer_counter[3:0] 4'0000 sync always sync init update \main_sdram_sequencer_counter $1\main_sdram_sequencer_counter[3:0] end - attribute \src "ls180.v:3777.1-3782.4" - process $proc$ls180.v:3777$291 + attribute \src "ls180.v:377.5-377.38" + process $proc$ls180.v:377$2895 + assign { } { } + assign $1\main_sdram_sequencer_count[0:0] 1'0 + sync always + sync init + update \main_sdram_sequencer_count $1\main_sdram_sequencer_count[0:0] + end + attribute \src "ls180.v:3773.1-3778.4" + process $proc$ls180.v:3773$290 assign { } { } assign $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] 1'0 - attribute \src "ls180.v:3779.2-3781.5" + attribute \src "ls180.v:3775.2-3777.5" switch \main_sdram_choose_cmd_cmd_valid - attribute \src "ls180.v:3779.6-3779.37" + attribute \src "ls180.v:3775.6-3775.37" case 1'1 assign $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] \builder_comb_t_array_muxed0 case @@ -117265,21 +117216,13 @@ module \ls180 sync always update \main_sdram_choose_cmd_cmd_payload_cas $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] end - attribute \src "ls180.v:378.5-378.38" - process $proc$ls180.v:378$2898 - assign { } { } - assign $1\main_sdram_sequencer_count[0:0] 1'0 - sync always - sync init - update \main_sdram_sequencer_count $1\main_sdram_sequencer_count[0:0] - end - attribute \src "ls180.v:3783.1-3788.4" - process $proc$ls180.v:3783$292 + attribute \src "ls180.v:3779.1-3784.4" + process $proc$ls180.v:3779$291 assign { } { } assign $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] 1'0 - attribute \src "ls180.v:3785.2-3787.5" + attribute \src "ls180.v:3781.2-3783.5" switch \main_sdram_choose_cmd_cmd_valid - attribute \src "ls180.v:3785.6-3785.37" + attribute \src "ls180.v:3781.6-3781.37" case 1'1 assign $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] \builder_comb_t_array_muxed1 case @@ -117287,13 +117230,13 @@ module \ls180 sync always update \main_sdram_choose_cmd_cmd_payload_ras $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] end - attribute \src "ls180.v:3789.1-3794.4" - process $proc$ls180.v:3789$293 + attribute \src "ls180.v:3785.1-3790.4" + process $proc$ls180.v:3785$292 assign { } { } assign $0\main_sdram_choose_cmd_cmd_payload_we[0:0] 1'0 - attribute \src "ls180.v:3791.2-3793.5" + attribute \src "ls180.v:3787.2-3789.5" switch \main_sdram_choose_cmd_cmd_valid - attribute \src "ls180.v:3791.6-3791.37" + attribute \src "ls180.v:3787.6-3787.37" case 1'1 assign $0\main_sdram_choose_cmd_cmd_payload_we[0:0] \builder_comb_t_array_muxed2 case @@ -117301,24 +117244,24 @@ module \ls180 sync always update \main_sdram_choose_cmd_cmd_payload_we $0\main_sdram_choose_cmd_cmd_payload_we[0:0] end - attribute \src "ls180.v:3796.1-3802.4" - process $proc$ls180.v:3796$296 + attribute \src "ls180.v:3792.1-3798.4" + process $proc$ls180.v:3792$295 assign { } { } assign { } { } - assign $0\main_sdram_choose_req_valids[3:0] [0] $and$ls180.v:3798$309_Y - assign $0\main_sdram_choose_req_valids[3:0] [1] $and$ls180.v:3799$322_Y - assign $0\main_sdram_choose_req_valids[3:0] [2] $and$ls180.v:3800$335_Y - assign $0\main_sdram_choose_req_valids[3:0] [3] $and$ls180.v:3801$348_Y + assign $0\main_sdram_choose_req_valids[3:0] [0] $and$ls180.v:3794$308_Y + assign $0\main_sdram_choose_req_valids[3:0] [1] $and$ls180.v:3795$321_Y + assign $0\main_sdram_choose_req_valids[3:0] [2] $and$ls180.v:3796$334_Y + assign $0\main_sdram_choose_req_valids[3:0] [3] $and$ls180.v:3797$347_Y sync always update \main_sdram_choose_req_valids $0\main_sdram_choose_req_valids[3:0] end - attribute \src "ls180.v:3810.1-3815.4" - process $proc$ls180.v:3810$349 + attribute \src "ls180.v:3806.1-3811.4" + process $proc$ls180.v:3806$348 assign { } { } assign $0\main_sdram_choose_req_cmd_payload_cas[0:0] 1'0 - attribute \src "ls180.v:3812.2-3814.5" + attribute \src "ls180.v:3808.2-3810.5" switch \main_sdram_choose_req_cmd_valid - attribute \src "ls180.v:3812.6-3812.37" + attribute \src "ls180.v:3808.6-3808.37" case 1'1 assign $0\main_sdram_choose_req_cmd_payload_cas[0:0] \builder_comb_t_array_muxed3 case @@ -117326,13 +117269,13 @@ module \ls180 sync always update \main_sdram_choose_req_cmd_payload_cas $0\main_sdram_choose_req_cmd_payload_cas[0:0] end - attribute \src "ls180.v:3816.1-3821.4" - process $proc$ls180.v:3816$350 + attribute \src "ls180.v:3812.1-3817.4" + process $proc$ls180.v:3812$349 assign { } { } assign $0\main_sdram_choose_req_cmd_payload_ras[0:0] 1'0 - attribute \src "ls180.v:3818.2-3820.5" + attribute \src "ls180.v:3814.2-3816.5" switch \main_sdram_choose_req_cmd_valid - attribute \src "ls180.v:3818.6-3818.37" + attribute \src "ls180.v:3814.6-3814.37" case 1'1 assign $0\main_sdram_choose_req_cmd_payload_ras[0:0] \builder_comb_t_array_muxed4 case @@ -117340,13 +117283,13 @@ module \ls180 sync always update \main_sdram_choose_req_cmd_payload_ras $0\main_sdram_choose_req_cmd_payload_ras[0:0] end - attribute \src "ls180.v:3822.1-3827.4" - process $proc$ls180.v:3822$351 + attribute \src "ls180.v:3818.1-3823.4" + process $proc$ls180.v:3818$350 assign { } { } assign $0\main_sdram_choose_req_cmd_payload_we[0:0] 1'0 - attribute \src "ls180.v:3824.2-3826.5" + attribute \src "ls180.v:3820.2-3822.5" switch \main_sdram_choose_req_cmd_valid - attribute \src "ls180.v:3824.6-3824.37" + attribute \src "ls180.v:3820.6-3820.37" case 1'1 assign $0\main_sdram_choose_req_cmd_payload_we[0:0] \builder_comb_t_array_muxed5 case @@ -117354,20 +117297,20 @@ module \ls180 sync always update \main_sdram_choose_req_cmd_payload_we $0\main_sdram_choose_req_cmd_payload_we[0:0] end - attribute \src "ls180.v:3828.1-3836.4" - process $proc$ls180.v:3828$352 + attribute \src "ls180.v:3824.1-3832.4" + process $proc$ls180.v:3824$351 assign { } { } assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'0 - attribute \src "ls180.v:3830.2-3832.5" - switch $and$ls180.v:3830$355_Y - attribute \src "ls180.v:3830.6-3830.115" + attribute \src "ls180.v:3826.2-3828.5" + switch $and$ls180.v:3826$354_Y + attribute \src "ls180.v:3826.6-3826.115" case 1'1 assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'1 case end - attribute \src "ls180.v:3833.2-3835.5" - switch $and$ls180.v:3833$358_Y - attribute \src "ls180.v:3833.6-3833.115" + attribute \src "ls180.v:3829.2-3831.5" + switch $and$ls180.v:3829$357_Y + attribute \src "ls180.v:3829.6-3829.115" case 1'1 assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'1 case @@ -117375,20 +117318,28 @@ module \ls180 sync always update \main_sdram_bankmachine0_cmd_ready $0\main_sdram_bankmachine0_cmd_ready[0:0] end - attribute \src "ls180.v:3837.1-3845.4" - process $proc$ls180.v:3837$359 + attribute \src "ls180.v:383.5-383.51" + process $proc$ls180.v:383$2896 + assign { } { } + assign $1\main_sdram_bankmachine0_req_wdata_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_req_wdata_ready $1\main_sdram_bankmachine0_req_wdata_ready[0:0] + end + attribute \src "ls180.v:3833.1-3841.4" + process $proc$ls180.v:3833$358 assign { } { } assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'0 - attribute \src "ls180.v:3839.2-3841.5" - switch $and$ls180.v:3839$362_Y - attribute \src "ls180.v:3839.6-3839.115" + attribute \src "ls180.v:3835.2-3837.5" + switch $and$ls180.v:3835$361_Y + attribute \src "ls180.v:3835.6-3835.115" case 1'1 assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'1 case end - attribute \src "ls180.v:3842.2-3844.5" - switch $and$ls180.v:3842$365_Y - attribute \src "ls180.v:3842.6-3842.115" + attribute \src "ls180.v:3838.2-3840.5" + switch $and$ls180.v:3838$364_Y + attribute \src "ls180.v:3838.6-3838.115" case 1'1 assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'1 case @@ -117397,27 +117348,27 @@ module \ls180 update \main_sdram_bankmachine1_cmd_ready $0\main_sdram_bankmachine1_cmd_ready[0:0] end attribute \src "ls180.v:384.5-384.51" - process $proc$ls180.v:384$2899 + process $proc$ls180.v:384$2897 assign { } { } - assign $1\main_sdram_bankmachine0_req_wdata_ready[0:0] 1'0 + assign $1\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_req_wdata_ready $1\main_sdram_bankmachine0_req_wdata_ready[0:0] + update \main_sdram_bankmachine0_req_rdata_valid $1\main_sdram_bankmachine0_req_rdata_valid[0:0] end - attribute \src "ls180.v:3846.1-3854.4" - process $proc$ls180.v:3846$366 + attribute \src "ls180.v:3842.1-3850.4" + process $proc$ls180.v:3842$365 assign { } { } assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'0 - attribute \src "ls180.v:3848.2-3850.5" - switch $and$ls180.v:3848$369_Y - attribute \src "ls180.v:3848.6-3848.115" + attribute \src "ls180.v:3844.2-3846.5" + switch $and$ls180.v:3844$368_Y + attribute \src "ls180.v:3844.6-3844.115" case 1'1 assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'1 case end - attribute \src "ls180.v:3851.2-3853.5" - switch $and$ls180.v:3851$372_Y - attribute \src "ls180.v:3851.6-3851.115" + attribute \src "ls180.v:3847.2-3849.5" + switch $and$ls180.v:3847$371_Y + attribute \src "ls180.v:3847.6-3847.115" case 1'1 assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'1 case @@ -117425,28 +117376,20 @@ module \ls180 sync always update \main_sdram_bankmachine2_cmd_ready $0\main_sdram_bankmachine2_cmd_ready[0:0] end - attribute \src "ls180.v:385.5-385.51" - process $proc$ls180.v:385$2900 - assign { } { } - assign $1\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_req_rdata_valid $1\main_sdram_bankmachine0_req_rdata_valid[0:0] - end - attribute \src "ls180.v:3855.1-3863.4" - process $proc$ls180.v:3855$373 + attribute \src "ls180.v:3851.1-3859.4" + process $proc$ls180.v:3851$372 assign { } { } assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'0 - attribute \src "ls180.v:3857.2-3859.5" - switch $and$ls180.v:3857$376_Y - attribute \src "ls180.v:3857.6-3857.115" + attribute \src "ls180.v:3853.2-3855.5" + switch $and$ls180.v:3853$375_Y + attribute \src "ls180.v:3853.6-3853.115" case 1'1 assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'1 case end - attribute \src "ls180.v:3860.2-3862.5" - switch $and$ls180.v:3860$379_Y - attribute \src "ls180.v:3860.6-3860.115" + attribute \src "ls180.v:3856.2-3858.5" + switch $and$ls180.v:3856$378_Y + attribute \src "ls180.v:3856.6-3856.115" case 1'1 assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'1 case @@ -117454,8 +117397,16 @@ module \ls180 sync always update \main_sdram_bankmachine3_cmd_ready $0\main_sdram_bankmachine3_cmd_ready[0:0] end - attribute \src "ls180.v:3868.1-3940.4" - process $proc$ls180.v:3868$382 + attribute \src "ls180.v:386.5-386.47" + process $proc$ls180.v:386$2898 + assign { } { } + assign $1\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_refresh_gnt $1\main_sdram_bankmachine0_refresh_gnt[0:0] + end + attribute \src "ls180.v:3864.1-3936.4" + process $proc$ls180.v:3864$381 assign { } { } assign { } { } assign { } { } @@ -117465,47 +117416,47 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdram_en0[0:0] 1'0 assign $0\main_sdram_en1[0:0] 1'0 assign $0\main_sdram_choose_req_want_reads[0:0] 1'0 assign $0\main_sdram_choose_req_want_writes[0:0] 1'0 - assign $0\main_sdram_cmd_ready[0:0] 1'0 assign { } { } assign { } { } - assign $0\main_sdram_choose_req_cmd_ready[0:0] 1'0 + assign $0\main_sdram_cmd_ready[0:0] 1'0 assign $0\main_sdram_steerer_sel[1:0] 2'00 + assign $0\main_sdram_choose_req_cmd_ready[0:0] 1'0 + assign $0\main_sdram_en0[0:0] 1'0 assign $0\main_sdram_choose_req_want_activates[0:0] \main_sdram_ras_allowed assign $0\builder_multiplexer_next_state[2:0] \builder_multiplexer_state - attribute \src "ls180.v:3880.2-3939.9" + attribute \src "ls180.v:3876.2-3935.9" switch \builder_multiplexer_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\main_sdram_en1[0:0] 1'1 assign $0\main_sdram_choose_req_want_writes[0:0] 1'1 assign $0\main_sdram_steerer_sel[1:0] 2'10 - attribute \src "ls180.v:3884.4-3890.7" + attribute \src "ls180.v:3880.4-3886.7" switch 1'1 - attribute \src "ls180.v:3884.8-3884.12" + attribute \src "ls180.v:3880.8-3880.12" case 1'1 - assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:3885$389_Y + assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:3881$388_Y case end - attribute \src "ls180.v:3892.4-3896.7" + attribute \src "ls180.v:3888.4-3892.7" switch \main_sdram_read_available - attribute \src "ls180.v:3892.8-3892.33" + attribute \src "ls180.v:3888.8-3888.33" case 1'1 - attribute \src "ls180.v:3893.5-3895.8" - switch $or$ls180.v:3893$391_Y - attribute \src "ls180.v:3893.9-3893.63" + attribute \src "ls180.v:3889.5-3891.8" + switch $or$ls180.v:3889$390_Y + attribute \src "ls180.v:3889.9-3889.63" case 1'1 assign $0\builder_multiplexer_next_state[2:0] 3'011 case end case end - attribute \src "ls180.v:3897.4-3899.7" + attribute \src "ls180.v:3893.4-3895.7" switch \main_sdram_go_to_refresh - attribute \src "ls180.v:3897.8-3897.32" + attribute \src "ls180.v:3893.8-3893.32" case 1'1 assign $0\builder_multiplexer_next_state[2:0] 3'010 case @@ -117514,18 +117465,18 @@ module \ls180 case 3'010 assign $0\main_sdram_steerer_sel[1:0] 2'11 assign $0\main_sdram_cmd_ready[0:0] 1'1 - attribute \src "ls180.v:3904.4-3906.7" + attribute \src "ls180.v:3900.4-3902.7" switch \main_sdram_cmd_last - attribute \src "ls180.v:3904.8-3904.27" + attribute \src "ls180.v:3900.8-3900.27" case 1'1 assign $0\builder_multiplexer_next_state[2:0] 3'000 case end attribute \src "ls180.v:0.0-0.0" case 3'011 - attribute \src "ls180.v:3909.4-3911.7" + attribute \src "ls180.v:3905.4-3907.7" switch \main_sdram_twtrcon_ready - attribute \src "ls180.v:3909.8-3909.32" + attribute \src "ls180.v:3905.8-3905.32" case 1'1 assign $0\builder_multiplexer_next_state[2:0] 3'000 case @@ -117541,29 +117492,29 @@ module \ls180 assign $0\main_sdram_en0[0:0] 1'1 assign $0\main_sdram_choose_req_want_reads[0:0] 1'1 assign $0\main_sdram_steerer_sel[1:0] 2'10 - attribute \src "ls180.v:3922.4-3928.7" + attribute \src "ls180.v:3918.4-3924.7" switch 1'1 - attribute \src "ls180.v:3922.8-3922.12" + attribute \src "ls180.v:3918.8-3918.12" case 1'1 - assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:3923$398_Y + assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:3919$397_Y case end - attribute \src "ls180.v:3930.4-3934.7" + attribute \src "ls180.v:3926.4-3930.7" switch \main_sdram_write_available - attribute \src "ls180.v:3930.8-3930.34" + attribute \src "ls180.v:3926.8-3926.34" case 1'1 - attribute \src "ls180.v:3931.5-3933.8" - switch $or$ls180.v:3931$400_Y - attribute \src "ls180.v:3931.9-3931.62" + attribute \src "ls180.v:3927.5-3929.8" + switch $or$ls180.v:3927$399_Y + attribute \src "ls180.v:3927.9-3927.62" case 1'1 assign $0\builder_multiplexer_next_state[2:0] 3'100 case end case end - attribute \src "ls180.v:3935.4-3937.7" + attribute \src "ls180.v:3931.4-3933.7" switch \main_sdram_go_to_refresh - attribute \src "ls180.v:3935.8-3935.32" + attribute \src "ls180.v:3931.8-3931.32" case 1'1 assign $0\builder_multiplexer_next_state[2:0] 3'010 case @@ -117580,85 +117531,85 @@ module \ls180 update \main_sdram_en1 $0\main_sdram_en1[0:0] update \builder_multiplexer_next_state $0\builder_multiplexer_next_state[2:0] end - attribute \src "ls180.v:387.5-387.47" - process $proc$ls180.v:387$2901 - assign { } { } - assign $1\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_refresh_gnt $1\main_sdram_bankmachine0_refresh_gnt[0:0] - end - attribute \src "ls180.v:388.5-388.45" - process $proc$ls180.v:388$2902 + attribute \src "ls180.v:387.5-387.45" + process $proc$ls180.v:387$2899 assign { } { } assign $1\main_sdram_bankmachine0_cmd_valid[0:0] 1'0 sync always sync init update \main_sdram_bankmachine0_cmd_valid $1\main_sdram_bankmachine0_cmd_valid[0:0] end - attribute \src "ls180.v:389.5-389.45" - process $proc$ls180.v:389$2903 + attribute \src "ls180.v:388.5-388.45" + process $proc$ls180.v:388$2900 assign { } { } assign $1\main_sdram_bankmachine0_cmd_ready[0:0] 1'0 sync always sync init update \main_sdram_bankmachine0_cmd_ready $1\main_sdram_bankmachine0_cmd_ready[0:0] end - attribute \src "ls180.v:390.12-390.57" - process $proc$ls180.v:390$2904 + attribute \src "ls180.v:389.12-389.57" + process $proc$ls180.v:389$2901 assign { } { } assign $1\main_sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000 sync always sync init update \main_sdram_bankmachine0_cmd_payload_a $1\main_sdram_bankmachine0_cmd_payload_a[12:0] end - attribute \src "ls180.v:392.5-392.51" - process $proc$ls180.v:392$2905 + attribute \src "ls180.v:391.5-391.51" + process $proc$ls180.v:391$2902 assign { } { } assign $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0 sync always sync init update \main_sdram_bankmachine0_cmd_payload_cas $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] end - attribute \src "ls180.v:393.5-393.51" - process $proc$ls180.v:393$2906 + attribute \src "ls180.v:392.5-392.51" + process $proc$ls180.v:392$2903 assign { } { } assign $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0 sync always sync init update \main_sdram_bankmachine0_cmd_payload_ras $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] end - attribute \src "ls180.v:394.5-394.50" - process $proc$ls180.v:394$2907 + attribute \src "ls180.v:393.5-393.50" + process $proc$ls180.v:393$2904 assign { } { } assign $1\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0 sync always sync init update \main_sdram_bankmachine0_cmd_payload_we $1\main_sdram_bankmachine0_cmd_payload_we[0:0] end - attribute \src "ls180.v:395.5-395.54" - process $proc$ls180.v:395$2908 + attribute \src "ls180.v:394.5-394.54" + process $proc$ls180.v:394$2905 assign { } { } assign $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0 sync always sync init update \main_sdram_bankmachine0_cmd_payload_is_cmd $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] end - attribute \src "ls180.v:396.5-396.55" - process $proc$ls180.v:396$2909 + attribute \src "ls180.v:395.5-395.55" + process $proc$ls180.v:395$2906 assign { } { } assign $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0 sync always sync init update \main_sdram_bankmachine0_cmd_payload_is_read $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] end - attribute \src "ls180.v:3964.1-3977.4" - process $proc$ls180.v:3964$529 + attribute \src "ls180.v:396.5-396.56" + process $proc$ls180.v:396$2907 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_is_write $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] + end + attribute \src "ls180.v:3960.1-3973.4" + process $proc$ls180.v:3960$528 assign { } { } assign { } { } assign $0\main_sdram_interface_wdata[15:0] 16'0000000000000000 assign $0\main_sdram_interface_wdata_we[1:0] 2'00 - attribute \src "ls180.v:3967.2-3976.9" + attribute \src "ls180.v:3963.2-3972.9" switch \builder_new_master_wdata_ready attribute \src "ls180.v:0.0-0.0" case 1'1 @@ -117673,27 +117624,19 @@ module \ls180 update \main_sdram_interface_wdata $0\main_sdram_interface_wdata[15:0] update \main_sdram_interface_wdata_we $0\main_sdram_interface_wdata_we[1:0] end - attribute \src "ls180.v:397.5-397.56" - process $proc$ls180.v:397$2910 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_payload_is_write $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] - end - attribute \src "ls180.v:398.5-398.50" - process $proc$ls180.v:398$2911 + attribute \src "ls180.v:397.5-397.50" + process $proc$ls180.v:397$2908 assign { } { } assign $1\main_sdram_bankmachine0_auto_precharge[0:0] 1'0 sync always sync init update \main_sdram_bankmachine0_auto_precharge $1\main_sdram_bankmachine0_auto_precharge[0:0] end - attribute \src "ls180.v:3984.1-3994.4" - process $proc$ls180.v:3984$531 + attribute \src "ls180.v:3980.1-3990.4" + process $proc$ls180.v:3980$530 assign { } { } assign $0\main_litedram_wb_dat_w[15:0] 16'0000000000000000 - attribute \src "ls180.v:3986.2-3993.9" + attribute \src "ls180.v:3982.2-3989.9" switch \main_converter_counter attribute \src "ls180.v:0.0-0.0" case 1'0 @@ -117706,8 +117649,8 @@ module \ls180 sync always update \main_litedram_wb_dat_w $0\main_litedram_wb_dat_w[15:0] end - attribute \src "ls180.v:3996.1-4042.4" - process $proc$ls180.v:3996$532 + attribute \src "ls180.v:3992.1-4038.4" + process $proc$ls180.v:3992$531 assign { } { } assign { } { } assign { } { } @@ -117718,23 +117661,23 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_converter_skip[0:0] 1'0 - assign { } { } - assign $0\main_wb_sdram_ack[0:0] 1'0 - assign $0\main_converter_counter_converter_next_value[0:0] 1'0 - assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'0 assign $0\main_litedram_wb_adr[29:0] 30'000000000000000000000000000000 + assign $0\main_wb_sdram_ack[0:0] 1'0 assign $0\main_litedram_wb_sel[1:0] 2'00 assign $0\main_litedram_wb_cyc[0:0] 1'0 assign $0\main_litedram_wb_stb[0:0] 1'0 assign $0\main_litedram_wb_we[0:0] 1'0 + assign { } { } + assign $0\main_converter_counter_converter_next_value[0:0] 1'0 + assign $0\main_converter_skip[0:0] 1'0 + assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'0 assign $0\builder_converter_next_state[0:0] \builder_converter_state - attribute \src "ls180.v:4008.2-4041.9" + attribute \src "ls180.v:4004.2-4037.9" switch \builder_converter_state attribute \src "ls180.v:0.0-0.0" case 1'1 assign $0\main_litedram_wb_adr[29:0] { \main_wb_sdram_adr [28:0] \main_converter_counter } - attribute \src "ls180.v:4011.4-4018.11" + attribute \src "ls180.v:4007.4-4014.11" switch \main_converter_counter attribute \src "ls180.v:0.0-0.0" case 1'0 @@ -117744,23 +117687,23 @@ module \ls180 assign $0\main_litedram_wb_sel[1:0] \main_wb_sdram_sel [3:2] case end - attribute \src "ls180.v:4019.4-4032.7" - switch $and$ls180.v:4019$533_Y - attribute \src "ls180.v:4019.8-4019.47" + attribute \src "ls180.v:4015.4-4028.7" + switch $and$ls180.v:4015$532_Y + attribute \src "ls180.v:4015.8-4015.47" case 1'1 - assign $0\main_converter_skip[0:0] $eq$ls180.v:4020$534_Y + assign $0\main_converter_skip[0:0] $eq$ls180.v:4016$533_Y assign $0\main_litedram_wb_we[0:0] \main_wb_sdram_we - assign $0\main_litedram_wb_cyc[0:0] $not$ls180.v:4022$535_Y - assign $0\main_litedram_wb_stb[0:0] $not$ls180.v:4023$536_Y - attribute \src "ls180.v:4024.5-4031.8" - switch $or$ls180.v:4024$537_Y - attribute \src "ls180.v:4024.9-4024.53" + assign $0\main_litedram_wb_cyc[0:0] $not$ls180.v:4018$534_Y + assign $0\main_litedram_wb_stb[0:0] $not$ls180.v:4019$535_Y + attribute \src "ls180.v:4020.5-4027.8" + switch $or$ls180.v:4020$536_Y + attribute \src "ls180.v:4020.9-4020.53" case 1'1 - assign $0\main_converter_counter_converter_next_value[0:0] $add$ls180.v:4025$538_Y + assign $0\main_converter_counter_converter_next_value[0:0] $add$ls180.v:4021$537_Y assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4027.6-4030.9" - switch $eq$ls180.v:4027$539_Y - attribute \src "ls180.v:4027.10-4027.42" + attribute \src "ls180.v:4023.6-4026.9" + switch $eq$ls180.v:4023$538_Y + attribute \src "ls180.v:4023.10-4023.42" case 1'1 assign $0\main_wb_sdram_ack[0:0] 1'1 assign $0\builder_converter_next_state[0:0] 1'0 @@ -117774,9 +117717,9 @@ module \ls180 case assign $0\main_converter_counter_converter_next_value[0:0] 1'0 assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4037.4-4039.7" - switch $and$ls180.v:4037$540_Y - attribute \src "ls180.v:4037.8-4037.47" + attribute \src "ls180.v:4033.4-4035.7" + switch $and$ls180.v:4033$539_Y + attribute \src "ls180.v:4033.8-4033.47" case 1'1 assign $0\builder_converter_next_state[0:0] 1'1 case @@ -117794,29 +117737,29 @@ module \ls180 update \main_converter_counter_converter_next_value $0\main_converter_counter_converter_next_value[0:0] update \main_converter_counter_converter_next_value_ce $0\main_converter_counter_converter_next_value_ce[0:0] end - attribute \src "ls180.v:401.5-401.67" - process $proc$ls180.v:401$2912 + attribute \src "ls180.v:400.5-400.67" + process $proc$ls180.v:400$2909 assign { } { } assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] 1'0 sync always update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] sync init end - attribute \src "ls180.v:402.5-402.66" - process $proc$ls180.v:402$2913 + attribute \src "ls180.v:401.5-401.66" + process $proc$ls180.v:401$2910 assign { } { } assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] 1'0 sync always update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] sync init end - attribute \src "ls180.v:4087.1-4092.4" - process $proc$ls180.v:4087$572 + attribute \src "ls180.v:4083.1-4088.4" + process $proc$ls180.v:4083$571 assign { } { } assign $0\main_uart_tx_clear[0:0] 1'0 - attribute \src "ls180.v:4089.2-4091.5" - switch $and$ls180.v:4089$573_Y - attribute \src "ls180.v:4089.6-4089.79" + attribute \src "ls180.v:4085.2-4087.5" + switch $and$ls180.v:4085$572_Y + attribute \src "ls180.v:4085.6-4085.79" case 1'1 assign $0\main_uart_tx_clear[0:0] 1'1 case @@ -117824,8 +117767,8 @@ module \ls180 sync always update \main_uart_tx_clear $0\main_uart_tx_clear[0:0] end - attribute \src "ls180.v:4093.1-4097.4" - process $proc$ls180.v:4093$574 + attribute \src "ls180.v:4089.1-4093.4" + process $proc$ls180.v:4089$573 assign { } { } assign { } { } assign $0\main_uart_eventmanager_status_w[1:0] [0] \main_uart_tx_status @@ -117833,13 +117776,13 @@ module \ls180 sync always update \main_uart_eventmanager_status_w $0\main_uart_eventmanager_status_w[1:0] end - attribute \src "ls180.v:4098.1-4103.4" - process $proc$ls180.v:4098$575 + attribute \src "ls180.v:4094.1-4099.4" + process $proc$ls180.v:4094$574 assign { } { } assign $0\main_uart_rx_clear[0:0] 1'0 - attribute \src "ls180.v:4100.2-4102.5" - switch $and$ls180.v:4100$576_Y - attribute \src "ls180.v:4100.6-4100.79" + attribute \src "ls180.v:4096.2-4098.5" + switch $and$ls180.v:4096$575_Y + attribute \src "ls180.v:4096.6-4096.79" case 1'1 assign $0\main_uart_rx_clear[0:0] 1'1 case @@ -117847,8 +117790,8 @@ module \ls180 sync always update \main_uart_rx_clear $0\main_uart_rx_clear[0:0] end - attribute \src "ls180.v:4104.1-4108.4" - process $proc$ls180.v:4104$577 + attribute \src "ls180.v:4100.1-4104.4" + process $proc$ls180.v:4100$576 assign { } { } assign { } { } assign $0\main_uart_eventmanager_pending_w[1:0] [0] \main_uart_tx_pending @@ -117856,56 +117799,64 @@ module \ls180 sync always update \main_uart_eventmanager_pending_w $0\main_uart_eventmanager_pending_w[1:0] end - attribute \src "ls180.v:4126.1-4133.4" - process $proc$ls180.v:4126$585 + attribute \src "ls180.v:4122.1-4129.4" + process $proc$ls180.v:4122$584 assign { } { } assign $0\main_uart_tx_fifo_wrport_adr[3:0] 4'0000 - attribute \src "ls180.v:4128.2-4132.5" + attribute \src "ls180.v:4124.2-4128.5" switch \main_uart_tx_fifo_replace - attribute \src "ls180.v:4128.6-4128.31" + attribute \src "ls180.v:4124.6-4124.31" case 1'1 - assign $0\main_uart_tx_fifo_wrport_adr[3:0] $sub$ls180.v:4129$586_Y - attribute \src "ls180.v:4130.6-4130.10" + assign $0\main_uart_tx_fifo_wrport_adr[3:0] $sub$ls180.v:4125$585_Y + attribute \src "ls180.v:4126.6-4126.10" case assign $0\main_uart_tx_fifo_wrport_adr[3:0] \main_uart_tx_fifo_produce end sync always update \main_uart_tx_fifo_wrport_adr $0\main_uart_tx_fifo_wrport_adr[3:0] end - attribute \src "ls180.v:4156.1-4163.4" - process $proc$ls180.v:4156$596 + attribute \src "ls180.v:4152.1-4159.4" + process $proc$ls180.v:4152$595 assign { } { } assign $0\main_uart_rx_fifo_wrport_adr[3:0] 4'0000 - attribute \src "ls180.v:4158.2-4162.5" + attribute \src "ls180.v:4154.2-4158.5" switch \main_uart_rx_fifo_replace - attribute \src "ls180.v:4158.6-4158.31" + attribute \src "ls180.v:4154.6-4154.31" case 1'1 - assign $0\main_uart_rx_fifo_wrport_adr[3:0] $sub$ls180.v:4159$597_Y - attribute \src "ls180.v:4160.6-4160.10" + assign $0\main_uart_rx_fifo_wrport_adr[3:0] $sub$ls180.v:4155$596_Y + attribute \src "ls180.v:4156.6-4156.10" case assign $0\main_uart_rx_fifo_wrport_adr[3:0] \main_uart_rx_fifo_produce end sync always update \main_uart_rx_fifo_wrport_adr $0\main_uart_rx_fifo_wrport_adr[3:0] end - attribute \src "ls180.v:417.11-417.68" - process $proc$ls180.v:417$2914 + attribute \src "ls180.v:416.11-416.68" + process $proc$ls180.v:416$2911 assign { } { } assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] 4'0000 sync always sync init update \main_sdram_bankmachine0_cmd_buffer_lookahead_level $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] end - attribute \src "ls180.v:418.5-418.64" - process $proc$ls180.v:418$2915 + attribute \src "ls180.v:417.5-417.64" + process $proc$ls180.v:417$2912 assign { } { } assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] 1'0 sync always update \main_sdram_bankmachine0_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] sync init end - attribute \src "ls180.v:4186.1-4234.4" - process $proc$ls180.v:4186$607 + attribute \src "ls180.v:418.11-418.70" + process $proc$ls180.v:418$2913 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] + end + attribute \src "ls180.v:4182.1-4230.4" + process $proc$ls180.v:4182$606 assign { } { } assign { } { } assign { } { } @@ -117915,25 +117866,25 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_spi_master_irq[0:0] 1'0 assign $0\main_spi_master_count_spimaster0_next_value[2:0] 3'000 - assign $0\main_spi_master_count_spimaster0_next_value_ce[0:0] 1'0 assign $0\main_spi_master_miso_latch[0:0] 1'0 assign $0\main_spi_master_clk_enable[0:0] 1'0 + assign $0\main_spi_master_irq[0:0] 1'0 assign $0\main_spi_master_cs_enable[0:0] 1'0 + assign { } { } assign $0\main_spi_master_mosi_latch[0:0] 1'0 assign $0\main_spi_master_done0[0:0] 1'0 - assign { } { } + assign $0\main_spi_master_count_spimaster0_next_value_ce[0:0] 1'0 assign $0\builder_spimaster0_next_state[1:0] \builder_spimaster0_state - attribute \src "ls180.v:4197.2-4233.9" + attribute \src "ls180.v:4193.2-4229.9" switch \builder_spimaster0_state attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\main_spi_master_count_spimaster0_next_value[2:0] 3'000 assign $0\main_spi_master_count_spimaster0_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4201.4-4204.7" + attribute \src "ls180.v:4197.4-4200.7" switch \main_spi_master_clk_fall - attribute \src "ls180.v:4201.8-4201.32" + attribute \src "ls180.v:4197.8-4197.32" case 1'1 assign $0\main_spi_master_cs_enable[0:0] 1'1 assign $0\builder_spimaster0_next_state[1:0] 2'10 @@ -117943,15 +117894,15 @@ module \ls180 case 2'10 assign $0\main_spi_master_clk_enable[0:0] 1'1 assign $0\main_spi_master_cs_enable[0:0] 1'1 - attribute \src "ls180.v:4209.4-4215.7" + attribute \src "ls180.v:4205.4-4211.7" switch \main_spi_master_clk_fall - attribute \src "ls180.v:4209.8-4209.32" + attribute \src "ls180.v:4205.8-4205.32" case 1'1 - assign $0\main_spi_master_count_spimaster0_next_value[2:0] $add$ls180.v:4210$608_Y + assign $0\main_spi_master_count_spimaster0_next_value[2:0] $add$ls180.v:4206$607_Y assign $0\main_spi_master_count_spimaster0_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4212.5-4214.8" - switch $eq$ls180.v:4212$610_Y - attribute \src "ls180.v:4212.9-4212.68" + attribute \src "ls180.v:4208.5-4210.8" + switch $eq$ls180.v:4208$609_Y + attribute \src "ls180.v:4208.9-4208.68" case 1'1 assign $0\builder_spimaster0_next_state[1:0] 2'11 case @@ -117961,9 +117912,9 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 2'11 assign $0\main_spi_master_cs_enable[0:0] 1'1 - attribute \src "ls180.v:4219.4-4223.7" + attribute \src "ls180.v:4215.4-4219.7" switch \main_spi_master_clk_rise - attribute \src "ls180.v:4219.8-4219.32" + attribute \src "ls180.v:4215.8-4215.32" case 1'1 assign $0\main_spi_master_miso_latch[0:0] 1'1 assign $0\main_spi_master_irq[0:0] 1'1 @@ -117973,9 +117924,9 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case assign $0\main_spi_master_done0[0:0] 1'1 - attribute \src "ls180.v:4227.4-4231.7" + attribute \src "ls180.v:4223.4-4227.7" switch \main_spi_master_start0 - attribute \src "ls180.v:4227.8-4227.30" + attribute \src "ls180.v:4223.8-4223.30" case 1'1 assign $0\main_spi_master_done0[0:0] 1'0 assign $0\main_spi_master_mosi_latch[0:0] 1'1 @@ -117995,34 +117946,26 @@ module \ls180 update \main_spi_master_count_spimaster0_next_value_ce $0\main_spi_master_count_spimaster0_next_value_ce[0:0] end attribute \src "ls180.v:419.11-419.70" - process $proc$ls180.v:419$2916 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] - end - attribute \src "ls180.v:420.11-420.70" - process $proc$ls180.v:420$2917 + process $proc$ls180.v:419$2914 assign { } { } assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] 3'000 sync always sync init update \main_sdram_bankmachine0_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] end - attribute \src "ls180.v:421.11-421.73" - process $proc$ls180.v:421$2918 + attribute \src "ls180.v:420.11-420.73" + process $proc$ls180.v:420$2915 assign { } { } assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 sync always sync init update \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "ls180.v:4262.1-4290.4" - process $proc$ls180.v:4262$632 + attribute \src "ls180.v:4258.1-4286.4" + process $proc$ls180.v:4258$631 assign { } { } assign $0\main_sdphy_clocker_clk1[0:0] 1'0 - attribute \src "ls180.v:4264.2-4289.9" + attribute \src "ls180.v:4260.2-4285.9" switch \main_sdphy_clocker_storage attribute \src "ls180.v:0.0-0.0" case 9'000000100 @@ -118052,8 +117995,8 @@ module \ls180 sync always update \main_sdphy_clocker_clk1 $0\main_sdphy_clocker_clk1[0:0] end - attribute \src "ls180.v:4292.1-4325.4" - process $proc$ls180.v:4292$635 + attribute \src "ls180.v:4288.1-4321.4" + process $proc$ls180.v:4288$634 assign { } { } assign { } { } assign { } { } @@ -118062,16 +118005,16 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdphy_init_pads_out_payload_clk[0:0] 1'0 - assign $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'0 assign $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'0 assign $0\main_sdphy_init_pads_out_payload_data_o[3:0] 4'0000 assign $0\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'0 assign { } { } assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'0 + assign $0\main_sdphy_init_pads_out_payload_clk[0:0] 1'0 + assign $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'0 assign $0\builder_sdphy_sdphyinit_next_state[0:0] \builder_sdphy_sdphyinit_state - attribute \src "ls180.v:4302.2-4324.9" + attribute \src "ls180.v:4298.2-4320.9" switch \builder_sdphy_sdphyinit_state attribute \src "ls180.v:0.0-0.0" case 1'1 @@ -118080,15 +118023,15 @@ module \ls180 assign $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'1 assign $0\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'1 assign $0\main_sdphy_init_pads_out_payload_data_o[3:0] 4'1111 - attribute \src "ls180.v:4309.4-4315.7" + attribute \src "ls180.v:4305.4-4311.7" switch \main_sdphy_init_pads_out_ready - attribute \src "ls180.v:4309.8-4309.38" + attribute \src "ls180.v:4305.8-4305.38" case 1'1 - assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] $add$ls180.v:4310$636_Y + assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] $add$ls180.v:4306$635_Y assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4312.5-4314.8" - switch $eq$ls180.v:4312$637_Y - attribute \src "ls180.v:4312.9-4312.41" + attribute \src "ls180.v:4308.5-4310.8" + switch $eq$ls180.v:4308$636_Y + attribute \src "ls180.v:4308.9-4308.41" case 1'1 assign $0\builder_sdphy_sdphyinit_next_state[0:0] 1'0 case @@ -118099,9 +118042,9 @@ module \ls180 case assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4320.4-4322.7" + attribute \src "ls180.v:4316.4-4318.7" switch \main_sdphy_init_initialize_re - attribute \src "ls180.v:4320.8-4320.37" + attribute \src "ls180.v:4316.8-4316.37" case 1'1 assign $0\builder_sdphy_sdphyinit_next_state[0:0] 1'1 case @@ -118117,8 +118060,8 @@ module \ls180 update \main_sdphy_init_count_sdphy_sdphyinit_next_value $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] update \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] end - attribute \src "ls180.v:4326.1-4402.4" - process $proc$ls180.v:4326$638 + attribute \src "ls180.v:4322.1-4398.4" + process $proc$ls180.v:4322$637 assign { } { } assign { } { } assign { } { } @@ -118127,22 +118070,22 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'0 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'0 assign { } { } assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'0 assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'0 assign $0\main_sdphy_cmdw_done[0:0] 1'0 assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'0 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'0 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'0 assign $0\builder_sdphy_sdphycmdw_next_state[1:0] \builder_sdphy_sdphycmdw_state - attribute \src "ls180.v:4336.2-4401.9" + attribute \src "ls180.v:4332.2-4397.9" switch \builder_sdphy_sdphycmdw_state attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'1 assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'1 - attribute \src "ls180.v:4340.4-4365.11" + attribute \src "ls180.v:4336.4-4361.11" switch \main_sdphy_cmdw_count attribute \src "ls180.v:0.0-0.0" case 8'00000000 @@ -118170,22 +118113,22 @@ module \ls180 assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [0] case end - attribute \src "ls180.v:4366.4-4377.7" + attribute \src "ls180.v:4362.4-4373.7" switch \main_sdphy_cmdw_pads_out_ready - attribute \src "ls180.v:4366.8-4366.38" + attribute \src "ls180.v:4362.8-4362.38" case 1'1 - assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4367$639_Y + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4363$638_Y assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4369.5-4376.8" - switch $eq$ls180.v:4369$640_Y - attribute \src "ls180.v:4369.9-4369.40" + attribute \src "ls180.v:4365.5-4372.8" + switch $eq$ls180.v:4365$639_Y + attribute \src "ls180.v:4365.9-4365.40" case 1'1 - attribute \src "ls180.v:4370.6-4375.9" + attribute \src "ls180.v:4366.6-4371.9" switch \main_sdphy_cmdw_sink_last - attribute \src "ls180.v:4370.10-4370.35" + attribute \src "ls180.v:4366.10-4366.35" case 1'1 assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'10 - attribute \src "ls180.v:4372.10-4372.14" + attribute \src "ls180.v:4368.10-4368.14" case assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'1 assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 @@ -118199,15 +118142,15 @@ module \ls180 assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'1 assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'1 assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'1 - attribute \src "ls180.v:4383.4-4390.7" + attribute \src "ls180.v:4379.4-4386.7" switch \main_sdphy_cmdw_pads_out_ready - attribute \src "ls180.v:4383.8-4383.38" + attribute \src "ls180.v:4379.8-4379.38" case 1'1 - assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4384$641_Y + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4380$640_Y assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4386.5-4389.8" - switch $eq$ls180.v:4386$642_Y - attribute \src "ls180.v:4386.9-4386.40" + attribute \src "ls180.v:4382.5-4385.8" + switch $eq$ls180.v:4382$641_Y + attribute \src "ls180.v:4382.9-4382.40" case 1'1 assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'1 assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 @@ -118219,12 +118162,12 @@ module \ls180 case assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4395.4-4399.7" - switch $and$ls180.v:4395$643_Y - attribute \src "ls180.v:4395.8-4395.69" + attribute \src "ls180.v:4391.4-4395.7" + switch $and$ls180.v:4391$642_Y + attribute \src "ls180.v:4391.8-4391.69" case 1'1 assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'01 - attribute \src "ls180.v:4397.8-4397.12" + attribute \src "ls180.v:4393.8-4393.12" case assign $0\main_sdphy_cmdw_done[0:0] 1'1 end @@ -118239,16 +118182,24 @@ module \ls180 update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] end - attribute \src "ls180.v:442.5-442.59" - process $proc$ls180.v:442$2919 + attribute \src "ls180.v:441.5-441.59" + process $proc$ls180.v:441$2916 assign { } { } assign $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] 1'0 sync always sync init update \main_sdram_bankmachine0_cmd_buffer_source_valid $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] end - attribute \src "ls180.v:4436.1-4529.4" - process $proc$ls180.v:4436$652 + attribute \src "ls180.v:443.5-443.59" + process $proc$ls180.v:443$2917 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_source_first $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] + end + attribute \src "ls180.v:4432.1-4525.4" + process $proc$ls180.v:4432$651 assign { } { } assign { } { } assign { } { } @@ -118282,25 +118233,25 @@ module \ls180 assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'0 assign $0\builder_sdphy_sdphycmdr_next_state[2:0] \builder_sdphy_sdphycmdr_state - attribute \src "ls180.v:4454.2-4528.9" + attribute \src "ls180.v:4450.2-4524.9" switch \builder_sdphy_sdphycmdr_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1 assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'1 - assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4462$653_Y + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4458$652_Y assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 - attribute \src "ls180.v:4459.4-4461.7" + attribute \src "ls180.v:4455.4-4457.7" switch \main_sdphy_cmdr_cmdr_source_source_valid0 - attribute \src "ls180.v:4459.8-4459.49" + attribute \src "ls180.v:4455.8-4455.49" case 1'1 assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'010 case end - attribute \src "ls180.v:4464.4-4467.7" - switch $eq$ls180.v:4464$654_Y - attribute \src "ls180.v:4464.8-4464.41" + attribute \src "ls180.v:4460.4-4463.7" + switch $eq$ls180.v:4460$653_Y + attribute \src "ls180.v:4460.8-4460.41" case 1'1 assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1 assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'100 @@ -118311,30 +118262,30 @@ module \ls180 assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1 assign $0\main_sdphy_cmdr_source_valid[0:0] \main_sdphy_cmdr_cmdr_source_source_valid0 assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'000 - assign $0\main_sdphy_cmdr_source_last[0:0] $eq$ls180.v:4473$656_Y + assign $0\main_sdphy_cmdr_source_last[0:0] $eq$ls180.v:4469$655_Y assign $0\main_sdphy_cmdr_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_source_source_payload_data0 - assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4490$659_Y + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4486$658_Y assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 - attribute \src "ls180.v:4475.4-4489.7" - switch $and$ls180.v:4475$657_Y - attribute \src "ls180.v:4475.8-4475.69" + attribute \src "ls180.v:4471.4-4485.7" + switch $and$ls180.v:4471$656_Y + attribute \src "ls180.v:4471.8-4471.69" case 1'1 assign $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'1 - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4477$658_Y + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4473$657_Y assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:4479.5-4488.8" + attribute \src "ls180.v:4475.5-4484.8" switch \main_sdphy_cmdr_source_last - attribute \src "ls180.v:4479.9-4479.36" + attribute \src "ls180.v:4475.9-4475.36" case 1'1 assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1 - attribute \src "ls180.v:4481.6-4487.9" + attribute \src "ls180.v:4477.6-4483.9" switch \main_sdphy_cmdr_sink_last - attribute \src "ls180.v:4481.10-4481.35" + attribute \src "ls180.v:4477.10-4477.35" case 1'1 assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'011 - attribute \src "ls180.v:4485.10-4485.14" + attribute \src "ls180.v:4481.10-4481.14" case assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 end @@ -118342,9 +118293,9 @@ module \ls180 end case end - attribute \src "ls180.v:4492.4-4495.7" - switch $eq$ls180.v:4492$660_Y - attribute \src "ls180.v:4492.8-4492.41" + attribute \src "ls180.v:4488.4-4491.7" + switch $eq$ls180.v:4488$659_Y + attribute \src "ls180.v:4488.8-4488.41" case 1'1 assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1 assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'100 @@ -118355,15 +118306,15 @@ module \ls180 assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1 assign $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'1 assign $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'1 - attribute \src "ls180.v:4501.4-4507.7" + attribute \src "ls180.v:4497.4-4503.7" switch \main_sdphy_cmdr_pads_out_ready - attribute \src "ls180.v:4501.8-4501.38" + attribute \src "ls180.v:4497.8-4497.38" case 1'1 - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4502$661_Y + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4498$660_Y assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:4504.5-4506.8" - switch $eq$ls180.v:4504$662_Y - attribute \src "ls180.v:4504.9-4504.40" + attribute \src "ls180.v:4500.5-4502.8" + switch $eq$ls180.v:4500$661_Y + attribute \src "ls180.v:4500.9-4500.40" case 1'1 assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 case @@ -118375,9 +118326,9 @@ module \ls180 assign $0\main_sdphy_cmdr_source_valid[0:0] 1'1 assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'001 assign $0\main_sdphy_cmdr_source_last[0:0] 1'1 - attribute \src "ls180.v:4513.4-4515.7" - switch $and$ls180.v:4513$663_Y - attribute \src "ls180.v:4513.8-4513.69" + attribute \src "ls180.v:4509.4-4511.7" + switch $and$ls180.v:4509$662_Y + attribute \src "ls180.v:4509.8-4509.69" case 1'1 assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 case @@ -118388,9 +118339,9 @@ module \ls180 assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 500000 assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 - attribute \src "ls180.v:4522.4-4526.7" - switch $and$ls180.v:4522$665_Y - attribute \src "ls180.v:4522.8-4522.94" + attribute \src "ls180.v:4518.4-4522.7" + switch $and$ls180.v:4518$664_Y + attribute \src "ls180.v:4518.8-4518.94" case 1'1 assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'1 assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'1 @@ -118416,130 +118367,122 @@ module \ls180 update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] end - attribute \src "ls180.v:444.5-444.59" - process $proc$ls180.v:444$2920 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_source_first $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] - end - attribute \src "ls180.v:445.5-445.58" - process $proc$ls180.v:445$2921 + attribute \src "ls180.v:444.5-444.58" + process $proc$ls180.v:444$2918 assign { } { } assign $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] 1'0 sync always sync init update \main_sdram_bankmachine0_cmd_buffer_source_last $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] end - attribute \src "ls180.v:446.5-446.64" - process $proc$ls180.v:446$2922 + attribute \src "ls180.v:445.5-445.64" + process $proc$ls180.v:445$2919 assign { } { } assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] 1'0 sync always sync init update \main_sdram_bankmachine0_cmd_buffer_source_payload_we $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] end - attribute \src "ls180.v:447.12-447.74" - process $proc$ls180.v:447$2923 + attribute \src "ls180.v:446.12-446.74" + process $proc$ls180.v:446$2920 assign { } { } assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 sync always sync init update \main_sdram_bankmachine0_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] end - attribute \src "ls180.v:448.12-448.47" - process $proc$ls180.v:448$2924 + attribute \src "ls180.v:447.12-447.47" + process $proc$ls180.v:447$2921 assign { } { } assign $1\main_sdram_bankmachine0_row[12:0] 13'0000000000000 sync always sync init update \main_sdram_bankmachine0_row $1\main_sdram_bankmachine0_row[12:0] end - attribute \src "ls180.v:449.5-449.46" - process $proc$ls180.v:449$2925 + attribute \src "ls180.v:448.5-448.46" + process $proc$ls180.v:448$2922 assign { } { } assign $1\main_sdram_bankmachine0_row_opened[0:0] 1'0 sync always sync init update \main_sdram_bankmachine0_row_opened $1\main_sdram_bankmachine0_row_opened[0:0] end - attribute \src "ls180.v:451.5-451.44" - process $proc$ls180.v:451$2926 + attribute \src "ls180.v:450.5-450.44" + process $proc$ls180.v:450$2923 assign { } { } assign $1\main_sdram_bankmachine0_row_open[0:0] 1'0 sync always sync init update \main_sdram_bankmachine0_row_open $1\main_sdram_bankmachine0_row_open[0:0] end - attribute \src "ls180.v:452.5-452.45" - process $proc$ls180.v:452$2927 + attribute \src "ls180.v:451.5-451.45" + process $proc$ls180.v:451$2924 assign { } { } assign $1\main_sdram_bankmachine0_row_close[0:0] 1'0 sync always sync init update \main_sdram_bankmachine0_row_close $1\main_sdram_bankmachine0_row_close[0:0] end - attribute \src "ls180.v:453.5-453.54" - process $proc$ls180.v:453$2928 + attribute \src "ls180.v:452.5-452.54" + process $proc$ls180.v:452$2925 assign { } { } assign $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0 sync always sync init update \main_sdram_bankmachine0_row_col_n_addr_sel $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] end - attribute \src "ls180.v:455.32-455.76" - process $proc$ls180.v:455$2929 + attribute \src "ls180.v:454.32-454.76" + process $proc$ls180.v:454$2926 assign { } { } assign $1\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 sync always sync init update \main_sdram_bankmachine0_twtpcon_ready $1\main_sdram_bankmachine0_twtpcon_ready[0:0] end - attribute \src "ls180.v:456.11-456.55" - process $proc$ls180.v:456$2930 + attribute \src "ls180.v:455.11-455.55" + process $proc$ls180.v:455$2927 assign { } { } assign $1\main_sdram_bankmachine0_twtpcon_count[2:0] 3'000 sync always sync init update \main_sdram_bankmachine0_twtpcon_count $1\main_sdram_bankmachine0_twtpcon_count[2:0] end - attribute \src "ls180.v:4563.1-4590.4" - process $proc$ls180.v:4563$673 + attribute \src "ls180.v:4559.1-4586.4" + process $proc$ls180.v:4559$672 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } + assign $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0 assign { } { } - assign $0\main_sdphy_dataw_valid[0:0] 1'0 - assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 assign $0\main_sdphy_dataw_error[0:0] 1'0 assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0 - assign $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 + assign $0\main_sdphy_dataw_valid[0:0] 1'0 assign $0\builder_sdphy_sdphycrcr_next_state[0:0] \builder_sdphy_sdphycrcr_state - attribute \src "ls180.v:4571.2-4589.9" + attribute \src "ls180.v:4567.2-4585.9" switch \builder_sdphy_sdphycrcr_state attribute \src "ls180.v:0.0-0.0" case 1'1 assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'1 assign $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'1 - attribute \src "ls180.v:4576.4-4580.7" + attribute \src "ls180.v:4572.4-4576.7" switch \main_sdphy_dataw_crcr_source_source_valid0 - attribute \src "ls180.v:4576.8-4576.50" + attribute \src "ls180.v:4572.8-4572.50" case 1'1 - assign $0\main_sdphy_dataw_valid[0:0] $ne$ls180.v:4577$674_Y - assign $0\main_sdphy_dataw_error[0:0] $eq$ls180.v:4578$675_Y + assign $0\main_sdphy_dataw_valid[0:0] $ne$ls180.v:4573$673_Y + assign $0\main_sdphy_dataw_error[0:0] $eq$ls180.v:4574$674_Y assign $0\builder_sdphy_sdphycrcr_next_state[0:0] 1'0 case end attribute \src "ls180.v:0.0-0.0" case - attribute \src "ls180.v:4583.4-4587.7" + attribute \src "ls180.v:4579.4-4583.7" switch \main_sdphy_dataw_start - attribute \src "ls180.v:4583.8-4583.30" + attribute \src "ls180.v:4579.8-4579.30" case 1'1 assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'1 assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'1 @@ -118555,16 +118498,16 @@ module \ls180 update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] end - attribute \src "ls180.v:458.32-458.75" - process $proc$ls180.v:458$2931 + attribute \src "ls180.v:457.32-457.75" + process $proc$ls180.v:457$2928 assign { } { } assign $0\main_sdram_bankmachine0_trccon_ready[0:0] 1'1 sync always update \main_sdram_bankmachine0_trccon_ready $0\main_sdram_bankmachine0_trccon_ready[0:0] sync init end - attribute \src "ls180.v:4591.1-4663.4" - process $proc$ls180.v:4591$676 + attribute \src "ls180.v:4587.1-4659.4" + process $proc$ls180.v:4587$675 assign { } { } assign { } { } assign { } { } @@ -118574,7 +118517,6 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdphy_dataw_stop[0:0] 1'0 assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'0 assign { } { } assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 @@ -118583,27 +118525,28 @@ module \ls180 assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'0 assign $0\main_sdphy_dataw_sink_ready[0:0] 1'0 assign $0\main_sdphy_dataw_start[0:0] 1'0 + assign $0\main_sdphy_dataw_stop[0:0] 1'0 assign $0\builder_sdphy_fsm_next_state[2:0] \builder_sdphy_fsm_state - attribute \src "ls180.v:4602.2-4662.9" + attribute \src "ls180.v:4598.2-4658.9" switch \builder_sdphy_fsm_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1 assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 - attribute \src "ls180.v:4607.4-4609.7" + attribute \src "ls180.v:4603.4-4605.7" switch \main_sdphy_dataw_pads_out_ready - attribute \src "ls180.v:4607.8-4607.39" + attribute \src "ls180.v:4603.8-4603.39" case 1'1 assign $0\builder_sdphy_fsm_next_state[2:0] 3'010 case end attribute \src "ls180.v:0.0-0.0" case 3'010 - assign $0\main_sdphy_dataw_stop[0:0] $not$ls180.v:4612$677_Y + assign $0\main_sdphy_dataw_stop[0:0] $not$ls180.v:4608$676_Y assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1 - attribute \src "ls180.v:4615.4-4622.11" + attribute \src "ls180.v:4611.4-4618.11" switch \main_sdphy_dataw_count attribute \src "ls180.v:0.0-0.0" case 8'00000000 @@ -118613,24 +118556,24 @@ module \ls180 assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] \main_sdphy_dataw_sink_payload_data [3:0] case end - attribute \src "ls180.v:4623.4-4635.7" + attribute \src "ls180.v:4619.4-4631.7" switch \main_sdphy_dataw_pads_out_ready - attribute \src "ls180.v:4623.8-4623.39" + attribute \src "ls180.v:4619.8-4619.39" case 1'1 - assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] $add$ls180.v:4624$678_Y + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] $add$ls180.v:4620$677_Y assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4626.5-4634.8" - switch $eq$ls180.v:4626$679_Y - attribute \src "ls180.v:4626.9-4626.41" + attribute \src "ls180.v:4622.5-4630.8" + switch $eq$ls180.v:4622$678_Y + attribute \src "ls180.v:4622.9-4622.41" case 1'1 assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4629.6-4633.9" + attribute \src "ls180.v:4625.6-4629.9" switch \main_sdphy_dataw_sink_last - attribute \src "ls180.v:4629.10-4629.36" + attribute \src "ls180.v:4625.10-4625.36" case 1'1 assign $0\builder_sdphy_fsm_next_state[2:0] 3'011 - attribute \src "ls180.v:4631.10-4631.14" + attribute \src "ls180.v:4627.10-4627.14" case assign $0\main_sdphy_dataw_sink_ready[0:0] 1'1 end @@ -118643,9 +118586,9 @@ module \ls180 assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1 assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'1111 - attribute \src "ls180.v:4641.4-4644.7" + attribute \src "ls180.v:4637.4-4640.7" switch \main_sdphy_dataw_pads_out_ready - attribute \src "ls180.v:4641.8-4641.39" + attribute \src "ls180.v:4637.8-4637.39" case 1'1 assign $0\main_sdphy_dataw_start[0:0] 1'1 assign $0\builder_sdphy_fsm_next_state[2:0] 3'100 @@ -118654,13 +118597,13 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'100 assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 - attribute \src "ls180.v:4648.4-4653.7" + attribute \src "ls180.v:4644.4-4649.7" switch \main_sdphy_dataw_pads_out_ready - attribute \src "ls180.v:4648.8-4648.39" + attribute \src "ls180.v:4644.8-4644.39" case 1'1 - attribute \src "ls180.v:4649.5-4652.8" + attribute \src "ls180.v:4645.5-4648.8" switch \main_sdphy_dataw_pads_in_payload_data_i [0] - attribute \src "ls180.v:4649.9-4649.51" + attribute \src "ls180.v:4645.9-4645.51" case 1'1 assign $0\main_sdphy_dataw_sink_ready[0:0] 1'1 assign $0\builder_sdphy_fsm_next_state[2:0] 3'000 @@ -118672,9 +118615,9 @@ module \ls180 case assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4658.4-4660.7" - switch $and$ls180.v:4658$680_Y - attribute \src "ls180.v:4658.8-4658.71" + attribute \src "ls180.v:4654.4-4656.7" + switch $and$ls180.v:4654$679_Y + attribute \src "ls180.v:4654.8-4654.71" case 1'1 assign $0\builder_sdphy_fsm_next_state[2:0] 3'001 case @@ -118691,40 +118634,48 @@ module \ls180 update \main_sdphy_dataw_count_sdphy_fsm_next_value $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] update \main_sdphy_dataw_count_sdphy_fsm_next_value_ce $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] end - attribute \src "ls180.v:460.32-460.76" - process $proc$ls180.v:460$2932 + attribute \src "ls180.v:459.32-459.76" + process $proc$ls180.v:459$2929 assign { } { } assign $0\main_sdram_bankmachine0_trascon_ready[0:0] 1'1 sync always update \main_sdram_bankmachine0_trascon_ready $0\main_sdram_bankmachine0_trascon_ready[0:0] sync init end - attribute \src "ls180.v:466.5-466.51" - process $proc$ls180.v:466$2933 + attribute \src "ls180.v:465.5-465.51" + process $proc$ls180.v:465$2930 assign { } { } assign $1\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0 sync always sync init update \main_sdram_bankmachine1_req_wdata_ready $1\main_sdram_bankmachine1_req_wdata_ready[0:0] end - attribute \src "ls180.v:467.5-467.51" - process $proc$ls180.v:467$2934 + attribute \src "ls180.v:466.5-466.51" + process $proc$ls180.v:466$2931 assign { } { } assign $1\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0 sync always sync init update \main_sdram_bankmachine1_req_rdata_valid $1\main_sdram_bankmachine1_req_rdata_valid[0:0] end - attribute \src "ls180.v:469.5-469.47" - process $proc$ls180.v:469$2935 + attribute \src "ls180.v:468.5-468.47" + process $proc$ls180.v:468$2932 assign { } { } assign $1\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0 sync always sync init update \main_sdram_bankmachine1_refresh_gnt $1\main_sdram_bankmachine1_refresh_gnt[0:0] end - attribute \src "ls180.v:4697.1-4798.4" - process $proc$ls180.v:4697$688 + attribute \src "ls180.v:469.5-469.45" + process $proc$ls180.v:469$2933 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_valid $1\main_sdram_bankmachine1_cmd_valid[0:0] + end + attribute \src "ls180.v:4693.1-4794.4" + process $proc$ls180.v:4693$687 assign { } { } assign { } { } assign { } { } @@ -118740,10 +118691,6 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'0 - assign $0\main_sdphy_datar_source_valid[0:0] 1'0 - assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 - assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0 assign $0\main_sdphy_datar_source_last[0:0] 1'0 assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0 assign $0\main_sdphy_datar_source_payload_data[7:0] 8'00000000 @@ -118755,8 +118702,12 @@ module \ls180 assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'0 assign $0\main_sdphy_datar_sink_ready[0:0] 1'0 assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 0 + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'0 + assign $0\main_sdphy_datar_source_valid[0:0] 1'0 + assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 + assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0 assign $0\builder_sdphy_sdphydatar_next_state[2:0] \builder_sdphy_sdphydatar_state - attribute \src "ls180.v:4714.2-4797.9" + attribute \src "ls180.v:4710.2-4793.9" switch \builder_sdphy_sdphydatar_state attribute \src "ls180.v:0.0-0.0" case 3'001 @@ -118765,18 +118716,18 @@ module \ls180 assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'1 assign { } { } assign { } { } - assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:4724$690_Y + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:4720$689_Y assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 - attribute \src "ls180.v:4721.4-4723.7" + attribute \src "ls180.v:4717.4-4719.7" switch \main_sdphy_datar_datar_source_source_valid0 - attribute \src "ls180.v:4721.8-4721.51" + attribute \src "ls180.v:4717.8-4717.51" case 1'1 assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'010 case end - attribute \src "ls180.v:4726.4-4729.7" - switch $eq$ls180.v:4726$691_Y - attribute \src "ls180.v:4726.8-4726.42" + attribute \src "ls180.v:4722.4-4725.7" + switch $eq$ls180.v:4722$690_Y + attribute \src "ls180.v:4722.8-4722.42" case 1'1 assign $0\main_sdphy_datar_sink_ready[0:0] 1'1 assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'100 @@ -118787,48 +118738,48 @@ module \ls180 assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 assign $0\main_sdphy_datar_source_valid[0:0] \main_sdphy_datar_datar_source_source_valid0 assign $0\main_sdphy_datar_source_payload_status[2:0] 3'000 - assign $0\main_sdphy_datar_source_last[0:0] $eq$ls180.v:4735$694_Y + assign $0\main_sdphy_datar_source_last[0:0] $eq$ls180.v:4731$693_Y assign $0\main_sdphy_datar_source_payload_data[7:0] \main_sdphy_datar_datar_source_source_payload_data0 - assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:4756$696_Y + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:4752$695_Y assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 - attribute \src "ls180.v:4737.4-4755.7" + attribute \src "ls180.v:4733.4-4751.7" switch \main_sdphy_datar_source_valid - attribute \src "ls180.v:4737.8-4737.37" + attribute \src "ls180.v:4733.8-4733.37" case 1'1 - attribute \src "ls180.v:4738.5-4754.8" + attribute \src "ls180.v:4734.5-4750.8" switch \main_sdphy_datar_source_ready - attribute \src "ls180.v:4738.9-4738.38" + attribute \src "ls180.v:4734.9-4734.38" case 1'1 assign $0\main_sdphy_datar_datar_source_source_ready0[0:0] 1'1 - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:4740$695_Y + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:4736$694_Y assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:4742.6-4751.9" + attribute \src "ls180.v:4738.6-4747.9" switch \main_sdphy_datar_source_last - attribute \src "ls180.v:4742.10-4742.38" + attribute \src "ls180.v:4738.10-4738.38" case 1'1 assign $0\main_sdphy_datar_sink_ready[0:0] 1'1 - attribute \src "ls180.v:4744.7-4750.10" + attribute \src "ls180.v:4740.7-4746.10" switch \main_sdphy_datar_sink_last - attribute \src "ls180.v:4744.11-4744.37" + attribute \src "ls180.v:4740.11-4740.37" case 1'1 assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'011 - attribute \src "ls180.v:4748.11-4748.15" + attribute \src "ls180.v:4744.11-4744.15" case assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 end case end - attribute \src "ls180.v:4752.9-4752.13" + attribute \src "ls180.v:4748.9-4748.13" case assign $0\main_sdphy_datar_stop[0:0] 1'1 end case end - attribute \src "ls180.v:4758.4-4761.7" - switch $eq$ls180.v:4758$697_Y - attribute \src "ls180.v:4758.8-4758.42" + attribute \src "ls180.v:4754.4-4757.7" + switch $eq$ls180.v:4754$696_Y + attribute \src "ls180.v:4754.8-4754.42" case 1'1 assign $0\main_sdphy_datar_sink_ready[0:0] 1'1 assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'100 @@ -118837,15 +118788,15 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'011 assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 - attribute \src "ls180.v:4765.4-4771.7" + attribute \src "ls180.v:4761.4-4767.7" switch \main_sdphy_datar_pads_out_ready - attribute \src "ls180.v:4765.8-4765.39" + attribute \src "ls180.v:4761.8-4761.39" case 1'1 - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:4766$698_Y + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:4762$697_Y assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:4768.5-4770.8" - switch $eq$ls180.v:4768$699_Y - attribute \src "ls180.v:4768.9-4768.42" + attribute \src "ls180.v:4764.5-4766.8" + switch $eq$ls180.v:4764$698_Y + attribute \src "ls180.v:4764.9-4764.42" case 1'1 assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 case @@ -118857,9 +118808,9 @@ module \ls180 assign $0\main_sdphy_datar_source_valid[0:0] 1'1 assign $0\main_sdphy_datar_source_payload_status[2:0] 3'001 assign $0\main_sdphy_datar_source_last[0:0] 1'1 - attribute \src "ls180.v:4777.4-4779.7" - switch $and$ls180.v:4777$700_Y - attribute \src "ls180.v:4777.8-4777.71" + attribute \src "ls180.v:4773.4-4775.7" + switch $and$ls180.v:4773$699_Y + attribute \src "ls180.v:4773.8-4773.71" case 1'1 assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 case @@ -118868,14 +118819,14 @@ module \ls180 case assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:4784.4-4795.7" - switch $and$ls180.v:4784$701_Y - attribute \src "ls180.v:4784.8-4784.71" + attribute \src "ls180.v:4780.4-4791.7" + switch $and$ls180.v:4780$700_Y + attribute \src "ls180.v:4780.8-4780.71" case 1'1 assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 - attribute \src "ls180.v:4786.5-4794.8" + attribute \src "ls180.v:4782.5-4790.8" switch \main_sdphy_datar_pads_out_ready - attribute \src "ls180.v:4786.9-4786.40" + attribute \src "ls180.v:4782.9-4782.40" case 1'1 assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 500000 assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 @@ -118907,159 +118858,151 @@ module \ls180 update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] end attribute \src "ls180.v:470.5-470.45" - process $proc$ls180.v:470$2936 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_valid $1\main_sdram_bankmachine1_cmd_valid[0:0] - end - attribute \src "ls180.v:471.5-471.45" - process $proc$ls180.v:471$2937 + process $proc$ls180.v:470$2934 assign { } { } assign $1\main_sdram_bankmachine1_cmd_ready[0:0] 1'0 sync always sync init update \main_sdram_bankmachine1_cmd_ready $1\main_sdram_bankmachine1_cmd_ready[0:0] end - attribute \src "ls180.v:472.12-472.57" - process $proc$ls180.v:472$2938 + attribute \src "ls180.v:471.12-471.57" + process $proc$ls180.v:471$2935 assign { } { } assign $1\main_sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000 sync always sync init update \main_sdram_bankmachine1_cmd_payload_a $1\main_sdram_bankmachine1_cmd_payload_a[12:0] end - attribute \src "ls180.v:474.5-474.51" - process $proc$ls180.v:474$2939 + attribute \src "ls180.v:473.5-473.51" + process $proc$ls180.v:473$2936 assign { } { } assign $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'0 sync always sync init update \main_sdram_bankmachine1_cmd_payload_cas $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] end - attribute \src "ls180.v:475.5-475.51" - process $proc$ls180.v:475$2940 + attribute \src "ls180.v:474.5-474.51" + process $proc$ls180.v:474$2937 assign { } { } assign $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'0 sync always sync init update \main_sdram_bankmachine1_cmd_payload_ras $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] end - attribute \src "ls180.v:476.5-476.50" - process $proc$ls180.v:476$2941 + attribute \src "ls180.v:475.5-475.50" + process $proc$ls180.v:475$2938 assign { } { } assign $1\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'0 sync always sync init update \main_sdram_bankmachine1_cmd_payload_we $1\main_sdram_bankmachine1_cmd_payload_we[0:0] end - attribute \src "ls180.v:477.5-477.54" - process $proc$ls180.v:477$2942 + attribute \src "ls180.v:476.5-476.54" + process $proc$ls180.v:476$2939 assign { } { } assign $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0 sync always sync init update \main_sdram_bankmachine1_cmd_payload_is_cmd $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] end - attribute \src "ls180.v:478.5-478.55" - process $proc$ls180.v:478$2943 + attribute \src "ls180.v:477.5-477.55" + process $proc$ls180.v:477$2940 assign { } { } assign $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0 sync always sync init update \main_sdram_bankmachine1_cmd_payload_is_read $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] end - attribute \src "ls180.v:479.5-479.56" - process $proc$ls180.v:479$2944 + attribute \src "ls180.v:478.5-478.56" + process $proc$ls180.v:478$2941 assign { } { } assign $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0 sync always sync init update \main_sdram_bankmachine1_cmd_payload_is_write $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] end - attribute \src "ls180.v:480.5-480.50" - process $proc$ls180.v:480$2945 + attribute \src "ls180.v:479.5-479.50" + process $proc$ls180.v:479$2942 assign { } { } assign $1\main_sdram_bankmachine1_auto_precharge[0:0] 1'0 sync always sync init update \main_sdram_bankmachine1_auto_precharge $1\main_sdram_bankmachine1_auto_precharge[0:0] end - attribute \src "ls180.v:483.5-483.67" - process $proc$ls180.v:483$2946 + attribute \src "ls180.v:482.5-482.67" + process $proc$ls180.v:482$2943 assign { } { } assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] 1'0 sync always update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] sync init end - attribute \src "ls180.v:484.5-484.66" - process $proc$ls180.v:484$2947 + attribute \src "ls180.v:483.5-483.66" + process $proc$ls180.v:483$2944 assign { } { } assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] 1'0 sync always update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] sync init end - attribute \src "ls180.v:4856.1-4863.4" - process $proc$ls180.v:4856$823 + attribute \src "ls180.v:4852.1-4859.4" + process $proc$ls180.v:4852$822 assign { } { } assign $0\main_sdcore_crc7_inserter_crc[6:0] 7'0000000 - attribute \src "ls180.v:4858.2-4862.5" + attribute \src "ls180.v:4854.2-4858.5" switch \main_sdcore_crc7_inserter_enable - attribute \src "ls180.v:4858.6-4858.38" + attribute \src "ls180.v:4854.6-4854.38" case 1'1 assign $0\main_sdcore_crc7_inserter_crc[6:0] \main_sdcore_crc7_inserter_crcreg40 - attribute \src "ls180.v:4860.6-4860.10" + attribute \src "ls180.v:4856.6-4856.10" case assign $0\main_sdcore_crc7_inserter_crc[6:0] \main_sdcore_crc7_inserter_crcreg0 end sync always update \main_sdcore_crc7_inserter_crc $0\main_sdcore_crc7_inserter_crc[6:0] end - attribute \src "ls180.v:4878.1-4885.4" - process $proc$ls180.v:4878$846 + attribute \src "ls180.v:4874.1-4881.4" + process $proc$ls180.v:4874$845 assign { } { } assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:4880.2-4884.5" + attribute \src "ls180.v:4876.2-4880.5" switch \main_sdcore_crc16_inserter_crc0_enable - attribute \src "ls180.v:4880.6-4880.44" + attribute \src "ls180.v:4876.6-4876.44" case 1'1 assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] \main_sdcore_crc16_inserter_crc0_crcreg2 - attribute \src "ls180.v:4882.6-4882.10" + attribute \src "ls180.v:4878.6-4878.10" case assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] \main_sdcore_crc16_inserter_crc0_crcreg0 end sync always update \main_sdcore_crc16_inserter_crc0_crc $0\main_sdcore_crc16_inserter_crc0_crc[15:0] end - attribute \src "ls180.v:4888.1-4895.4" - process $proc$ls180.v:4888$857 + attribute \src "ls180.v:4884.1-4891.4" + process $proc$ls180.v:4884$856 assign { } { } assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:4890.2-4894.5" + attribute \src "ls180.v:4886.2-4890.5" switch \main_sdcore_crc16_inserter_crc1_enable - attribute \src "ls180.v:4890.6-4890.44" + attribute \src "ls180.v:4886.6-4886.44" case 1'1 assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] \main_sdcore_crc16_inserter_crc1_crcreg2 - attribute \src "ls180.v:4892.6-4892.10" + attribute \src "ls180.v:4888.6-4888.10" case assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] \main_sdcore_crc16_inserter_crc1_crcreg0 end sync always update \main_sdcore_crc16_inserter_crc1_crc $0\main_sdcore_crc16_inserter_crc1_crc[15:0] end - attribute \src "ls180.v:4898.1-4905.4" - process $proc$ls180.v:4898$868 + attribute \src "ls180.v:4894.1-4901.4" + process $proc$ls180.v:4894$867 assign { } { } assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:4900.2-4904.5" + attribute \src "ls180.v:4896.2-4900.5" switch \main_sdcore_crc16_inserter_crc2_enable - attribute \src "ls180.v:4900.6-4900.44" + attribute \src "ls180.v:4896.6-4896.44" case 1'1 assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] \main_sdcore_crc16_inserter_crc2_crcreg2 - attribute \src "ls180.v:4902.6-4902.10" + attribute \src "ls180.v:4898.6-4898.10" case assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] \main_sdcore_crc16_inserter_crc2_crcreg0 end @@ -119067,31 +119010,31 @@ module \ls180 update \main_sdcore_crc16_inserter_crc2_crc $0\main_sdcore_crc16_inserter_crc2_crc[15:0] end attribute \src "ls180.v:49.5-49.42" - process $proc$ls180.v:49$2767 + process $proc$ls180.v:49$2765 assign { } { } assign $1\main_libresocsim_reset_storage[0:0] 1'0 sync always sync init update \main_libresocsim_reset_storage $1\main_libresocsim_reset_storage[0:0] end - attribute \src "ls180.v:4908.1-4915.4" - process $proc$ls180.v:4908$879 + attribute \src "ls180.v:4904.1-4911.4" + process $proc$ls180.v:4904$878 assign { } { } assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:4910.2-4914.5" + attribute \src "ls180.v:4906.2-4910.5" switch \main_sdcore_crc16_inserter_crc3_enable - attribute \src "ls180.v:4910.6-4910.44" + attribute \src "ls180.v:4906.6-4906.44" case 1'1 assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] \main_sdcore_crc16_inserter_crc3_crcreg2 - attribute \src "ls180.v:4912.6-4912.10" + attribute \src "ls180.v:4908.6-4908.10" case assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] \main_sdcore_crc16_inserter_crc3_crcreg0 end sync always update \main_sdcore_crc16_inserter_crc3_crc $0\main_sdcore_crc16_inserter_crc3_crc[15:0] end - attribute \src "ls180.v:4916.1-4995.4" - process $proc$ls180.v:4916$880 + attribute \src "ls180.v:4912.1-4991.4" + process $proc$ls180.v:4912$879 assign { } { } assign { } { } assign { } { } @@ -119107,36 +119050,36 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdcore_crc16_inserter_source_valid[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 - assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] 8'00000000 - assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0 assign { } { } assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0 assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] 16'0000000000000000 assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'0 assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0 assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'0 assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_source_valid[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] 8'00000000 assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] \builder_sdcore_crcupstreaminserter_state - attribute \src "ls180.v:4933.2-4994.9" + attribute \src "ls180.v:4929.2-4990.9" switch \builder_sdcore_crcupstreaminserter_state attribute \src "ls180.v:0.0-0.0" case 1'1 assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 assign $0\main_sdcore_crc16_inserter_source_valid[0:0] 1'1 - attribute \src "ls180.v:4937.4-4939.7" - switch $eq$ls180.v:4937$881_Y - attribute \src "ls180.v:4937.8-4937.48" + attribute \src "ls180.v:4933.4-4935.7" + switch $eq$ls180.v:4933$880_Y + attribute \src "ls180.v:4933.8-4933.48" case 1'1 assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'1 case end - attribute \src "ls180.v:4940.4-4965.11" + attribute \src "ls180.v:4936.4-4961.11" switch \main_sdcore_crc16_inserter_cnt attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -119164,18 +119107,18 @@ module \ls180 assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [1] \main_sdcore_crc16_inserter_crctmp2 [1] \main_sdcore_crc16_inserter_crctmp1 [1] \main_sdcore_crc16_inserter_crctmp0 [1] \main_sdcore_crc16_inserter_crctmp3 [0] \main_sdcore_crc16_inserter_crctmp2 [0] \main_sdcore_crc16_inserter_crctmp1 [0] \main_sdcore_crc16_inserter_crctmp0 [0] } case end - attribute \src "ls180.v:4966.4-4973.7" + attribute \src "ls180.v:4962.4-4969.7" switch \main_sdcore_crc16_inserter_source_ready - attribute \src "ls180.v:4966.8-4966.47" + attribute \src "ls180.v:4962.8-4962.47" case 1'1 - attribute \src "ls180.v:4967.5-4972.8" - switch $eq$ls180.v:4967$882_Y - attribute \src "ls180.v:4967.9-4967.49" + attribute \src "ls180.v:4963.5-4968.8" + switch $eq$ls180.v:4963$881_Y + attribute \src "ls180.v:4963.9-4963.49" case 1'1 assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'0 - attribute \src "ls180.v:4969.9-4969.13" + attribute \src "ls180.v:4965.9-4965.13" case - assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] $add$ls180.v:4970$883_Y + assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] $add$ls180.v:4966$882_Y assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'1 end case @@ -119194,9 +119137,9 @@ module \ls180 assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'1 assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] \main_sdcore_crc16_inserter_crc3_crc assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'1 - attribute \src "ls180.v:4988.4-4992.7" - switch $and$ls180.v:4988$885_Y - attribute \src "ls180.v:4988.8-4988.128" + attribute \src "ls180.v:4984.4-4988.7" + switch $and$ls180.v:4984$884_Y + attribute \src "ls180.v:4984.8-4984.128" case 1'1 assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'1 assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 @@ -119221,21 +119164,29 @@ module \ls180 update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] end - attribute \src "ls180.v:499.11-499.68" - process $proc$ls180.v:499$2948 + attribute \src "ls180.v:498.11-498.68" + process $proc$ls180.v:498$2945 assign { } { } assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] 4'0000 sync always sync init update \main_sdram_bankmachine1_cmd_buffer_lookahead_level $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] end - attribute \src "ls180.v:4996.1-5001.4" - process $proc$ls180.v:4996$886 + attribute \src "ls180.v:499.5-499.64" + process $proc$ls180.v:499$2946 + assign { } { } + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] 1'0 + sync always + update \main_sdram_bankmachine1_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] + sync init + end + attribute \src "ls180.v:4992.1-4997.4" + process $proc$ls180.v:4992$885 assign { } { } assign $0\main_sdcore_crc16_checker_valid[0:0] 1'0 - attribute \src "ls180.v:4998.2-5000.5" - switch $and$ls180.v:4998$893_Y - attribute \src "ls180.v:4998.6-4998.301" + attribute \src "ls180.v:4994.2-4996.5" + switch $and$ls180.v:4994$892_Y + attribute \src "ls180.v:4994.6-4994.301" case 1'1 assign $0\main_sdcore_crc16_checker_valid[0:0] 1'1 case @@ -119244,31 +119195,31 @@ module \ls180 update \main_sdcore_crc16_checker_valid $0\main_sdcore_crc16_checker_valid[0:0] end attribute \src "ls180.v:50.5-50.37" - process $proc$ls180.v:50$2768 + process $proc$ls180.v:50$2766 assign { } { } assign $1\main_libresocsim_reset_re[0:0] 1'0 sync always sync init update \main_libresocsim_reset_re $1\main_libresocsim_reset_re[0:0] end - attribute \src "ls180.v:500.5-500.64" - process $proc$ls180.v:500$2949 + attribute \src "ls180.v:500.11-500.70" + process $proc$ls180.v:500$2947 assign { } { } - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] 1'0 + assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] 3'000 sync always - update \main_sdram_bankmachine1_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] sync init + update \main_sdram_bankmachine1_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] end - attribute \src "ls180.v:5004.1-5011.4" - process $proc$ls180.v:5004$895 + attribute \src "ls180.v:5000.1-5007.4" + process $proc$ls180.v:5000$894 assign { } { } assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0 - attribute \src "ls180.v:5006.2-5010.5" - switch $eq$ls180.v:5006$896_Y - attribute \src "ls180.v:5006.6-5006.45" + attribute \src "ls180.v:5002.2-5006.5" + switch $eq$ls180.v:5002$895_Y + attribute \src "ls180.v:5002.6-5002.45" case 1'1 assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'1 - attribute \src "ls180.v:5008.6-5008.10" + attribute \src "ls180.v:5004.6-5004.10" case assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0 end @@ -119276,84 +119227,76 @@ module \ls180 update \main_sdcore_crc16_checker_crc0_clr $0\main_sdcore_crc16_checker_crc0_clr[0:0] end attribute \src "ls180.v:501.11-501.70" - process $proc$ls180.v:501$2950 + process $proc$ls180.v:501$2948 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] 3'000 sync always sync init - update \main_sdram_bankmachine1_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] + update \main_sdram_bankmachine1_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] end - attribute \src "ls180.v:5014.1-5021.4" - process $proc$ls180.v:5014$898 + attribute \src "ls180.v:5010.1-5017.4" + process $proc$ls180.v:5010$897 assign { } { } assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0 - attribute \src "ls180.v:5016.2-5020.5" - switch $eq$ls180.v:5016$899_Y - attribute \src "ls180.v:5016.6-5016.45" + attribute \src "ls180.v:5012.2-5016.5" + switch $eq$ls180.v:5012$898_Y + attribute \src "ls180.v:5012.6-5012.45" case 1'1 assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'1 - attribute \src "ls180.v:5018.6-5018.10" + attribute \src "ls180.v:5014.6-5014.10" case assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0 end sync always update \main_sdcore_crc16_checker_crc1_clr $0\main_sdcore_crc16_checker_crc1_clr[0:0] end - attribute \src "ls180.v:502.11-502.70" - process $proc$ls180.v:502$2951 + attribute \src "ls180.v:502.11-502.73" + process $proc$ls180.v:502$2949 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 sync always sync init - update \main_sdram_bankmachine1_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] + update \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "ls180.v:5024.1-5031.4" - process $proc$ls180.v:5024$901 + attribute \src "ls180.v:5020.1-5027.4" + process $proc$ls180.v:5020$900 assign { } { } assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0 - attribute \src "ls180.v:5026.2-5030.5" - switch $eq$ls180.v:5026$902_Y - attribute \src "ls180.v:5026.6-5026.45" + attribute \src "ls180.v:5022.2-5026.5" + switch $eq$ls180.v:5022$901_Y + attribute \src "ls180.v:5022.6-5022.45" case 1'1 assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'1 - attribute \src "ls180.v:5028.6-5028.10" + attribute \src "ls180.v:5024.6-5024.10" case assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0 end sync always update \main_sdcore_crc16_checker_crc2_clr $0\main_sdcore_crc16_checker_crc2_clr[0:0] end - attribute \src "ls180.v:503.11-503.73" - process $proc$ls180.v:503$2952 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] - end - attribute \src "ls180.v:5034.1-5041.4" - process $proc$ls180.v:5034$904 + attribute \src "ls180.v:5030.1-5037.4" + process $proc$ls180.v:5030$903 assign { } { } assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0 - attribute \src "ls180.v:5036.2-5040.5" - switch $eq$ls180.v:5036$905_Y - attribute \src "ls180.v:5036.6-5036.45" + attribute \src "ls180.v:5032.2-5036.5" + switch $eq$ls180.v:5032$904_Y + attribute \src "ls180.v:5032.6-5032.45" case 1'1 assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'1 - attribute \src "ls180.v:5038.6-5038.10" + attribute \src "ls180.v:5034.6-5034.10" case assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0 end sync always update \main_sdcore_crc16_checker_crc3_clr $0\main_sdcore_crc16_checker_crc3_clr[0:0] end - attribute \src "ls180.v:5043.1-5048.4" - process $proc$ls180.v:5043$906 + attribute \src "ls180.v:5039.1-5044.4" + process $proc$ls180.v:5039$905 assign { } { } assign $0\main_sdcore_crc16_checker_source_valid[0:0] 1'0 - attribute \src "ls180.v:5045.2-5047.5" - switch $and$ls180.v:5045$908_Y - attribute \src "ls180.v:5045.6-5045.85" + attribute \src "ls180.v:5041.2-5043.5" + switch $and$ls180.v:5041$907_Y + attribute \src "ls180.v:5041.6-5041.85" case 1'1 assign $0\main_sdcore_crc16_checker_source_valid[0:0] 1'1 case @@ -119361,89 +119304,88 @@ module \ls180 sync always update \main_sdcore_crc16_checker_source_valid $0\main_sdcore_crc16_checker_source_valid[0:0] end - attribute \src "ls180.v:5049.1-5056.4" - process $proc$ls180.v:5049$909 + attribute \src "ls180.v:5045.1-5052.4" + process $proc$ls180.v:5045$908 assign { } { } assign $0\main_sdcore_crc16_checker_sink_ready[0:0] 1'0 - attribute \src "ls180.v:5051.2-5055.5" - switch $lt$ls180.v:5051$910_Y - attribute \src "ls180.v:5051.6-5051.44" + attribute \src "ls180.v:5047.2-5051.5" + switch $lt$ls180.v:5047$909_Y + attribute \src "ls180.v:5047.6-5047.44" case 1'1 assign $0\main_sdcore_crc16_checker_sink_ready[0:0] 1'1 - attribute \src "ls180.v:5053.6-5053.10" + attribute \src "ls180.v:5049.6-5049.10" case assign $0\main_sdcore_crc16_checker_sink_ready[0:0] \main_sdcore_crc16_checker_source_ready end sync always update \main_sdcore_crc16_checker_sink_ready $0\main_sdcore_crc16_checker_sink_ready[0:0] end - attribute \src "ls180.v:5060.1-5067.4" - process $proc$ls180.v:5060$921 + attribute \src "ls180.v:5056.1-5063.4" + process $proc$ls180.v:5056$920 assign { } { } assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5062.2-5066.5" + attribute \src "ls180.v:5058.2-5062.5" switch \main_sdcore_crc16_checker_crc0_enable - attribute \src "ls180.v:5062.6-5062.43" + attribute \src "ls180.v:5058.6-5058.43" case 1'1 assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] \main_sdcore_crc16_checker_crc0_crcreg2 - attribute \src "ls180.v:5064.6-5064.10" + attribute \src "ls180.v:5060.6-5060.10" case assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] \main_sdcore_crc16_checker_crc0_crcreg0 end sync always update \main_sdcore_crc16_checker_crc0_crc $0\main_sdcore_crc16_checker_crc0_crc[15:0] end - attribute \src "ls180.v:5070.1-5077.4" - process $proc$ls180.v:5070$932 + attribute \src "ls180.v:5066.1-5073.4" + process $proc$ls180.v:5066$931 assign { } { } assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5072.2-5076.5" + attribute \src "ls180.v:5068.2-5072.5" switch \main_sdcore_crc16_checker_crc1_enable - attribute \src "ls180.v:5072.6-5072.43" + attribute \src "ls180.v:5068.6-5068.43" case 1'1 assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] \main_sdcore_crc16_checker_crc1_crcreg2 - attribute \src "ls180.v:5074.6-5074.10" + attribute \src "ls180.v:5070.6-5070.10" case assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] \main_sdcore_crc16_checker_crc1_crcreg0 end sync always update \main_sdcore_crc16_checker_crc1_crc $0\main_sdcore_crc16_checker_crc1_crc[15:0] end - attribute \src "ls180.v:5080.1-5087.4" - process $proc$ls180.v:5080$943 + attribute \src "ls180.v:5076.1-5083.4" + process $proc$ls180.v:5076$942 assign { } { } assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5082.2-5086.5" + attribute \src "ls180.v:5078.2-5082.5" switch \main_sdcore_crc16_checker_crc2_enable - attribute \src "ls180.v:5082.6-5082.43" + attribute \src "ls180.v:5078.6-5078.43" case 1'1 assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] \main_sdcore_crc16_checker_crc2_crcreg2 - attribute \src "ls180.v:5084.6-5084.10" + attribute \src "ls180.v:5080.6-5080.10" case assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] \main_sdcore_crc16_checker_crc2_crcreg0 end sync always update \main_sdcore_crc16_checker_crc2_crc $0\main_sdcore_crc16_checker_crc2_crc[15:0] end - attribute \src "ls180.v:5090.1-5097.4" - process $proc$ls180.v:5090$954 + attribute \src "ls180.v:5086.1-5093.4" + process $proc$ls180.v:5086$953 assign { } { } assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5092.2-5096.5" + attribute \src "ls180.v:5088.2-5092.5" switch \main_sdcore_crc16_checker_crc3_enable - attribute \src "ls180.v:5092.6-5092.43" + attribute \src "ls180.v:5088.6-5088.43" case 1'1 assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] \main_sdcore_crc16_checker_crc3_crcreg2 - attribute \src "ls180.v:5094.6-5094.10" + attribute \src "ls180.v:5090.6-5090.10" case assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] \main_sdcore_crc16_checker_crc3_crcreg0 end sync always update \main_sdcore_crc16_checker_crc3_crc $0\main_sdcore_crc16_checker_crc3_crc[15:0] end - attribute \src "ls180.v:5098.1-5288.4" - process $proc$ls180.v:5098$955 - assign { } { } + attribute \src "ls180.v:5094.1-5284.4" + process $proc$ls180.v:5094$954 assign { } { } assign { } { } assign { } { } @@ -119483,9 +119425,6 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 - assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'0 - assign $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0 assign $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'0 assign $0\main_sdphy_cmdw_sink_valid[0:0] 1'0 assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000 @@ -119521,13 +119460,17 @@ module \ls180 assign $0\main_sdphy_cmdr_sink_last[0:0] 1'0 assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000000 assign $0\main_sdphy_cmdr_source_ready[0:0] 1'0 + assign { } { } + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'0 + assign $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0 assign $0\builder_sdcore_fsm_next_state[2:0] \builder_sdcore_fsm_state - attribute \src "ls180.v:5139.2-5287.9" + attribute \src "ls180.v:5135.2-5283.9" switch \builder_sdcore_fsm_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\main_sdphy_cmdw_sink_valid[0:0] 1'1 - attribute \src "ls180.v:5142.4-5162.11" + attribute \src "ls180.v:5138.4-5158.11" switch \main_sdcore_cmd_count attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -119547,27 +119490,27 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'101 assign $0\main_sdphy_cmdw_sink_payload_data[7:0] { \main_sdcore_crc7_inserter_crc 1'1 } - assign $0\main_sdphy_cmdw_sink_last[0:0] $eq$ls180.v:5160$956_Y + assign $0\main_sdphy_cmdw_sink_last[0:0] $eq$ls180.v:5156$955_Y case end - attribute \src "ls180.v:5163.4-5175.7" - switch $and$ls180.v:5163$957_Y - attribute \src "ls180.v:5163.8-5163.65" + attribute \src "ls180.v:5159.4-5171.7" + switch $and$ls180.v:5159$956_Y + attribute \src "ls180.v:5159.8-5159.65" case 1'1 - assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] $add$ls180.v:5164$958_Y + assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] $add$ls180.v:5160$957_Y assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'1 - attribute \src "ls180.v:5166.5-5174.8" - switch $eq$ls180.v:5166$959_Y - attribute \src "ls180.v:5166.9-5166.40" + attribute \src "ls180.v:5162.5-5170.8" + switch $eq$ls180.v:5162$958_Y + attribute \src "ls180.v:5162.9-5162.40" case 1'1 - attribute \src "ls180.v:5167.6-5173.9" - switch $eq$ls180.v:5167$960_Y - attribute \src "ls180.v:5167.10-5167.40" + attribute \src "ls180.v:5163.6-5169.9" + switch $eq$ls180.v:5163$959_Y + attribute \src "ls180.v:5163.10-5163.40" case 1'1 assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'1 assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1 assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 - attribute \src "ls180.v:5171.10-5171.14" + attribute \src "ls180.v:5167.10-5167.14" case assign $0\builder_sdcore_fsm_next_state[2:0] 3'010 end @@ -119578,52 +119521,52 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'010 assign $0\main_sdphy_cmdr_sink_valid[0:0] 1'1 - assign $0\main_sdphy_cmdr_sink_last[0:0] $eq$ls180.v:5179$961_Y + assign $0\main_sdphy_cmdr_sink_last[0:0] $eq$ls180.v:5175$960_Y assign $0\main_sdphy_cmdr_source_ready[0:0] 1'1 - attribute \src "ls180.v:5180.4-5184.7" - switch $eq$ls180.v:5180$962_Y - attribute \src "ls180.v:5180.8-5180.38" + attribute \src "ls180.v:5176.4-5180.7" + switch $eq$ls180.v:5176$961_Y + attribute \src "ls180.v:5176.8-5176.38" case 1'1 assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00010001 - attribute \src "ls180.v:5182.8-5182.12" + attribute \src "ls180.v:5178.8-5178.12" case assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000110 end - attribute \src "ls180.v:5186.4-5207.7" + attribute \src "ls180.v:5182.4-5203.7" switch \main_sdphy_cmdr_source_valid - attribute \src "ls180.v:5186.8-5186.36" + attribute \src "ls180.v:5182.8-5182.36" case 1'1 - attribute \src "ls180.v:5187.5-5206.8" - switch $eq$ls180.v:5187$963_Y - attribute \src "ls180.v:5187.9-5187.56" + attribute \src "ls180.v:5183.5-5202.8" + switch $eq$ls180.v:5183$962_Y + attribute \src "ls180.v:5183.9-5183.56" case 1'1 assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'1 assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'1 assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 - attribute \src "ls180.v:5191.9-5191.13" + attribute \src "ls180.v:5187.9-5187.13" case - attribute \src "ls180.v:5192.6-5205.9" + attribute \src "ls180.v:5188.6-5201.9" switch \main_sdphy_cmdr_source_last - attribute \src "ls180.v:5192.10-5192.37" + attribute \src "ls180.v:5188.10-5188.37" case 1'1 - attribute \src "ls180.v:5193.7-5201.10" - switch $eq$ls180.v:5193$964_Y - attribute \src "ls180.v:5193.11-5193.42" + attribute \src "ls180.v:5189.7-5197.10" + switch $eq$ls180.v:5189$963_Y + attribute \src "ls180.v:5189.11-5189.42" case 1'1 assign $0\builder_sdcore_fsm_next_state[2:0] 3'011 - attribute \src "ls180.v:5195.11-5195.15" + attribute \src "ls180.v:5191.11-5191.15" case - attribute \src "ls180.v:5196.8-5200.11" - switch $eq$ls180.v:5196$965_Y - attribute \src "ls180.v:5196.12-5196.43" + attribute \src "ls180.v:5192.8-5196.11" + switch $eq$ls180.v:5192$964_Y + attribute \src "ls180.v:5192.12-5192.43" case 1'1 assign $0\builder_sdcore_fsm_next_state[2:0] 3'100 - attribute \src "ls180.v:5198.12-5198.16" + attribute \src "ls180.v:5194.12-5194.16" case assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 end end - attribute \src "ls180.v:5202.10-5202.14" + attribute \src "ls180.v:5198.10-5198.14" case assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] { \main_sdcore_cmd_response_status [119:0] \main_sdphy_cmdr_source_payload_data } assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'1 @@ -119639,28 +119582,28 @@ module \ls180 assign $0\main_sdphy_dataw_sink_last[0:0] \main_sdcore_crc16_inserter_source_last assign $0\main_sdphy_dataw_sink_payload_data[7:0] \main_sdcore_crc16_inserter_source_payload_data assign $0\main_sdphy_datar_source_ready[0:0] 1'1 - attribute \src "ls180.v:5215.4-5221.7" - switch $and$ls180.v:5215$967_Y - attribute \src "ls180.v:5215.8-5215.98" + attribute \src "ls180.v:5211.4-5217.7" + switch $and$ls180.v:5211$966_Y + attribute \src "ls180.v:5211.8-5211.98" case 1'1 - assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5216$968_Y + assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5212$967_Y assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 - attribute \src "ls180.v:5218.5-5220.8" - switch $eq$ls180.v:5218$970_Y - attribute \src "ls180.v:5218.9-5218.77" + attribute \src "ls180.v:5214.5-5216.8" + switch $eq$ls180.v:5214$969_Y + attribute \src "ls180.v:5214.9-5214.77" case 1'1 assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 case end case end - attribute \src "ls180.v:5223.4-5228.7" + attribute \src "ls180.v:5219.4-5224.7" switch \main_sdphy_datar_source_valid - attribute \src "ls180.v:5223.8-5223.37" + attribute \src "ls180.v:5219.8-5219.37" case 1'1 - attribute \src "ls180.v:5224.5-5227.8" - switch $ne$ls180.v:5224$971_Y - attribute \src "ls180.v:5224.9-5224.57" + attribute \src "ls180.v:5220.5-5223.8" + switch $ne$ls180.v:5220$970_Y + attribute \src "ls180.v:5220.9-5220.57" case 1'1 assign $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'1 assign $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'1 @@ -119672,42 +119615,42 @@ module \ls180 case 3'100 assign $0\main_sdphy_datar_sink_valid[0:0] 1'1 assign $0\main_sdphy_datar_sink_payload_block_length[9:0] \main_sdcore_block_length_storage - assign $0\main_sdphy_datar_sink_last[0:0] $eq$ls180.v:5233$973_Y - attribute \src "ls180.v:5234.4-5260.7" + assign $0\main_sdphy_datar_sink_last[0:0] $eq$ls180.v:5229$972_Y + attribute \src "ls180.v:5230.4-5256.7" switch \main_sdphy_datar_source_valid - attribute \src "ls180.v:5234.8-5234.37" + attribute \src "ls180.v:5230.8-5230.37" case 1'1 - attribute \src "ls180.v:5235.5-5259.8" - switch $eq$ls180.v:5235$974_Y - attribute \src "ls180.v:5235.9-5235.57" + attribute \src "ls180.v:5231.5-5255.8" + switch $eq$ls180.v:5231$973_Y + attribute \src "ls180.v:5231.9-5231.57" case 1'1 assign $0\main_sdcore_crc16_checker_sink_valid[0:0] \main_sdphy_datar_source_valid assign $0\main_sdphy_datar_source_ready[0:0] \main_sdcore_crc16_checker_sink_ready assign $0\main_sdcore_crc16_checker_sink_first[0:0] \main_sdphy_datar_source_first assign $0\main_sdcore_crc16_checker_sink_last[0:0] \main_sdphy_datar_source_last assign $0\main_sdcore_crc16_checker_sink_payload_data[7:0] \main_sdphy_datar_source_payload_data - attribute \src "ls180.v:5241.6-5249.9" - switch $and$ls180.v:5241$975_Y - attribute \src "ls180.v:5241.10-5241.72" + attribute \src "ls180.v:5237.6-5245.9" + switch $and$ls180.v:5237$974_Y + attribute \src "ls180.v:5237.10-5237.72" case 1'1 - assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5242$976_Y + assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5238$975_Y assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 - attribute \src "ls180.v:5244.7-5248.10" - switch $eq$ls180.v:5244$978_Y - attribute \src "ls180.v:5244.11-5244.79" + attribute \src "ls180.v:5240.7-5244.10" + switch $eq$ls180.v:5240$977_Y + attribute \src "ls180.v:5240.11-5240.79" case 1'1 assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 - attribute \src "ls180.v:5246.11-5246.15" + attribute \src "ls180.v:5242.11-5242.15" case assign $0\builder_sdcore_fsm_next_state[2:0] 3'100 end case end - attribute \src "ls180.v:5250.9-5250.13" + attribute \src "ls180.v:5246.9-5246.13" case - attribute \src "ls180.v:5251.6-5258.9" - switch $eq$ls180.v:5251$979_Y - attribute \src "ls180.v:5251.10-5251.58" + attribute \src "ls180.v:5247.6-5254.9" + switch $eq$ls180.v:5247$978_Y + attribute \src "ls180.v:5247.10-5247.58" case 1'1 assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'1 assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'1 @@ -119730,9 +119673,9 @@ module \ls180 assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'1 assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 - attribute \src "ls180.v:5271.4-5285.7" + attribute \src "ls180.v:5267.4-5281.7" switch \main_sdcore_cmd_send_re - attribute \src "ls180.v:5271.8-5271.31" + attribute \src "ls180.v:5267.8-5267.31" case 1'1 assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1 @@ -119792,7 +119735,7 @@ module \ls180 update \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] end attribute \src "ls180.v:51.12-51.60" - process $proc$ls180.v:51$2769 + process $proc$ls180.v:51$2767 assign { } { } assign $1\main_libresocsim_scratch_storage[31:0] 305419896 sync always @@ -119800,103 +119743,111 @@ module \ls180 update \main_libresocsim_scratch_storage $1\main_libresocsim_scratch_storage[31:0] end attribute \src "ls180.v:52.5-52.39" - process $proc$ls180.v:52$2770 + process $proc$ls180.v:52$2768 assign { } { } assign $1\main_libresocsim_scratch_re[0:0] 1'0 sync always sync init update \main_libresocsim_scratch_re $1\main_libresocsim_scratch_re[0:0] end - attribute \src "ls180.v:524.5-524.59" - process $proc$ls180.v:524$2953 + attribute \src "ls180.v:523.5-523.59" + process $proc$ls180.v:523$2950 assign { } { } assign $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] 1'0 sync always sync init update \main_sdram_bankmachine1_cmd_buffer_source_valid $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] end - attribute \src "ls180.v:526.5-526.59" - process $proc$ls180.v:526$2954 + attribute \src "ls180.v:525.5-525.59" + process $proc$ls180.v:525$2951 assign { } { } assign $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] 1'0 sync always sync init update \main_sdram_bankmachine1_cmd_buffer_source_first $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] end - attribute \src "ls180.v:527.5-527.58" - process $proc$ls180.v:527$2955 + attribute \src "ls180.v:526.5-526.58" + process $proc$ls180.v:526$2952 assign { } { } assign $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] 1'0 sync always sync init update \main_sdram_bankmachine1_cmd_buffer_source_last $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] end - attribute \src "ls180.v:528.5-528.64" - process $proc$ls180.v:528$2956 + attribute \src "ls180.v:527.5-527.64" + process $proc$ls180.v:527$2953 assign { } { } assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] 1'0 sync always sync init update \main_sdram_bankmachine1_cmd_buffer_source_payload_we $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] end - attribute \src "ls180.v:529.12-529.74" - process $proc$ls180.v:529$2957 + attribute \src "ls180.v:528.12-528.74" + process $proc$ls180.v:528$2954 assign { } { } assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 sync always sync init update \main_sdram_bankmachine1_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] end - attribute \src "ls180.v:530.12-530.47" - process $proc$ls180.v:530$2958 + attribute \src "ls180.v:529.12-529.47" + process $proc$ls180.v:529$2955 assign { } { } assign $1\main_sdram_bankmachine1_row[12:0] 13'0000000000000 sync always sync init update \main_sdram_bankmachine1_row $1\main_sdram_bankmachine1_row[12:0] end - attribute \src "ls180.v:531.5-531.46" - process $proc$ls180.v:531$2959 + attribute \src "ls180.v:530.5-530.46" + process $proc$ls180.v:530$2956 assign { } { } assign $1\main_sdram_bankmachine1_row_opened[0:0] 1'0 sync always sync init update \main_sdram_bankmachine1_row_opened $1\main_sdram_bankmachine1_row_opened[0:0] end - attribute \src "ls180.v:5316.1-5323.4" - process $proc$ls180.v:5316$980 + attribute \src "ls180.v:5312.1-5319.4" + process $proc$ls180.v:5312$979 assign { } { } assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] 5'00000 - attribute \src "ls180.v:5318.2-5322.5" + attribute \src "ls180.v:5314.2-5318.5" switch \main_sdblock2mem_fifo_replace - attribute \src "ls180.v:5318.6-5318.35" + attribute \src "ls180.v:5314.6-5314.35" case 1'1 - assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] $sub$ls180.v:5319$981_Y - attribute \src "ls180.v:5320.6-5320.10" + assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] $sub$ls180.v:5315$980_Y + attribute \src "ls180.v:5316.6-5316.10" case assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] \main_sdblock2mem_fifo_produce end sync always update \main_sdblock2mem_fifo_wrport_adr $0\main_sdblock2mem_fifo_wrport_adr[4:0] end - attribute \src "ls180.v:533.5-533.44" - process $proc$ls180.v:533$2960 + attribute \src "ls180.v:532.5-532.44" + process $proc$ls180.v:532$2957 assign { } { } assign $1\main_sdram_bankmachine1_row_open[0:0] 1'0 sync always sync init update \main_sdram_bankmachine1_row_open $1\main_sdram_bankmachine1_row_open[0:0] end - attribute \src "ls180.v:534.5-534.45" - process $proc$ls180.v:534$2961 + attribute \src "ls180.v:533.5-533.45" + process $proc$ls180.v:533$2958 assign { } { } assign $1\main_sdram_bankmachine1_row_close[0:0] 1'0 sync always sync init update \main_sdram_bankmachine1_row_close $1\main_sdram_bankmachine1_row_close[0:0] end - attribute \src "ls180.v:5349.1-5388.4" - process $proc$ls180.v:5349$991 + attribute \src "ls180.v:534.5-534.54" + process $proc$ls180.v:534$2959 + assign { } { } + assign $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_row_col_n_addr_sel $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] + end + attribute \src "ls180.v:5345.1-5384.4" + process $proc$ls180.v:5345$990 assign { } { } assign { } { } assign { } { } @@ -119905,40 +119856,40 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdblock2mem_sink_sink_valid1[0:0] 1'0 - assign $0\main_sdblock2mem_sink_sink_payload_address[31:0] 0 assign $0\main_sdblock2mem_sink_sink_payload_data1[31:0] 0 assign $0\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'0 assign $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'0 assign { } { } assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'0 + assign $0\main_sdblock2mem_sink_sink_valid1[0:0] 1'0 + assign $0\main_sdblock2mem_sink_sink_payload_address[31:0] 0 assign $0\builder_sdblock2memdma_next_state[1:0] \builder_sdblock2memdma_state - attribute \src "ls180.v:5359.2-5387.9" + attribute \src "ls180.v:5355.2-5383.9" switch \builder_sdblock2memdma_state attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\main_sdblock2mem_sink_sink_valid1[0:0] \main_sdblock2mem_wishbonedmawriter_sink_valid assign $0\main_sdblock2mem_sink_sink_payload_data1[31:0] \main_sdblock2mem_wishbonedmawriter_sink_payload_data - assign $0\main_sdblock2mem_sink_sink_payload_address[31:0] $add$ls180.v:5363$992_Y + assign $0\main_sdblock2mem_sink_sink_payload_address[31:0] $add$ls180.v:5359$991_Y assign $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] \main_sdblock2mem_sink_sink_ready1 - attribute \src "ls180.v:5365.4-5376.7" - switch $and$ls180.v:5365$993_Y - attribute \src "ls180.v:5365.8-5365.103" + attribute \src "ls180.v:5361.4-5372.7" + switch $and$ls180.v:5361$992_Y + attribute \src "ls180.v:5361.8-5361.103" case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] $add$ls180.v:5366$994_Y + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] $add$ls180.v:5362$993_Y assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:5368.5-5375.8" - switch $eq$ls180.v:5368$996_Y - attribute \src "ls180.v:5368.9-5368.106" + attribute \src "ls180.v:5364.5-5371.8" + switch $eq$ls180.v:5364$995_Y + attribute \src "ls180.v:5364.9-5364.106" case 1'1 - attribute \src "ls180.v:5369.6-5374.9" + attribute \src "ls180.v:5365.6-5370.9" switch \main_sdblock2mem_wishbonedmawriter_loop_storage - attribute \src "ls180.v:5369.10-5369.57" + attribute \src "ls180.v:5365.10-5365.57" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:5372.10-5372.14" + attribute \src "ls180.v:5368.10-5368.14" case assign $0\builder_sdblock2memdma_next_state[1:0] 2'10 end @@ -119966,40 +119917,32 @@ module \ls180 update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] end - attribute \src "ls180.v:535.5-535.54" - process $proc$ls180.v:535$2962 - assign { } { } - assign $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_row_col_n_addr_sel $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] - end - attribute \src "ls180.v:537.32-537.76" - process $proc$ls180.v:537$2963 + attribute \src "ls180.v:536.32-536.76" + process $proc$ls180.v:536$2960 assign { } { } assign $1\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0 sync always sync init update \main_sdram_bankmachine1_twtpcon_ready $1\main_sdram_bankmachine1_twtpcon_ready[0:0] end - attribute \src "ls180.v:538.11-538.55" - process $proc$ls180.v:538$2964 + attribute \src "ls180.v:537.11-537.55" + process $proc$ls180.v:537$2961 assign { } { } assign $1\main_sdram_bankmachine1_twtpcon_count[2:0] 3'000 sync always sync init update \main_sdram_bankmachine1_twtpcon_count $1\main_sdram_bankmachine1_twtpcon_count[2:0] end - attribute \src "ls180.v:540.32-540.75" - process $proc$ls180.v:540$2965 + attribute \src "ls180.v:539.32-539.75" + process $proc$ls180.v:539$2962 assign { } { } assign $0\main_sdram_bankmachine1_trccon_ready[0:0] 1'1 sync always update \main_sdram_bankmachine1_trccon_ready $0\main_sdram_bankmachine1_trccon_ready[0:0] sync init end - attribute \src "ls180.v:5408.1-5445.4" - process $proc$ls180.v:5408$998 + attribute \src "ls180.v:5404.1-5441.4" + process $proc$ls180.v:5404$997 assign { } { } assign { } { } assign { } { } @@ -120012,29 +119955,29 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdmem2block_dma_source_valid[0:0] 1'0 assign $0\main_interface1_bus_adr[31:0] 0 assign $0\main_sdmem2block_dma_sink_ready[0:0] 1'0 - assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'0 assign { } { } assign $0\main_interface1_bus_sel[3:0] 4'0000 assign $0\main_interface1_bus_cyc[0:0] 1'0 assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] 0 assign $0\main_interface1_bus_stb[0:0] 1'0 + assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'0 + assign $0\main_sdmem2block_dma_source_valid[0:0] 1'0 assign $0\main_interface1_bus_we[0:0] 1'0 assign $0\main_sdmem2block_dma_source_last[0:0] 1'0 assign $0\main_sdmem2block_dma_source_payload_data[31:0] 0 assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] \builder_sdmem2blockdma_fsm_state - attribute \src "ls180.v:5422.2-5444.9" + attribute \src "ls180.v:5418.2-5440.9" switch \builder_sdmem2blockdma_fsm_state attribute \src "ls180.v:0.0-0.0" case 1'1 assign $0\main_sdmem2block_dma_source_valid[0:0] 1'1 assign $0\main_sdmem2block_dma_source_last[0:0] \main_sdmem2block_dma_sink_last assign $0\main_sdmem2block_dma_source_payload_data[31:0] \main_sdmem2block_dma_data - attribute \src "ls180.v:5427.4-5430.7" + attribute \src "ls180.v:5423.4-5426.7" switch \main_sdmem2block_dma_source_ready - attribute \src "ls180.v:5427.8-5427.41" + attribute \src "ls180.v:5423.8-5423.41" case 1'1 assign $0\main_sdmem2block_dma_sink_ready[0:0] 1'1 assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] 1'0 @@ -120047,9 +119990,9 @@ module \ls180 assign $0\main_interface1_bus_we[0:0] 1'0 assign $0\main_interface1_bus_sel[3:0] 4'1111 assign $0\main_interface1_bus_adr[31:0] \main_sdmem2block_dma_sink_payload_address - attribute \src "ls180.v:5438.4-5442.7" - switch $and$ls180.v:5438$999_Y - attribute \src "ls180.v:5438.8-5438.59" + attribute \src "ls180.v:5434.4-5438.7" + switch $and$ls180.v:5434$998_Y + attribute \src "ls180.v:5434.8-5434.59" case 1'1 assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] { \main_interface1_bus_dat_r [7:0] \main_interface1_bus_dat_r [15:8] \main_interface1_bus_dat_r [23:16] \main_interface1_bus_dat_r [31:24] } assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'1 @@ -120071,17 +120014,16 @@ module \ls180 update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] end - attribute \src "ls180.v:542.32-542.76" - process $proc$ls180.v:542$2966 + attribute \src "ls180.v:541.32-541.76" + process $proc$ls180.v:541$2963 assign { } { } assign $0\main_sdram_bankmachine1_trascon_ready[0:0] 1'1 sync always update \main_sdram_bankmachine1_trascon_ready $0\main_sdram_bankmachine1_trascon_ready[0:0] sync init end - attribute \src "ls180.v:5446.1-5482.4" - process $proc$ls180.v:5446$1000 - assign { } { } + attribute \src "ls180.v:5442.1-5478.4" + process $proc$ls180.v:5442$999 assign { } { } assign { } { } assign { } { } @@ -120089,37 +120031,38 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdmem2block_dma_sink_last[0:0] 1'0 + assign $0\main_sdmem2block_dma_sink_valid[0:0] 1'0 + assign $0\main_sdmem2block_dma_done_status[0:0] 1'0 assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 + assign $0\main_sdmem2block_dma_sink_last[0:0] 1'0 + assign { } { } assign $0\main_sdmem2block_dma_sink_payload_address[31:0] 0 assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0 - assign $0\main_sdmem2block_dma_done_status[0:0] 1'0 - assign $0\main_sdmem2block_dma_sink_valid[0:0] 1'0 assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] \builder_sdmem2blockdma_resetinserter_state - attribute \src "ls180.v:5455.2-5481.9" + attribute \src "ls180.v:5451.2-5477.9" switch \builder_sdmem2blockdma_resetinserter_state attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\main_sdmem2block_dma_sink_valid[0:0] 1'1 - assign $0\main_sdmem2block_dma_sink_last[0:0] $eq$ls180.v:5458$1002_Y - assign $0\main_sdmem2block_dma_sink_payload_address[31:0] $add$ls180.v:5459$1003_Y - attribute \src "ls180.v:5460.4-5471.7" + assign $0\main_sdmem2block_dma_sink_last[0:0] $eq$ls180.v:5454$1001_Y + assign $0\main_sdmem2block_dma_sink_payload_address[31:0] $add$ls180.v:5455$1002_Y + attribute \src "ls180.v:5456.4-5467.7" switch \main_sdmem2block_dma_sink_ready - attribute \src "ls180.v:5460.8-5460.39" + attribute \src "ls180.v:5456.8-5456.39" case 1'1 - assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] $add$ls180.v:5461$1004_Y + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] $add$ls180.v:5457$1003_Y assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:5463.5-5470.8" + attribute \src "ls180.v:5459.5-5466.8" switch \main_sdmem2block_dma_sink_last - attribute \src "ls180.v:5463.9-5463.39" + attribute \src "ls180.v:5459.9-5459.39" case 1'1 - attribute \src "ls180.v:5464.6-5469.9" + attribute \src "ls180.v:5460.6-5465.9" switch \main_sdmem2block_dma_loop_storage - attribute \src "ls180.v:5464.10-5464.43" + attribute \src "ls180.v:5460.10-5460.43" case 1'1 assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:5467.10-5467.14" + attribute \src "ls180.v:5463.10-5463.14" case assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'10 end @@ -120145,27 +120088,27 @@ module \ls180 update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] end - attribute \src "ls180.v:548.5-548.51" - process $proc$ls180.v:548$2967 + attribute \src "ls180.v:547.5-547.51" + process $proc$ls180.v:547$2964 assign { } { } assign $1\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0 sync always sync init update \main_sdram_bankmachine2_req_wdata_ready $1\main_sdram_bankmachine2_req_wdata_ready[0:0] end - attribute \src "ls180.v:549.5-549.51" - process $proc$ls180.v:549$2968 + attribute \src "ls180.v:548.5-548.51" + process $proc$ls180.v:548$2965 assign { } { } assign $1\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0 sync always sync init update \main_sdram_bankmachine2_req_rdata_valid $1\main_sdram_bankmachine2_req_rdata_valid[0:0] end - attribute \src "ls180.v:5494.1-5510.4" - process $proc$ls180.v:5494$1010 + attribute \src "ls180.v:5490.1-5506.4" + process $proc$ls180.v:5490$1009 assign { } { } assign $0\main_sdmem2block_converter_source_payload_data[7:0] 8'00000000 - attribute \src "ls180.v:5496.2-5509.9" + attribute \src "ls180.v:5492.2-5505.9" switch \main_sdmem2block_converter_mux attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -120183,56 +120126,57 @@ module \ls180 sync always update \main_sdmem2block_converter_source_payload_data $0\main_sdmem2block_converter_source_payload_data[7:0] end - attribute \src "ls180.v:551.5-551.47" - process $proc$ls180.v:551$2969 + attribute \src "ls180.v:550.5-550.47" + process $proc$ls180.v:550$2966 assign { } { } assign $1\main_sdram_bankmachine2_refresh_gnt[0:0] 1'0 sync always sync init update \main_sdram_bankmachine2_refresh_gnt $1\main_sdram_bankmachine2_refresh_gnt[0:0] end - attribute \src "ls180.v:552.5-552.45" - process $proc$ls180.v:552$2970 + attribute \src "ls180.v:551.5-551.45" + process $proc$ls180.v:551$2967 assign { } { } assign $1\main_sdram_bankmachine2_cmd_valid[0:0] 1'0 sync always sync init update \main_sdram_bankmachine2_cmd_valid $1\main_sdram_bankmachine2_cmd_valid[0:0] end - attribute \src "ls180.v:5524.1-5531.4" - process $proc$ls180.v:5524$1011 + attribute \src "ls180.v:552.5-552.45" + process $proc$ls180.v:552$2968 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_ready $1\main_sdram_bankmachine2_cmd_ready[0:0] + end + attribute \src "ls180.v:5520.1-5527.4" + process $proc$ls180.v:5520$1010 assign { } { } assign $0\main_sdmem2block_fifo_wrport_adr[4:0] 5'00000 - attribute \src "ls180.v:5526.2-5530.5" + attribute \src "ls180.v:5522.2-5526.5" switch \main_sdmem2block_fifo_replace - attribute \src "ls180.v:5526.6-5526.35" + attribute \src "ls180.v:5522.6-5522.35" case 1'1 - assign $0\main_sdmem2block_fifo_wrport_adr[4:0] $sub$ls180.v:5527$1012_Y - attribute \src "ls180.v:5528.6-5528.10" + assign $0\main_sdmem2block_fifo_wrport_adr[4:0] $sub$ls180.v:5523$1011_Y + attribute \src "ls180.v:5524.6-5524.10" case assign $0\main_sdmem2block_fifo_wrport_adr[4:0] \main_sdmem2block_fifo_produce end sync always update \main_sdmem2block_fifo_wrport_adr $0\main_sdmem2block_fifo_wrport_adr[4:0] end - attribute \src "ls180.v:553.5-553.45" - process $proc$ls180.v:553$2971 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_ready $1\main_sdram_bankmachine2_cmd_ready[0:0] - end - attribute \src "ls180.v:554.12-554.57" - process $proc$ls180.v:554$2972 + attribute \src "ls180.v:553.12-553.57" + process $proc$ls180.v:553$2969 assign { } { } assign $1\main_sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000 sync always sync init update \main_sdram_bankmachine2_cmd_payload_a $1\main_sdram_bankmachine2_cmd_payload_a[12:0] end - attribute \src "ls180.v:5549.1-5597.4" - process $proc$ls180.v:5549$1022 + attribute \src "ls180.v:5545.1-5593.4" + process $proc$ls180.v:5545$1021 + assign { } { } assign { } { } assign { } { } assign { } { } @@ -120242,25 +120186,24 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\libresocsim_clk_enable[0:0] 1'0 + assign $0\libresocsim_count_spimaster1_next_value[2:0] 3'000 + assign $0\libresocsim_cs_enable[0:0] 1'0 assign $0\libresocsim_count_spimaster1_next_value_ce[0:0] 1'0 assign $0\libresocsim_mosi_latch[0:0] 1'0 assign $0\libresocsim_done0[0:0] 1'0 - assign $0\libresocsim_miso_latch[0:0] 1'0 assign $0\libresocsim_irq[0:0] 1'0 - assign $0\libresocsim_cs_enable[0:0] 1'0 - assign { } { } - assign $0\libresocsim_clk_enable[0:0] 1'0 - assign $0\libresocsim_count_spimaster1_next_value[2:0] 3'000 + assign $0\libresocsim_miso_latch[0:0] 1'0 assign $0\builder_spimaster1_next_state[1:0] \builder_spimaster1_state - attribute \src "ls180.v:5560.2-5596.9" + attribute \src "ls180.v:5556.2-5592.9" switch \builder_spimaster1_state attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\libresocsim_count_spimaster1_next_value[2:0] 3'000 assign $0\libresocsim_count_spimaster1_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:5564.4-5567.7" + attribute \src "ls180.v:5560.4-5563.7" switch \libresocsim_clk_fall - attribute \src "ls180.v:5564.8-5564.28" + attribute \src "ls180.v:5560.8-5560.28" case 1'1 assign $0\libresocsim_cs_enable[0:0] 1'1 assign $0\builder_spimaster1_next_state[1:0] 2'10 @@ -120270,15 +120213,15 @@ module \ls180 case 2'10 assign $0\libresocsim_clk_enable[0:0] 1'1 assign $0\libresocsim_cs_enable[0:0] 1'1 - attribute \src "ls180.v:5572.4-5578.7" + attribute \src "ls180.v:5568.4-5574.7" switch \libresocsim_clk_fall - attribute \src "ls180.v:5572.8-5572.28" + attribute \src "ls180.v:5568.8-5568.28" case 1'1 - assign $0\libresocsim_count_spimaster1_next_value[2:0] $add$ls180.v:5573$1023_Y + assign $0\libresocsim_count_spimaster1_next_value[2:0] $add$ls180.v:5569$1022_Y assign $0\libresocsim_count_spimaster1_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:5575.5-5577.8" - switch $eq$ls180.v:5575$1025_Y - attribute \src "ls180.v:5575.9-5575.60" + attribute \src "ls180.v:5571.5-5573.8" + switch $eq$ls180.v:5571$1024_Y + attribute \src "ls180.v:5571.9-5571.60" case 1'1 assign $0\builder_spimaster1_next_state[1:0] 2'11 case @@ -120288,9 +120231,9 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 2'11 assign $0\libresocsim_cs_enable[0:0] 1'1 - attribute \src "ls180.v:5582.4-5586.7" + attribute \src "ls180.v:5578.4-5582.7" switch \libresocsim_clk_rise - attribute \src "ls180.v:5582.8-5582.28" + attribute \src "ls180.v:5578.8-5578.28" case 1'1 assign $0\libresocsim_miso_latch[0:0] 1'1 assign $0\libresocsim_irq[0:0] 1'1 @@ -120300,9 +120243,9 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case assign $0\libresocsim_done0[0:0] 1'1 - attribute \src "ls180.v:5590.4-5594.7" + attribute \src "ls180.v:5586.4-5590.7" switch \libresocsim_start0 - attribute \src "ls180.v:5590.8-5590.26" + attribute \src "ls180.v:5586.8-5586.26" case 1'1 assign $0\libresocsim_done0[0:0] 1'0 assign $0\libresocsim_mosi_latch[0:0] 1'1 @@ -120321,40 +120264,48 @@ module \ls180 update \libresocsim_count_spimaster1_next_value $0\libresocsim_count_spimaster1_next_value[2:0] update \libresocsim_count_spimaster1_next_value_ce $0\libresocsim_count_spimaster1_next_value_ce[0:0] end - attribute \src "ls180.v:556.5-556.51" - process $proc$ls180.v:556$2973 + attribute \src "ls180.v:555.5-555.51" + process $proc$ls180.v:555$2970 assign { } { } assign $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'0 sync always sync init update \main_sdram_bankmachine2_cmd_payload_cas $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] end - attribute \src "ls180.v:557.5-557.51" - process $proc$ls180.v:557$2974 + attribute \src "ls180.v:556.5-556.51" + process $proc$ls180.v:556$2971 assign { } { } assign $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'0 sync always sync init update \main_sdram_bankmachine2_cmd_payload_ras $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] end - attribute \src "ls180.v:558.5-558.50" - process $proc$ls180.v:558$2975 + attribute \src "ls180.v:557.5-557.50" + process $proc$ls180.v:557$2972 assign { } { } assign $1\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0 sync always sync init update \main_sdram_bankmachine2_cmd_payload_we $1\main_sdram_bankmachine2_cmd_payload_we[0:0] end - attribute \src "ls180.v:559.5-559.54" - process $proc$ls180.v:559$2976 + attribute \src "ls180.v:558.5-558.54" + process $proc$ls180.v:558$2973 assign { } { } assign $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0 sync always sync init update \main_sdram_bankmachine2_cmd_payload_is_cmd $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] end - attribute \src "ls180.v:5598.1-5634.4" - process $proc$ls180.v:5598$1026 + attribute \src "ls180.v:559.5-559.55" + process $proc$ls180.v:559$2974 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_is_read $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] + end + attribute \src "ls180.v:5594.1-5630.4" + process $proc$ls180.v:5594$1025 assign { } { } assign { } { } assign { } { } @@ -120364,7 +120315,6 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\builder_libresocsim_wishbone_ack[0:0] 1'0 assign { } { } assign $0\builder_libresocsim_dat_w_next_value0[7:0] 8'00000000 assign $0\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'0 @@ -120373,8 +120323,9 @@ module \ls180 assign $0\builder_libresocsim_we_next_value2[0:0] 1'0 assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'0 assign $0\builder_libresocsim_wishbone_dat_r[31:0] 0 + assign $0\builder_libresocsim_wishbone_ack[0:0] 1'0 assign $0\builder_next_state[1:0] \builder_state - attribute \src "ls180.v:5609.2-5633.9" + attribute \src "ls180.v:5605.2-5629.9" switch \builder_state attribute \src "ls180.v:0.0-0.0" case 2'01 @@ -120392,13 +120343,13 @@ module \ls180 case assign $0\builder_libresocsim_dat_w_next_value0[7:0] \builder_libresocsim_wishbone_dat_w [7:0] assign $0\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:5625.4-5631.7" - switch $and$ls180.v:5625$1027_Y - attribute \src "ls180.v:5625.8-5625.77" + attribute \src "ls180.v:5621.4-5627.7" + switch $and$ls180.v:5621$1026_Y + attribute \src "ls180.v:5621.8-5621.77" case 1'1 assign $0\builder_libresocsim_adr_next_value1[13:0] \builder_libresocsim_wishbone_adr [13:0] assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'1 - assign $0\builder_libresocsim_we_next_value2[0:0] $and$ls180.v:5628$1029_Y + assign $0\builder_libresocsim_we_next_value2[0:0] $and$ls180.v:5624$1028_Y assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'1 assign $0\builder_next_state[1:0] 2'01 case @@ -120415,79 +120366,71 @@ module \ls180 update \builder_libresocsim_we_next_value2 $0\builder_libresocsim_we_next_value2[0:0] update \builder_libresocsim_we_next_value_ce2 $0\builder_libresocsim_we_next_value_ce2[0:0] end - attribute \src "ls180.v:560.5-560.55" - process $proc$ls180.v:560$2977 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_payload_is_read $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] - end - attribute \src "ls180.v:561.5-561.56" - process $proc$ls180.v:561$2978 + attribute \src "ls180.v:560.5-560.56" + process $proc$ls180.v:560$2975 assign { } { } assign $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 sync always sync init update \main_sdram_bankmachine2_cmd_payload_is_write $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] end - attribute \src "ls180.v:562.5-562.50" - process $proc$ls180.v:562$2979 + attribute \src "ls180.v:561.5-561.50" + process $proc$ls180.v:561$2976 assign { } { } assign $1\main_sdram_bankmachine2_auto_precharge[0:0] 1'0 sync always sync init update \main_sdram_bankmachine2_auto_precharge $1\main_sdram_bankmachine2_auto_precharge[0:0] end - attribute \src "ls180.v:565.5-565.67" - process $proc$ls180.v:565$2980 + attribute \src "ls180.v:564.5-564.67" + process $proc$ls180.v:564$2977 assign { } { } assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] 1'0 sync always update \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] sync init end - attribute \src "ls180.v:5659.1-5666.4" - process $proc$ls180.v:5659$1050 - assign { } { } - assign { } { } - assign $0\builder_slave_sel[4:0] [0] $eq$ls180.v:5661$1051_Y - assign $0\builder_slave_sel[4:0] [1] $eq$ls180.v:5662$1052_Y - assign $0\builder_slave_sel[4:0] [2] $eq$ls180.v:5663$1053_Y - assign $0\builder_slave_sel[4:0] [3] $eq$ls180.v:5664$1054_Y - assign $0\builder_slave_sel[4:0] [4] $eq$ls180.v:5665$1055_Y - sync always - update \builder_slave_sel $0\builder_slave_sel[4:0] - end - attribute \src "ls180.v:566.5-566.66" - process $proc$ls180.v:566$2981 + attribute \src "ls180.v:565.5-565.66" + process $proc$ls180.v:565$2978 assign { } { } assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] 1'0 sync always update \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] sync init end + attribute \src "ls180.v:5655.1-5662.4" + process $proc$ls180.v:5655$1049 + assign { } { } + assign { } { } + assign $0\builder_slave_sel[4:0] [0] $eq$ls180.v:5657$1050_Y + assign $0\builder_slave_sel[4:0] [1] $eq$ls180.v:5658$1051_Y + assign $0\builder_slave_sel[4:0] [2] $eq$ls180.v:5659$1052_Y + assign $0\builder_slave_sel[4:0] [3] $eq$ls180.v:5660$1053_Y + assign $0\builder_slave_sel[4:0] [4] $eq$ls180.v:5661$1054_Y + sync always + update \builder_slave_sel $0\builder_slave_sel[4:0] + end attribute \src "ls180.v:57.12-57.47" - process $proc$ls180.v:57$2771 + process $proc$ls180.v:57$2769 assign { } { } assign $1\main_libresocsim_bus_errors[31:0] 0 sync always sync init update \main_libresocsim_bus_errors $1\main_libresocsim_bus_errors[31:0] end - attribute \src "ls180.v:5709.1-5720.4" - process $proc$ls180.v:5709$1068 + attribute \src "ls180.v:5705.1-5716.4" + process $proc$ls180.v:5705$1067 assign { } { } assign { } { } assign { } { } + assign $0\builder_error[0:0] 1'0 assign { } { } assign { } { } - assign $0\builder_error[0:0] 1'0 - assign $0\builder_shared_ack[0:0] $or$ls180.v:5713$1072_Y - assign $0\builder_shared_dat_r[31:0] $or$ls180.v:5714$1081_Y - attribute \src "ls180.v:5715.2-5719.5" + assign $0\builder_shared_ack[0:0] $or$ls180.v:5709$1071_Y + assign $0\builder_shared_dat_r[31:0] $or$ls180.v:5710$1080_Y + attribute \src "ls180.v:5711.2-5715.5" switch \builder_done - attribute \src "ls180.v:5715.6-5715.18" + attribute \src "ls180.v:5711.6-5711.18" case 1'1 assign $0\builder_shared_dat_r[31:0] 32'11111111111111111111111111111111 assign $0\builder_shared_ack[0:0] 1'1 @@ -120499,40 +120442,40 @@ module \ls180 update \builder_shared_ack $0\builder_shared_ack[0:0] update \builder_error $0\builder_error[0:0] end - attribute \src "ls180.v:581.11-581.68" - process $proc$ls180.v:581$2982 + attribute \src "ls180.v:580.11-580.68" + process $proc$ls180.v:580$2979 assign { } { } assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] 4'0000 sync always sync init update \main_sdram_bankmachine2_cmd_buffer_lookahead_level $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] end - attribute \src "ls180.v:582.5-582.64" - process $proc$ls180.v:582$2983 + attribute \src "ls180.v:581.5-581.64" + process $proc$ls180.v:581$2980 assign { } { } assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] 1'0 sync always update \main_sdram_bankmachine2_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] sync init end - attribute \src "ls180.v:583.11-583.70" - process $proc$ls180.v:583$2984 + attribute \src "ls180.v:582.11-582.70" + process $proc$ls180.v:582$2981 assign { } { } assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] 3'000 sync always sync init update \main_sdram_bankmachine2_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] end - attribute \src "ls180.v:584.11-584.70" - process $proc$ls180.v:584$2985 + attribute \src "ls180.v:583.11-583.70" + process $proc$ls180.v:583$2982 assign { } { } assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] 3'000 sync always sync init update \main_sdram_bankmachine2_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] end - attribute \src "ls180.v:585.11-585.73" - process $proc$ls180.v:585$2986 + attribute \src "ls180.v:584.11-584.73" + process $proc$ls180.v:584$2983 assign { } { } assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 sync always @@ -120540,124 +120483,124 @@ module \ls180 update \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] end attribute \src "ls180.v:59.12-59.55" - process $proc$ls180.v:59$2772 + process $proc$ls180.v:59$2770 assign { } { } assign $1\main_libresocsim_libresoc_interrupt[15:0] 16'0000000000000000 sync always sync init update \main_libresocsim_libresoc_interrupt $1\main_libresocsim_libresoc_interrupt[15:0] end - attribute \src "ls180.v:606.5-606.59" - process $proc$ls180.v:606$2987 + attribute \src "ls180.v:605.5-605.59" + process $proc$ls180.v:605$2984 assign { } { } assign $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] 1'0 sync always sync init update \main_sdram_bankmachine2_cmd_buffer_source_valid $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] end - attribute \src "ls180.v:608.5-608.59" - process $proc$ls180.v:608$2988 + attribute \src "ls180.v:607.5-607.59" + process $proc$ls180.v:607$2985 assign { } { } assign $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] 1'0 sync always sync init update \main_sdram_bankmachine2_cmd_buffer_source_first $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] end - attribute \src "ls180.v:609.5-609.58" - process $proc$ls180.v:609$2989 + attribute \src "ls180.v:608.5-608.58" + process $proc$ls180.v:608$2986 assign { } { } assign $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] 1'0 sync always sync init update \main_sdram_bankmachine2_cmd_buffer_source_last $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] end - attribute \src "ls180.v:610.5-610.64" - process $proc$ls180.v:610$2990 + attribute \src "ls180.v:609.5-609.64" + process $proc$ls180.v:609$2987 assign { } { } assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] 1'0 sync always sync init update \main_sdram_bankmachine2_cmd_buffer_source_payload_we $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] end - attribute \src "ls180.v:611.12-611.74" - process $proc$ls180.v:611$2991 + attribute \src "ls180.v:610.12-610.74" + process $proc$ls180.v:610$2988 assign { } { } assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 sync always sync init update \main_sdram_bankmachine2_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] end - attribute \src "ls180.v:612.12-612.47" - process $proc$ls180.v:612$2992 + attribute \src "ls180.v:611.12-611.47" + process $proc$ls180.v:611$2989 assign { } { } assign $1\main_sdram_bankmachine2_row[12:0] 13'0000000000000 sync always sync init update \main_sdram_bankmachine2_row $1\main_sdram_bankmachine2_row[12:0] end - attribute \src "ls180.v:613.5-613.46" - process $proc$ls180.v:613$2993 + attribute \src "ls180.v:612.5-612.46" + process $proc$ls180.v:612$2990 assign { } { } assign $1\main_sdram_bankmachine2_row_opened[0:0] 1'0 sync always sync init update \main_sdram_bankmachine2_row_opened $1\main_sdram_bankmachine2_row_opened[0:0] end - attribute \src "ls180.v:615.5-615.44" - process $proc$ls180.v:615$2994 + attribute \src "ls180.v:614.5-614.44" + process $proc$ls180.v:614$2991 assign { } { } assign $1\main_sdram_bankmachine2_row_open[0:0] 1'0 sync always sync init update \main_sdram_bankmachine2_row_open $1\main_sdram_bankmachine2_row_open[0:0] end - attribute \src "ls180.v:616.5-616.45" - process $proc$ls180.v:616$2995 + attribute \src "ls180.v:615.5-615.45" + process $proc$ls180.v:615$2992 assign { } { } assign $1\main_sdram_bankmachine2_row_close[0:0] 1'0 sync always sync init update \main_sdram_bankmachine2_row_close $1\main_sdram_bankmachine2_row_close[0:0] end - attribute \src "ls180.v:617.5-617.54" - process $proc$ls180.v:617$2996 + attribute \src "ls180.v:616.5-616.54" + process $proc$ls180.v:616$2993 assign { } { } assign $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 sync always sync init update \main_sdram_bankmachine2_row_col_n_addr_sel $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] end - attribute \src "ls180.v:619.32-619.76" - process $proc$ls180.v:619$2997 + attribute \src "ls180.v:618.32-618.76" + process $proc$ls180.v:618$2994 assign { } { } assign $1\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 sync always sync init update \main_sdram_bankmachine2_twtpcon_ready $1\main_sdram_bankmachine2_twtpcon_ready[0:0] end - attribute \src "ls180.v:620.11-620.55" - process $proc$ls180.v:620$2998 + attribute \src "ls180.v:619.11-619.55" + process $proc$ls180.v:619$2995 assign { } { } assign $1\main_sdram_bankmachine2_twtpcon_count[2:0] 3'000 sync always sync init update \main_sdram_bankmachine2_twtpcon_count $1\main_sdram_bankmachine2_twtpcon_count[2:0] end - attribute \src "ls180.v:622.32-622.75" - process $proc$ls180.v:622$2999 + attribute \src "ls180.v:621.32-621.75" + process $proc$ls180.v:621$2996 assign { } { } assign $0\main_sdram_bankmachine2_trccon_ready[0:0] 1'1 sync always update \main_sdram_bankmachine2_trccon_ready $0\main_sdram_bankmachine2_trccon_ready[0:0] sync init end - attribute \src "ls180.v:6220.1-6225.4" - process $proc$ls180.v:6220$1940 + attribute \src "ls180.v:6216.1-6221.4" + process $proc$ls180.v:6216$1939 assign { } { } assign $0\main_spi_master_start1[0:0] 1'0 - attribute \src "ls180.v:6222.2-6224.5" + attribute \src "ls180.v:6218.2-6220.5" switch \main_spi_master_control_re - attribute \src "ls180.v:6222.6-6222.32" + attribute \src "ls180.v:6218.6-6218.32" case 1'1 assign $0\main_spi_master_start1[0:0] \main_spi_master_control_storage [0] case @@ -120665,21 +120608,21 @@ module \ls180 sync always update \main_spi_master_start1 $0\main_spi_master_start1[0:0] end - attribute \src "ls180.v:624.32-624.76" - process $proc$ls180.v:624$3000 + attribute \src "ls180.v:623.32-623.76" + process $proc$ls180.v:623$2997 assign { } { } assign $0\main_sdram_bankmachine2_trascon_ready[0:0] 1'1 sync always update \main_sdram_bankmachine2_trascon_ready $0\main_sdram_bankmachine2_trascon_ready[0:0] sync init end - attribute \src "ls180.v:6266.1-6271.4" - process $proc$ls180.v:6266$2005 + attribute \src "ls180.v:6262.1-6267.4" + process $proc$ls180.v:6262$2004 assign { } { } assign $0\libresocsim_start1[0:0] 1'0 - attribute \src "ls180.v:6268.2-6270.5" + attribute \src "ls180.v:6264.2-6266.5" switch \libresocsim_control_re - attribute \src "ls180.v:6268.6-6268.28" + attribute \src "ls180.v:6264.6-6264.28" case 1'1 assign $0\libresocsim_start1[0:0] \libresocsim_control_storage [0] case @@ -120687,115 +120630,115 @@ module \ls180 sync always update \libresocsim_start1 $0\libresocsim_start1[0:0] end - attribute \src "ls180.v:630.5-630.51" - process $proc$ls180.v:630$3001 + attribute \src "ls180.v:629.5-629.51" + process $proc$ls180.v:629$2998 assign { } { } assign $1\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0 sync always sync init update \main_sdram_bankmachine3_req_wdata_ready $1\main_sdram_bankmachine3_req_wdata_ready[0:0] end - attribute \src "ls180.v:631.5-631.51" - process $proc$ls180.v:631$3002 + attribute \src "ls180.v:630.5-630.51" + process $proc$ls180.v:630$2999 assign { } { } assign $1\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0 sync always sync init update \main_sdram_bankmachine3_req_rdata_valid $1\main_sdram_bankmachine3_req_rdata_valid[0:0] end - attribute \src "ls180.v:633.5-633.47" - process $proc$ls180.v:633$3003 + attribute \src "ls180.v:632.5-632.47" + process $proc$ls180.v:632$3000 assign { } { } assign $1\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0 sync always sync init update \main_sdram_bankmachine3_refresh_gnt $1\main_sdram_bankmachine3_refresh_gnt[0:0] end - attribute \src "ls180.v:634.5-634.45" - process $proc$ls180.v:634$3004 + attribute \src "ls180.v:633.5-633.45" + process $proc$ls180.v:633$3001 assign { } { } assign $1\main_sdram_bankmachine3_cmd_valid[0:0] 1'0 sync always sync init update \main_sdram_bankmachine3_cmd_valid $1\main_sdram_bankmachine3_cmd_valid[0:0] end - attribute \src "ls180.v:635.5-635.45" - process $proc$ls180.v:635$3005 + attribute \src "ls180.v:634.5-634.45" + process $proc$ls180.v:634$3002 assign { } { } assign $1\main_sdram_bankmachine3_cmd_ready[0:0] 1'0 sync always sync init update \main_sdram_bankmachine3_cmd_ready $1\main_sdram_bankmachine3_cmd_ready[0:0] end - attribute \src "ls180.v:636.12-636.57" - process $proc$ls180.v:636$3006 + attribute \src "ls180.v:635.12-635.57" + process $proc$ls180.v:635$3003 assign { } { } assign $1\main_sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000 sync always sync init update \main_sdram_bankmachine3_cmd_payload_a $1\main_sdram_bankmachine3_cmd_payload_a[12:0] end - attribute \src "ls180.v:638.5-638.51" - process $proc$ls180.v:638$3007 + attribute \src "ls180.v:637.5-637.51" + process $proc$ls180.v:637$3004 assign { } { } assign $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 sync always sync init update \main_sdram_bankmachine3_cmd_payload_cas $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] end - attribute \src "ls180.v:639.5-639.51" - process $proc$ls180.v:639$3008 + attribute \src "ls180.v:638.5-638.51" + process $proc$ls180.v:638$3005 assign { } { } assign $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 sync always sync init update \main_sdram_bankmachine3_cmd_payload_ras $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] end - attribute \src "ls180.v:640.5-640.50" - process $proc$ls180.v:640$3009 + attribute \src "ls180.v:639.5-639.50" + process $proc$ls180.v:639$3006 assign { } { } assign $1\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0 sync always sync init update \main_sdram_bankmachine3_cmd_payload_we $1\main_sdram_bankmachine3_cmd_payload_we[0:0] end - attribute \src "ls180.v:641.5-641.54" - process $proc$ls180.v:641$3010 + attribute \src "ls180.v:640.5-640.54" + process $proc$ls180.v:640$3007 assign { } { } assign $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0 sync always sync init update \main_sdram_bankmachine3_cmd_payload_is_cmd $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] end - attribute \src "ls180.v:642.5-642.55" - process $proc$ls180.v:642$3011 + attribute \src "ls180.v:641.5-641.55" + process $proc$ls180.v:641$3008 assign { } { } assign $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0 sync always sync init update \main_sdram_bankmachine3_cmd_payload_is_read $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] end - attribute \src "ls180.v:643.5-643.56" - process $proc$ls180.v:643$3012 + attribute \src "ls180.v:642.5-642.56" + process $proc$ls180.v:642$3009 assign { } { } assign $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0 sync always sync init update \main_sdram_bankmachine3_cmd_payload_is_write $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] end - attribute \src "ls180.v:644.5-644.50" - process $proc$ls180.v:644$3013 + attribute \src "ls180.v:643.5-643.50" + process $proc$ls180.v:643$3010 assign { } { } assign $1\main_sdram_bankmachine3_auto_precharge[0:0] 1'0 sync always sync init update \main_sdram_bankmachine3_auto_precharge $1\main_sdram_bankmachine3_auto_precharge[0:0] end - attribute \src "ls180.v:6452.1-6468.4" - process $proc$ls180.v:6452$2225 + attribute \src "ls180.v:6448.1-6464.4" + process $proc$ls180.v:6448$2224 assign { } { } assign $0\builder_comb_rhs_array_muxed0[0:0] 1'0 - attribute \src "ls180.v:6454.2-6467.9" + attribute \src "ls180.v:6450.2-6463.9" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -120813,11 +120756,19 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed0 $0\builder_comb_rhs_array_muxed0[0:0] end - attribute \src "ls180.v:6469.1-6485.4" - process $proc$ls180.v:6469$2226 + attribute \src "ls180.v:646.5-646.67" + process $proc$ls180.v:646$3011 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] 1'0 + sync always + update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] + sync init + end + attribute \src "ls180.v:6465.1-6481.4" + process $proc$ls180.v:6465$2225 assign { } { } assign $0\builder_comb_rhs_array_muxed1[12:0] 13'0000000000000 - attribute \src "ls180.v:6471.2-6484.9" + attribute \src "ls180.v:6467.2-6480.9" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -120835,27 +120786,19 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed1 $0\builder_comb_rhs_array_muxed1[12:0] end - attribute \src "ls180.v:647.5-647.67" - process $proc$ls180.v:647$3014 - assign { } { } - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] 1'0 - sync always - update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] - sync init - end - attribute \src "ls180.v:648.5-648.66" - process $proc$ls180.v:648$3015 + attribute \src "ls180.v:647.5-647.66" + process $proc$ls180.v:647$3012 assign { } { } assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] 1'0 sync always update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] sync init end - attribute \src "ls180.v:6486.1-6502.4" - process $proc$ls180.v:6486$2227 + attribute \src "ls180.v:6482.1-6498.4" + process $proc$ls180.v:6482$2226 assign { } { } assign $0\builder_comb_rhs_array_muxed2[1:0] 2'00 - attribute \src "ls180.v:6488.2-6501.9" + attribute \src "ls180.v:6484.2-6497.9" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -120873,11 +120816,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed2 $0\builder_comb_rhs_array_muxed2[1:0] end - attribute \src "ls180.v:6503.1-6519.4" - process $proc$ls180.v:6503$2228 + attribute \src "ls180.v:6499.1-6515.4" + process $proc$ls180.v:6499$2227 assign { } { } assign $0\builder_comb_rhs_array_muxed3[0:0] 1'0 - attribute \src "ls180.v:6505.2-6518.9" + attribute \src "ls180.v:6501.2-6514.9" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -120895,11 +120838,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed3 $0\builder_comb_rhs_array_muxed3[0:0] end - attribute \src "ls180.v:6520.1-6536.4" - process $proc$ls180.v:6520$2229 + attribute \src "ls180.v:6516.1-6532.4" + process $proc$ls180.v:6516$2228 assign { } { } assign $0\builder_comb_rhs_array_muxed4[0:0] 1'0 - attribute \src "ls180.v:6522.2-6535.9" + attribute \src "ls180.v:6518.2-6531.9" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -120917,11 +120860,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed4 $0\builder_comb_rhs_array_muxed4[0:0] end - attribute \src "ls180.v:6537.1-6553.4" - process $proc$ls180.v:6537$2230 + attribute \src "ls180.v:6533.1-6549.4" + process $proc$ls180.v:6533$2229 assign { } { } assign $0\builder_comb_rhs_array_muxed5[0:0] 1'0 - attribute \src "ls180.v:6539.2-6552.9" + attribute \src "ls180.v:6535.2-6548.9" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -120939,11 +120882,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed5 $0\builder_comb_rhs_array_muxed5[0:0] end - attribute \src "ls180.v:6554.1-6570.4" - process $proc$ls180.v:6554$2231 + attribute \src "ls180.v:6550.1-6566.4" + process $proc$ls180.v:6550$2230 assign { } { } assign $0\builder_comb_t_array_muxed0[0:0] 1'0 - attribute \src "ls180.v:6556.2-6569.9" + attribute \src "ls180.v:6552.2-6565.9" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -120961,11 +120904,11 @@ module \ls180 sync always update \builder_comb_t_array_muxed0 $0\builder_comb_t_array_muxed0[0:0] end - attribute \src "ls180.v:6571.1-6587.4" - process $proc$ls180.v:6571$2232 + attribute \src "ls180.v:6567.1-6583.4" + process $proc$ls180.v:6567$2231 assign { } { } assign $0\builder_comb_t_array_muxed1[0:0] 1'0 - attribute \src "ls180.v:6573.2-6586.9" + attribute \src "ls180.v:6569.2-6582.9" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -120983,11 +120926,11 @@ module \ls180 sync always update \builder_comb_t_array_muxed1 $0\builder_comb_t_array_muxed1[0:0] end - attribute \src "ls180.v:6588.1-6604.4" - process $proc$ls180.v:6588$2233 + attribute \src "ls180.v:6584.1-6600.4" + process $proc$ls180.v:6584$2232 assign { } { } assign $0\builder_comb_t_array_muxed2[0:0] 1'0 - attribute \src "ls180.v:6590.2-6603.9" + attribute \src "ls180.v:6586.2-6599.9" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -121006,18 +120949,18 @@ module \ls180 update \builder_comb_t_array_muxed2 $0\builder_comb_t_array_muxed2[0:0] end attribute \src "ls180.v:66.5-66.46" - process $proc$ls180.v:66$2773 + process $proc$ls180.v:66$2771 assign { } { } assign $1\main_libresocsim_libresoc_dbus_ack[0:0] 1'0 sync always sync init update \main_libresocsim_libresoc_dbus_ack $1\main_libresocsim_libresoc_dbus_ack[0:0] end - attribute \src "ls180.v:6605.1-6621.4" - process $proc$ls180.v:6605$2234 + attribute \src "ls180.v:6601.1-6617.4" + process $proc$ls180.v:6601$2233 assign { } { } assign $0\builder_comb_rhs_array_muxed6[0:0] 1'0 - attribute \src "ls180.v:6607.2-6620.9" + attribute \src "ls180.v:6603.2-6616.9" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -121035,11 +120978,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed6 $0\builder_comb_rhs_array_muxed6[0:0] end - attribute \src "ls180.v:6622.1-6638.4" - process $proc$ls180.v:6622$2235 + attribute \src "ls180.v:6618.1-6634.4" + process $proc$ls180.v:6618$2234 assign { } { } assign $0\builder_comb_rhs_array_muxed7[12:0] 13'0000000000000 - attribute \src "ls180.v:6624.2-6637.9" + attribute \src "ls180.v:6620.2-6633.9" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -121057,19 +121000,27 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed7 $0\builder_comb_rhs_array_muxed7[12:0] end - attribute \src "ls180.v:663.11-663.68" - process $proc$ls180.v:663$3016 + attribute \src "ls180.v:662.11-662.68" + process $proc$ls180.v:662$3013 assign { } { } assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] 4'0000 sync always sync init update \main_sdram_bankmachine3_cmd_buffer_lookahead_level $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] end - attribute \src "ls180.v:6639.1-6655.4" - process $proc$ls180.v:6639$2236 + attribute \src "ls180.v:663.5-663.64" + process $proc$ls180.v:663$3014 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] 1'0 + sync always + update \main_sdram_bankmachine3_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] + sync init + end + attribute \src "ls180.v:6635.1-6651.4" + process $proc$ls180.v:6635$2235 assign { } { } assign $0\builder_comb_rhs_array_muxed8[1:0] 2'00 - attribute \src "ls180.v:6641.2-6654.9" + attribute \src "ls180.v:6637.2-6650.9" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -121087,27 +121038,27 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed8 $0\builder_comb_rhs_array_muxed8[1:0] end - attribute \src "ls180.v:664.5-664.64" - process $proc$ls180.v:664$3017 + attribute \src "ls180.v:664.11-664.70" + process $proc$ls180.v:664$3015 assign { } { } - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] 1'0 + assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] 3'000 sync always - update \main_sdram_bankmachine3_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] sync init + update \main_sdram_bankmachine3_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] end attribute \src "ls180.v:665.11-665.70" - process $proc$ls180.v:665$3018 + process $proc$ls180.v:665$3016 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] 3'000 sync always sync init - update \main_sdram_bankmachine3_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] + update \main_sdram_bankmachine3_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] end - attribute \src "ls180.v:6656.1-6672.4" - process $proc$ls180.v:6656$2237 + attribute \src "ls180.v:6652.1-6668.4" + process $proc$ls180.v:6652$2236 assign { } { } assign $0\builder_comb_rhs_array_muxed9[0:0] 1'0 - attribute \src "ls180.v:6658.2-6671.9" + attribute \src "ls180.v:6654.2-6667.9" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -121125,27 +121076,19 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed9 $0\builder_comb_rhs_array_muxed9[0:0] end - attribute \src "ls180.v:666.11-666.70" - process $proc$ls180.v:666$3019 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine3_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] - end - attribute \src "ls180.v:667.11-667.73" - process $proc$ls180.v:667$3020 + attribute \src "ls180.v:666.11-666.73" + process $proc$ls180.v:666$3017 assign { } { } assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 sync always sync init update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "ls180.v:6673.1-6689.4" - process $proc$ls180.v:6673$2238 + attribute \src "ls180.v:6669.1-6685.4" + process $proc$ls180.v:6669$2237 assign { } { } assign $0\builder_comb_rhs_array_muxed10[0:0] 1'0 - attribute \src "ls180.v:6675.2-6688.9" + attribute \src "ls180.v:6671.2-6684.9" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -121163,11 +121106,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed10 $0\builder_comb_rhs_array_muxed10[0:0] end - attribute \src "ls180.v:6690.1-6706.4" - process $proc$ls180.v:6690$2239 + attribute \src "ls180.v:6686.1-6702.4" + process $proc$ls180.v:6686$2238 assign { } { } assign $0\builder_comb_rhs_array_muxed11[0:0] 1'0 - attribute \src "ls180.v:6692.2-6705.9" + attribute \src "ls180.v:6688.2-6701.9" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -121185,11 +121128,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed11 $0\builder_comb_rhs_array_muxed11[0:0] end - attribute \src "ls180.v:6707.1-6723.4" - process $proc$ls180.v:6707$2240 + attribute \src "ls180.v:6703.1-6719.4" + process $proc$ls180.v:6703$2239 assign { } { } assign $0\builder_comb_t_array_muxed3[0:0] 1'0 - attribute \src "ls180.v:6709.2-6722.9" + attribute \src "ls180.v:6705.2-6718.9" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -121207,11 +121150,11 @@ module \ls180 sync always update \builder_comb_t_array_muxed3 $0\builder_comb_t_array_muxed3[0:0] end - attribute \src "ls180.v:6724.1-6740.4" - process $proc$ls180.v:6724$2241 + attribute \src "ls180.v:6720.1-6736.4" + process $proc$ls180.v:6720$2240 assign { } { } assign $0\builder_comb_t_array_muxed4[0:0] 1'0 - attribute \src "ls180.v:6726.2-6739.9" + attribute \src "ls180.v:6722.2-6735.9" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -121229,11 +121172,11 @@ module \ls180 sync always update \builder_comb_t_array_muxed4 $0\builder_comb_t_array_muxed4[0:0] end - attribute \src "ls180.v:6741.1-6757.4" - process $proc$ls180.v:6741$2242 + attribute \src "ls180.v:6737.1-6753.4" + process $proc$ls180.v:6737$2241 assign { } { } assign $0\builder_comb_t_array_muxed5[0:0] 1'0 - attribute \src "ls180.v:6743.2-6756.9" + attribute \src "ls180.v:6739.2-6752.9" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -121251,11 +121194,11 @@ module \ls180 sync always update \builder_comb_t_array_muxed5 $0\builder_comb_t_array_muxed5[0:0] end - attribute \src "ls180.v:6758.1-6765.4" - process $proc$ls180.v:6758$2243 + attribute \src "ls180.v:6754.1-6761.4" + process $proc$ls180.v:6754$2242 assign { } { } assign $0\builder_comb_rhs_array_muxed12[21:0] 22'0000000000000000000000 - attribute \src "ls180.v:6760.2-6764.9" + attribute \src "ls180.v:6756.2-6760.9" switch \builder_roundrobin0_grant attribute \src "ls180.v:0.0-0.0" case @@ -121264,11 +121207,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed12 $0\builder_comb_rhs_array_muxed12[21:0] end - attribute \src "ls180.v:6766.1-6773.4" - process $proc$ls180.v:6766$2244 + attribute \src "ls180.v:6762.1-6769.4" + process $proc$ls180.v:6762$2243 assign { } { } assign $0\builder_comb_rhs_array_muxed13[0:0] 1'0 - attribute \src "ls180.v:6768.2-6772.9" + attribute \src "ls180.v:6764.2-6768.9" switch \builder_roundrobin0_grant attribute \src "ls180.v:0.0-0.0" case @@ -121277,24 +121220,24 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed13 $0\builder_comb_rhs_array_muxed13[0:0] end - attribute \src "ls180.v:6774.1-6781.4" - process $proc$ls180.v:6774$2245 + attribute \src "ls180.v:6770.1-6777.4" + process $proc$ls180.v:6770$2244 assign { } { } assign $0\builder_comb_rhs_array_muxed14[0:0] 1'0 - attribute \src "ls180.v:6776.2-6780.9" + attribute \src "ls180.v:6772.2-6776.9" switch \builder_roundrobin0_grant attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed14[0:0] $and$ls180.v:6778$2258_Y + assign $0\builder_comb_rhs_array_muxed14[0:0] $and$ls180.v:6774$2257_Y end sync always update \builder_comb_rhs_array_muxed14 $0\builder_comb_rhs_array_muxed14[0:0] end - attribute \src "ls180.v:6782.1-6789.4" - process $proc$ls180.v:6782$2259 + attribute \src "ls180.v:6778.1-6785.4" + process $proc$ls180.v:6778$2258 assign { } { } assign $0\builder_comb_rhs_array_muxed15[21:0] 22'0000000000000000000000 - attribute \src "ls180.v:6784.2-6788.9" + attribute \src "ls180.v:6780.2-6784.9" switch \builder_roundrobin1_grant attribute \src "ls180.v:0.0-0.0" case @@ -121303,11 +121246,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed15 $0\builder_comb_rhs_array_muxed15[21:0] end - attribute \src "ls180.v:6790.1-6797.4" - process $proc$ls180.v:6790$2260 + attribute \src "ls180.v:6786.1-6793.4" + process $proc$ls180.v:6786$2259 assign { } { } assign $0\builder_comb_rhs_array_muxed16[0:0] 1'0 - attribute \src "ls180.v:6792.2-6796.9" + attribute \src "ls180.v:6788.2-6792.9" switch \builder_roundrobin1_grant attribute \src "ls180.v:0.0-0.0" case @@ -121316,24 +121259,24 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed16 $0\builder_comb_rhs_array_muxed16[0:0] end - attribute \src "ls180.v:6798.1-6805.4" - process $proc$ls180.v:6798$2261 + attribute \src "ls180.v:6794.1-6801.4" + process $proc$ls180.v:6794$2260 assign { } { } assign $0\builder_comb_rhs_array_muxed17[0:0] 1'0 - attribute \src "ls180.v:6800.2-6804.9" + attribute \src "ls180.v:6796.2-6800.9" switch \builder_roundrobin1_grant attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed17[0:0] $and$ls180.v:6802$2274_Y + assign $0\builder_comb_rhs_array_muxed17[0:0] $and$ls180.v:6798$2273_Y end sync always update \builder_comb_rhs_array_muxed17 $0\builder_comb_rhs_array_muxed17[0:0] end - attribute \src "ls180.v:6806.1-6813.4" - process $proc$ls180.v:6806$2275 + attribute \src "ls180.v:6802.1-6809.4" + process $proc$ls180.v:6802$2274 assign { } { } assign $0\builder_comb_rhs_array_muxed18[21:0] 22'0000000000000000000000 - attribute \src "ls180.v:6808.2-6812.9" + attribute \src "ls180.v:6804.2-6808.9" switch \builder_roundrobin2_grant attribute \src "ls180.v:0.0-0.0" case @@ -121342,11 +121285,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed18 $0\builder_comb_rhs_array_muxed18[21:0] end - attribute \src "ls180.v:6814.1-6821.4" - process $proc$ls180.v:6814$2276 + attribute \src "ls180.v:6810.1-6817.4" + process $proc$ls180.v:6810$2275 assign { } { } assign $0\builder_comb_rhs_array_muxed19[0:0] 1'0 - attribute \src "ls180.v:6816.2-6820.9" + attribute \src "ls180.v:6812.2-6816.9" switch \builder_roundrobin2_grant attribute \src "ls180.v:0.0-0.0" case @@ -121355,24 +121298,24 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed19 $0\builder_comb_rhs_array_muxed19[0:0] end - attribute \src "ls180.v:6822.1-6829.4" - process $proc$ls180.v:6822$2277 + attribute \src "ls180.v:6818.1-6825.4" + process $proc$ls180.v:6818$2276 assign { } { } assign $0\builder_comb_rhs_array_muxed20[0:0] 1'0 - attribute \src "ls180.v:6824.2-6828.9" + attribute \src "ls180.v:6820.2-6824.9" switch \builder_roundrobin2_grant attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed20[0:0] $and$ls180.v:6826$2290_Y + assign $0\builder_comb_rhs_array_muxed20[0:0] $and$ls180.v:6822$2289_Y end sync always update \builder_comb_rhs_array_muxed20 $0\builder_comb_rhs_array_muxed20[0:0] end - attribute \src "ls180.v:6830.1-6837.4" - process $proc$ls180.v:6830$2291 + attribute \src "ls180.v:6826.1-6833.4" + process $proc$ls180.v:6826$2290 assign { } { } assign $0\builder_comb_rhs_array_muxed21[21:0] 22'0000000000000000000000 - attribute \src "ls180.v:6832.2-6836.9" + attribute \src "ls180.v:6828.2-6832.9" switch \builder_roundrobin3_grant attribute \src "ls180.v:0.0-0.0" case @@ -121381,11 +121324,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed21 $0\builder_comb_rhs_array_muxed21[21:0] end - attribute \src "ls180.v:6838.1-6845.4" - process $proc$ls180.v:6838$2292 + attribute \src "ls180.v:6834.1-6841.4" + process $proc$ls180.v:6834$2291 assign { } { } assign $0\builder_comb_rhs_array_muxed22[0:0] 1'0 - attribute \src "ls180.v:6840.2-6844.9" + attribute \src "ls180.v:6836.2-6840.9" switch \builder_roundrobin3_grant attribute \src "ls180.v:0.0-0.0" case @@ -121394,24 +121337,24 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed22 $0\builder_comb_rhs_array_muxed22[0:0] end - attribute \src "ls180.v:6846.1-6853.4" - process $proc$ls180.v:6846$2293 + attribute \src "ls180.v:6842.1-6849.4" + process $proc$ls180.v:6842$2292 assign { } { } assign $0\builder_comb_rhs_array_muxed23[0:0] 1'0 - attribute \src "ls180.v:6848.2-6852.9" + attribute \src "ls180.v:6844.2-6848.9" switch \builder_roundrobin3_grant attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed23[0:0] $and$ls180.v:6850$2306_Y + assign $0\builder_comb_rhs_array_muxed23[0:0] $and$ls180.v:6846$2305_Y end sync always update \builder_comb_rhs_array_muxed23 $0\builder_comb_rhs_array_muxed23[0:0] end - attribute \src "ls180.v:6854.1-6873.4" - process $proc$ls180.v:6854$2307 + attribute \src "ls180.v:6850.1-6869.4" + process $proc$ls180.v:6850$2306 assign { } { } assign $0\builder_comb_rhs_array_muxed24[31:0] 0 - attribute \src "ls180.v:6856.2-6872.9" + attribute \src "ls180.v:6852.2-6868.9" switch \builder_grant attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -121432,11 +121375,19 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed24 $0\builder_comb_rhs_array_muxed24[31:0] end - attribute \src "ls180.v:6874.1-6893.4" - process $proc$ls180.v:6874$2308 + attribute \src "ls180.v:687.5-687.59" + process $proc$ls180.v:687$3018 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_source_valid $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] + end + attribute \src "ls180.v:6870.1-6889.4" + process $proc$ls180.v:6870$2307 assign { } { } assign $0\builder_comb_rhs_array_muxed25[31:0] 0 - attribute \src "ls180.v:6876.2-6892.9" + attribute \src "ls180.v:6872.2-6888.9" switch \builder_grant attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -121457,19 +121408,19 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed25 $0\builder_comb_rhs_array_muxed25[31:0] end - attribute \src "ls180.v:688.5-688.59" - process $proc$ls180.v:688$3021 + attribute \src "ls180.v:689.5-689.59" + process $proc$ls180.v:689$3019 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] 1'0 + assign $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine3_cmd_buffer_source_valid $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] + update \main_sdram_bankmachine3_cmd_buffer_source_first $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] end - attribute \src "ls180.v:6894.1-6913.4" - process $proc$ls180.v:6894$2309 + attribute \src "ls180.v:6890.1-6909.4" + process $proc$ls180.v:6890$2308 assign { } { } assign $0\builder_comb_rhs_array_muxed26[3:0] 4'0000 - attribute \src "ls180.v:6896.2-6912.9" + attribute \src "ls180.v:6892.2-6908.9" switch \builder_grant attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -121490,27 +121441,27 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed26 $0\builder_comb_rhs_array_muxed26[3:0] end - attribute \src "ls180.v:690.5-690.59" - process $proc$ls180.v:690$3022 + attribute \src "ls180.v:690.5-690.58" + process $proc$ls180.v:690$3020 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] 1'0 + assign $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine3_cmd_buffer_source_first $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] + update \main_sdram_bankmachine3_cmd_buffer_source_last $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] end - attribute \src "ls180.v:691.5-691.58" - process $proc$ls180.v:691$3023 + attribute \src "ls180.v:691.5-691.64" + process $proc$ls180.v:691$3021 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] 1'0 + assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine3_cmd_buffer_source_last $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] + update \main_sdram_bankmachine3_cmd_buffer_source_payload_we $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] end - attribute \src "ls180.v:6914.1-6933.4" - process $proc$ls180.v:6914$2310 + attribute \src "ls180.v:6910.1-6929.4" + process $proc$ls180.v:6910$2309 assign { } { } assign $0\builder_comb_rhs_array_muxed27[0:0] 1'0 - attribute \src "ls180.v:6916.2-6932.9" + attribute \src "ls180.v:6912.2-6928.9" switch \builder_grant attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -121531,27 +121482,27 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed27 $0\builder_comb_rhs_array_muxed27[0:0] end - attribute \src "ls180.v:692.5-692.64" - process $proc$ls180.v:692$3024 + attribute \src "ls180.v:692.12-692.74" + process $proc$ls180.v:692$3022 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] 1'0 + assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 sync always sync init - update \main_sdram_bankmachine3_cmd_buffer_source_payload_we $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] + update \main_sdram_bankmachine3_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] end - attribute \src "ls180.v:693.12-693.74" - process $proc$ls180.v:693$3025 + attribute \src "ls180.v:693.12-693.47" + process $proc$ls180.v:693$3023 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 + assign $1\main_sdram_bankmachine3_row[12:0] 13'0000000000000 sync always sync init - update \main_sdram_bankmachine3_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] + update \main_sdram_bankmachine3_row $1\main_sdram_bankmachine3_row[12:0] end - attribute \src "ls180.v:6934.1-6953.4" - process $proc$ls180.v:6934$2311 + attribute \src "ls180.v:6930.1-6949.4" + process $proc$ls180.v:6930$2310 assign { } { } assign $0\builder_comb_rhs_array_muxed28[0:0] 1'0 - attribute \src "ls180.v:6936.2-6952.9" + attribute \src "ls180.v:6932.2-6948.9" switch \builder_grant attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -121572,27 +121523,19 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed28 $0\builder_comb_rhs_array_muxed28[0:0] end - attribute \src "ls180.v:694.12-694.47" - process $proc$ls180.v:694$3026 - assign { } { } - assign $1\main_sdram_bankmachine3_row[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_bankmachine3_row $1\main_sdram_bankmachine3_row[12:0] - end - attribute \src "ls180.v:695.5-695.46" - process $proc$ls180.v:695$3027 + attribute \src "ls180.v:694.5-694.46" + process $proc$ls180.v:694$3024 assign { } { } assign $1\main_sdram_bankmachine3_row_opened[0:0] 1'0 sync always sync init update \main_sdram_bankmachine3_row_opened $1\main_sdram_bankmachine3_row_opened[0:0] end - attribute \src "ls180.v:6954.1-6973.4" - process $proc$ls180.v:6954$2312 + attribute \src "ls180.v:6950.1-6969.4" + process $proc$ls180.v:6950$2311 assign { } { } assign $0\builder_comb_rhs_array_muxed29[0:0] 1'0 - attribute \src "ls180.v:6956.2-6972.9" + attribute \src "ls180.v:6952.2-6968.9" switch \builder_grant attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -121613,19 +121556,27 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed29 $0\builder_comb_rhs_array_muxed29[0:0] end - attribute \src "ls180.v:697.5-697.44" - process $proc$ls180.v:697$3028 + attribute \src "ls180.v:696.5-696.44" + process $proc$ls180.v:696$3025 assign { } { } assign $1\main_sdram_bankmachine3_row_open[0:0] 1'0 sync always sync init update \main_sdram_bankmachine3_row_open $1\main_sdram_bankmachine3_row_open[0:0] end - attribute \src "ls180.v:6974.1-6993.4" - process $proc$ls180.v:6974$2313 + attribute \src "ls180.v:697.5-697.45" + process $proc$ls180.v:697$3026 + assign { } { } + assign $1\main_sdram_bankmachine3_row_close[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_row_close $1\main_sdram_bankmachine3_row_close[0:0] + end + attribute \src "ls180.v:6970.1-6989.4" + process $proc$ls180.v:6970$2312 assign { } { } assign $0\builder_comb_rhs_array_muxed30[2:0] 3'000 - attribute \src "ls180.v:6976.2-6992.9" + attribute \src "ls180.v:6972.2-6988.9" switch \builder_grant attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -121646,27 +121597,19 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed30 $0\builder_comb_rhs_array_muxed30[2:0] end - attribute \src "ls180.v:698.5-698.45" - process $proc$ls180.v:698$3029 - assign { } { } - assign $1\main_sdram_bankmachine3_row_close[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_row_close $1\main_sdram_bankmachine3_row_close[0:0] - end - attribute \src "ls180.v:699.5-699.54" - process $proc$ls180.v:699$3030 + attribute \src "ls180.v:698.5-698.54" + process $proc$ls180.v:698$3027 assign { } { } assign $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 sync always sync init update \main_sdram_bankmachine3_row_col_n_addr_sel $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] end - attribute \src "ls180.v:6994.1-7013.4" - process $proc$ls180.v:6994$2314 + attribute \src "ls180.v:6990.1-7009.4" + process $proc$ls180.v:6990$2313 assign { } { } assign $0\builder_comb_rhs_array_muxed31[1:0] 2'00 - attribute \src "ls180.v:6996.2-7012.9" + attribute \src "ls180.v:6992.2-7008.9" switch \builder_grant attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -121688,26 +121631,34 @@ module \ls180 update \builder_comb_rhs_array_muxed31 $0\builder_comb_rhs_array_muxed31[1:0] end attribute \src "ls180.v:70.5-70.46" - process $proc$ls180.v:70$2774 + process $proc$ls180.v:70$2772 assign { } { } assign $0\main_libresocsim_libresoc_dbus_err[0:0] 1'0 sync always update \main_libresocsim_libresoc_dbus_err $0\main_libresocsim_libresoc_dbus_err[0:0] sync init end - attribute \src "ls180.v:701.32-701.76" - process $proc$ls180.v:701$3031 + attribute \src "ls180.v:700.32-700.76" + process $proc$ls180.v:700$3028 assign { } { } assign $1\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0 sync always sync init update \main_sdram_bankmachine3_twtpcon_ready $1\main_sdram_bankmachine3_twtpcon_ready[0:0] end - attribute \src "ls180.v:7014.1-7030.4" - process $proc$ls180.v:7014$2315 + attribute \src "ls180.v:701.11-701.55" + process $proc$ls180.v:701$3029 + assign { } { } + assign $1\main_sdram_bankmachine3_twtpcon_count[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine3_twtpcon_count $1\main_sdram_bankmachine3_twtpcon_count[2:0] + end + attribute \src "ls180.v:7010.1-7026.4" + process $proc$ls180.v:7010$2314 assign { } { } assign $0\builder_sync_rhs_array_muxed0[1:0] 2'00 - attribute \src "ls180.v:7016.2-7029.9" + attribute \src "ls180.v:7012.2-7025.9" switch \main_sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -121725,19 +121676,11 @@ module \ls180 sync always update \builder_sync_rhs_array_muxed0 $0\builder_sync_rhs_array_muxed0[1:0] end - attribute \src "ls180.v:702.11-702.55" - process $proc$ls180.v:702$3032 - assign { } { } - assign $1\main_sdram_bankmachine3_twtpcon_count[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine3_twtpcon_count $1\main_sdram_bankmachine3_twtpcon_count[2:0] - end - attribute \src "ls180.v:7031.1-7047.4" - process $proc$ls180.v:7031$2316 + attribute \src "ls180.v:7027.1-7043.4" + process $proc$ls180.v:7027$2315 assign { } { } assign $0\builder_sync_rhs_array_muxed1[12:0] 13'0000000000000 - attribute \src "ls180.v:7033.2-7046.9" + attribute \src "ls180.v:7029.2-7042.9" switch \main_sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -121755,169 +121698,169 @@ module \ls180 sync always update \builder_sync_rhs_array_muxed1 $0\builder_sync_rhs_array_muxed1[12:0] end - attribute \src "ls180.v:704.32-704.75" - process $proc$ls180.v:704$3033 + attribute \src "ls180.v:703.32-703.75" + process $proc$ls180.v:703$3030 assign { } { } assign $0\main_sdram_bankmachine3_trccon_ready[0:0] 1'1 sync always update \main_sdram_bankmachine3_trccon_ready $0\main_sdram_bankmachine3_trccon_ready[0:0] sync init end - attribute \src "ls180.v:7048.1-7064.4" - process $proc$ls180.v:7048$2317 + attribute \src "ls180.v:7044.1-7060.4" + process $proc$ls180.v:7044$2316 assign { } { } assign $0\builder_sync_rhs_array_muxed2[0:0] 1'0 - attribute \src "ls180.v:7050.2-7063.9" + attribute \src "ls180.v:7046.2-7059.9" switch \main_sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\builder_sync_rhs_array_muxed2[0:0] 1'0 attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7055$2319_Y + assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7051$2318_Y attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7058$2321_Y + assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7054$2320_Y attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7061$2323_Y + assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7057$2322_Y end sync always update \builder_sync_rhs_array_muxed2 $0\builder_sync_rhs_array_muxed2[0:0] end - attribute \src "ls180.v:706.32-706.76" - process $proc$ls180.v:706$3034 + attribute \src "ls180.v:705.32-705.76" + process $proc$ls180.v:705$3031 assign { } { } assign $0\main_sdram_bankmachine3_trascon_ready[0:0] 1'1 sync always update \main_sdram_bankmachine3_trascon_ready $0\main_sdram_bankmachine3_trascon_ready[0:0] sync init end - attribute \src "ls180.v:7065.1-7081.4" - process $proc$ls180.v:7065$2324 + attribute \src "ls180.v:7061.1-7077.4" + process $proc$ls180.v:7061$2323 assign { } { } assign $0\builder_sync_rhs_array_muxed3[0:0] 1'0 - attribute \src "ls180.v:7067.2-7080.9" + attribute \src "ls180.v:7063.2-7076.9" switch \main_sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\builder_sync_rhs_array_muxed3[0:0] 1'0 attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7072$2326_Y + assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7068$2325_Y attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7075$2328_Y + assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7071$2327_Y attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7078$2330_Y + assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7074$2329_Y end sync always update \builder_sync_rhs_array_muxed3 $0\builder_sync_rhs_array_muxed3[0:0] end - attribute \src "ls180.v:7082.1-7098.4" - process $proc$ls180.v:7082$2331 + attribute \src "ls180.v:7078.1-7094.4" + process $proc$ls180.v:7078$2330 assign { } { } assign $0\builder_sync_rhs_array_muxed4[0:0] 1'0 - attribute \src "ls180.v:7084.2-7097.9" + attribute \src "ls180.v:7080.2-7093.9" switch \main_sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\builder_sync_rhs_array_muxed4[0:0] 1'0 attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7089$2333_Y + assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7085$2332_Y attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7092$2335_Y + assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7088$2334_Y attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7095$2337_Y + assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7091$2336_Y end sync always update \builder_sync_rhs_array_muxed4 $0\builder_sync_rhs_array_muxed4[0:0] end - attribute \src "ls180.v:709.5-709.44" - process $proc$ls180.v:709$3035 + attribute \src "ls180.v:708.5-708.44" + process $proc$ls180.v:708$3032 assign { } { } assign $0\main_sdram_choose_cmd_want_reads[0:0] 1'0 sync always update \main_sdram_choose_cmd_want_reads $0\main_sdram_choose_cmd_want_reads[0:0] sync init end - attribute \src "ls180.v:7099.1-7115.4" - process $proc$ls180.v:7099$2338 + attribute \src "ls180.v:709.5-709.45" + process $proc$ls180.v:709$3033 + assign { } { } + assign $0\main_sdram_choose_cmd_want_writes[0:0] 1'0 + sync always + update \main_sdram_choose_cmd_want_writes $0\main_sdram_choose_cmd_want_writes[0:0] + sync init + end + attribute \src "ls180.v:7095.1-7111.4" + process $proc$ls180.v:7095$2337 assign { } { } assign $0\builder_sync_rhs_array_muxed5[0:0] 1'0 - attribute \src "ls180.v:7101.2-7114.9" + attribute \src "ls180.v:7097.2-7110.9" switch \main_sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\builder_sync_rhs_array_muxed5[0:0] 1'0 attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7106$2340_Y + assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7102$2339_Y attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7109$2342_Y + assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7105$2341_Y attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7112$2344_Y + assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7108$2343_Y end sync always update \builder_sync_rhs_array_muxed5 $0\builder_sync_rhs_array_muxed5[0:0] end - attribute \src "ls180.v:710.5-710.45" - process $proc$ls180.v:710$3036 + attribute \src "ls180.v:710.5-710.43" + process $proc$ls180.v:710$3034 assign { } { } - assign $0\main_sdram_choose_cmd_want_writes[0:0] 1'0 + assign $0\main_sdram_choose_cmd_want_cmds[0:0] 1'0 sync always - update \main_sdram_choose_cmd_want_writes $0\main_sdram_choose_cmd_want_writes[0:0] + update \main_sdram_choose_cmd_want_cmds $0\main_sdram_choose_cmd_want_cmds[0:0] sync init end - attribute \src "ls180.v:711.5-711.43" - process $proc$ls180.v:711$3037 + attribute \src "ls180.v:711.5-711.48" + process $proc$ls180.v:711$3035 assign { } { } - assign $0\main_sdram_choose_cmd_want_cmds[0:0] 1'0 + assign $0\main_sdram_choose_cmd_want_activates[0:0] 1'0 sync always - update \main_sdram_choose_cmd_want_cmds $0\main_sdram_choose_cmd_want_cmds[0:0] + update \main_sdram_choose_cmd_want_activates $0\main_sdram_choose_cmd_want_activates[0:0] sync init end - attribute \src "ls180.v:7116.1-7132.4" - process $proc$ls180.v:7116$2345 + attribute \src "ls180.v:7112.1-7128.4" + process $proc$ls180.v:7112$2344 assign { } { } assign $0\builder_sync_rhs_array_muxed6[0:0] 1'0 - attribute \src "ls180.v:7118.2-7131.9" + attribute \src "ls180.v:7114.2-7127.9" switch \main_sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\builder_sync_rhs_array_muxed6[0:0] 1'0 attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7123$2347_Y + assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7119$2346_Y attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7126$2349_Y + assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7122$2348_Y attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7129$2351_Y + assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7125$2350_Y end sync always update \builder_sync_rhs_array_muxed6 $0\builder_sync_rhs_array_muxed6[0:0] end - attribute \src "ls180.v:712.5-712.48" - process $proc$ls180.v:712$3038 - assign { } { } - assign $0\main_sdram_choose_cmd_want_activates[0:0] 1'0 - sync always - update \main_sdram_choose_cmd_want_activates $0\main_sdram_choose_cmd_want_activates[0:0] - sync init - end - attribute \src "ls180.v:7133.1-7161.4" - process $proc$ls180.v:7133$2352 + attribute \src "ls180.v:7129.1-7157.4" + process $proc$ls180.v:7129$2351 assign { } { } assign $0\builder_sync_f_array_muxed0[0:0] 1'0 - attribute \src "ls180.v:7135.2-7160.9" + attribute \src "ls180.v:7131.2-7156.9" switch \main_spi_master_mosi_sel attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -121947,19 +121890,19 @@ module \ls180 sync always update \builder_sync_f_array_muxed0 $0\builder_sync_f_array_muxed0[0:0] end - attribute \src "ls180.v:714.5-714.43" - process $proc$ls180.v:714$3039 + attribute \src "ls180.v:713.5-713.43" + process $proc$ls180.v:713$3036 assign { } { } assign $0\main_sdram_choose_cmd_cmd_ready[0:0] 1'0 sync always update \main_sdram_choose_cmd_cmd_ready $0\main_sdram_choose_cmd_cmd_ready[0:0] sync init end - attribute \src "ls180.v:7162.1-7190.4" - process $proc$ls180.v:7162$2353 + attribute \src "ls180.v:7158.1-7186.4" + process $proc$ls180.v:7158$2352 assign { } { } assign $0\builder_sync_f_array_muxed1[0:0] 1'0 - attribute \src "ls180.v:7164.2-7189.9" + attribute \src "ls180.v:7160.2-7185.9" switch \libresocsim_mosi_sel attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -121989,40 +121932,48 @@ module \ls180 sync always update \builder_sync_f_array_muxed1 $0\builder_sync_f_array_muxed1[0:0] end - attribute \src "ls180.v:717.5-717.49" - process $proc$ls180.v:717$3040 + attribute \src "ls180.v:716.5-716.49" + process $proc$ls180.v:716$3037 assign { } { } assign $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] 1'0 sync always sync init update \main_sdram_choose_cmd_cmd_payload_cas $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] end - attribute \src "ls180.v:718.5-718.49" - process $proc$ls180.v:718$3041 + attribute \src "ls180.v:717.5-717.49" + process $proc$ls180.v:717$3038 assign { } { } assign $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] 1'0 sync always sync init update \main_sdram_choose_cmd_cmd_payload_ras $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] end - attribute \src "ls180.v:719.5-719.48" - process $proc$ls180.v:719$3042 + attribute \src "ls180.v:718.5-718.48" + process $proc$ls180.v:718$3039 assign { } { } assign $1\main_sdram_choose_cmd_cmd_payload_we[0:0] 1'0 sync always sync init update \main_sdram_choose_cmd_cmd_payload_we $1\main_sdram_choose_cmd_cmd_payload_we[0:0] end - attribute \src "ls180.v:723.11-723.46" - process $proc$ls180.v:723$3043 + attribute \src "ls180.v:722.11-722.46" + process $proc$ls180.v:722$3040 assign { } { } assign $1\main_sdram_choose_cmd_valids[3:0] 4'0000 sync always sync init update \main_sdram_choose_cmd_valids $1\main_sdram_choose_cmd_valids[3:0] end - attribute \src "ls180.v:7246.1-7264.4" - process $proc$ls180.v:7246$2354 + attribute \src "ls180.v:724.11-724.45" + process $proc$ls180.v:724$3041 + assign { } { } + assign $1\main_sdram_choose_cmd_grant[1:0] 2'00 + sync always + sync init + update \main_sdram_choose_cmd_grant $1\main_sdram_choose_cmd_grant[1:0] + end + attribute \src "ls180.v:7244.1-7262.4" + process $proc$ls180.v:7244$2353 assign { } { } assign { } { } assign $0\main_gpio_status[15:0] [0] \builder_multiregimpl1_regs1 @@ -122044,39 +121995,32 @@ module \ls180 sync always update \main_gpio_status $0\main_gpio_status[15:0] end - attribute \src "ls180.v:725.11-725.45" - process $proc$ls180.v:725$3044 - assign { } { } - assign $1\main_sdram_choose_cmd_grant[1:0] 2'00 - sync always - sync init - update \main_sdram_choose_cmd_grant $1\main_sdram_choose_cmd_grant[1:0] - end - attribute \src "ls180.v:727.5-727.44" - process $proc$ls180.v:727$3045 + attribute \src "ls180.v:726.5-726.44" + process $proc$ls180.v:726$3042 assign { } { } assign $1\main_sdram_choose_req_want_reads[0:0] 1'0 sync always sync init update \main_sdram_choose_req_want_reads $1\main_sdram_choose_req_want_reads[0:0] end - attribute \src "ls180.v:728.5-728.45" - process $proc$ls180.v:728$3046 + attribute \src "ls180.v:727.5-727.45" + process $proc$ls180.v:727$3043 assign { } { } assign $1\main_sdram_choose_req_want_writes[0:0] 1'0 sync always sync init update \main_sdram_choose_req_want_writes $1\main_sdram_choose_req_want_writes[0:0] end - attribute \src "ls180.v:7285.1-7287.4" - process $proc$ls180.v:7285$2355 + attribute \src "ls180.v:7283.1-7285.4" + process $proc$ls180.v:7283$2354 assign { } { } assign $0\main_int_rst[0:0] \sys_rst sync posedge \por_clk update \main_int_rst $0\main_int_rst[0:0] end - attribute \src "ls180.v:7289.1-7357.4" - process $proc$ls180.v:7289$2356 + attribute \src "ls180.v:7287.1-7357.4" + process $proc$ls180.v:7287$2355 + assign { } { } assign { } { } assign { } { } assign { } { } @@ -122148,8 +122092,10 @@ module \ls180 assign $0\main_dfi_p0_rddata[15:0] [14] \sdram_dq_i [14] assign $0\sdram_dq_o[15:0] [15] \main_dfi_p0_wrdata [15] assign $0\main_dfi_p0_rddata[15:0] [15] \sdram_dq_i [15] + assign $0\sdram_dm[1:0] [0] \main_dfi_p0_wrdata_mask [0] + assign $0\sdram_dm[1:0] [1] \main_dfi_p0_wrdata_mask [1] assign $0\sdram_clock[0:0] \sys_clk_1 - assign $0\sdcard_clk[0:0] $and$ls180.v:7344$2358_Y + assign $0\sdcard_clk[0:0] $and$ls180.v:7344$2357_Y assign $0\sdcard_cmd_oe[0:0] \main_sdphy_sdpads_cmd_oe assign $0\sdcard_cmd_o[0:0] \main_sdphy_sdpads_cmd_o assign $0\main_sdphy_sdpads_cmd_i[0:0] \sdcard_cmd_i @@ -122172,6 +122118,7 @@ module \ls180 update \sdram_cs_n $0\sdram_cs_n[0:0] update \sdram_cke $0\sdram_cke[0:0] update \sdram_ba $0\sdram_ba[1:0] + update \sdram_dm $0\sdram_dm[1:0] update \sdram_clock $0\sdram_clock[0:0] update \sdcard_clk $0\sdcard_clk[0:0] update \sdcard_cmd_o $0\sdcard_cmd_o[0:0] @@ -122182,33 +122129,40 @@ module \ls180 update \main_sdphy_sdpads_cmd_i $0\main_sdphy_sdpads_cmd_i[0:0] update \main_sdphy_sdpads_data_i $0\main_sdphy_sdpads_data_i[3:0] end - attribute \src "ls180.v:730.5-730.48" - process $proc$ls180.v:730$3047 + attribute \src "ls180.v:729.5-729.48" + process $proc$ls180.v:729$3044 assign { } { } assign $1\main_sdram_choose_req_want_activates[0:0] 1'0 sync always sync init update \main_sdram_choose_req_want_activates $1\main_sdram_choose_req_want_activates[0:0] end - attribute \src "ls180.v:732.5-732.43" - process $proc$ls180.v:732$3048 + attribute \src "ls180.v:731.5-731.43" + process $proc$ls180.v:731$3045 assign { } { } assign $1\main_sdram_choose_req_cmd_ready[0:0] 1'0 sync always sync init update \main_sdram_choose_req_cmd_ready $1\main_sdram_choose_req_cmd_ready[0:0] end - attribute \src "ls180.v:735.5-735.49" - process $proc$ls180.v:735$3049 + attribute \src "ls180.v:734.5-734.49" + process $proc$ls180.v:734$3046 assign { } { } assign $1\main_sdram_choose_req_cmd_payload_cas[0:0] 1'0 sync always sync init update \main_sdram_choose_req_cmd_payload_cas $1\main_sdram_choose_req_cmd_payload_cas[0:0] end - attribute \src "ls180.v:7359.1-9977.4" - process $proc$ls180.v:7359$2359 + attribute \src "ls180.v:735.5-735.49" + process $proc$ls180.v:735$3047 assign { } { } + assign $1\main_sdram_choose_req_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_req_cmd_payload_ras $1\main_sdram_choose_req_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:7359.1-9973.4" + process $proc$ls180.v:7359$2358 assign $0\spi_master_clk[0:0] \spi_master_clk assign $0\spi_master_mosi[0:0] \spi_master_mosi assign { } { } @@ -122619,56 +122573,53 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_dummy[42:0] [0] $or$ls180.v:7360$2360_Y - assign $0\main_dummy[42:0] [1] $or$ls180.v:7361$2361_Y - assign $0\main_dummy[42:0] [2] $or$ls180.v:7362$2362_Y - assign $0\main_dummy[42:0] [3] $or$ls180.v:7363$2363_Y - assign $0\main_dummy[42:0] [4] $or$ls180.v:7364$2364_Y - assign $0\main_dummy[42:0] [5] $or$ls180.v:7365$2365_Y - assign $0\main_dummy[42:0] [6] $or$ls180.v:7366$2366_Y - assign $0\main_dummy[42:0] [7] $or$ls180.v:7367$2367_Y - assign $0\main_dummy[42:0] [8] $or$ls180.v:7368$2368_Y - assign $0\main_dummy[42:0] [9] $or$ls180.v:7369$2369_Y - assign $0\main_dummy[42:0] [10] $or$ls180.v:7370$2370_Y - assign $0\main_dummy[42:0] [11] $or$ls180.v:7371$2371_Y - assign $0\main_dummy[42:0] [12] $or$ls180.v:7372$2372_Y - assign $0\main_dummy[42:0] [13] $or$ls180.v:7373$2373_Y - assign $0\main_dummy[42:0] [14] $or$ls180.v:7374$2374_Y - assign $0\main_dummy[42:0] [15] $or$ls180.v:7375$2375_Y - assign $0\main_dummy[42:0] [16] $or$ls180.v:7376$2376_Y - assign $0\main_dummy[42:0] [17] $or$ls180.v:7377$2377_Y - assign $0\main_dummy[42:0] [18] $or$ls180.v:7378$2378_Y - assign $0\main_dummy[42:0] [19] $or$ls180.v:7379$2379_Y - assign $0\main_dummy[42:0] [20] $or$ls180.v:7380$2380_Y - assign $0\main_dummy[42:0] [21] $or$ls180.v:7381$2381_Y - assign $0\main_dummy[42:0] [22] $or$ls180.v:7382$2382_Y - assign $0\main_dummy[42:0] [23] $or$ls180.v:7383$2383_Y - assign $0\main_dummy[42:0] [24] $or$ls180.v:7384$2384_Y - assign $0\main_dummy[42:0] [25] $or$ls180.v:7385$2385_Y - assign $0\main_dummy[42:0] [26] $or$ls180.v:7386$2386_Y - assign $0\main_dummy[42:0] [27] $or$ls180.v:7387$2387_Y - assign $0\main_dummy[42:0] [28] $or$ls180.v:7388$2388_Y - assign $0\main_dummy[42:0] [29] $or$ls180.v:7389$2389_Y - assign $0\main_dummy[42:0] [30] $or$ls180.v:7390$2390_Y - assign $0\main_dummy[42:0] [31] $or$ls180.v:7391$2391_Y - assign $0\main_dummy[42:0] [32] $or$ls180.v:7392$2392_Y - assign $0\main_dummy[42:0] [33] $or$ls180.v:7393$2393_Y - assign $0\main_dummy[42:0] [34] $or$ls180.v:7394$2394_Y - assign $0\main_dummy[42:0] [35] $or$ls180.v:7395$2395_Y - assign $0\main_dummy[42:0] [36] $or$ls180.v:7396$2396_Y - assign $0\main_dummy[42:0] [37] $or$ls180.v:7397$2397_Y - assign $0\main_dummy[42:0] [38] $or$ls180.v:7398$2398_Y - assign $0\main_dummy[42:0] [39] $or$ls180.v:7399$2399_Y - assign $0\main_dummy[42:0] [40] $or$ls180.v:7400$2400_Y - assign $0\main_dummy[42:0] [41] $or$ls180.v:7401$2401_Y - assign $0\main_dummy[42:0] [42] $or$ls180.v:7402$2402_Y + assign $0\main_dummy[41:0] [0] $or$ls180.v:7360$2359_Y + assign $0\main_dummy[41:0] [1] $or$ls180.v:7361$2360_Y + assign $0\main_dummy[41:0] [2] $or$ls180.v:7362$2361_Y + assign $0\main_dummy[41:0] [3] $or$ls180.v:7363$2362_Y + assign $0\main_dummy[41:0] [4] $or$ls180.v:7364$2363_Y + assign $0\main_dummy[41:0] [5] $or$ls180.v:7365$2364_Y + assign $0\main_dummy[41:0] [6] $or$ls180.v:7366$2365_Y + assign $0\main_dummy[41:0] [7] $or$ls180.v:7367$2366_Y + assign $0\main_dummy[41:0] [8] $or$ls180.v:7368$2367_Y + assign $0\main_dummy[41:0] [9] $or$ls180.v:7369$2368_Y + assign $0\main_dummy[41:0] [10] $or$ls180.v:7370$2369_Y + assign $0\main_dummy[41:0] [11] $or$ls180.v:7371$2370_Y + assign $0\main_dummy[41:0] [12] $or$ls180.v:7372$2371_Y + assign $0\main_dummy[41:0] [13] $or$ls180.v:7373$2372_Y + assign $0\main_dummy[41:0] [14] $or$ls180.v:7374$2373_Y + assign $0\main_dummy[41:0] [15] $or$ls180.v:7375$2374_Y + assign $0\main_dummy[41:0] [16] $or$ls180.v:7376$2375_Y + assign $0\main_dummy[41:0] [17] $or$ls180.v:7377$2376_Y + assign $0\main_dummy[41:0] [18] $or$ls180.v:7378$2377_Y + assign $0\main_dummy[41:0] [19] $or$ls180.v:7379$2378_Y + assign $0\main_dummy[41:0] [20] $or$ls180.v:7380$2379_Y + assign $0\main_dummy[41:0] [21] $or$ls180.v:7381$2380_Y + assign $0\main_dummy[41:0] [22] $or$ls180.v:7382$2381_Y + assign $0\main_dummy[41:0] [23] $or$ls180.v:7383$2382_Y + assign $0\main_dummy[41:0] [24] $or$ls180.v:7384$2383_Y + assign $0\main_dummy[41:0] [25] $or$ls180.v:7385$2384_Y + assign $0\main_dummy[41:0] [26] $or$ls180.v:7386$2385_Y + assign $0\main_dummy[41:0] [27] $or$ls180.v:7387$2386_Y + assign $0\main_dummy[41:0] [28] $or$ls180.v:7388$2387_Y + assign $0\main_dummy[41:0] [29] $or$ls180.v:7389$2388_Y + assign $0\main_dummy[41:0] [30] $or$ls180.v:7390$2389_Y + assign $0\main_dummy[41:0] [31] $or$ls180.v:7391$2390_Y + assign $0\main_dummy[41:0] [32] $or$ls180.v:7392$2391_Y + assign $0\main_dummy[41:0] [33] $or$ls180.v:7393$2392_Y + assign $0\main_dummy[41:0] [34] $or$ls180.v:7394$2393_Y + assign $0\main_dummy[41:0] [35] $or$ls180.v:7395$2394_Y + assign $0\main_dummy[41:0] [36] $or$ls180.v:7396$2395_Y + assign $0\main_dummy[41:0] [37] $or$ls180.v:7397$2396_Y + assign $0\main_dummy[41:0] [38] $or$ls180.v:7398$2397_Y + assign $0\main_dummy[41:0] [39] $or$ls180.v:7399$2398_Y + assign $0\main_dummy[41:0] [40] $or$ls180.v:7400$2399_Y + assign $0\main_dummy[41:0] [41] $or$ls180.v:7401$2400_Y assign $0\builder_converter0_state[0:0] \builder_converter0_next_state assign $0\builder_converter1_state[0:0] \builder_converter1_next_state assign $0\builder_converter2_state[0:0] \builder_converter2_next_state assign $0\main_libresocsim_ram_bus_ack[0:0] 1'0 assign $0\main_libresocsim_zero_old_trigger[0:0] \main_libresocsim_zero_trigger - assign $0\sdram_dm[1:0] [0] \main_dm [0] - assign $0\sdram_dm[1:0] [1] \main_dm [1] assign $0\main_rddata_en[2:0] { \main_rddata_en [1:0] \main_dfi_p0_rddata_en } assign $0\main_dfi_p0_rddata_valid[0:0] \main_rddata_en [2] assign $0\main_sdram_postponer_req_o[0:0] 1'0 @@ -122686,14 +122637,14 @@ module \ls180 assign $0\main_sdram_dfi_p0_cs_n[0:0] 1'0 assign $0\main_sdram_dfi_p0_bank[1:0] \builder_sync_rhs_array_muxed0 assign $0\main_sdram_dfi_p0_address[12:0] \builder_sync_rhs_array_muxed1 - assign $0\main_sdram_dfi_p0_cas_n[0:0] $not$ls180.v:7846$2499_Y - assign $0\main_sdram_dfi_p0_ras_n[0:0] $not$ls180.v:7847$2500_Y - assign $0\main_sdram_dfi_p0_we_n[0:0] $not$ls180.v:7848$2501_Y + assign $0\main_sdram_dfi_p0_cas_n[0:0] $not$ls180.v:7843$2497_Y + assign $0\main_sdram_dfi_p0_ras_n[0:0] $not$ls180.v:7844$2498_Y + assign $0\main_sdram_dfi_p0_we_n[0:0] $not$ls180.v:7845$2499_Y assign $0\main_sdram_dfi_p0_rddata_en[0:0] \builder_sync_rhs_array_muxed5 assign $0\main_sdram_dfi_p0_wrdata_en[0:0] \builder_sync_rhs_array_muxed6 assign $0\builder_multiplexer_state[2:0] \builder_multiplexer_next_state - assign $0\builder_new_master_wdata_ready[0:0] $or$ls180.v:7882$2519_Y - assign $0\builder_new_master_rdata_valid0[0:0] $or$ls180.v:7883$2531_Y + assign $0\builder_new_master_wdata_ready[0:0] $or$ls180.v:7879$2517_Y + assign $0\builder_new_master_rdata_valid0[0:0] $or$ls180.v:7880$2529_Y assign $0\builder_new_master_rdata_valid1[0:0] \builder_new_master_rdata_valid0 assign $0\builder_new_master_rdata_valid2[0:0] \builder_new_master_rdata_valid1 assign $0\builder_new_master_rdata_valid3[0:0] \builder_new_master_rdata_valid2 @@ -122703,8 +122654,8 @@ module \ls180 assign $0\main_rx_r[0:0] \main_rx assign $0\main_uart_tx_old_trigger[0:0] \main_uart_tx_trigger assign $0\main_uart_rx_old_trigger[0:0] \main_uart_rx_trigger - assign $0\main_spi_master_clk_divider1[15:0] $add$ls180.v:8041$2577_Y - assign $0\spi_master_cs_n[0:0] $or$ls180.v:8050$2580_Y + assign $0\main_spi_master_clk_divider1[15:0] $add$ls180.v:8038$2575_Y + assign $0\spi_master_cs_n[0:0] $or$ls180.v:8047$2578_Y assign $0\builder_spimaster0_state[1:0] \builder_spimaster0_next_state assign $0\main_sdphy_clocker_clk_d[0:0] \main_sdphy_clocker_clk1 assign $0\main_sdphy_clocker_clk0[0:0] \main_sdphy_clocker_clk1 @@ -122719,8 +122670,8 @@ module \ls180 assign $0\builder_sdblock2memdma_state[1:0] \builder_sdblock2memdma_next_state assign $0\builder_sdmem2blockdma_fsm_state[0:0] \builder_sdmem2blockdma_fsm_next_state assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] \builder_sdmem2blockdma_resetinserter_next_state - assign $0\libresocsim_clk_divider1[15:0] $add$ls180.v:8589$2672_Y - assign $0\spisdcard_cs_n[0:0] $or$ls180.v:8598$2675_Y + assign $0\libresocsim_clk_divider1[15:0] $add$ls180.v:8586$2670_Y + assign $0\spisdcard_cs_n[0:0] $or$ls180.v:8595$2673_Y assign $0\builder_spimaster1_state[1:0] \builder_spimaster1_next_state assign $0\builder_state[1:0] \builder_next_state assign $0\builder_slave_sel_r[4:0] \builder_slave_sel @@ -122816,154 +122767,154 @@ module \ls180 assign $0\builder_multiregimpl15_regs1[0:0] \builder_multiregimpl15_regs0 assign $0\builder_multiregimpl16_regs0[0:0] \main_gpio_pads_i [15] assign $0\builder_multiregimpl16_regs1[0:0] \builder_multiregimpl16_regs0 - attribute \src "ls180.v:7403.2-7405.5" - switch $or$ls180.v:7403$2403_Y - attribute \src "ls180.v:7403.6-7403.94" + attribute \src "ls180.v:7402.2-7404.5" + switch $or$ls180.v:7402$2401_Y + attribute \src "ls180.v:7402.6-7402.94" case 1'1 assign $0\main_libresocsim_converter0_dat_r[63:0] \main_libresocsim_libresoc_ibus_dat_r case end - attribute \src "ls180.v:7407.2-7409.5" + attribute \src "ls180.v:7406.2-7408.5" switch \main_libresocsim_converter0_counter_converter0_next_value_ce - attribute \src "ls180.v:7407.6-7407.66" + attribute \src "ls180.v:7406.6-7406.66" case 1'1 assign $0\main_libresocsim_converter0_counter[0:0] \main_libresocsim_converter0_counter_converter0_next_value case end - attribute \src "ls180.v:7410.2-7413.5" + attribute \src "ls180.v:7409.2-7412.5" switch \main_libresocsim_converter0_reset - attribute \src "ls180.v:7410.6-7410.39" + attribute \src "ls180.v:7409.6-7409.39" case 1'1 assign $0\main_libresocsim_converter0_counter[0:0] 1'0 assign $0\builder_converter0_state[0:0] 1'0 case end - attribute \src "ls180.v:7414.2-7416.5" - switch $or$ls180.v:7414$2404_Y - attribute \src "ls180.v:7414.6-7414.94" + attribute \src "ls180.v:7413.2-7415.5" + switch $or$ls180.v:7413$2402_Y + attribute \src "ls180.v:7413.6-7413.94" case 1'1 assign $0\main_libresocsim_converter1_dat_r[63:0] \main_libresocsim_libresoc_dbus_dat_r case end - attribute \src "ls180.v:7418.2-7420.5" + attribute \src "ls180.v:7417.2-7419.5" switch \main_libresocsim_converter1_counter_converter1_next_value_ce - attribute \src "ls180.v:7418.6-7418.66" + attribute \src "ls180.v:7417.6-7417.66" case 1'1 assign $0\main_libresocsim_converter1_counter[0:0] \main_libresocsim_converter1_counter_converter1_next_value case end - attribute \src "ls180.v:7421.2-7424.5" + attribute \src "ls180.v:7420.2-7423.5" switch \main_libresocsim_converter1_reset - attribute \src "ls180.v:7421.6-7421.39" + attribute \src "ls180.v:7420.6-7420.39" case 1'1 assign $0\main_libresocsim_converter1_counter[0:0] 1'0 assign $0\builder_converter1_state[0:0] 1'0 case end - attribute \src "ls180.v:7425.2-7427.5" - switch $or$ls180.v:7425$2405_Y - attribute \src "ls180.v:7425.6-7425.94" + attribute \src "ls180.v:7424.2-7426.5" + switch $or$ls180.v:7424$2403_Y + attribute \src "ls180.v:7424.6-7424.94" case 1'1 assign $0\main_libresocsim_converter2_dat_r[63:0] \main_libresocsim_libresoc_jtag_wb_dat_r case end - attribute \src "ls180.v:7429.2-7431.5" + attribute \src "ls180.v:7428.2-7430.5" switch \main_libresocsim_converter2_counter_converter2_next_value_ce - attribute \src "ls180.v:7429.6-7429.66" + attribute \src "ls180.v:7428.6-7428.66" case 1'1 assign $0\main_libresocsim_converter2_counter[0:0] \main_libresocsim_converter2_counter_converter2_next_value case end - attribute \src "ls180.v:7432.2-7435.5" + attribute \src "ls180.v:7431.2-7434.5" switch \main_libresocsim_converter2_reset - attribute \src "ls180.v:7432.6-7432.39" + attribute \src "ls180.v:7431.6-7431.39" case 1'1 assign $0\main_libresocsim_converter2_counter[0:0] 1'0 assign $0\builder_converter2_state[0:0] 1'0 case end - attribute \src "ls180.v:7436.2-7440.5" - switch $ne$ls180.v:7436$2406_Y - attribute \src "ls180.v:7436.6-7436.53" + attribute \src "ls180.v:7435.2-7439.5" + switch $ne$ls180.v:7435$2404_Y + attribute \src "ls180.v:7435.6-7435.53" case 1'1 - attribute \src "ls180.v:7437.3-7439.6" + attribute \src "ls180.v:7436.3-7438.6" switch \main_libresocsim_bus_error - attribute \src "ls180.v:7437.7-7437.33" + attribute \src "ls180.v:7436.7-7436.33" case 1'1 - assign $0\main_libresocsim_bus_errors[31:0] $add$ls180.v:7438$2407_Y + assign $0\main_libresocsim_bus_errors[31:0] $add$ls180.v:7437$2405_Y case end case end - attribute \src "ls180.v:7442.2-7444.5" - switch $and$ls180.v:7442$2410_Y - attribute \src "ls180.v:7442.6-7442.103" + attribute \src "ls180.v:7441.2-7443.5" + switch $and$ls180.v:7441$2408_Y + attribute \src "ls180.v:7441.6-7441.103" case 1'1 assign $0\main_libresocsim_ram_bus_ack[0:0] 1'1 case end - attribute \src "ls180.v:7445.2-7453.5" + attribute \src "ls180.v:7444.2-7452.5" switch \main_libresocsim_en_storage - attribute \src "ls180.v:7445.6-7445.33" + attribute \src "ls180.v:7444.6-7444.33" case 1'1 - attribute \src "ls180.v:7446.3-7450.6" - switch $eq$ls180.v:7446$2411_Y - attribute \src "ls180.v:7446.7-7446.39" + attribute \src "ls180.v:7445.3-7449.6" + switch $eq$ls180.v:7445$2409_Y + attribute \src "ls180.v:7445.7-7445.39" case 1'1 assign $0\main_libresocsim_value[31:0] \main_libresocsim_reload_storage - attribute \src "ls180.v:7448.7-7448.11" + attribute \src "ls180.v:7447.7-7447.11" case - assign $0\main_libresocsim_value[31:0] $sub$ls180.v:7449$2412_Y + assign $0\main_libresocsim_value[31:0] $sub$ls180.v:7448$2410_Y end - attribute \src "ls180.v:7451.6-7451.10" + attribute \src "ls180.v:7450.6-7450.10" case assign $0\main_libresocsim_value[31:0] \main_libresocsim_load_storage end - attribute \src "ls180.v:7454.2-7456.5" + attribute \src "ls180.v:7453.2-7455.5" switch \main_libresocsim_update_value_re - attribute \src "ls180.v:7454.6-7454.38" + attribute \src "ls180.v:7453.6-7453.38" case 1'1 assign $0\main_libresocsim_value_status[31:0] \main_libresocsim_value case end - attribute \src "ls180.v:7457.2-7459.5" + attribute \src "ls180.v:7456.2-7458.5" switch \main_libresocsim_zero_clear - attribute \src "ls180.v:7457.6-7457.33" + attribute \src "ls180.v:7456.6-7456.33" case 1'1 assign $0\main_libresocsim_zero_pending[0:0] 1'0 case end - attribute \src "ls180.v:7461.2-7463.5" - switch $and$ls180.v:7461$2414_Y - attribute \src "ls180.v:7461.6-7461.76" + attribute \src "ls180.v:7460.2-7462.5" + switch $and$ls180.v:7460$2412_Y + attribute \src "ls180.v:7460.6-7460.76" case 1'1 assign $0\main_libresocsim_zero_pending[0:0] 1'1 case end - attribute \src "ls180.v:7468.2-7470.5" + attribute \src "ls180.v:7465.2-7467.5" switch \main_sdram_inti_p0_rddata_valid - attribute \src "ls180.v:7468.6-7468.37" + attribute \src "ls180.v:7465.6-7465.37" case 1'1 assign $0\main_sdram_status[15:0] \main_sdram_inti_p0_rddata case end - attribute \src "ls180.v:7471.2-7475.5" - switch $and$ls180.v:7471$2416_Y - attribute \src "ls180.v:7471.6-7471.57" + attribute \src "ls180.v:7468.2-7472.5" + switch $and$ls180.v:7468$2414_Y + attribute \src "ls180.v:7468.6-7468.57" case 1'1 - assign $0\main_sdram_timer_count1[9:0] $sub$ls180.v:7472$2417_Y - attribute \src "ls180.v:7473.6-7473.10" + assign $0\main_sdram_timer_count1[9:0] $sub$ls180.v:7469$2415_Y + attribute \src "ls180.v:7470.6-7470.10" case assign $0\main_sdram_timer_count1[9:0] 10'1100001101 end - attribute \src "ls180.v:7477.2-7483.5" + attribute \src "ls180.v:7474.2-7480.5" switch \main_sdram_postponer_req_i - attribute \src "ls180.v:7477.6-7477.32" + attribute \src "ls180.v:7474.6-7474.32" case 1'1 - assign $0\main_sdram_postponer_count[0:0] $sub$ls180.v:7478$2418_Y - attribute \src "ls180.v:7479.3-7482.6" - switch $eq$ls180.v:7479$2419_Y - attribute \src "ls180.v:7479.7-7479.43" + assign $0\main_sdram_postponer_count[0:0] $sub$ls180.v:7475$2416_Y + attribute \src "ls180.v:7476.3-7479.6" + switch $eq$ls180.v:7476$2417_Y + attribute \src "ls180.v:7476.7-7476.43" case 1'1 assign $0\main_sdram_postponer_count[0:0] 1'0 assign $0\main_sdram_postponer_req_o[0:0] 1'1 @@ -122971,30 +122922,30 @@ module \ls180 end case end - attribute \src "ls180.v:7484.2-7492.5" + attribute \src "ls180.v:7481.2-7489.5" switch \main_sdram_sequencer_start0 - attribute \src "ls180.v:7484.6-7484.33" + attribute \src "ls180.v:7481.6-7481.33" case 1'1 assign $0\main_sdram_sequencer_count[0:0] 1'0 - attribute \src "ls180.v:7486.6-7486.10" + attribute \src "ls180.v:7483.6-7483.10" case - attribute \src "ls180.v:7487.3-7491.6" + attribute \src "ls180.v:7484.3-7488.6" switch \main_sdram_sequencer_done1 - attribute \src "ls180.v:7487.7-7487.33" + attribute \src "ls180.v:7484.7-7484.33" case 1'1 - attribute \src "ls180.v:7488.4-7490.7" - switch $ne$ls180.v:7488$2420_Y - attribute \src "ls180.v:7488.8-7488.44" + attribute \src "ls180.v:7485.4-7487.7" + switch $ne$ls180.v:7485$2418_Y + attribute \src "ls180.v:7485.8-7485.44" case 1'1 - assign $0\main_sdram_sequencer_count[0:0] $sub$ls180.v:7489$2421_Y + assign $0\main_sdram_sequencer_count[0:0] $sub$ls180.v:7486$2419_Y case end case end end - attribute \src "ls180.v:7499.2-7505.5" - switch $and$ls180.v:7499$2423_Y - attribute \src "ls180.v:7499.6-7499.76" + attribute \src "ls180.v:7496.2-7502.5" + switch $and$ls180.v:7496$2421_Y + attribute \src "ls180.v:7496.6-7496.76" case 1'1 assign $0\main_sdram_cmd_payload_a[12:0] 13'0010000000000 assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 @@ -123003,9 +122954,9 @@ module \ls180 assign $0\main_sdram_cmd_payload_we[0:0] 1'1 case end - attribute \src "ls180.v:7506.2-7512.5" - switch $eq$ls180.v:7506$2424_Y - attribute \src "ls180.v:7506.6-7506.44" + attribute \src "ls180.v:7503.2-7509.5" + switch $eq$ls180.v:7503$2422_Y + attribute \src "ls180.v:7503.6-7503.44" case 1'1 assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000 assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 @@ -123014,9 +122965,9 @@ module \ls180 assign $0\main_sdram_cmd_payload_we[0:0] 1'0 case end - attribute \src "ls180.v:7513.2-7520.5" - switch $eq$ls180.v:7513$2425_Y - attribute \src "ls180.v:7513.6-7513.44" + attribute \src "ls180.v:7510.2-7517.5" + switch $eq$ls180.v:7510$2423_Y + attribute \src "ls180.v:7510.6-7510.44" case 1'1 assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000 assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 @@ -123026,83 +122977,83 @@ module \ls180 assign $0\main_sdram_sequencer_done1[0:0] 1'1 case end - attribute \src "ls180.v:7521.2-7531.5" - switch $eq$ls180.v:7521$2426_Y - attribute \src "ls180.v:7521.6-7521.44" + attribute \src "ls180.v:7518.2-7528.5" + switch $eq$ls180.v:7518$2424_Y + attribute \src "ls180.v:7518.6-7518.44" case 1'1 assign $0\main_sdram_sequencer_counter[3:0] 4'0000 - attribute \src "ls180.v:7523.6-7523.10" + attribute \src "ls180.v:7520.6-7520.10" case - attribute \src "ls180.v:7524.3-7530.6" - switch $ne$ls180.v:7524$2427_Y - attribute \src "ls180.v:7524.7-7524.45" + attribute \src "ls180.v:7521.3-7527.6" + switch $ne$ls180.v:7521$2425_Y + attribute \src "ls180.v:7521.7-7521.45" case 1'1 - assign $0\main_sdram_sequencer_counter[3:0] $add$ls180.v:7525$2428_Y - attribute \src "ls180.v:7526.7-7526.11" + assign $0\main_sdram_sequencer_counter[3:0] $add$ls180.v:7522$2426_Y + attribute \src "ls180.v:7523.7-7523.11" case - attribute \src "ls180.v:7527.4-7529.7" + attribute \src "ls180.v:7524.4-7526.7" switch \main_sdram_sequencer_start1 - attribute \src "ls180.v:7527.8-7527.35" + attribute \src "ls180.v:7524.8-7524.35" case 1'1 assign $0\main_sdram_sequencer_counter[3:0] 4'0001 case end end end - attribute \src "ls180.v:7533.2-7540.5" + attribute \src "ls180.v:7530.2-7537.5" switch \main_sdram_bankmachine0_row_close - attribute \src "ls180.v:7533.6-7533.39" + attribute \src "ls180.v:7530.6-7530.39" case 1'1 assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'0 - attribute \src "ls180.v:7535.6-7535.10" + attribute \src "ls180.v:7532.6-7532.10" case - attribute \src "ls180.v:7536.3-7539.6" + attribute \src "ls180.v:7533.3-7536.6" switch \main_sdram_bankmachine0_row_open - attribute \src "ls180.v:7536.7-7536.39" + attribute \src "ls180.v:7533.7-7533.39" case 1'1 assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'1 assign $0\main_sdram_bankmachine0_row[12:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] case end end - attribute \src "ls180.v:7541.2-7543.5" - switch $and$ls180.v:7541$2431_Y - attribute \src "ls180.v:7541.6-7541.191" + attribute \src "ls180.v:7538.2-7540.5" + switch $and$ls180.v:7538$2429_Y + attribute \src "ls180.v:7538.6-7538.191" case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7542$2432_Y + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7539$2430_Y case end - attribute \src "ls180.v:7544.2-7546.5" + attribute \src "ls180.v:7541.2-7543.5" switch \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7544.6-7544.58" + attribute \src "ls180.v:7541.6-7541.58" case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7545$2433_Y + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7542$2431_Y case end - attribute \src "ls180.v:7547.2-7555.5" - switch $and$ls180.v:7547$2436_Y - attribute \src "ls180.v:7547.6-7547.191" + attribute \src "ls180.v:7544.2-7552.5" + switch $and$ls180.v:7544$2434_Y + attribute \src "ls180.v:7544.6-7544.191" case 1'1 - attribute \src "ls180.v:7548.3-7550.6" - switch $not$ls180.v:7548$2437_Y - attribute \src "ls180.v:7548.7-7548.62" + attribute \src "ls180.v:7545.3-7547.6" + switch $not$ls180.v:7545$2435_Y + attribute \src "ls180.v:7545.7-7545.62" case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7549$2438_Y + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7546$2436_Y case end - attribute \src "ls180.v:7551.6-7551.10" + attribute \src "ls180.v:7548.6-7548.10" case - attribute \src "ls180.v:7552.3-7554.6" + attribute \src "ls180.v:7549.3-7551.6" switch \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7552.7-7552.59" + attribute \src "ls180.v:7549.7-7549.59" case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7553$2439_Y + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7550$2437_Y case end end - attribute \src "ls180.v:7556.2-7562.5" - switch $or$ls180.v:7556$2441_Y - attribute \src "ls180.v:7556.6-7556.108" + attribute \src "ls180.v:7553.2-7559.5" + switch $or$ls180.v:7553$2439_Y + attribute \src "ls180.v:7553.6-7553.108" case 1'1 assign $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_valid assign $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_first @@ -123111,27 +123062,27 @@ module \ls180 assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr case end - attribute \src "ls180.v:7563.2-7577.5" + attribute \src "ls180.v:7560.2-7574.5" switch \main_sdram_bankmachine0_twtpcon_valid - attribute \src "ls180.v:7563.6-7563.43" + attribute \src "ls180.v:7560.6-7560.43" case 1'1 assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] 3'100 - attribute \src "ls180.v:7565.3-7569.6" + attribute \src "ls180.v:7562.3-7566.6" switch 1'0 - attribute \src "ls180.v:7567.7-7567.11" + attribute \src "ls180.v:7564.7-7564.11" case assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 end - attribute \src "ls180.v:7570.6-7570.10" + attribute \src "ls180.v:7567.6-7567.10" case - attribute \src "ls180.v:7571.3-7576.6" - switch $not$ls180.v:7571$2442_Y - attribute \src "ls180.v:7571.7-7571.47" + attribute \src "ls180.v:7568.3-7573.6" + switch $not$ls180.v:7568$2440_Y + attribute \src "ls180.v:7568.7-7568.47" case 1'1 - assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] $sub$ls180.v:7572$2443_Y - attribute \src "ls180.v:7573.4-7575.7" - switch $eq$ls180.v:7573$2444_Y - attribute \src "ls180.v:7573.8-7573.55" + assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] $sub$ls180.v:7569$2441_Y + attribute \src "ls180.v:7570.4-7572.7" + switch $eq$ls180.v:7570$2442_Y + attribute \src "ls180.v:7570.8-7570.55" case 1'1 assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'1 case @@ -123139,60 +123090,60 @@ module \ls180 case end end - attribute \src "ls180.v:7579.2-7586.5" + attribute \src "ls180.v:7576.2-7583.5" switch \main_sdram_bankmachine1_row_close - attribute \src "ls180.v:7579.6-7579.39" + attribute \src "ls180.v:7576.6-7576.39" case 1'1 assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'0 - attribute \src "ls180.v:7581.6-7581.10" + attribute \src "ls180.v:7578.6-7578.10" case - attribute \src "ls180.v:7582.3-7585.6" + attribute \src "ls180.v:7579.3-7582.6" switch \main_sdram_bankmachine1_row_open - attribute \src "ls180.v:7582.7-7582.39" + attribute \src "ls180.v:7579.7-7579.39" case 1'1 assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'1 assign $0\main_sdram_bankmachine1_row[12:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] case end end - attribute \src "ls180.v:7587.2-7589.5" - switch $and$ls180.v:7587$2447_Y - attribute \src "ls180.v:7587.6-7587.191" + attribute \src "ls180.v:7584.2-7586.5" + switch $and$ls180.v:7584$2445_Y + attribute \src "ls180.v:7584.6-7584.191" case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7588$2448_Y + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7585$2446_Y case end - attribute \src "ls180.v:7590.2-7592.5" + attribute \src "ls180.v:7587.2-7589.5" switch \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7590.6-7590.58" + attribute \src "ls180.v:7587.6-7587.58" case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7591$2449_Y + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7588$2447_Y case end - attribute \src "ls180.v:7593.2-7601.5" - switch $and$ls180.v:7593$2452_Y - attribute \src "ls180.v:7593.6-7593.191" + attribute \src "ls180.v:7590.2-7598.5" + switch $and$ls180.v:7590$2450_Y + attribute \src "ls180.v:7590.6-7590.191" case 1'1 - attribute \src "ls180.v:7594.3-7596.6" - switch $not$ls180.v:7594$2453_Y - attribute \src "ls180.v:7594.7-7594.62" + attribute \src "ls180.v:7591.3-7593.6" + switch $not$ls180.v:7591$2451_Y + attribute \src "ls180.v:7591.7-7591.62" case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7595$2454_Y + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7592$2452_Y case end - attribute \src "ls180.v:7597.6-7597.10" + attribute \src "ls180.v:7594.6-7594.10" case - attribute \src "ls180.v:7598.3-7600.6" + attribute \src "ls180.v:7595.3-7597.6" switch \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7598.7-7598.59" + attribute \src "ls180.v:7595.7-7595.59" case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7599$2455_Y + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7596$2453_Y case end end - attribute \src "ls180.v:7602.2-7608.5" - switch $or$ls180.v:7602$2457_Y - attribute \src "ls180.v:7602.6-7602.108" + attribute \src "ls180.v:7599.2-7605.5" + switch $or$ls180.v:7599$2455_Y + attribute \src "ls180.v:7599.6-7599.108" case 1'1 assign $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_valid assign $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_first @@ -123201,27 +123152,27 @@ module \ls180 assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr case end - attribute \src "ls180.v:7609.2-7623.5" + attribute \src "ls180.v:7606.2-7620.5" switch \main_sdram_bankmachine1_twtpcon_valid - attribute \src "ls180.v:7609.6-7609.43" + attribute \src "ls180.v:7606.6-7606.43" case 1'1 assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] 3'100 - attribute \src "ls180.v:7611.3-7615.6" + attribute \src "ls180.v:7608.3-7612.6" switch 1'0 - attribute \src "ls180.v:7613.7-7613.11" + attribute \src "ls180.v:7610.7-7610.11" case assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0 end - attribute \src "ls180.v:7616.6-7616.10" + attribute \src "ls180.v:7613.6-7613.10" case - attribute \src "ls180.v:7617.3-7622.6" - switch $not$ls180.v:7617$2458_Y - attribute \src "ls180.v:7617.7-7617.47" + attribute \src "ls180.v:7614.3-7619.6" + switch $not$ls180.v:7614$2456_Y + attribute \src "ls180.v:7614.7-7614.47" case 1'1 - assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] $sub$ls180.v:7618$2459_Y - attribute \src "ls180.v:7619.4-7621.7" - switch $eq$ls180.v:7619$2460_Y - attribute \src "ls180.v:7619.8-7619.55" + assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] $sub$ls180.v:7615$2457_Y + attribute \src "ls180.v:7616.4-7618.7" + switch $eq$ls180.v:7616$2458_Y + attribute \src "ls180.v:7616.8-7616.55" case 1'1 assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'1 case @@ -123229,60 +123180,60 @@ module \ls180 case end end - attribute \src "ls180.v:7625.2-7632.5" + attribute \src "ls180.v:7622.2-7629.5" switch \main_sdram_bankmachine2_row_close - attribute \src "ls180.v:7625.6-7625.39" + attribute \src "ls180.v:7622.6-7622.39" case 1'1 assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'0 - attribute \src "ls180.v:7627.6-7627.10" + attribute \src "ls180.v:7624.6-7624.10" case - attribute \src "ls180.v:7628.3-7631.6" + attribute \src "ls180.v:7625.3-7628.6" switch \main_sdram_bankmachine2_row_open - attribute \src "ls180.v:7628.7-7628.39" + attribute \src "ls180.v:7625.7-7625.39" case 1'1 assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'1 assign $0\main_sdram_bankmachine2_row[12:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] case end end - attribute \src "ls180.v:7633.2-7635.5" - switch $and$ls180.v:7633$2463_Y - attribute \src "ls180.v:7633.6-7633.191" + attribute \src "ls180.v:7630.2-7632.5" + switch $and$ls180.v:7630$2461_Y + attribute \src "ls180.v:7630.6-7630.191" case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7634$2464_Y + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7631$2462_Y case end - attribute \src "ls180.v:7636.2-7638.5" + attribute \src "ls180.v:7633.2-7635.5" switch \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7636.6-7636.58" + attribute \src "ls180.v:7633.6-7633.58" case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7637$2465_Y + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7634$2463_Y case end - attribute \src "ls180.v:7639.2-7647.5" - switch $and$ls180.v:7639$2468_Y - attribute \src "ls180.v:7639.6-7639.191" + attribute \src "ls180.v:7636.2-7644.5" + switch $and$ls180.v:7636$2466_Y + attribute \src "ls180.v:7636.6-7636.191" case 1'1 - attribute \src "ls180.v:7640.3-7642.6" - switch $not$ls180.v:7640$2469_Y - attribute \src "ls180.v:7640.7-7640.62" + attribute \src "ls180.v:7637.3-7639.6" + switch $not$ls180.v:7637$2467_Y + attribute \src "ls180.v:7637.7-7637.62" case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7641$2470_Y + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7638$2468_Y case end - attribute \src "ls180.v:7643.6-7643.10" + attribute \src "ls180.v:7640.6-7640.10" case - attribute \src "ls180.v:7644.3-7646.6" + attribute \src "ls180.v:7641.3-7643.6" switch \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7644.7-7644.59" + attribute \src "ls180.v:7641.7-7641.59" case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7645$2471_Y + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7642$2469_Y case end end - attribute \src "ls180.v:7648.2-7654.5" - switch $or$ls180.v:7648$2473_Y - attribute \src "ls180.v:7648.6-7648.108" + attribute \src "ls180.v:7645.2-7651.5" + switch $or$ls180.v:7645$2471_Y + attribute \src "ls180.v:7645.6-7645.108" case 1'1 assign $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_valid assign $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_first @@ -123291,27 +123242,27 @@ module \ls180 assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr case end - attribute \src "ls180.v:7655.2-7669.5" + attribute \src "ls180.v:7652.2-7666.5" switch \main_sdram_bankmachine2_twtpcon_valid - attribute \src "ls180.v:7655.6-7655.43" + attribute \src "ls180.v:7652.6-7652.43" case 1'1 assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] 3'100 - attribute \src "ls180.v:7657.3-7661.6" + attribute \src "ls180.v:7654.3-7658.6" switch 1'0 - attribute \src "ls180.v:7659.7-7659.11" + attribute \src "ls180.v:7656.7-7656.11" case assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 end - attribute \src "ls180.v:7662.6-7662.10" + attribute \src "ls180.v:7659.6-7659.10" case - attribute \src "ls180.v:7663.3-7668.6" - switch $not$ls180.v:7663$2474_Y - attribute \src "ls180.v:7663.7-7663.47" + attribute \src "ls180.v:7660.3-7665.6" + switch $not$ls180.v:7660$2472_Y + attribute \src "ls180.v:7660.7-7660.47" case 1'1 - assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] $sub$ls180.v:7664$2475_Y - attribute \src "ls180.v:7665.4-7667.7" - switch $eq$ls180.v:7665$2476_Y - attribute \src "ls180.v:7665.8-7665.55" + assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] $sub$ls180.v:7661$2473_Y + attribute \src "ls180.v:7662.4-7664.7" + switch $eq$ls180.v:7662$2474_Y + attribute \src "ls180.v:7662.8-7662.55" case 1'1 assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'1 case @@ -123319,60 +123270,60 @@ module \ls180 case end end - attribute \src "ls180.v:7671.2-7678.5" + attribute \src "ls180.v:7668.2-7675.5" switch \main_sdram_bankmachine3_row_close - attribute \src "ls180.v:7671.6-7671.39" + attribute \src "ls180.v:7668.6-7668.39" case 1'1 assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'0 - attribute \src "ls180.v:7673.6-7673.10" + attribute \src "ls180.v:7670.6-7670.10" case - attribute \src "ls180.v:7674.3-7677.6" + attribute \src "ls180.v:7671.3-7674.6" switch \main_sdram_bankmachine3_row_open - attribute \src "ls180.v:7674.7-7674.39" + attribute \src "ls180.v:7671.7-7671.39" case 1'1 assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'1 assign $0\main_sdram_bankmachine3_row[12:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] case end end - attribute \src "ls180.v:7679.2-7681.5" - switch $and$ls180.v:7679$2479_Y - attribute \src "ls180.v:7679.6-7679.191" + attribute \src "ls180.v:7676.2-7678.5" + switch $and$ls180.v:7676$2477_Y + attribute \src "ls180.v:7676.6-7676.191" case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7680$2480_Y + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7677$2478_Y case end - attribute \src "ls180.v:7682.2-7684.5" + attribute \src "ls180.v:7679.2-7681.5" switch \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7682.6-7682.58" + attribute \src "ls180.v:7679.6-7679.58" case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7683$2481_Y + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7680$2479_Y case end - attribute \src "ls180.v:7685.2-7693.5" - switch $and$ls180.v:7685$2484_Y - attribute \src "ls180.v:7685.6-7685.191" + attribute \src "ls180.v:7682.2-7690.5" + switch $and$ls180.v:7682$2482_Y + attribute \src "ls180.v:7682.6-7682.191" case 1'1 - attribute \src "ls180.v:7686.3-7688.6" - switch $not$ls180.v:7686$2485_Y - attribute \src "ls180.v:7686.7-7686.62" + attribute \src "ls180.v:7683.3-7685.6" + switch $not$ls180.v:7683$2483_Y + attribute \src "ls180.v:7683.7-7683.62" case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7687$2486_Y + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7684$2484_Y case end - attribute \src "ls180.v:7689.6-7689.10" + attribute \src "ls180.v:7686.6-7686.10" case - attribute \src "ls180.v:7690.3-7692.6" + attribute \src "ls180.v:7687.3-7689.6" switch \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7690.7-7690.59" + attribute \src "ls180.v:7687.7-7687.59" case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7691$2487_Y + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7688$2485_Y case end end - attribute \src "ls180.v:7694.2-7700.5" - switch $or$ls180.v:7694$2489_Y - attribute \src "ls180.v:7694.6-7694.108" + attribute \src "ls180.v:7691.2-7697.5" + switch $or$ls180.v:7691$2487_Y + attribute \src "ls180.v:7691.6-7691.108" case 1'1 assign $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_valid assign $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_first @@ -123381,27 +123332,27 @@ module \ls180 assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr case end - attribute \src "ls180.v:7701.2-7715.5" + attribute \src "ls180.v:7698.2-7712.5" switch \main_sdram_bankmachine3_twtpcon_valid - attribute \src "ls180.v:7701.6-7701.43" + attribute \src "ls180.v:7698.6-7698.43" case 1'1 assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] 3'100 - attribute \src "ls180.v:7703.3-7707.6" + attribute \src "ls180.v:7700.3-7704.6" switch 1'0 - attribute \src "ls180.v:7705.7-7705.11" + attribute \src "ls180.v:7702.7-7702.11" case assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0 end - attribute \src "ls180.v:7708.6-7708.10" + attribute \src "ls180.v:7705.6-7705.10" case - attribute \src "ls180.v:7709.3-7714.6" - switch $not$ls180.v:7709$2490_Y - attribute \src "ls180.v:7709.7-7709.47" + attribute \src "ls180.v:7706.3-7711.6" + switch $not$ls180.v:7706$2488_Y + attribute \src "ls180.v:7706.7-7706.47" case 1'1 - assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] $sub$ls180.v:7710$2491_Y - attribute \src "ls180.v:7711.4-7713.7" - switch $eq$ls180.v:7711$2492_Y - attribute \src "ls180.v:7711.8-7711.55" + assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] $sub$ls180.v:7707$2489_Y + attribute \src "ls180.v:7708.4-7710.7" + switch $eq$ls180.v:7708$2490_Y + attribute \src "ls180.v:7708.8-7708.55" case 1'1 assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'1 case @@ -123409,61 +123360,61 @@ module \ls180 case end end - attribute \src "ls180.v:7717.2-7723.5" - switch $not$ls180.v:7717$2493_Y - attribute \src "ls180.v:7717.6-7717.23" + attribute \src "ls180.v:7714.2-7720.5" + switch $not$ls180.v:7714$2491_Y + attribute \src "ls180.v:7714.6-7714.23" case 1'1 assign $0\main_sdram_time0[4:0] 5'11111 - attribute \src "ls180.v:7719.6-7719.10" + attribute \src "ls180.v:7716.6-7716.10" case - attribute \src "ls180.v:7720.3-7722.6" - switch $not$ls180.v:7720$2494_Y - attribute \src "ls180.v:7720.7-7720.30" + attribute \src "ls180.v:7717.3-7719.6" + switch $not$ls180.v:7717$2492_Y + attribute \src "ls180.v:7717.7-7717.30" case 1'1 - assign $0\main_sdram_time0[4:0] $sub$ls180.v:7721$2495_Y + assign $0\main_sdram_time0[4:0] $sub$ls180.v:7718$2493_Y case end end - attribute \src "ls180.v:7724.2-7730.5" - switch $not$ls180.v:7724$2496_Y - attribute \src "ls180.v:7724.6-7724.23" + attribute \src "ls180.v:7721.2-7727.5" + switch $not$ls180.v:7721$2494_Y + attribute \src "ls180.v:7721.6-7721.23" case 1'1 assign $0\main_sdram_time1[3:0] 4'1111 - attribute \src "ls180.v:7726.6-7726.10" + attribute \src "ls180.v:7723.6-7723.10" case - attribute \src "ls180.v:7727.3-7729.6" - switch $not$ls180.v:7727$2497_Y - attribute \src "ls180.v:7727.7-7727.30" + attribute \src "ls180.v:7724.3-7726.6" + switch $not$ls180.v:7724$2495_Y + attribute \src "ls180.v:7724.7-7724.30" case 1'1 - assign $0\main_sdram_time1[3:0] $sub$ls180.v:7728$2498_Y + assign $0\main_sdram_time1[3:0] $sub$ls180.v:7725$2496_Y case end end - attribute \src "ls180.v:7731.2-7786.5" + attribute \src "ls180.v:7728.2-7783.5" switch \main_sdram_choose_cmd_ce - attribute \src "ls180.v:7731.6-7731.30" + attribute \src "ls180.v:7728.6-7728.30" case 1'1 - attribute \src "ls180.v:7732.3-7785.10" + attribute \src "ls180.v:7729.3-7782.10" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 - attribute \src "ls180.v:7734.5-7744.8" + attribute \src "ls180.v:7731.5-7741.8" switch \main_sdram_choose_cmd_request [1] - attribute \src "ls180.v:7734.9-7734.41" + attribute \src "ls180.v:7731.9-7731.41" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 - attribute \src "ls180.v:7736.9-7736.13" + attribute \src "ls180.v:7733.9-7733.13" case - attribute \src "ls180.v:7737.6-7743.9" + attribute \src "ls180.v:7734.6-7740.9" switch \main_sdram_choose_cmd_request [2] - attribute \src "ls180.v:7737.10-7737.42" + attribute \src "ls180.v:7734.10-7734.42" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 - attribute \src "ls180.v:7739.10-7739.14" + attribute \src "ls180.v:7736.10-7736.14" case - attribute \src "ls180.v:7740.7-7742.10" + attribute \src "ls180.v:7737.7-7739.10" switch \main_sdram_choose_cmd_request [3] - attribute \src "ls180.v:7740.11-7740.43" + attribute \src "ls180.v:7737.11-7737.43" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 case @@ -123472,23 +123423,23 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 2'01 - attribute \src "ls180.v:7747.5-7757.8" + attribute \src "ls180.v:7744.5-7754.8" switch \main_sdram_choose_cmd_request [2] - attribute \src "ls180.v:7747.9-7747.41" + attribute \src "ls180.v:7744.9-7744.41" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 - attribute \src "ls180.v:7749.9-7749.13" + attribute \src "ls180.v:7746.9-7746.13" case - attribute \src "ls180.v:7750.6-7756.9" + attribute \src "ls180.v:7747.6-7753.9" switch \main_sdram_choose_cmd_request [3] - attribute \src "ls180.v:7750.10-7750.42" + attribute \src "ls180.v:7747.10-7747.42" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 - attribute \src "ls180.v:7752.10-7752.14" + attribute \src "ls180.v:7749.10-7749.14" case - attribute \src "ls180.v:7753.7-7755.10" + attribute \src "ls180.v:7750.7-7752.10" switch \main_sdram_choose_cmd_request [0] - attribute \src "ls180.v:7753.11-7753.43" + attribute \src "ls180.v:7750.11-7750.43" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 case @@ -123497,23 +123448,23 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 2'10 - attribute \src "ls180.v:7760.5-7770.8" + attribute \src "ls180.v:7757.5-7767.8" switch \main_sdram_choose_cmd_request [3] - attribute \src "ls180.v:7760.9-7760.41" + attribute \src "ls180.v:7757.9-7757.41" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 - attribute \src "ls180.v:7762.9-7762.13" + attribute \src "ls180.v:7759.9-7759.13" case - attribute \src "ls180.v:7763.6-7769.9" + attribute \src "ls180.v:7760.6-7766.9" switch \main_sdram_choose_cmd_request [0] - attribute \src "ls180.v:7763.10-7763.42" + attribute \src "ls180.v:7760.10-7760.42" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 - attribute \src "ls180.v:7765.10-7765.14" + attribute \src "ls180.v:7762.10-7762.14" case - attribute \src "ls180.v:7766.7-7768.10" + attribute \src "ls180.v:7763.7-7765.10" switch \main_sdram_choose_cmd_request [1] - attribute \src "ls180.v:7766.11-7766.43" + attribute \src "ls180.v:7763.11-7763.43" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 case @@ -123522,23 +123473,23 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 2'11 - attribute \src "ls180.v:7773.5-7783.8" + attribute \src "ls180.v:7770.5-7780.8" switch \main_sdram_choose_cmd_request [0] - attribute \src "ls180.v:7773.9-7773.41" + attribute \src "ls180.v:7770.9-7770.41" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 - attribute \src "ls180.v:7775.9-7775.13" + attribute \src "ls180.v:7772.9-7772.13" case - attribute \src "ls180.v:7776.6-7782.9" + attribute \src "ls180.v:7773.6-7779.9" switch \main_sdram_choose_cmd_request [1] - attribute \src "ls180.v:7776.10-7776.42" + attribute \src "ls180.v:7773.10-7773.42" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 - attribute \src "ls180.v:7778.10-7778.14" + attribute \src "ls180.v:7775.10-7775.14" case - attribute \src "ls180.v:7779.7-7781.10" + attribute \src "ls180.v:7776.7-7778.10" switch \main_sdram_choose_cmd_request [2] - attribute \src "ls180.v:7779.11-7779.43" + attribute \src "ls180.v:7776.11-7776.43" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 case @@ -123549,31 +123500,31 @@ module \ls180 end case end - attribute \src "ls180.v:7787.2-7842.5" + attribute \src "ls180.v:7784.2-7839.5" switch \main_sdram_choose_req_ce - attribute \src "ls180.v:7787.6-7787.30" + attribute \src "ls180.v:7784.6-7784.30" case 1'1 - attribute \src "ls180.v:7788.3-7841.10" + attribute \src "ls180.v:7785.3-7838.10" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 - attribute \src "ls180.v:7790.5-7800.8" + attribute \src "ls180.v:7787.5-7797.8" switch \main_sdram_choose_req_request [1] - attribute \src "ls180.v:7790.9-7790.41" + attribute \src "ls180.v:7787.9-7787.41" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'01 - attribute \src "ls180.v:7792.9-7792.13" + attribute \src "ls180.v:7789.9-7789.13" case - attribute \src "ls180.v:7793.6-7799.9" + attribute \src "ls180.v:7790.6-7796.9" switch \main_sdram_choose_req_request [2] - attribute \src "ls180.v:7793.10-7793.42" + attribute \src "ls180.v:7790.10-7790.42" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'10 - attribute \src "ls180.v:7795.10-7795.14" + attribute \src "ls180.v:7792.10-7792.14" case - attribute \src "ls180.v:7796.7-7798.10" + attribute \src "ls180.v:7793.7-7795.10" switch \main_sdram_choose_req_request [3] - attribute \src "ls180.v:7796.11-7796.43" + attribute \src "ls180.v:7793.11-7793.43" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'11 case @@ -123582,23 +123533,23 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 2'01 - attribute \src "ls180.v:7803.5-7813.8" + attribute \src "ls180.v:7800.5-7810.8" switch \main_sdram_choose_req_request [2] - attribute \src "ls180.v:7803.9-7803.41" + attribute \src "ls180.v:7800.9-7800.41" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'10 - attribute \src "ls180.v:7805.9-7805.13" + attribute \src "ls180.v:7802.9-7802.13" case - attribute \src "ls180.v:7806.6-7812.9" + attribute \src "ls180.v:7803.6-7809.9" switch \main_sdram_choose_req_request [3] - attribute \src "ls180.v:7806.10-7806.42" + attribute \src "ls180.v:7803.10-7803.42" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'11 - attribute \src "ls180.v:7808.10-7808.14" + attribute \src "ls180.v:7805.10-7805.14" case - attribute \src "ls180.v:7809.7-7811.10" + attribute \src "ls180.v:7806.7-7808.10" switch \main_sdram_choose_req_request [0] - attribute \src "ls180.v:7809.11-7809.43" + attribute \src "ls180.v:7806.11-7806.43" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'00 case @@ -123607,23 +123558,23 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 2'10 - attribute \src "ls180.v:7816.5-7826.8" + attribute \src "ls180.v:7813.5-7823.8" switch \main_sdram_choose_req_request [3] - attribute \src "ls180.v:7816.9-7816.41" + attribute \src "ls180.v:7813.9-7813.41" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'11 - attribute \src "ls180.v:7818.9-7818.13" + attribute \src "ls180.v:7815.9-7815.13" case - attribute \src "ls180.v:7819.6-7825.9" + attribute \src "ls180.v:7816.6-7822.9" switch \main_sdram_choose_req_request [0] - attribute \src "ls180.v:7819.10-7819.42" + attribute \src "ls180.v:7816.10-7816.42" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'00 - attribute \src "ls180.v:7821.10-7821.14" + attribute \src "ls180.v:7818.10-7818.14" case - attribute \src "ls180.v:7822.7-7824.10" + attribute \src "ls180.v:7819.7-7821.10" switch \main_sdram_choose_req_request [1] - attribute \src "ls180.v:7822.11-7822.43" + attribute \src "ls180.v:7819.11-7819.43" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'01 case @@ -123632,23 +123583,23 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 2'11 - attribute \src "ls180.v:7829.5-7839.8" + attribute \src "ls180.v:7826.5-7836.8" switch \main_sdram_choose_req_request [0] - attribute \src "ls180.v:7829.9-7829.41" + attribute \src "ls180.v:7826.9-7826.41" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'00 - attribute \src "ls180.v:7831.9-7831.13" + attribute \src "ls180.v:7828.9-7828.13" case - attribute \src "ls180.v:7832.6-7838.9" + attribute \src "ls180.v:7829.6-7835.9" switch \main_sdram_choose_req_request [1] - attribute \src "ls180.v:7832.10-7832.42" + attribute \src "ls180.v:7829.10-7829.42" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'01 - attribute \src "ls180.v:7834.10-7834.14" + attribute \src "ls180.v:7831.10-7831.14" case - attribute \src "ls180.v:7835.7-7837.10" + attribute \src "ls180.v:7832.7-7834.10" switch \main_sdram_choose_req_request [2] - attribute \src "ls180.v:7835.11-7835.43" + attribute \src "ls180.v:7832.11-7832.43" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'10 case @@ -123659,28 +123610,28 @@ module \ls180 end case end - attribute \src "ls180.v:7851.2-7865.5" + attribute \src "ls180.v:7848.2-7862.5" switch \main_sdram_tccdcon_valid - attribute \src "ls180.v:7851.6-7851.30" + attribute \src "ls180.v:7848.6-7848.30" case 1'1 assign $0\main_sdram_tccdcon_count[0:0] 1'0 - attribute \src "ls180.v:7853.3-7857.6" + attribute \src "ls180.v:7850.3-7854.6" switch 1'1 - attribute \src "ls180.v:7853.7-7853.11" + attribute \src "ls180.v:7850.7-7850.11" case 1'1 assign $0\main_sdram_tccdcon_ready[0:0] 1'1 case end - attribute \src "ls180.v:7858.6-7858.10" + attribute \src "ls180.v:7855.6-7855.10" case - attribute \src "ls180.v:7859.3-7864.6" - switch $not$ls180.v:7859$2502_Y - attribute \src "ls180.v:7859.7-7859.34" + attribute \src "ls180.v:7856.3-7861.6" + switch $not$ls180.v:7856$2500_Y + attribute \src "ls180.v:7856.7-7856.34" case 1'1 - assign $0\main_sdram_tccdcon_count[0:0] $sub$ls180.v:7860$2503_Y - attribute \src "ls180.v:7861.4-7863.7" - switch $eq$ls180.v:7861$2504_Y - attribute \src "ls180.v:7861.8-7861.42" + assign $0\main_sdram_tccdcon_count[0:0] $sub$ls180.v:7857$2501_Y + attribute \src "ls180.v:7858.4-7860.7" + switch $eq$ls180.v:7858$2502_Y + attribute \src "ls180.v:7858.8-7858.42" case 1'1 assign $0\main_sdram_tccdcon_ready[0:0] 1'1 case @@ -123688,27 +123639,27 @@ module \ls180 case end end - attribute \src "ls180.v:7866.2-7880.5" + attribute \src "ls180.v:7863.2-7877.5" switch \main_sdram_twtrcon_valid - attribute \src "ls180.v:7866.6-7866.30" + attribute \src "ls180.v:7863.6-7863.30" case 1'1 assign $0\main_sdram_twtrcon_count[2:0] 3'100 - attribute \src "ls180.v:7868.3-7872.6" + attribute \src "ls180.v:7865.3-7869.6" switch 1'0 - attribute \src "ls180.v:7870.7-7870.11" + attribute \src "ls180.v:7867.7-7867.11" case assign $0\main_sdram_twtrcon_ready[0:0] 1'0 end - attribute \src "ls180.v:7873.6-7873.10" + attribute \src "ls180.v:7870.6-7870.10" case - attribute \src "ls180.v:7874.3-7879.6" - switch $not$ls180.v:7874$2505_Y - attribute \src "ls180.v:7874.7-7874.34" + attribute \src "ls180.v:7871.3-7876.6" + switch $not$ls180.v:7871$2503_Y + attribute \src "ls180.v:7871.7-7871.34" case 1'1 - assign $0\main_sdram_twtrcon_count[2:0] $sub$ls180.v:7875$2506_Y - attribute \src "ls180.v:7876.4-7878.7" - switch $eq$ls180.v:7876$2507_Y - attribute \src "ls180.v:7876.8-7876.42" + assign $0\main_sdram_twtrcon_count[2:0] $sub$ls180.v:7872$2504_Y + attribute \src "ls180.v:7873.4-7875.7" + switch $eq$ls180.v:7873$2505_Y + attribute \src "ls180.v:7873.8-7873.42" case 1'1 assign $0\main_sdram_twtrcon_ready[0:0] 1'1 case @@ -123716,81 +123667,81 @@ module \ls180 case end end - attribute \src "ls180.v:7887.2-7889.5" - switch $or$ls180.v:7887$2532_Y - attribute \src "ls180.v:7887.6-7887.50" + attribute \src "ls180.v:7884.2-7886.5" + switch $or$ls180.v:7884$2530_Y + attribute \src "ls180.v:7884.6-7884.50" case 1'1 assign $0\main_converter_dat_r[31:0] \main_wb_sdram_dat_r case end - attribute \src "ls180.v:7891.2-7893.5" + attribute \src "ls180.v:7888.2-7890.5" switch \main_converter_counter_converter_next_value_ce - attribute \src "ls180.v:7891.6-7891.52" + attribute \src "ls180.v:7888.6-7888.52" case 1'1 assign $0\main_converter_counter[0:0] \main_converter_counter_converter_next_value case end - attribute \src "ls180.v:7894.2-7897.5" + attribute \src "ls180.v:7891.2-7894.5" switch \main_converter_reset - attribute \src "ls180.v:7894.6-7894.26" + attribute \src "ls180.v:7891.6-7891.26" case 1'1 assign $0\main_converter_counter[0:0] 1'0 assign $0\builder_converter_state[0:0] 1'0 case end - attribute \src "ls180.v:7898.2-7908.5" + attribute \src "ls180.v:7895.2-7905.5" switch \main_litedram_wb_ack - attribute \src "ls180.v:7898.6-7898.26" + attribute \src "ls180.v:7895.6-7895.26" case 1'1 assign $0\main_cmd_consumed[0:0] 1'0 assign $0\main_wdata_consumed[0:0] 1'0 - attribute \src "ls180.v:7901.6-7901.10" + attribute \src "ls180.v:7898.6-7898.10" case - attribute \src "ls180.v:7902.3-7904.6" - switch $and$ls180.v:7902$2533_Y - attribute \src "ls180.v:7902.7-7902.50" + attribute \src "ls180.v:7899.3-7901.6" + switch $and$ls180.v:7899$2531_Y + attribute \src "ls180.v:7899.7-7899.50" case 1'1 assign $0\main_cmd_consumed[0:0] 1'1 case end - attribute \src "ls180.v:7905.3-7907.6" - switch $and$ls180.v:7905$2534_Y - attribute \src "ls180.v:7905.7-7905.54" + attribute \src "ls180.v:7902.3-7904.6" + switch $and$ls180.v:7902$2532_Y + attribute \src "ls180.v:7902.7-7902.54" case 1'1 assign $0\main_wdata_consumed[0:0] 1'1 case end end - attribute \src "ls180.v:7910.2-7931.5" - switch $and$ls180.v:7910$2538_Y - attribute \src "ls180.v:7910.6-7910.64" + attribute \src "ls180.v:7907.2-7928.5" + switch $and$ls180.v:7907$2536_Y + attribute \src "ls180.v:7907.6-7907.64" case 1'1 assign $0\main_tx_reg[7:0] \main_sink_payload_data assign $0\main_tx_bitcount[3:0] 4'0000 assign $0\main_tx_busy[0:0] 1'1 assign $0\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] 1'0 - attribute \src "ls180.v:7915.6-7915.10" + attribute \src "ls180.v:7912.6-7912.10" case - attribute \src "ls180.v:7916.3-7930.6" - switch $and$ls180.v:7916$2539_Y - attribute \src "ls180.v:7916.7-7916.42" + attribute \src "ls180.v:7913.3-7927.6" + switch $and$ls180.v:7913$2537_Y + attribute \src "ls180.v:7913.7-7913.42" case 1'1 - assign $0\main_tx_bitcount[3:0] $add$ls180.v:7917$2540_Y - attribute \src "ls180.v:7918.4-7929.7" - switch $eq$ls180.v:7918$2541_Y - attribute \src "ls180.v:7918.8-7918.34" + assign $0\main_tx_bitcount[3:0] $add$ls180.v:7914$2538_Y + attribute \src "ls180.v:7915.4-7926.7" + switch $eq$ls180.v:7915$2539_Y + attribute \src "ls180.v:7915.8-7915.34" case 1'1 assign $0\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] 1'1 - attribute \src "ls180.v:7920.8-7920.12" + attribute \src "ls180.v:7917.8-7917.12" case - attribute \src "ls180.v:7921.5-7928.8" - switch $eq$ls180.v:7921$2542_Y - attribute \src "ls180.v:7921.9-7921.35" + attribute \src "ls180.v:7918.5-7925.8" + switch $eq$ls180.v:7918$2540_Y + attribute \src "ls180.v:7918.9-7918.35" case 1'1 assign $0\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] 1'1 assign $0\main_tx_busy[0:0] 1'0 assign $0\main_sink_ready[0:0] 1'1 - attribute \src "ls180.v:7925.9-7925.13" + attribute \src "ls180.v:7922.9-7922.13" case assign $0\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] \main_tx_reg [0] assign $0\main_tx_reg[7:0] { 1'0 \main_tx_reg [7:1] } @@ -123799,61 +123750,61 @@ module \ls180 case end end - attribute \src "ls180.v:7932.2-7936.5" + attribute \src "ls180.v:7929.2-7933.5" switch \main_tx_busy - attribute \src "ls180.v:7932.6-7932.18" + attribute \src "ls180.v:7929.6-7929.18" case 1'1 - assign { $0\main_uart_clk_txen[0:0] $0\main_phase_accumulator_tx[31:0] } $add$ls180.v:7933$2543_Y - attribute \src "ls180.v:7934.6-7934.10" + assign { $0\main_uart_clk_txen[0:0] $0\main_phase_accumulator_tx[31:0] } $add$ls180.v:7930$2541_Y + attribute \src "ls180.v:7931.6-7931.10" case assign { $0\main_uart_clk_txen[0:0] $0\main_phase_accumulator_tx[31:0] } { 1'0 \main_storage } end - attribute \src "ls180.v:7939.2-7963.5" - switch $not$ls180.v:7939$2544_Y - attribute \src "ls180.v:7939.6-7939.21" + attribute \src "ls180.v:7936.2-7960.5" + switch $not$ls180.v:7936$2542_Y + attribute \src "ls180.v:7936.6-7936.21" case 1'1 - attribute \src "ls180.v:7940.3-7943.6" - switch $and$ls180.v:7940$2546_Y - attribute \src "ls180.v:7940.7-7940.31" + attribute \src "ls180.v:7937.3-7940.6" + switch $and$ls180.v:7937$2544_Y + attribute \src "ls180.v:7937.7-7937.31" case 1'1 assign $0\main_rx_busy[0:0] 1'1 assign $0\main_rx_bitcount[3:0] 4'0000 case end - attribute \src "ls180.v:7944.6-7944.10" + attribute \src "ls180.v:7941.6-7941.10" case - attribute \src "ls180.v:7945.3-7962.6" + attribute \src "ls180.v:7942.3-7959.6" switch \main_uart_clk_rxen - attribute \src "ls180.v:7945.7-7945.25" + attribute \src "ls180.v:7942.7-7942.25" case 1'1 - assign $0\main_rx_bitcount[3:0] $add$ls180.v:7946$2547_Y - attribute \src "ls180.v:7947.4-7961.7" - switch $eq$ls180.v:7947$2548_Y - attribute \src "ls180.v:7947.8-7947.34" + assign $0\main_rx_bitcount[3:0] $add$ls180.v:7943$2545_Y + attribute \src "ls180.v:7944.4-7958.7" + switch $eq$ls180.v:7944$2546_Y + attribute \src "ls180.v:7944.8-7944.34" case 1'1 - attribute \src "ls180.v:7948.5-7950.8" + attribute \src "ls180.v:7945.5-7947.8" switch \main_rx - attribute \src "ls180.v:7948.9-7948.16" + attribute \src "ls180.v:7945.9-7945.16" case 1'1 assign $0\main_rx_busy[0:0] 1'0 case end - attribute \src "ls180.v:7951.8-7951.12" + attribute \src "ls180.v:7948.8-7948.12" case - attribute \src "ls180.v:7952.5-7960.8" - switch $eq$ls180.v:7952$2549_Y - attribute \src "ls180.v:7952.9-7952.35" + attribute \src "ls180.v:7949.5-7957.8" + switch $eq$ls180.v:7949$2547_Y + attribute \src "ls180.v:7949.9-7949.35" case 1'1 assign $0\main_rx_busy[0:0] 1'0 - attribute \src "ls180.v:7954.6-7957.9" + attribute \src "ls180.v:7951.6-7954.9" switch \main_rx - attribute \src "ls180.v:7954.10-7954.17" + attribute \src "ls180.v:7951.10-7951.17" case 1'1 assign $0\main_source_payload_data[7:0] \main_rx_reg assign $0\main_source_valid[0:0] 1'1 case end - attribute \src "ls180.v:7958.9-7958.13" + attribute \src "ls180.v:7955.9-7955.13" case assign $0\main_rx_reg[7:0] { \main_rx \main_rx_reg [7:1] } end @@ -123861,146 +123812,146 @@ module \ls180 case end end - attribute \src "ls180.v:7964.2-7968.5" + attribute \src "ls180.v:7961.2-7965.5" switch \main_rx_busy - attribute \src "ls180.v:7964.6-7964.18" + attribute \src "ls180.v:7961.6-7961.18" case 1'1 - assign { $0\main_uart_clk_rxen[0:0] $0\main_phase_accumulator_rx[31:0] } $add$ls180.v:7965$2550_Y - attribute \src "ls180.v:7966.6-7966.10" + assign { $0\main_uart_clk_rxen[0:0] $0\main_phase_accumulator_rx[31:0] } $add$ls180.v:7962$2548_Y + attribute \src "ls180.v:7963.6-7963.10" case assign { $0\main_uart_clk_rxen[0:0] $0\main_phase_accumulator_rx[31:0] } 33'010000000000000000000000000000000 end - attribute \src "ls180.v:7969.2-7971.5" + attribute \src "ls180.v:7966.2-7968.5" switch \main_uart_tx_clear - attribute \src "ls180.v:7969.6-7969.24" + attribute \src "ls180.v:7966.6-7966.24" case 1'1 assign $0\main_uart_tx_pending[0:0] 1'0 case end - attribute \src "ls180.v:7973.2-7975.5" - switch $and$ls180.v:7973$2552_Y - attribute \src "ls180.v:7973.6-7973.58" + attribute \src "ls180.v:7970.2-7972.5" + switch $and$ls180.v:7970$2550_Y + attribute \src "ls180.v:7970.6-7970.58" case 1'1 assign $0\main_uart_tx_pending[0:0] 1'1 case end - attribute \src "ls180.v:7976.2-7978.5" + attribute \src "ls180.v:7973.2-7975.5" switch \main_uart_rx_clear - attribute \src "ls180.v:7976.6-7976.24" + attribute \src "ls180.v:7973.6-7973.24" case 1'1 assign $0\main_uart_rx_pending[0:0] 1'0 case end - attribute \src "ls180.v:7980.2-7982.5" - switch $and$ls180.v:7980$2554_Y - attribute \src "ls180.v:7980.6-7980.58" + attribute \src "ls180.v:7977.2-7979.5" + switch $and$ls180.v:7977$2552_Y + attribute \src "ls180.v:7977.6-7977.58" case 1'1 assign $0\main_uart_rx_pending[0:0] 1'1 case end - attribute \src "ls180.v:7983.2-7989.5" + attribute \src "ls180.v:7980.2-7986.5" switch \main_uart_tx_fifo_syncfifo_re - attribute \src "ls180.v:7983.6-7983.35" + attribute \src "ls180.v:7980.6-7980.35" case 1'1 assign $0\main_uart_tx_fifo_readable[0:0] 1'1 - attribute \src "ls180.v:7985.6-7985.10" + attribute \src "ls180.v:7982.6-7982.10" case - attribute \src "ls180.v:7986.3-7988.6" + attribute \src "ls180.v:7983.3-7985.6" switch \main_uart_tx_fifo_re - attribute \src "ls180.v:7986.7-7986.27" + attribute \src "ls180.v:7983.7-7983.27" case 1'1 assign $0\main_uart_tx_fifo_readable[0:0] 1'0 case end end - attribute \src "ls180.v:7990.2-7992.5" - switch $and$ls180.v:7990$2557_Y - attribute \src "ls180.v:7990.6-7990.108" + attribute \src "ls180.v:7987.2-7989.5" + switch $and$ls180.v:7987$2555_Y + attribute \src "ls180.v:7987.6-7987.108" case 1'1 - assign $0\main_uart_tx_fifo_produce[3:0] $add$ls180.v:7991$2558_Y + assign $0\main_uart_tx_fifo_produce[3:0] $add$ls180.v:7988$2556_Y case end - attribute \src "ls180.v:7993.2-7995.5" + attribute \src "ls180.v:7990.2-7992.5" switch \main_uart_tx_fifo_do_read - attribute \src "ls180.v:7993.6-7993.31" + attribute \src "ls180.v:7990.6-7990.31" case 1'1 - assign $0\main_uart_tx_fifo_consume[3:0] $add$ls180.v:7994$2559_Y + assign $0\main_uart_tx_fifo_consume[3:0] $add$ls180.v:7991$2557_Y case end - attribute \src "ls180.v:7996.2-8004.5" - switch $and$ls180.v:7996$2562_Y - attribute \src "ls180.v:7996.6-7996.108" + attribute \src "ls180.v:7993.2-8001.5" + switch $and$ls180.v:7993$2560_Y + attribute \src "ls180.v:7993.6-7993.108" case 1'1 - attribute \src "ls180.v:7997.3-7999.6" - switch $not$ls180.v:7997$2563_Y - attribute \src "ls180.v:7997.7-7997.35" + attribute \src "ls180.v:7994.3-7996.6" + switch $not$ls180.v:7994$2561_Y + attribute \src "ls180.v:7994.7-7994.35" case 1'1 - assign $0\main_uart_tx_fifo_level0[4:0] $add$ls180.v:7998$2564_Y + assign $0\main_uart_tx_fifo_level0[4:0] $add$ls180.v:7995$2562_Y case end - attribute \src "ls180.v:8000.6-8000.10" + attribute \src "ls180.v:7997.6-7997.10" case - attribute \src "ls180.v:8001.3-8003.6" + attribute \src "ls180.v:7998.3-8000.6" switch \main_uart_tx_fifo_do_read - attribute \src "ls180.v:8001.7-8001.32" + attribute \src "ls180.v:7998.7-7998.32" case 1'1 - assign $0\main_uart_tx_fifo_level0[4:0] $sub$ls180.v:8002$2565_Y + assign $0\main_uart_tx_fifo_level0[4:0] $sub$ls180.v:7999$2563_Y case end end - attribute \src "ls180.v:8005.2-8011.5" + attribute \src "ls180.v:8002.2-8008.5" switch \main_uart_rx_fifo_syncfifo_re - attribute \src "ls180.v:8005.6-8005.35" + attribute \src "ls180.v:8002.6-8002.35" case 1'1 assign $0\main_uart_rx_fifo_readable[0:0] 1'1 - attribute \src "ls180.v:8007.6-8007.10" + attribute \src "ls180.v:8004.6-8004.10" case - attribute \src "ls180.v:8008.3-8010.6" + attribute \src "ls180.v:8005.3-8007.6" switch \main_uart_rx_fifo_re - attribute \src "ls180.v:8008.7-8008.27" + attribute \src "ls180.v:8005.7-8005.27" case 1'1 assign $0\main_uart_rx_fifo_readable[0:0] 1'0 case end end - attribute \src "ls180.v:8012.2-8014.5" - switch $and$ls180.v:8012$2568_Y - attribute \src "ls180.v:8012.6-8012.108" + attribute \src "ls180.v:8009.2-8011.5" + switch $and$ls180.v:8009$2566_Y + attribute \src "ls180.v:8009.6-8009.108" case 1'1 - assign $0\main_uart_rx_fifo_produce[3:0] $add$ls180.v:8013$2569_Y + assign $0\main_uart_rx_fifo_produce[3:0] $add$ls180.v:8010$2567_Y case end - attribute \src "ls180.v:8015.2-8017.5" + attribute \src "ls180.v:8012.2-8014.5" switch \main_uart_rx_fifo_do_read - attribute \src "ls180.v:8015.6-8015.31" + attribute \src "ls180.v:8012.6-8012.31" case 1'1 - assign $0\main_uart_rx_fifo_consume[3:0] $add$ls180.v:8016$2570_Y + assign $0\main_uart_rx_fifo_consume[3:0] $add$ls180.v:8013$2568_Y case end - attribute \src "ls180.v:8018.2-8026.5" - switch $and$ls180.v:8018$2573_Y - attribute \src "ls180.v:8018.6-8018.108" + attribute \src "ls180.v:8015.2-8023.5" + switch $and$ls180.v:8015$2571_Y + attribute \src "ls180.v:8015.6-8015.108" case 1'1 - attribute \src "ls180.v:8019.3-8021.6" - switch $not$ls180.v:8019$2574_Y - attribute \src "ls180.v:8019.7-8019.35" + attribute \src "ls180.v:8016.3-8018.6" + switch $not$ls180.v:8016$2572_Y + attribute \src "ls180.v:8016.7-8016.35" case 1'1 - assign $0\main_uart_rx_fifo_level0[4:0] $add$ls180.v:8020$2575_Y + assign $0\main_uart_rx_fifo_level0[4:0] $add$ls180.v:8017$2573_Y case end - attribute \src "ls180.v:8022.6-8022.10" + attribute \src "ls180.v:8019.6-8019.10" case - attribute \src "ls180.v:8023.3-8025.6" + attribute \src "ls180.v:8020.3-8022.6" switch \main_uart_rx_fifo_do_read - attribute \src "ls180.v:8023.7-8023.32" + attribute \src "ls180.v:8020.7-8020.32" case 1'1 - assign $0\main_uart_rx_fifo_level0[4:0] $sub$ls180.v:8024$2576_Y + assign $0\main_uart_rx_fifo_level0[4:0] $sub$ls180.v:8021$2574_Y case end end - attribute \src "ls180.v:8027.2-8040.5" + attribute \src "ls180.v:8024.2-8037.5" switch \main_uart_reset - attribute \src "ls180.v:8027.6-8027.21" + attribute \src "ls180.v:8024.6-8024.21" case 1'1 assign $0\main_uart_tx_pending[0:0] 1'0 assign $0\main_uart_tx_old_trigger[0:0] 1'0 @@ -124016,38 +123967,38 @@ module \ls180 assign $0\main_uart_rx_fifo_consume[3:0] 4'0000 case end - attribute \src "ls180.v:8042.2-8049.5" + attribute \src "ls180.v:8039.2-8046.5" switch \main_spi_master_clk_rise - attribute \src "ls180.v:8042.6-8042.30" + attribute \src "ls180.v:8039.6-8039.30" case 1'1 assign $0\spi_master_clk[0:0] \main_spi_master_clk_enable - attribute \src "ls180.v:8044.6-8044.10" + attribute \src "ls180.v:8041.6-8041.10" case - attribute \src "ls180.v:8045.3-8048.6" + attribute \src "ls180.v:8042.3-8045.6" switch \main_spi_master_clk_fall - attribute \src "ls180.v:8045.7-8045.31" + attribute \src "ls180.v:8042.7-8042.31" case 1'1 assign $0\main_spi_master_clk_divider1[15:0] 16'0000000000000000 assign $0\spi_master_clk[0:0] 1'0 case end end - attribute \src "ls180.v:8051.2-8061.5" + attribute \src "ls180.v:8048.2-8058.5" switch \main_spi_master_mosi_latch - attribute \src "ls180.v:8051.6-8051.32" + attribute \src "ls180.v:8048.6-8048.32" case 1'1 assign $0\main_spi_master_mosi_data[7:0] \main_spi_master_mosi assign $0\main_spi_master_mosi_sel[2:0] 3'111 - attribute \src "ls180.v:8054.6-8054.10" + attribute \src "ls180.v:8051.6-8051.10" case - attribute \src "ls180.v:8055.3-8060.6" + attribute \src "ls180.v:8052.3-8057.6" switch \main_spi_master_clk_fall - attribute \src "ls180.v:8055.7-8055.31" + attribute \src "ls180.v:8052.7-8052.31" case 1'1 - assign $0\main_spi_master_mosi_sel[2:0] $sub$ls180.v:8059$2581_Y - attribute \src "ls180.v:8056.4-8058.7" + assign $0\main_spi_master_mosi_sel[2:0] $sub$ls180.v:8056$2579_Y + attribute \src "ls180.v:8053.4-8055.7" switch \main_spi_master_cs_enable - attribute \src "ls180.v:8056.8-8056.33" + attribute \src "ls180.v:8053.8-8053.33" case 1'1 assign $0\spi_master_mosi[0:0] \builder_sync_f_array_muxed0 case @@ -124055,169 +124006,169 @@ module \ls180 case end end - attribute \src "ls180.v:8062.2-8068.5" + attribute \src "ls180.v:8059.2-8065.5" switch \main_spi_master_clk_rise - attribute \src "ls180.v:8062.6-8062.30" + attribute \src "ls180.v:8059.6-8059.30" case 1'1 - attribute \src "ls180.v:8063.3-8067.6" + attribute \src "ls180.v:8060.3-8064.6" switch \main_spi_master_loopback - attribute \src "ls180.v:8063.7-8063.31" + attribute \src "ls180.v:8060.7-8060.31" case 1'1 assign $0\main_spi_master_miso_data[7:0] { \main_spi_master_miso_data [6:0] \spi_master_mosi } - attribute \src "ls180.v:8065.7-8065.11" + attribute \src "ls180.v:8062.7-8062.11" case assign $0\main_spi_master_miso_data[7:0] { \main_spi_master_miso_data [6:0] \spi_master_miso } end case end - attribute \src "ls180.v:8069.2-8071.5" + attribute \src "ls180.v:8066.2-8068.5" switch \main_spi_master_miso_latch - attribute \src "ls180.v:8069.6-8069.32" + attribute \src "ls180.v:8066.6-8066.32" case 1'1 assign $0\main_spi_master_miso[7:0] \main_spi_master_miso_data case end - attribute \src "ls180.v:8073.2-8075.5" + attribute \src "ls180.v:8070.2-8072.5" switch \main_spi_master_count_spimaster0_next_value_ce - attribute \src "ls180.v:8073.6-8073.52" + attribute \src "ls180.v:8070.6-8070.52" case 1'1 assign $0\main_spi_master_count[2:0] \main_spi_master_count_spimaster0_next_value case end - attribute \src "ls180.v:8076.2-8089.5" + attribute \src "ls180.v:8073.2-8086.5" switch \main_pwm0_enable - attribute \src "ls180.v:8076.6-8076.22" + attribute \src "ls180.v:8073.6-8073.22" case 1'1 - assign $0\main_pwm0_counter[31:0] $add$ls180.v:8077$2582_Y - attribute \src "ls180.v:8078.3-8082.6" - switch $lt$ls180.v:8078$2583_Y - attribute \src "ls180.v:8078.7-8078.44" + assign $0\main_pwm0_counter[31:0] $add$ls180.v:8074$2580_Y + attribute \src "ls180.v:8075.3-8079.6" + switch $lt$ls180.v:8075$2581_Y + attribute \src "ls180.v:8075.7-8075.44" case 1'1 assign $0\pwm0[0:0] 1'1 - attribute \src "ls180.v:8080.7-8080.11" + attribute \src "ls180.v:8077.7-8077.11" case assign $0\pwm0[0:0] 1'0 end - attribute \src "ls180.v:8083.3-8085.6" - switch $ge$ls180.v:8083$2585_Y - attribute \src "ls180.v:8083.7-8083.55" + attribute \src "ls180.v:8080.3-8082.6" + switch $ge$ls180.v:8080$2583_Y + attribute \src "ls180.v:8080.7-8080.55" case 1'1 assign $0\main_pwm0_counter[31:0] 0 case end - attribute \src "ls180.v:8086.6-8086.10" + attribute \src "ls180.v:8083.6-8083.10" case assign $0\main_pwm0_counter[31:0] 0 assign $0\pwm0[0:0] 1'0 end - attribute \src "ls180.v:8090.2-8103.5" + attribute \src "ls180.v:8087.2-8100.5" switch \main_pwm1_enable - attribute \src "ls180.v:8090.6-8090.22" + attribute \src "ls180.v:8087.6-8087.22" case 1'1 - assign $0\main_pwm1_counter[31:0] $add$ls180.v:8091$2586_Y - attribute \src "ls180.v:8092.3-8096.6" - switch $lt$ls180.v:8092$2587_Y - attribute \src "ls180.v:8092.7-8092.44" + assign $0\main_pwm1_counter[31:0] $add$ls180.v:8088$2584_Y + attribute \src "ls180.v:8089.3-8093.6" + switch $lt$ls180.v:8089$2585_Y + attribute \src "ls180.v:8089.7-8089.44" case 1'1 assign $0\pwm1[0:0] 1'1 - attribute \src "ls180.v:8094.7-8094.11" + attribute \src "ls180.v:8091.7-8091.11" case assign $0\pwm1[0:0] 1'0 end - attribute \src "ls180.v:8097.3-8099.6" - switch $ge$ls180.v:8097$2589_Y - attribute \src "ls180.v:8097.7-8097.55" + attribute \src "ls180.v:8094.3-8096.6" + switch $ge$ls180.v:8094$2587_Y + attribute \src "ls180.v:8094.7-8094.55" case 1'1 assign $0\main_pwm1_counter[31:0] 0 case end - attribute \src "ls180.v:8100.6-8100.10" + attribute \src "ls180.v:8097.6-8097.10" case assign $0\main_pwm1_counter[31:0] 0 assign $0\pwm1[0:0] 1'0 end - attribute \src "ls180.v:8104.2-8106.5" - switch $not$ls180.v:8104$2590_Y - attribute \src "ls180.v:8104.6-8104.32" + attribute \src "ls180.v:8101.2-8103.5" + switch $not$ls180.v:8101$2588_Y + attribute \src "ls180.v:8101.6-8101.32" case 1'1 - assign $0\main_sdphy_clocker_clks[8:0] $add$ls180.v:8105$2591_Y + assign $0\main_sdphy_clocker_clks[8:0] $add$ls180.v:8102$2589_Y case end - attribute \src "ls180.v:8110.2-8112.5" + attribute \src "ls180.v:8107.2-8109.5" switch \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce - attribute \src "ls180.v:8110.6-8110.57" + attribute \src "ls180.v:8107.6-8107.57" case 1'1 assign $0\main_sdphy_init_count[7:0] \main_sdphy_init_count_sdphy_sdphyinit_next_value case end - attribute \src "ls180.v:8114.2-8116.5" + attribute \src "ls180.v:8111.2-8113.5" switch \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce - attribute \src "ls180.v:8114.6-8114.57" + attribute \src "ls180.v:8111.6-8111.57" case 1'1 assign $0\main_sdphy_cmdw_count[7:0] \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value case end - attribute \src "ls180.v:8117.2-8119.5" + attribute \src "ls180.v:8114.2-8116.5" switch \main_sdphy_cmdr_cmdr_pads_in_valid - attribute \src "ls180.v:8117.6-8117.40" + attribute \src "ls180.v:8114.6-8114.40" case 1'1 - assign $0\main_sdphy_cmdr_cmdr_run[0:0] $or$ls180.v:8118$2592_Y + assign $0\main_sdphy_cmdr_cmdr_run[0:0] $or$ls180.v:8115$2590_Y case end - attribute \src "ls180.v:8120.2-8122.5" + attribute \src "ls180.v:8117.2-8119.5" switch \main_sdphy_cmdr_cmdr_converter_source_ready - attribute \src "ls180.v:8120.6-8120.49" + attribute \src "ls180.v:8117.6-8117.49" case 1'1 assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 case end - attribute \src "ls180.v:8123.2-8130.5" + attribute \src "ls180.v:8120.2-8127.5" switch \main_sdphy_cmdr_cmdr_converter_load_part - attribute \src "ls180.v:8123.6-8123.46" + attribute \src "ls180.v:8120.6-8120.46" case 1'1 - attribute \src "ls180.v:8124.3-8129.6" - switch $or$ls180.v:8124$2594_Y - attribute \src "ls180.v:8124.7-8124.98" + attribute \src "ls180.v:8121.3-8126.6" + switch $or$ls180.v:8121$2592_Y + attribute \src "ls180.v:8121.7-8121.98" case 1'1 assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'1 - attribute \src "ls180.v:8127.7-8127.11" + attribute \src "ls180.v:8124.7-8124.11" case - assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] $add$ls180.v:8128$2595_Y + assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] $add$ls180.v:8125$2593_Y end case end - attribute \src "ls180.v:8131.2-8144.5" - switch $and$ls180.v:8131$2596_Y - attribute \src "ls180.v:8131.6-8131.97" + attribute \src "ls180.v:8128.2-8141.5" + switch $and$ls180.v:8128$2594_Y + attribute \src "ls180.v:8128.6-8128.97" case 1'1 - attribute \src "ls180.v:8132.3-8138.6" - switch $and$ls180.v:8132$2597_Y - attribute \src "ls180.v:8132.7-8132.94" + attribute \src "ls180.v:8129.3-8135.6" + switch $and$ls180.v:8129$2595_Y + attribute \src "ls180.v:8129.7-8129.94" case 1'1 assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] \main_sdphy_cmdr_cmdr_converter_sink_first assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] \main_sdphy_cmdr_cmdr_converter_sink_last - attribute \src "ls180.v:8135.7-8135.11" + attribute \src "ls180.v:8132.7-8132.11" case assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] 1'0 assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] 1'0 end - attribute \src "ls180.v:8139.6-8139.10" + attribute \src "ls180.v:8136.6-8136.10" case - attribute \src "ls180.v:8140.3-8143.6" - switch $and$ls180.v:8140$2598_Y - attribute \src "ls180.v:8140.7-8140.94" + attribute \src "ls180.v:8137.3-8140.6" + switch $and$ls180.v:8137$2596_Y + attribute \src "ls180.v:8137.7-8137.94" case 1'1 - assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] $or$ls180.v:8141$2599_Y - assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] $or$ls180.v:8142$2600_Y + assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] $or$ls180.v:8138$2597_Y + assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] $or$ls180.v:8139$2598_Y case end end - attribute \src "ls180.v:8145.2-8172.5" + attribute \src "ls180.v:8142.2-8169.5" switch \main_sdphy_cmdr_cmdr_converter_load_part - attribute \src "ls180.v:8145.6-8145.46" + attribute \src "ls180.v:8142.6-8142.46" case 1'1 - attribute \src "ls180.v:8146.3-8171.10" + attribute \src "ls180.v:8143.3-8168.10" switch \main_sdphy_cmdr_cmdr_converter_demux attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -124247,16 +124198,16 @@ module \ls180 end case end - attribute \src "ls180.v:8173.2-8175.5" + attribute \src "ls180.v:8170.2-8172.5" switch \main_sdphy_cmdr_cmdr_converter_load_part - attribute \src "ls180.v:8173.6-8173.46" + attribute \src "ls180.v:8170.6-8170.46" case 1'1 - assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8174$2601_Y + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8171$2599_Y case end - attribute \src "ls180.v:8176.2-8181.5" - switch $or$ls180.v:8176$2603_Y - attribute \src "ls180.v:8176.6-8176.88" + attribute \src "ls180.v:8173.2-8178.5" + switch $or$ls180.v:8173$2601_Y + attribute \src "ls180.v:8173.6-8173.88" case 1'1 assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] \main_sdphy_cmdr_cmdr_buf_sink_valid assign $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] \main_sdphy_cmdr_cmdr_buf_sink_first @@ -124264,9 +124215,9 @@ module \ls180 assign $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_buf_sink_payload_data case end - attribute \src "ls180.v:8182.2-8187.5" + attribute \src "ls180.v:8179.2-8184.5" switch \main_sdphy_cmdr_cmdr_reset - attribute \src "ls180.v:8182.6-8182.32" + attribute \src "ls180.v:8179.6-8179.32" case 1'1 assign $0\main_sdphy_cmdr_cmdr_run[0:0] 1'0 assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 @@ -124274,88 +124225,88 @@ module \ls180 assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0 case end - attribute \src "ls180.v:8189.2-8191.5" + attribute \src "ls180.v:8186.2-8188.5" switch \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 - attribute \src "ls180.v:8189.6-8189.58" + attribute \src "ls180.v:8186.6-8186.58" case 1'1 assign $0\main_sdphy_cmdr_count[7:0] \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 case end - attribute \src "ls180.v:8192.2-8194.5" + attribute \src "ls180.v:8189.2-8191.5" switch \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 - attribute \src "ls180.v:8192.6-8192.60" + attribute \src "ls180.v:8189.6-8189.60" case 1'1 assign $0\main_sdphy_cmdr_timeout[31:0] \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 case end - attribute \src "ls180.v:8195.2-8197.5" + attribute \src "ls180.v:8192.2-8194.5" switch \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 - attribute \src "ls180.v:8195.6-8195.63" + attribute \src "ls180.v:8192.6-8192.63" case 1'1 assign $0\main_sdphy_cmdr_cmdr_reset[0:0] \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 case end - attribute \src "ls180.v:8198.2-8200.5" + attribute \src "ls180.v:8195.2-8197.5" switch \main_sdphy_dataw_crcr_pads_in_valid - attribute \src "ls180.v:8198.6-8198.41" + attribute \src "ls180.v:8195.6-8195.41" case 1'1 - assign $0\main_sdphy_dataw_crcr_run[0:0] $or$ls180.v:8199$2604_Y + assign $0\main_sdphy_dataw_crcr_run[0:0] $or$ls180.v:8196$2602_Y case end - attribute \src "ls180.v:8201.2-8203.5" + attribute \src "ls180.v:8198.2-8200.5" switch \main_sdphy_dataw_crcr_converter_source_ready - attribute \src "ls180.v:8201.6-8201.50" + attribute \src "ls180.v:8198.6-8198.50" case 1'1 assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 case end - attribute \src "ls180.v:8204.2-8211.5" + attribute \src "ls180.v:8201.2-8208.5" switch \main_sdphy_dataw_crcr_converter_load_part - attribute \src "ls180.v:8204.6-8204.47" + attribute \src "ls180.v:8201.6-8201.47" case 1'1 - attribute \src "ls180.v:8205.3-8210.6" - switch $or$ls180.v:8205$2606_Y - attribute \src "ls180.v:8205.7-8205.100" + attribute \src "ls180.v:8202.3-8207.6" + switch $or$ls180.v:8202$2604_Y + attribute \src "ls180.v:8202.7-8202.100" case 1'1 assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'1 - attribute \src "ls180.v:8208.7-8208.11" + attribute \src "ls180.v:8205.7-8205.11" case - assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] $add$ls180.v:8209$2607_Y + assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] $add$ls180.v:8206$2605_Y end case end - attribute \src "ls180.v:8212.2-8225.5" - switch $and$ls180.v:8212$2608_Y - attribute \src "ls180.v:8212.6-8212.99" + attribute \src "ls180.v:8209.2-8222.5" + switch $and$ls180.v:8209$2606_Y + attribute \src "ls180.v:8209.6-8209.99" case 1'1 - attribute \src "ls180.v:8213.3-8219.6" - switch $and$ls180.v:8213$2609_Y - attribute \src "ls180.v:8213.7-8213.96" + attribute \src "ls180.v:8210.3-8216.6" + switch $and$ls180.v:8210$2607_Y + attribute \src "ls180.v:8210.7-8210.96" case 1'1 assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] \main_sdphy_dataw_crcr_converter_sink_first assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] \main_sdphy_dataw_crcr_converter_sink_last - attribute \src "ls180.v:8216.7-8216.11" + attribute \src "ls180.v:8213.7-8213.11" case assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] 1'0 assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] 1'0 end - attribute \src "ls180.v:8220.6-8220.10" + attribute \src "ls180.v:8217.6-8217.10" case - attribute \src "ls180.v:8221.3-8224.6" - switch $and$ls180.v:8221$2610_Y - attribute \src "ls180.v:8221.7-8221.96" + attribute \src "ls180.v:8218.3-8221.6" + switch $and$ls180.v:8218$2608_Y + attribute \src "ls180.v:8218.7-8218.96" case 1'1 - assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] $or$ls180.v:8222$2611_Y - assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] $or$ls180.v:8223$2612_Y + assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] $or$ls180.v:8219$2609_Y + assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] $or$ls180.v:8220$2610_Y case end end - attribute \src "ls180.v:8226.2-8253.5" + attribute \src "ls180.v:8223.2-8250.5" switch \main_sdphy_dataw_crcr_converter_load_part - attribute \src "ls180.v:8226.6-8226.47" + attribute \src "ls180.v:8223.6-8223.47" case 1'1 - attribute \src "ls180.v:8227.3-8252.10" + attribute \src "ls180.v:8224.3-8249.10" switch \main_sdphy_dataw_crcr_converter_demux attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -124385,16 +124336,16 @@ module \ls180 end case end - attribute \src "ls180.v:8254.2-8256.5" + attribute \src "ls180.v:8251.2-8253.5" switch \main_sdphy_dataw_crcr_converter_load_part - attribute \src "ls180.v:8254.6-8254.47" + attribute \src "ls180.v:8251.6-8251.47" case 1'1 - assign $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8255$2613_Y + assign $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8252$2611_Y case end - attribute \src "ls180.v:8257.2-8262.5" - switch $or$ls180.v:8257$2615_Y - attribute \src "ls180.v:8257.6-8257.90" + attribute \src "ls180.v:8254.2-8259.5" + switch $or$ls180.v:8254$2613_Y + attribute \src "ls180.v:8254.6-8254.90" case 1'1 assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] \main_sdphy_dataw_crcr_buf_sink_valid assign $0\main_sdphy_dataw_crcr_buf_source_first[0:0] \main_sdphy_dataw_crcr_buf_sink_first @@ -124402,9 +124353,9 @@ module \ls180 assign $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] \main_sdphy_dataw_crcr_buf_sink_payload_data case end - attribute \src "ls180.v:8263.2-8268.5" + attribute \src "ls180.v:8260.2-8265.5" switch \main_sdphy_dataw_crcr_reset - attribute \src "ls180.v:8263.6-8263.33" + attribute \src "ls180.v:8260.6-8260.33" case 1'1 assign $0\main_sdphy_dataw_crcr_run[0:0] 1'0 assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 @@ -124412,81 +124363,81 @@ module \ls180 assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0 case end - attribute \src "ls180.v:8270.2-8272.5" + attribute \src "ls180.v:8267.2-8269.5" switch \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce - attribute \src "ls180.v:8270.6-8270.63" + attribute \src "ls180.v:8267.6-8267.63" case 1'1 assign $0\main_sdphy_dataw_crcr_reset[0:0] \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value case end - attribute \src "ls180.v:8274.2-8276.5" + attribute \src "ls180.v:8271.2-8273.5" switch \main_sdphy_dataw_count_sdphy_fsm_next_value_ce - attribute \src "ls180.v:8274.6-8274.52" + attribute \src "ls180.v:8271.6-8271.52" case 1'1 assign $0\main_sdphy_dataw_count[7:0] \main_sdphy_dataw_count_sdphy_fsm_next_value case end - attribute \src "ls180.v:8277.2-8279.5" + attribute \src "ls180.v:8274.2-8276.5" switch \main_sdphy_datar_datar_pads_in_valid - attribute \src "ls180.v:8277.6-8277.42" + attribute \src "ls180.v:8274.6-8274.42" case 1'1 - assign $0\main_sdphy_datar_datar_run[0:0] $or$ls180.v:8278$2616_Y + assign $0\main_sdphy_datar_datar_run[0:0] $or$ls180.v:8275$2614_Y case end - attribute \src "ls180.v:8280.2-8282.5" + attribute \src "ls180.v:8277.2-8279.5" switch \main_sdphy_datar_datar_converter_source_ready - attribute \src "ls180.v:8280.6-8280.51" + attribute \src "ls180.v:8277.6-8277.51" case 1'1 assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 case end - attribute \src "ls180.v:8283.2-8290.5" + attribute \src "ls180.v:8280.2-8287.5" switch \main_sdphy_datar_datar_converter_load_part - attribute \src "ls180.v:8283.6-8283.48" + attribute \src "ls180.v:8280.6-8280.48" case 1'1 - attribute \src "ls180.v:8284.3-8289.6" - switch $or$ls180.v:8284$2618_Y - attribute \src "ls180.v:8284.7-8284.102" + attribute \src "ls180.v:8281.3-8286.6" + switch $or$ls180.v:8281$2616_Y + attribute \src "ls180.v:8281.7-8281.102" case 1'1 assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0 assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'1 - attribute \src "ls180.v:8287.7-8287.11" + attribute \src "ls180.v:8284.7-8284.11" case - assign $0\main_sdphy_datar_datar_converter_demux[0:0] $add$ls180.v:8288$2619_Y + assign $0\main_sdphy_datar_datar_converter_demux[0:0] $add$ls180.v:8285$2617_Y end case end - attribute \src "ls180.v:8291.2-8304.5" - switch $and$ls180.v:8291$2620_Y - attribute \src "ls180.v:8291.6-8291.101" + attribute \src "ls180.v:8288.2-8301.5" + switch $and$ls180.v:8288$2618_Y + attribute \src "ls180.v:8288.6-8288.101" case 1'1 - attribute \src "ls180.v:8292.3-8298.6" - switch $and$ls180.v:8292$2621_Y - attribute \src "ls180.v:8292.7-8292.98" + attribute \src "ls180.v:8289.3-8295.6" + switch $and$ls180.v:8289$2619_Y + attribute \src "ls180.v:8289.7-8289.98" case 1'1 assign $0\main_sdphy_datar_datar_converter_source_first[0:0] \main_sdphy_datar_datar_converter_sink_first assign $0\main_sdphy_datar_datar_converter_source_last[0:0] \main_sdphy_datar_datar_converter_sink_last - attribute \src "ls180.v:8295.7-8295.11" + attribute \src "ls180.v:8292.7-8292.11" case assign $0\main_sdphy_datar_datar_converter_source_first[0:0] 1'0 assign $0\main_sdphy_datar_datar_converter_source_last[0:0] 1'0 end - attribute \src "ls180.v:8299.6-8299.10" + attribute \src "ls180.v:8296.6-8296.10" case - attribute \src "ls180.v:8300.3-8303.6" - switch $and$ls180.v:8300$2622_Y - attribute \src "ls180.v:8300.7-8300.98" + attribute \src "ls180.v:8297.3-8300.6" + switch $and$ls180.v:8297$2620_Y + attribute \src "ls180.v:8297.7-8297.98" case 1'1 - assign $0\main_sdphy_datar_datar_converter_source_first[0:0] $or$ls180.v:8301$2623_Y - assign $0\main_sdphy_datar_datar_converter_source_last[0:0] $or$ls180.v:8302$2624_Y + assign $0\main_sdphy_datar_datar_converter_source_first[0:0] $or$ls180.v:8298$2621_Y + assign $0\main_sdphy_datar_datar_converter_source_last[0:0] $or$ls180.v:8299$2622_Y case end end - attribute \src "ls180.v:8305.2-8314.5" + attribute \src "ls180.v:8302.2-8311.5" switch \main_sdphy_datar_datar_converter_load_part - attribute \src "ls180.v:8305.6-8305.48" + attribute \src "ls180.v:8302.6-8302.48" case 1'1 - attribute \src "ls180.v:8306.3-8313.10" + attribute \src "ls180.v:8303.3-8310.10" switch \main_sdphy_datar_datar_converter_demux attribute \src "ls180.v:0.0-0.0" case 1'0 @@ -124498,16 +124449,16 @@ module \ls180 end case end - attribute \src "ls180.v:8315.2-8317.5" + attribute \src "ls180.v:8312.2-8314.5" switch \main_sdphy_datar_datar_converter_load_part - attribute \src "ls180.v:8315.6-8315.48" + attribute \src "ls180.v:8312.6-8312.48" case 1'1 - assign $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] $add$ls180.v:8316$2625_Y + assign $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] $add$ls180.v:8313$2623_Y case end - attribute \src "ls180.v:8318.2-8323.5" - switch $or$ls180.v:8318$2627_Y - attribute \src "ls180.v:8318.6-8318.92" + attribute \src "ls180.v:8315.2-8320.5" + switch $or$ls180.v:8315$2625_Y + attribute \src "ls180.v:8315.6-8315.92" case 1'1 assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] \main_sdphy_datar_datar_buf_sink_valid assign $0\main_sdphy_datar_datar_buf_source_first[0:0] \main_sdphy_datar_datar_buf_sink_first @@ -124515,9 +124466,9 @@ module \ls180 assign $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] \main_sdphy_datar_datar_buf_sink_payload_data case end - attribute \src "ls180.v:8324.2-8329.5" + attribute \src "ls180.v:8321.2-8326.5" switch \main_sdphy_datar_datar_reset - attribute \src "ls180.v:8324.6-8324.34" + attribute \src "ls180.v:8321.6-8321.34" case 1'1 assign $0\main_sdphy_datar_datar_run[0:0] 1'0 assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0 @@ -124525,434 +124476,434 @@ module \ls180 assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0 case end - attribute \src "ls180.v:8331.2-8333.5" + attribute \src "ls180.v:8328.2-8330.5" switch \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 - attribute \src "ls180.v:8331.6-8331.60" + attribute \src "ls180.v:8328.6-8328.60" case 1'1 assign $0\main_sdphy_datar_count[9:0] \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 case end - attribute \src "ls180.v:8334.2-8336.5" + attribute \src "ls180.v:8331.2-8333.5" switch \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 - attribute \src "ls180.v:8334.6-8334.62" + attribute \src "ls180.v:8331.6-8331.62" case 1'1 assign $0\main_sdphy_datar_timeout[31:0] \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 case end - attribute \src "ls180.v:8337.2-8339.5" + attribute \src "ls180.v:8334.2-8336.5" switch \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 - attribute \src "ls180.v:8337.6-8337.66" + attribute \src "ls180.v:8334.6-8334.66" case 1'1 assign $0\main_sdphy_datar_datar_reset[0:0] \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 case end - attribute \src "ls180.v:8340.2-8346.5" + attribute \src "ls180.v:8337.2-8343.5" switch \main_sdcore_crc7_inserter_clr - attribute \src "ls180.v:8340.6-8340.35" + attribute \src "ls180.v:8337.6-8337.35" case 1'1 assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000 - attribute \src "ls180.v:8342.6-8342.10" + attribute \src "ls180.v:8339.6-8339.10" case - attribute \src "ls180.v:8343.3-8345.6" + attribute \src "ls180.v:8340.3-8342.6" switch \main_sdcore_crc7_inserter_enable - attribute \src "ls180.v:8343.7-8343.39" + attribute \src "ls180.v:8340.7-8340.39" case 1'1 assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] \main_sdcore_crc7_inserter_crcreg40 case end end - attribute \src "ls180.v:8347.2-8353.5" + attribute \src "ls180.v:8344.2-8350.5" switch \main_sdcore_crc16_inserter_crc0_clr - attribute \src "ls180.v:8347.6-8347.41" + attribute \src "ls180.v:8344.6-8344.41" case 1'1 assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8349.6-8349.10" + attribute \src "ls180.v:8346.6-8346.10" case - attribute \src "ls180.v:8350.3-8352.6" + attribute \src "ls180.v:8347.3-8349.6" switch \main_sdcore_crc16_inserter_crc0_enable - attribute \src "ls180.v:8350.7-8350.45" + attribute \src "ls180.v:8347.7-8347.45" case 1'1 assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] \main_sdcore_crc16_inserter_crc0_crcreg2 case end end - attribute \src "ls180.v:8354.2-8360.5" + attribute \src "ls180.v:8351.2-8357.5" switch \main_sdcore_crc16_inserter_crc1_clr - attribute \src "ls180.v:8354.6-8354.41" + attribute \src "ls180.v:8351.6-8351.41" case 1'1 assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8356.6-8356.10" + attribute \src "ls180.v:8353.6-8353.10" case - attribute \src "ls180.v:8357.3-8359.6" + attribute \src "ls180.v:8354.3-8356.6" switch \main_sdcore_crc16_inserter_crc1_enable - attribute \src "ls180.v:8357.7-8357.45" + attribute \src "ls180.v:8354.7-8354.45" case 1'1 assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] \main_sdcore_crc16_inserter_crc1_crcreg2 case end end - attribute \src "ls180.v:8361.2-8367.5" + attribute \src "ls180.v:8358.2-8364.5" switch \main_sdcore_crc16_inserter_crc2_clr - attribute \src "ls180.v:8361.6-8361.41" + attribute \src "ls180.v:8358.6-8358.41" case 1'1 assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8363.6-8363.10" + attribute \src "ls180.v:8360.6-8360.10" case - attribute \src "ls180.v:8364.3-8366.6" + attribute \src "ls180.v:8361.3-8363.6" switch \main_sdcore_crc16_inserter_crc2_enable - attribute \src "ls180.v:8364.7-8364.45" + attribute \src "ls180.v:8361.7-8361.45" case 1'1 assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] \main_sdcore_crc16_inserter_crc2_crcreg2 case end end - attribute \src "ls180.v:8368.2-8374.5" + attribute \src "ls180.v:8365.2-8371.5" switch \main_sdcore_crc16_inserter_crc3_clr - attribute \src "ls180.v:8368.6-8368.41" + attribute \src "ls180.v:8365.6-8365.41" case 1'1 assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8370.6-8370.10" + attribute \src "ls180.v:8367.6-8367.10" case - attribute \src "ls180.v:8371.3-8373.6" + attribute \src "ls180.v:8368.3-8370.6" switch \main_sdcore_crc16_inserter_crc3_enable - attribute \src "ls180.v:8371.7-8371.45" + attribute \src "ls180.v:8368.7-8368.45" case 1'1 assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] \main_sdcore_crc16_inserter_crc3_crcreg2 case end end - attribute \src "ls180.v:8376.2-8378.5" + attribute \src "ls180.v:8373.2-8375.5" switch \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 - attribute \src "ls180.v:8376.6-8376.82" + attribute \src "ls180.v:8373.6-8373.82" case 1'1 assign $0\main_sdcore_crc16_inserter_crctmp0[15:0] \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 case end - attribute \src "ls180.v:8379.2-8381.5" + attribute \src "ls180.v:8376.2-8378.5" switch \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 - attribute \src "ls180.v:8379.6-8379.82" + attribute \src "ls180.v:8376.6-8376.82" case 1'1 assign $0\main_sdcore_crc16_inserter_crctmp1[15:0] \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 case end - attribute \src "ls180.v:8382.2-8384.5" + attribute \src "ls180.v:8379.2-8381.5" switch \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 - attribute \src "ls180.v:8382.6-8382.82" + attribute \src "ls180.v:8379.6-8379.82" case 1'1 assign $0\main_sdcore_crc16_inserter_crctmp2[15:0] \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 case end - attribute \src "ls180.v:8385.2-8387.5" + attribute \src "ls180.v:8382.2-8384.5" switch \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 - attribute \src "ls180.v:8385.6-8385.82" + attribute \src "ls180.v:8382.6-8382.82" case 1'1 assign $0\main_sdcore_crc16_inserter_crctmp3[15:0] \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 case end - attribute \src "ls180.v:8388.2-8390.5" + attribute \src "ls180.v:8385.2-8387.5" switch \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 - attribute \src "ls180.v:8388.6-8388.78" + attribute \src "ls180.v:8385.6-8385.78" case 1'1 assign $0\main_sdcore_crc16_inserter_cnt[2:0] \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 case end - attribute \src "ls180.v:8391.2-8393.5" - switch $and$ls180.v:8391$2628_Y - attribute \src "ls180.v:8391.6-8391.83" + attribute \src "ls180.v:8388.2-8390.5" + switch $and$ls180.v:8388$2626_Y + attribute \src "ls180.v:8388.6-8388.83" case 1'1 assign $0\main_sdcore_crc16_checker_crctmp0[15:0] \main_sdcore_crc16_checker_crc0_crc case end - attribute \src "ls180.v:8394.2-8396.5" - switch $and$ls180.v:8394$2629_Y - attribute \src "ls180.v:8394.6-8394.83" + attribute \src "ls180.v:8391.2-8393.5" + switch $and$ls180.v:8391$2627_Y + attribute \src "ls180.v:8391.6-8391.83" case 1'1 assign $0\main_sdcore_crc16_checker_crctmp1[15:0] \main_sdcore_crc16_checker_crc1_crc case end - attribute \src "ls180.v:8397.2-8399.5" - switch $and$ls180.v:8397$2630_Y - attribute \src "ls180.v:8397.6-8397.83" + attribute \src "ls180.v:8394.2-8396.5" + switch $and$ls180.v:8394$2628_Y + attribute \src "ls180.v:8394.6-8394.83" case 1'1 assign $0\main_sdcore_crc16_checker_crctmp2[15:0] \main_sdcore_crc16_checker_crc2_crc case end - attribute \src "ls180.v:8400.2-8402.5" - switch $and$ls180.v:8400$2631_Y - attribute \src "ls180.v:8400.6-8400.83" + attribute \src "ls180.v:8397.2-8399.5" + switch $and$ls180.v:8397$2629_Y + attribute \src "ls180.v:8397.6-8397.83" case 1'1 assign $0\main_sdcore_crc16_checker_crctmp3[15:0] \main_sdcore_crc16_checker_crc3_crc case end - attribute \src "ls180.v:8403.2-8407.5" - switch $and$ls180.v:8403$2632_Y - attribute \src "ls180.v:8403.6-8403.83" + attribute \src "ls180.v:8400.2-8404.5" + switch $and$ls180.v:8400$2630_Y + attribute \src "ls180.v:8400.6-8400.83" case 1'1 assign $0\main_sdcore_crc16_checker_fifo0[15:0] { \main_sdcore_crc16_checker_fifo0 [13:0] \main_sdcore_crc16_checker_sink_payload_data [7] \main_sdcore_crc16_checker_sink_payload_data [3] } assign $0\main_sdcore_crc16_checker_val[7:0] [7] \main_sdcore_crc16_checker_fifo0 [13] assign $0\main_sdcore_crc16_checker_val[7:0] [3] \main_sdcore_crc16_checker_fifo0 [12] case end - attribute \src "ls180.v:8408.2-8412.5" - switch $and$ls180.v:8408$2633_Y - attribute \src "ls180.v:8408.6-8408.83" + attribute \src "ls180.v:8405.2-8409.5" + switch $and$ls180.v:8405$2631_Y + attribute \src "ls180.v:8405.6-8405.83" case 1'1 assign $0\main_sdcore_crc16_checker_fifo1[15:0] { \main_sdcore_crc16_checker_fifo1 [13:0] \main_sdcore_crc16_checker_sink_payload_data [6] \main_sdcore_crc16_checker_sink_payload_data [2] } assign $0\main_sdcore_crc16_checker_val[7:0] [6] \main_sdcore_crc16_checker_fifo1 [13] assign $0\main_sdcore_crc16_checker_val[7:0] [2] \main_sdcore_crc16_checker_fifo1 [12] case end - attribute \src "ls180.v:8413.2-8417.5" - switch $and$ls180.v:8413$2634_Y - attribute \src "ls180.v:8413.6-8413.83" + attribute \src "ls180.v:8410.2-8414.5" + switch $and$ls180.v:8410$2632_Y + attribute \src "ls180.v:8410.6-8410.83" case 1'1 assign $0\main_sdcore_crc16_checker_fifo2[15:0] { \main_sdcore_crc16_checker_fifo2 [13:0] \main_sdcore_crc16_checker_sink_payload_data [5] \main_sdcore_crc16_checker_sink_payload_data [1] } assign $0\main_sdcore_crc16_checker_val[7:0] [5] \main_sdcore_crc16_checker_fifo2 [13] assign $0\main_sdcore_crc16_checker_val[7:0] [1] \main_sdcore_crc16_checker_fifo2 [12] case end - attribute \src "ls180.v:8418.2-8422.5" - switch $and$ls180.v:8418$2635_Y - attribute \src "ls180.v:8418.6-8418.83" + attribute \src "ls180.v:8415.2-8419.5" + switch $and$ls180.v:8415$2633_Y + attribute \src "ls180.v:8415.6-8415.83" case 1'1 assign $0\main_sdcore_crc16_checker_fifo3[15:0] { \main_sdcore_crc16_checker_fifo3 [13:0] \main_sdcore_crc16_checker_sink_payload_data [4] \main_sdcore_crc16_checker_sink_payload_data [0] } assign $0\main_sdcore_crc16_checker_val[7:0] [4] \main_sdcore_crc16_checker_fifo3 [13] assign $0\main_sdcore_crc16_checker_val[7:0] [0] \main_sdcore_crc16_checker_fifo3 [12] case end - attribute \src "ls180.v:8423.2-8431.5" - switch $and$ls180.v:8423$2636_Y - attribute \src "ls180.v:8423.6-8423.83" + attribute \src "ls180.v:8420.2-8428.5" + switch $and$ls180.v:8420$2634_Y + attribute \src "ls180.v:8420.6-8420.83" case 1'1 - attribute \src "ls180.v:8424.3-8430.6" + attribute \src "ls180.v:8421.3-8427.6" switch \main_sdcore_crc16_checker_sink_last - attribute \src "ls180.v:8424.7-8424.42" + attribute \src "ls180.v:8421.7-8421.42" case 1'1 assign $0\main_sdcore_crc16_checker_cnt[3:0] 4'0000 - attribute \src "ls180.v:8426.7-8426.11" + attribute \src "ls180.v:8423.7-8423.11" case - attribute \src "ls180.v:8427.4-8429.7" - switch $ne$ls180.v:8427$2637_Y - attribute \src "ls180.v:8427.8-8427.48" + attribute \src "ls180.v:8424.4-8426.7" + switch $ne$ls180.v:8424$2635_Y + attribute \src "ls180.v:8424.8-8424.48" case 1'1 - assign $0\main_sdcore_crc16_checker_cnt[3:0] $add$ls180.v:8428$2638_Y + assign $0\main_sdcore_crc16_checker_cnt[3:0] $add$ls180.v:8425$2636_Y case end end case end - attribute \src "ls180.v:8432.2-8438.5" + attribute \src "ls180.v:8429.2-8435.5" switch \main_sdcore_crc16_checker_crc0_clr - attribute \src "ls180.v:8432.6-8432.40" + attribute \src "ls180.v:8429.6-8429.40" case 1'1 assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8434.6-8434.10" + attribute \src "ls180.v:8431.6-8431.10" case - attribute \src "ls180.v:8435.3-8437.6" + attribute \src "ls180.v:8432.3-8434.6" switch \main_sdcore_crc16_checker_crc0_enable - attribute \src "ls180.v:8435.7-8435.44" + attribute \src "ls180.v:8432.7-8432.44" case 1'1 assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] \main_sdcore_crc16_checker_crc0_crcreg2 case end end - attribute \src "ls180.v:8439.2-8445.5" + attribute \src "ls180.v:8436.2-8442.5" switch \main_sdcore_crc16_checker_crc1_clr - attribute \src "ls180.v:8439.6-8439.40" + attribute \src "ls180.v:8436.6-8436.40" case 1'1 assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8441.6-8441.10" + attribute \src "ls180.v:8438.6-8438.10" case - attribute \src "ls180.v:8442.3-8444.6" + attribute \src "ls180.v:8439.3-8441.6" switch \main_sdcore_crc16_checker_crc1_enable - attribute \src "ls180.v:8442.7-8442.44" + attribute \src "ls180.v:8439.7-8439.44" case 1'1 assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] \main_sdcore_crc16_checker_crc1_crcreg2 case end end - attribute \src "ls180.v:8446.2-8452.5" + attribute \src "ls180.v:8443.2-8449.5" switch \main_sdcore_crc16_checker_crc2_clr - attribute \src "ls180.v:8446.6-8446.40" + attribute \src "ls180.v:8443.6-8443.40" case 1'1 assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8448.6-8448.10" + attribute \src "ls180.v:8445.6-8445.10" case - attribute \src "ls180.v:8449.3-8451.6" + attribute \src "ls180.v:8446.3-8448.6" switch \main_sdcore_crc16_checker_crc2_enable - attribute \src "ls180.v:8449.7-8449.44" + attribute \src "ls180.v:8446.7-8446.44" case 1'1 assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] \main_sdcore_crc16_checker_crc2_crcreg2 case end end - attribute \src "ls180.v:8453.2-8459.5" + attribute \src "ls180.v:8450.2-8456.5" switch \main_sdcore_crc16_checker_crc3_clr - attribute \src "ls180.v:8453.6-8453.40" + attribute \src "ls180.v:8450.6-8450.40" case 1'1 assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8455.6-8455.10" + attribute \src "ls180.v:8452.6-8452.10" case - attribute \src "ls180.v:8456.3-8458.6" + attribute \src "ls180.v:8453.3-8455.6" switch \main_sdcore_crc16_checker_crc3_enable - attribute \src "ls180.v:8456.7-8456.44" + attribute \src "ls180.v:8453.7-8453.44" case 1'1 assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] \main_sdcore_crc16_checker_crc3_crcreg2 case end end - attribute \src "ls180.v:8461.2-8463.5" + attribute \src "ls180.v:8458.2-8460.5" switch \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 - attribute \src "ls180.v:8461.6-8461.52" + attribute \src "ls180.v:8458.6-8458.52" case 1'1 assign $0\main_sdcore_cmd_done[0:0] \main_sdcore_cmd_done_sdcore_fsm_next_value0 case end - attribute \src "ls180.v:8464.2-8466.5" + attribute \src "ls180.v:8461.2-8463.5" switch \main_sdcore_data_done_sdcore_fsm_next_value_ce1 - attribute \src "ls180.v:8464.6-8464.53" + attribute \src "ls180.v:8461.6-8461.53" case 1'1 assign $0\main_sdcore_data_done[0:0] \main_sdcore_data_done_sdcore_fsm_next_value1 case end - attribute \src "ls180.v:8467.2-8469.5" + attribute \src "ls180.v:8464.2-8466.5" switch \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 - attribute \src "ls180.v:8467.6-8467.53" + attribute \src "ls180.v:8464.6-8464.53" case 1'1 assign $0\main_sdcore_cmd_count[2:0] \main_sdcore_cmd_count_sdcore_fsm_next_value2 case end - attribute \src "ls180.v:8470.2-8472.5" + attribute \src "ls180.v:8467.2-8469.5" switch \main_sdcore_data_count_sdcore_fsm_next_value_ce3 - attribute \src "ls180.v:8470.6-8470.54" + attribute \src "ls180.v:8467.6-8467.54" case 1'1 assign $0\main_sdcore_data_count[31:0] \main_sdcore_data_count_sdcore_fsm_next_value3 case end - attribute \src "ls180.v:8473.2-8475.5" + attribute \src "ls180.v:8470.2-8472.5" switch \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 - attribute \src "ls180.v:8473.6-8473.53" + attribute \src "ls180.v:8470.6-8470.53" case 1'1 assign $0\main_sdcore_cmd_error[0:0] \main_sdcore_cmd_error_sdcore_fsm_next_value4 case end - attribute \src "ls180.v:8476.2-8478.5" + attribute \src "ls180.v:8473.2-8475.5" switch \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 - attribute \src "ls180.v:8476.6-8476.55" + attribute \src "ls180.v:8473.6-8473.55" case 1'1 assign $0\main_sdcore_cmd_timeout[0:0] \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 case end - attribute \src "ls180.v:8479.2-8481.5" + attribute \src "ls180.v:8476.2-8478.5" switch \main_sdcore_data_error_sdcore_fsm_next_value_ce6 - attribute \src "ls180.v:8479.6-8479.54" + attribute \src "ls180.v:8476.6-8476.54" case 1'1 assign $0\main_sdcore_data_error[0:0] \main_sdcore_data_error_sdcore_fsm_next_value6 case end - attribute \src "ls180.v:8482.2-8484.5" + attribute \src "ls180.v:8479.2-8481.5" switch \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 - attribute \src "ls180.v:8482.6-8482.56" + attribute \src "ls180.v:8479.6-8479.56" case 1'1 assign $0\main_sdcore_data_timeout[0:0] \main_sdcore_data_timeout_sdcore_fsm_next_value7 case end - attribute \src "ls180.v:8485.2-8487.5" + attribute \src "ls180.v:8482.2-8484.5" switch \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 - attribute \src "ls180.v:8485.6-8485.63" + attribute \src "ls180.v:8482.6-8482.63" case 1'1 assign $0\main_sdcore_cmd_response_status[127:0] \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 case end - attribute \src "ls180.v:8488.2-8490.5" - switch $and$ls180.v:8488$2641_Y - attribute \src "ls180.v:8488.6-8488.120" + attribute \src "ls180.v:8485.2-8487.5" + switch $and$ls180.v:8485$2639_Y + attribute \src "ls180.v:8485.6-8485.120" case 1'1 - assign $0\main_sdblock2mem_fifo_produce[4:0] $add$ls180.v:8489$2642_Y + assign $0\main_sdblock2mem_fifo_produce[4:0] $add$ls180.v:8486$2640_Y case end - attribute \src "ls180.v:8491.2-8493.5" + attribute \src "ls180.v:8488.2-8490.5" switch \main_sdblock2mem_fifo_do_read - attribute \src "ls180.v:8491.6-8491.35" + attribute \src "ls180.v:8488.6-8488.35" case 1'1 - assign $0\main_sdblock2mem_fifo_consume[4:0] $add$ls180.v:8492$2643_Y + assign $0\main_sdblock2mem_fifo_consume[4:0] $add$ls180.v:8489$2641_Y case end - attribute \src "ls180.v:8494.2-8502.5" - switch $and$ls180.v:8494$2646_Y - attribute \src "ls180.v:8494.6-8494.120" + attribute \src "ls180.v:8491.2-8499.5" + switch $and$ls180.v:8491$2644_Y + attribute \src "ls180.v:8491.6-8491.120" case 1'1 - attribute \src "ls180.v:8495.3-8497.6" - switch $not$ls180.v:8495$2647_Y - attribute \src "ls180.v:8495.7-8495.39" + attribute \src "ls180.v:8492.3-8494.6" + switch $not$ls180.v:8492$2645_Y + attribute \src "ls180.v:8492.7-8492.39" case 1'1 - assign $0\main_sdblock2mem_fifo_level[5:0] $add$ls180.v:8496$2648_Y + assign $0\main_sdblock2mem_fifo_level[5:0] $add$ls180.v:8493$2646_Y case end - attribute \src "ls180.v:8498.6-8498.10" + attribute \src "ls180.v:8495.6-8495.10" case - attribute \src "ls180.v:8499.3-8501.6" + attribute \src "ls180.v:8496.3-8498.6" switch \main_sdblock2mem_fifo_do_read - attribute \src "ls180.v:8499.7-8499.36" + attribute \src "ls180.v:8496.7-8496.36" case 1'1 - assign $0\main_sdblock2mem_fifo_level[5:0] $sub$ls180.v:8500$2649_Y + assign $0\main_sdblock2mem_fifo_level[5:0] $sub$ls180.v:8497$2647_Y case end end - attribute \src "ls180.v:8503.2-8505.5" + attribute \src "ls180.v:8500.2-8502.5" switch \main_sdblock2mem_converter_source_ready - attribute \src "ls180.v:8503.6-8503.45" + attribute \src "ls180.v:8500.6-8500.45" case 1'1 assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'0 case end - attribute \src "ls180.v:8506.2-8513.5" + attribute \src "ls180.v:8503.2-8510.5" switch \main_sdblock2mem_converter_load_part - attribute \src "ls180.v:8506.6-8506.42" + attribute \src "ls180.v:8503.6-8503.42" case 1'1 - attribute \src "ls180.v:8507.3-8512.6" - switch $or$ls180.v:8507$2651_Y - attribute \src "ls180.v:8507.7-8507.90" + attribute \src "ls180.v:8504.3-8509.6" + switch $or$ls180.v:8504$2649_Y + attribute \src "ls180.v:8504.7-8504.90" case 1'1 assign $0\main_sdblock2mem_converter_demux[1:0] 2'00 assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'1 - attribute \src "ls180.v:8510.7-8510.11" + attribute \src "ls180.v:8507.7-8507.11" case - assign $0\main_sdblock2mem_converter_demux[1:0] $add$ls180.v:8511$2652_Y + assign $0\main_sdblock2mem_converter_demux[1:0] $add$ls180.v:8508$2650_Y end case end - attribute \src "ls180.v:8514.2-8527.5" - switch $and$ls180.v:8514$2653_Y - attribute \src "ls180.v:8514.6-8514.89" + attribute \src "ls180.v:8511.2-8524.5" + switch $and$ls180.v:8511$2651_Y + attribute \src "ls180.v:8511.6-8511.89" case 1'1 - attribute \src "ls180.v:8515.3-8521.6" - switch $and$ls180.v:8515$2654_Y - attribute \src "ls180.v:8515.7-8515.86" + attribute \src "ls180.v:8512.3-8518.6" + switch $and$ls180.v:8512$2652_Y + attribute \src "ls180.v:8512.7-8512.86" case 1'1 assign $0\main_sdblock2mem_converter_source_first[0:0] \main_sdblock2mem_converter_sink_first assign $0\main_sdblock2mem_converter_source_last[0:0] \main_sdblock2mem_converter_sink_last - attribute \src "ls180.v:8518.7-8518.11" + attribute \src "ls180.v:8515.7-8515.11" case assign $0\main_sdblock2mem_converter_source_first[0:0] 1'0 assign $0\main_sdblock2mem_converter_source_last[0:0] 1'0 end - attribute \src "ls180.v:8522.6-8522.10" + attribute \src "ls180.v:8519.6-8519.10" case - attribute \src "ls180.v:8523.3-8526.6" - switch $and$ls180.v:8523$2655_Y - attribute \src "ls180.v:8523.7-8523.86" + attribute \src "ls180.v:8520.3-8523.6" + switch $and$ls180.v:8520$2653_Y + attribute \src "ls180.v:8520.7-8520.86" case 1'1 - assign $0\main_sdblock2mem_converter_source_first[0:0] $or$ls180.v:8524$2656_Y - assign $0\main_sdblock2mem_converter_source_last[0:0] $or$ls180.v:8525$2657_Y + assign $0\main_sdblock2mem_converter_source_first[0:0] $or$ls180.v:8521$2654_Y + assign $0\main_sdblock2mem_converter_source_last[0:0] $or$ls180.v:8522$2655_Y case end end - attribute \src "ls180.v:8528.2-8543.5" + attribute \src "ls180.v:8525.2-8540.5" switch \main_sdblock2mem_converter_load_part - attribute \src "ls180.v:8528.6-8528.42" + attribute \src "ls180.v:8525.6-8525.42" case 1'1 - attribute \src "ls180.v:8529.3-8542.10" + attribute \src "ls180.v:8526.3-8539.10" switch \main_sdblock2mem_converter_demux attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -124970,132 +124921,132 @@ module \ls180 end case end - attribute \src "ls180.v:8544.2-8546.5" + attribute \src "ls180.v:8541.2-8543.5" switch \main_sdblock2mem_converter_load_part - attribute \src "ls180.v:8544.6-8544.42" + attribute \src "ls180.v:8541.6-8541.42" case 1'1 - assign $0\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] $add$ls180.v:8545$2658_Y + assign $0\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] $add$ls180.v:8542$2656_Y case end - attribute \src "ls180.v:8548.2-8550.5" + attribute \src "ls180.v:8545.2-8547.5" switch \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce - attribute \src "ls180.v:8548.6-8548.76" + attribute \src "ls180.v:8545.6-8545.76" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value case end - attribute \src "ls180.v:8551.2-8554.5" + attribute \src "ls180.v:8548.2-8551.5" switch \main_sdblock2mem_wishbonedmawriter_reset - attribute \src "ls180.v:8551.6-8551.46" + attribute \src "ls180.v:8548.6-8548.46" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0 assign $0\builder_sdblock2memdma_state[1:0] 2'00 case end - attribute \src "ls180.v:8556.2-8558.5" + attribute \src "ls180.v:8553.2-8555.5" switch \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce - attribute \src "ls180.v:8556.6-8556.64" + attribute \src "ls180.v:8553.6-8553.64" case 1'1 assign $0\main_sdmem2block_dma_data[31:0] \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value case end - attribute \src "ls180.v:8560.2-8562.5" + attribute \src "ls180.v:8557.2-8559.5" switch \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce - attribute \src "ls180.v:8560.6-8560.76" + attribute \src "ls180.v:8557.6-8557.76" case 1'1 assign $0\main_sdmem2block_dma_offset[31:0] \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value case end - attribute \src "ls180.v:8563.2-8566.5" + attribute \src "ls180.v:8560.2-8563.5" switch \main_sdmem2block_dma_reset - attribute \src "ls180.v:8563.6-8563.32" + attribute \src "ls180.v:8560.6-8560.32" case 1'1 assign $0\main_sdmem2block_dma_offset[31:0] 0 assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00 case end - attribute \src "ls180.v:8567.2-8573.5" - switch $and$ls180.v:8567$2659_Y - attribute \src "ls180.v:8567.6-8567.89" + attribute \src "ls180.v:8564.2-8570.5" + switch $and$ls180.v:8564$2657_Y + attribute \src "ls180.v:8564.6-8564.89" case 1'1 - attribute \src "ls180.v:8568.3-8572.6" + attribute \src "ls180.v:8565.3-8569.6" switch \main_sdmem2block_converter_last - attribute \src "ls180.v:8568.7-8568.38" + attribute \src "ls180.v:8565.7-8565.38" case 1'1 assign $0\main_sdmem2block_converter_mux[1:0] 2'00 - attribute \src "ls180.v:8570.7-8570.11" + attribute \src "ls180.v:8567.7-8567.11" case - assign $0\main_sdmem2block_converter_mux[1:0] $add$ls180.v:8571$2660_Y + assign $0\main_sdmem2block_converter_mux[1:0] $add$ls180.v:8568$2658_Y end case end - attribute \src "ls180.v:8574.2-8576.5" - switch $and$ls180.v:8574$2663_Y - attribute \src "ls180.v:8574.6-8574.120" + attribute \src "ls180.v:8571.2-8573.5" + switch $and$ls180.v:8571$2661_Y + attribute \src "ls180.v:8571.6-8571.120" case 1'1 - assign $0\main_sdmem2block_fifo_produce[4:0] $add$ls180.v:8575$2664_Y + assign $0\main_sdmem2block_fifo_produce[4:0] $add$ls180.v:8572$2662_Y case end - attribute \src "ls180.v:8577.2-8579.5" + attribute \src "ls180.v:8574.2-8576.5" switch \main_sdmem2block_fifo_do_read - attribute \src "ls180.v:8577.6-8577.35" + attribute \src "ls180.v:8574.6-8574.35" case 1'1 - assign $0\main_sdmem2block_fifo_consume[4:0] $add$ls180.v:8578$2665_Y + assign $0\main_sdmem2block_fifo_consume[4:0] $add$ls180.v:8575$2663_Y case end - attribute \src "ls180.v:8580.2-8588.5" - switch $and$ls180.v:8580$2668_Y - attribute \src "ls180.v:8580.6-8580.120" + attribute \src "ls180.v:8577.2-8585.5" + switch $and$ls180.v:8577$2666_Y + attribute \src "ls180.v:8577.6-8577.120" case 1'1 - attribute \src "ls180.v:8581.3-8583.6" - switch $not$ls180.v:8581$2669_Y - attribute \src "ls180.v:8581.7-8581.39" + attribute \src "ls180.v:8578.3-8580.6" + switch $not$ls180.v:8578$2667_Y + attribute \src "ls180.v:8578.7-8578.39" case 1'1 - assign $0\main_sdmem2block_fifo_level[5:0] $add$ls180.v:8582$2670_Y + assign $0\main_sdmem2block_fifo_level[5:0] $add$ls180.v:8579$2668_Y case end - attribute \src "ls180.v:8584.6-8584.10" + attribute \src "ls180.v:8581.6-8581.10" case - attribute \src "ls180.v:8585.3-8587.6" + attribute \src "ls180.v:8582.3-8584.6" switch \main_sdmem2block_fifo_do_read - attribute \src "ls180.v:8585.7-8585.36" + attribute \src "ls180.v:8582.7-8582.36" case 1'1 - assign $0\main_sdmem2block_fifo_level[5:0] $sub$ls180.v:8586$2671_Y + assign $0\main_sdmem2block_fifo_level[5:0] $sub$ls180.v:8583$2669_Y case end end - attribute \src "ls180.v:8590.2-8597.5" + attribute \src "ls180.v:8587.2-8594.5" switch \libresocsim_clk_rise - attribute \src "ls180.v:8590.6-8590.26" + attribute \src "ls180.v:8587.6-8587.26" case 1'1 assign $0\spisdcard_clk[0:0] \libresocsim_clk_enable - attribute \src "ls180.v:8592.6-8592.10" + attribute \src "ls180.v:8589.6-8589.10" case - attribute \src "ls180.v:8593.3-8596.6" + attribute \src "ls180.v:8590.3-8593.6" switch \libresocsim_clk_fall - attribute \src "ls180.v:8593.7-8593.27" + attribute \src "ls180.v:8590.7-8590.27" case 1'1 assign $0\libresocsim_clk_divider1[15:0] 16'0000000000000000 assign $0\spisdcard_clk[0:0] 1'0 case end end - attribute \src "ls180.v:8599.2-8609.5" + attribute \src "ls180.v:8596.2-8606.5" switch \libresocsim_mosi_latch - attribute \src "ls180.v:8599.6-8599.28" + attribute \src "ls180.v:8596.6-8596.28" case 1'1 assign $0\libresocsim_mosi_data[7:0] \libresocsim_mosi assign $0\libresocsim_mosi_sel[2:0] 3'111 - attribute \src "ls180.v:8602.6-8602.10" + attribute \src "ls180.v:8599.6-8599.10" case - attribute \src "ls180.v:8603.3-8608.6" + attribute \src "ls180.v:8600.3-8605.6" switch \libresocsim_clk_fall - attribute \src "ls180.v:8603.7-8603.27" + attribute \src "ls180.v:8600.7-8600.27" case 1'1 - assign $0\libresocsim_mosi_sel[2:0] $sub$ls180.v:8607$2676_Y - attribute \src "ls180.v:8604.4-8606.7" + assign $0\libresocsim_mosi_sel[2:0] $sub$ls180.v:8604$2674_Y + attribute \src "ls180.v:8601.4-8603.7" switch \libresocsim_cs_enable - attribute \src "ls180.v:8604.8-8604.29" + attribute \src "ls180.v:8601.8-8601.29" case 1'1 assign $0\spisdcard_mosi[0:0] \builder_sync_f_array_muxed1 case @@ -125103,88 +125054,88 @@ module \ls180 case end end - attribute \src "ls180.v:8610.2-8616.5" + attribute \src "ls180.v:8607.2-8613.5" switch \libresocsim_clk_rise - attribute \src "ls180.v:8610.6-8610.26" + attribute \src "ls180.v:8607.6-8607.26" case 1'1 - attribute \src "ls180.v:8611.3-8615.6" + attribute \src "ls180.v:8608.3-8612.6" switch \libresocsim_loopback - attribute \src "ls180.v:8611.7-8611.27" + attribute \src "ls180.v:8608.7-8608.27" case 1'1 assign $0\libresocsim_miso_data[7:0] { \libresocsim_miso_data [6:0] \spisdcard_mosi } - attribute \src "ls180.v:8613.7-8613.11" + attribute \src "ls180.v:8610.7-8610.11" case assign $0\libresocsim_miso_data[7:0] { \libresocsim_miso_data [6:0] \spisdcard_miso } end case end - attribute \src "ls180.v:8617.2-8619.5" + attribute \src "ls180.v:8614.2-8616.5" switch \libresocsim_miso_latch - attribute \src "ls180.v:8617.6-8617.28" + attribute \src "ls180.v:8614.6-8614.28" case 1'1 assign $0\libresocsim_miso[7:0] \libresocsim_miso_data case end - attribute \src "ls180.v:8621.2-8623.5" + attribute \src "ls180.v:8618.2-8620.5" switch \libresocsim_count_spimaster1_next_value_ce - attribute \src "ls180.v:8621.6-8621.48" + attribute \src "ls180.v:8618.6-8618.48" case 1'1 assign $0\libresocsim_count[2:0] \libresocsim_count_spimaster1_next_value case end - attribute \src "ls180.v:8625.2-8627.5" + attribute \src "ls180.v:8622.2-8624.5" switch \builder_libresocsim_dat_w_next_value_ce0 - attribute \src "ls180.v:8625.6-8625.46" + attribute \src "ls180.v:8622.6-8622.46" case 1'1 assign $0\builder_libresocsim_dat_w[7:0] \builder_libresocsim_dat_w_next_value0 case end - attribute \src "ls180.v:8628.2-8630.5" + attribute \src "ls180.v:8625.2-8627.5" switch \builder_libresocsim_adr_next_value_ce1 - attribute \src "ls180.v:8628.6-8628.44" + attribute \src "ls180.v:8625.6-8625.44" case 1'1 assign $0\builder_libresocsim_adr[13:0] \builder_libresocsim_adr_next_value1 case end - attribute \src "ls180.v:8631.2-8633.5" + attribute \src "ls180.v:8628.2-8630.5" switch \builder_libresocsim_we_next_value_ce2 - attribute \src "ls180.v:8631.6-8631.43" + attribute \src "ls180.v:8628.6-8628.43" case 1'1 assign $0\builder_libresocsim_we[0:0] \builder_libresocsim_we_next_value2 case end - attribute \src "ls180.v:8634.2-8730.9" + attribute \src "ls180.v:8631.2-8727.9" switch \builder_grant attribute \src "ls180.v:0.0-0.0" case 3'000 - attribute \src "ls180.v:8636.4-8652.7" - switch $not$ls180.v:8636$2677_Y - attribute \src "ls180.v:8636.8-8636.29" + attribute \src "ls180.v:8633.4-8649.7" + switch $not$ls180.v:8633$2675_Y + attribute \src "ls180.v:8633.8-8633.29" case 1'1 - attribute \src "ls180.v:8637.5-8651.8" + attribute \src "ls180.v:8634.5-8648.8" switch \builder_request [1] - attribute \src "ls180.v:8637.9-8637.27" + attribute \src "ls180.v:8634.9-8634.27" case 1'1 assign $0\builder_grant[2:0] 3'001 - attribute \src "ls180.v:8639.9-8639.13" + attribute \src "ls180.v:8636.9-8636.13" case - attribute \src "ls180.v:8640.6-8650.9" + attribute \src "ls180.v:8637.6-8647.9" switch \builder_request [2] - attribute \src "ls180.v:8640.10-8640.28" + attribute \src "ls180.v:8637.10-8637.28" case 1'1 assign $0\builder_grant[2:0] 3'010 - attribute \src "ls180.v:8642.10-8642.14" + attribute \src "ls180.v:8639.10-8639.14" case - attribute \src "ls180.v:8643.7-8649.10" + attribute \src "ls180.v:8640.7-8646.10" switch \builder_request [3] - attribute \src "ls180.v:8643.11-8643.29" + attribute \src "ls180.v:8640.11-8640.29" case 1'1 assign $0\builder_grant[2:0] 3'011 - attribute \src "ls180.v:8645.11-8645.15" + attribute \src "ls180.v:8642.11-8642.15" case - attribute \src "ls180.v:8646.8-8648.11" + attribute \src "ls180.v:8643.8-8645.11" switch \builder_request [4] - attribute \src "ls180.v:8646.12-8646.30" + attribute \src "ls180.v:8643.12-8643.30" case 1'1 assign $0\builder_grant[2:0] 3'100 case @@ -125196,34 +125147,34 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 3'001 - attribute \src "ls180.v:8655.4-8671.7" - switch $not$ls180.v:8655$2678_Y - attribute \src "ls180.v:8655.8-8655.29" + attribute \src "ls180.v:8652.4-8668.7" + switch $not$ls180.v:8652$2676_Y + attribute \src "ls180.v:8652.8-8652.29" case 1'1 - attribute \src "ls180.v:8656.5-8670.8" + attribute \src "ls180.v:8653.5-8667.8" switch \builder_request [2] - attribute \src "ls180.v:8656.9-8656.27" + attribute \src "ls180.v:8653.9-8653.27" case 1'1 assign $0\builder_grant[2:0] 3'010 - attribute \src "ls180.v:8658.9-8658.13" + attribute \src "ls180.v:8655.9-8655.13" case - attribute \src "ls180.v:8659.6-8669.9" + attribute \src "ls180.v:8656.6-8666.9" switch \builder_request [3] - attribute \src "ls180.v:8659.10-8659.28" + attribute \src "ls180.v:8656.10-8656.28" case 1'1 assign $0\builder_grant[2:0] 3'011 - attribute \src "ls180.v:8661.10-8661.14" + attribute \src "ls180.v:8658.10-8658.14" case - attribute \src "ls180.v:8662.7-8668.10" + attribute \src "ls180.v:8659.7-8665.10" switch \builder_request [4] - attribute \src "ls180.v:8662.11-8662.29" + attribute \src "ls180.v:8659.11-8659.29" case 1'1 assign $0\builder_grant[2:0] 3'100 - attribute \src "ls180.v:8664.11-8664.15" + attribute \src "ls180.v:8661.11-8661.15" case - attribute \src "ls180.v:8665.8-8667.11" + attribute \src "ls180.v:8662.8-8664.11" switch \builder_request [0] - attribute \src "ls180.v:8665.12-8665.30" + attribute \src "ls180.v:8662.12-8662.30" case 1'1 assign $0\builder_grant[2:0] 3'000 case @@ -125235,34 +125186,34 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 3'010 - attribute \src "ls180.v:8674.4-8690.7" - switch $not$ls180.v:8674$2679_Y - attribute \src "ls180.v:8674.8-8674.29" + attribute \src "ls180.v:8671.4-8687.7" + switch $not$ls180.v:8671$2677_Y + attribute \src "ls180.v:8671.8-8671.29" case 1'1 - attribute \src "ls180.v:8675.5-8689.8" + attribute \src "ls180.v:8672.5-8686.8" switch \builder_request [3] - attribute \src "ls180.v:8675.9-8675.27" + attribute \src "ls180.v:8672.9-8672.27" case 1'1 assign $0\builder_grant[2:0] 3'011 - attribute \src "ls180.v:8677.9-8677.13" + attribute \src "ls180.v:8674.9-8674.13" case - attribute \src "ls180.v:8678.6-8688.9" + attribute \src "ls180.v:8675.6-8685.9" switch \builder_request [4] - attribute \src "ls180.v:8678.10-8678.28" + attribute \src "ls180.v:8675.10-8675.28" case 1'1 assign $0\builder_grant[2:0] 3'100 - attribute \src "ls180.v:8680.10-8680.14" + attribute \src "ls180.v:8677.10-8677.14" case - attribute \src "ls180.v:8681.7-8687.10" + attribute \src "ls180.v:8678.7-8684.10" switch \builder_request [0] - attribute \src "ls180.v:8681.11-8681.29" + attribute \src "ls180.v:8678.11-8678.29" case 1'1 assign $0\builder_grant[2:0] 3'000 - attribute \src "ls180.v:8683.11-8683.15" + attribute \src "ls180.v:8680.11-8680.15" case - attribute \src "ls180.v:8684.8-8686.11" + attribute \src "ls180.v:8681.8-8683.11" switch \builder_request [1] - attribute \src "ls180.v:8684.12-8684.30" + attribute \src "ls180.v:8681.12-8681.30" case 1'1 assign $0\builder_grant[2:0] 3'001 case @@ -125274,34 +125225,34 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 3'011 - attribute \src "ls180.v:8693.4-8709.7" - switch $not$ls180.v:8693$2680_Y - attribute \src "ls180.v:8693.8-8693.29" + attribute \src "ls180.v:8690.4-8706.7" + switch $not$ls180.v:8690$2678_Y + attribute \src "ls180.v:8690.8-8690.29" case 1'1 - attribute \src "ls180.v:8694.5-8708.8" + attribute \src "ls180.v:8691.5-8705.8" switch \builder_request [4] - attribute \src "ls180.v:8694.9-8694.27" + attribute \src "ls180.v:8691.9-8691.27" case 1'1 assign $0\builder_grant[2:0] 3'100 - attribute \src "ls180.v:8696.9-8696.13" + attribute \src "ls180.v:8693.9-8693.13" case - attribute \src "ls180.v:8697.6-8707.9" + attribute \src "ls180.v:8694.6-8704.9" switch \builder_request [0] - attribute \src "ls180.v:8697.10-8697.28" + attribute \src "ls180.v:8694.10-8694.28" case 1'1 assign $0\builder_grant[2:0] 3'000 - attribute \src "ls180.v:8699.10-8699.14" + attribute \src "ls180.v:8696.10-8696.14" case - attribute \src "ls180.v:8700.7-8706.10" + attribute \src "ls180.v:8697.7-8703.10" switch \builder_request [1] - attribute \src "ls180.v:8700.11-8700.29" + attribute \src "ls180.v:8697.11-8697.29" case 1'1 assign $0\builder_grant[2:0] 3'001 - attribute \src "ls180.v:8702.11-8702.15" + attribute \src "ls180.v:8699.11-8699.15" case - attribute \src "ls180.v:8703.8-8705.11" + attribute \src "ls180.v:8700.8-8702.11" switch \builder_request [2] - attribute \src "ls180.v:8703.12-8703.30" + attribute \src "ls180.v:8700.12-8700.30" case 1'1 assign $0\builder_grant[2:0] 3'010 case @@ -125313,34 +125264,34 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 3'100 - attribute \src "ls180.v:8712.4-8728.7" - switch $not$ls180.v:8712$2681_Y - attribute \src "ls180.v:8712.8-8712.29" + attribute \src "ls180.v:8709.4-8725.7" + switch $not$ls180.v:8709$2679_Y + attribute \src "ls180.v:8709.8-8709.29" case 1'1 - attribute \src "ls180.v:8713.5-8727.8" + attribute \src "ls180.v:8710.5-8724.8" switch \builder_request [0] - attribute \src "ls180.v:8713.9-8713.27" + attribute \src "ls180.v:8710.9-8710.27" case 1'1 assign $0\builder_grant[2:0] 3'000 - attribute \src "ls180.v:8715.9-8715.13" + attribute \src "ls180.v:8712.9-8712.13" case - attribute \src "ls180.v:8716.6-8726.9" + attribute \src "ls180.v:8713.6-8723.9" switch \builder_request [1] - attribute \src "ls180.v:8716.10-8716.28" + attribute \src "ls180.v:8713.10-8713.28" case 1'1 assign $0\builder_grant[2:0] 3'001 - attribute \src "ls180.v:8718.10-8718.14" + attribute \src "ls180.v:8715.10-8715.14" case - attribute \src "ls180.v:8719.7-8725.10" + attribute \src "ls180.v:8716.7-8722.10" switch \builder_request [2] - attribute \src "ls180.v:8719.11-8719.29" + attribute \src "ls180.v:8716.11-8716.29" case 1'1 assign $0\builder_grant[2:0] 3'010 - attribute \src "ls180.v:8721.11-8721.15" + attribute \src "ls180.v:8718.11-8718.15" case - attribute \src "ls180.v:8722.8-8724.11" + attribute \src "ls180.v:8719.8-8721.11" switch \builder_request [3] - attribute \src "ls180.v:8722.12-8722.30" + attribute \src "ls180.v:8719.12-8719.30" case 1'1 assign $0\builder_grant[2:0] 3'011 case @@ -125352,26 +125303,26 @@ module \ls180 end case end - attribute \src "ls180.v:8732.2-8738.5" + attribute \src "ls180.v:8729.2-8735.5" switch \builder_wait - attribute \src "ls180.v:8732.6-8732.18" + attribute \src "ls180.v:8729.6-8729.18" case 1'1 - attribute \src "ls180.v:8733.3-8735.6" - switch $not$ls180.v:8733$2682_Y - attribute \src "ls180.v:8733.7-8733.22" + attribute \src "ls180.v:8730.3-8732.6" + switch $not$ls180.v:8730$2680_Y + attribute \src "ls180.v:8730.7-8730.22" case 1'1 - assign $0\builder_count[19:0] $sub$ls180.v:8734$2683_Y + assign $0\builder_count[19:0] $sub$ls180.v:8731$2681_Y case end - attribute \src "ls180.v:8736.6-8736.10" + attribute \src "ls180.v:8733.6-8733.10" case assign $0\builder_count[19:0] 20'11110100001001000000 end - attribute \src "ls180.v:8740.2-8770.5" + attribute \src "ls180.v:8737.2-8767.5" switch \builder_csrbank0_sel - attribute \src "ls180.v:8740.6-8740.26" + attribute \src "ls180.v:8737.6-8737.26" case 1'1 - attribute \src "ls180.v:8741.3-8769.10" + attribute \src "ls180.v:8738.3-8766.10" switch \builder_interface0_bank_bus_adr [3:0] attribute \src "ls180.v:0.0-0.0" case 4'0000 @@ -125404,46 +125355,46 @@ module \ls180 end case end - attribute \src "ls180.v:8771.2-8773.5" + attribute \src "ls180.v:8768.2-8770.5" switch \builder_csrbank0_reset0_re - attribute \src "ls180.v:8771.6-8771.32" + attribute \src "ls180.v:8768.6-8768.32" case 1'1 assign $0\main_libresocsim_reset_storage[0:0] \builder_csrbank0_reset0_r case end - attribute \src "ls180.v:8775.2-8777.5" + attribute \src "ls180.v:8772.2-8774.5" switch \builder_csrbank0_scratch3_re - attribute \src "ls180.v:8775.6-8775.34" + attribute \src "ls180.v:8772.6-8772.34" case 1'1 assign $0\main_libresocsim_scratch_storage[31:0] [31:24] \builder_csrbank0_scratch3_r case end - attribute \src "ls180.v:8778.2-8780.5" + attribute \src "ls180.v:8775.2-8777.5" switch \builder_csrbank0_scratch2_re - attribute \src "ls180.v:8778.6-8778.34" + attribute \src "ls180.v:8775.6-8775.34" case 1'1 assign $0\main_libresocsim_scratch_storage[31:0] [23:16] \builder_csrbank0_scratch2_r case end - attribute \src "ls180.v:8781.2-8783.5" + attribute \src "ls180.v:8778.2-8780.5" switch \builder_csrbank0_scratch1_re - attribute \src "ls180.v:8781.6-8781.34" + attribute \src "ls180.v:8778.6-8778.34" case 1'1 assign $0\main_libresocsim_scratch_storage[31:0] [15:8] \builder_csrbank0_scratch1_r case end - attribute \src "ls180.v:8784.2-8786.5" + attribute \src "ls180.v:8781.2-8783.5" switch \builder_csrbank0_scratch0_re - attribute \src "ls180.v:8784.6-8784.34" + attribute \src "ls180.v:8781.6-8781.34" case 1'1 assign $0\main_libresocsim_scratch_storage[31:0] [7:0] \builder_csrbank0_scratch0_r case end - attribute \src "ls180.v:8789.2-8810.5" + attribute \src "ls180.v:8786.2-8807.5" switch \builder_csrbank1_sel - attribute \src "ls180.v:8789.6-8789.26" + attribute \src "ls180.v:8786.6-8786.26" case 1'1 - attribute \src "ls180.v:8790.3-8809.10" + attribute \src "ls180.v:8787.3-8806.10" switch \builder_interface1_bank_bus_adr [2:0] attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -125467,39 +125418,39 @@ module \ls180 end case end - attribute \src "ls180.v:8811.2-8813.5" + attribute \src "ls180.v:8808.2-8810.5" switch \builder_csrbank1_oe1_re - attribute \src "ls180.v:8811.6-8811.29" + attribute \src "ls180.v:8808.6-8808.29" case 1'1 assign $0\main_gpio_oe_storage[15:0] [15:8] \builder_csrbank1_oe1_r case end - attribute \src "ls180.v:8814.2-8816.5" + attribute \src "ls180.v:8811.2-8813.5" switch \builder_csrbank1_oe0_re - attribute \src "ls180.v:8814.6-8814.29" + attribute \src "ls180.v:8811.6-8811.29" case 1'1 assign $0\main_gpio_oe_storage[15:0] [7:0] \builder_csrbank1_oe0_r case end - attribute \src "ls180.v:8818.2-8820.5" + attribute \src "ls180.v:8815.2-8817.5" switch \builder_csrbank1_out1_re - attribute \src "ls180.v:8818.6-8818.30" + attribute \src "ls180.v:8815.6-8815.30" case 1'1 assign $0\main_gpio_out_storage[15:0] [15:8] \builder_csrbank1_out1_r case end - attribute \src "ls180.v:8821.2-8823.5" + attribute \src "ls180.v:8818.2-8820.5" switch \builder_csrbank1_out0_re - attribute \src "ls180.v:8821.6-8821.30" + attribute \src "ls180.v:8818.6-8818.30" case 1'1 assign $0\main_gpio_out_storage[15:0] [7:0] \builder_csrbank1_out0_r case end - attribute \src "ls180.v:8826.2-8856.5" + attribute \src "ls180.v:8823.2-8853.5" switch \builder_csrbank2_sel - attribute \src "ls180.v:8826.6-8826.26" + attribute \src "ls180.v:8823.6-8823.26" case 1'1 - attribute \src "ls180.v:8827.3-8855.10" + attribute \src "ls180.v:8824.3-8852.10" switch \builder_interface2_bank_bus_adr [3:0] attribute \src "ls180.v:0.0-0.0" case 4'0000 @@ -125532,74 +125483,74 @@ module \ls180 end case end - attribute \src "ls180.v:8857.2-8859.5" + attribute \src "ls180.v:8854.2-8856.5" switch \builder_csrbank2_enable0_re - attribute \src "ls180.v:8857.6-8857.33" + attribute \src "ls180.v:8854.6-8854.33" case 1'1 assign $0\main_pwm0_enable_storage[0:0] \builder_csrbank2_enable0_r case end - attribute \src "ls180.v:8861.2-8863.5" + attribute \src "ls180.v:8858.2-8860.5" switch \builder_csrbank2_width3_re - attribute \src "ls180.v:8861.6-8861.32" + attribute \src "ls180.v:8858.6-8858.32" case 1'1 assign $0\main_pwm0_width_storage[31:0] [31:24] \builder_csrbank2_width3_r case end - attribute \src "ls180.v:8864.2-8866.5" + attribute \src "ls180.v:8861.2-8863.5" switch \builder_csrbank2_width2_re - attribute \src "ls180.v:8864.6-8864.32" + attribute \src "ls180.v:8861.6-8861.32" case 1'1 assign $0\main_pwm0_width_storage[31:0] [23:16] \builder_csrbank2_width2_r case end - attribute \src "ls180.v:8867.2-8869.5" + attribute \src "ls180.v:8864.2-8866.5" switch \builder_csrbank2_width1_re - attribute \src "ls180.v:8867.6-8867.32" + attribute \src "ls180.v:8864.6-8864.32" case 1'1 assign $0\main_pwm0_width_storage[31:0] [15:8] \builder_csrbank2_width1_r case end - attribute \src "ls180.v:8870.2-8872.5" + attribute \src "ls180.v:8867.2-8869.5" switch \builder_csrbank2_width0_re - attribute \src "ls180.v:8870.6-8870.32" + attribute \src "ls180.v:8867.6-8867.32" case 1'1 assign $0\main_pwm0_width_storage[31:0] [7:0] \builder_csrbank2_width0_r case end - attribute \src "ls180.v:8874.2-8876.5" + attribute \src "ls180.v:8871.2-8873.5" switch \builder_csrbank2_period3_re - attribute \src "ls180.v:8874.6-8874.33" + attribute \src "ls180.v:8871.6-8871.33" case 1'1 assign $0\main_pwm0_period_storage[31:0] [31:24] \builder_csrbank2_period3_r case end - attribute \src "ls180.v:8877.2-8879.5" + attribute \src "ls180.v:8874.2-8876.5" switch \builder_csrbank2_period2_re - attribute \src "ls180.v:8877.6-8877.33" + attribute \src "ls180.v:8874.6-8874.33" case 1'1 assign $0\main_pwm0_period_storage[31:0] [23:16] \builder_csrbank2_period2_r case end - attribute \src "ls180.v:8880.2-8882.5" + attribute \src "ls180.v:8877.2-8879.5" switch \builder_csrbank2_period1_re - attribute \src "ls180.v:8880.6-8880.33" + attribute \src "ls180.v:8877.6-8877.33" case 1'1 assign $0\main_pwm0_period_storage[31:0] [15:8] \builder_csrbank2_period1_r case end - attribute \src "ls180.v:8883.2-8885.5" + attribute \src "ls180.v:8880.2-8882.5" switch \builder_csrbank2_period0_re - attribute \src "ls180.v:8883.6-8883.33" + attribute \src "ls180.v:8880.6-8880.33" case 1'1 assign $0\main_pwm0_period_storage[31:0] [7:0] \builder_csrbank2_period0_r case end - attribute \src "ls180.v:8888.2-8918.5" + attribute \src "ls180.v:8885.2-8915.5" switch \builder_csrbank3_sel - attribute \src "ls180.v:8888.6-8888.26" + attribute \src "ls180.v:8885.6-8885.26" case 1'1 - attribute \src "ls180.v:8889.3-8917.10" + attribute \src "ls180.v:8886.3-8914.10" switch \builder_interface3_bank_bus_adr [3:0] attribute \src "ls180.v:0.0-0.0" case 4'0000 @@ -125632,74 +125583,74 @@ module \ls180 end case end - attribute \src "ls180.v:8919.2-8921.5" + attribute \src "ls180.v:8916.2-8918.5" switch \builder_csrbank3_enable0_re - attribute \src "ls180.v:8919.6-8919.33" + attribute \src "ls180.v:8916.6-8916.33" case 1'1 assign $0\main_pwm1_enable_storage[0:0] \builder_csrbank3_enable0_r case end - attribute \src "ls180.v:8923.2-8925.5" + attribute \src "ls180.v:8920.2-8922.5" switch \builder_csrbank3_width3_re - attribute \src "ls180.v:8923.6-8923.32" + attribute \src "ls180.v:8920.6-8920.32" case 1'1 assign $0\main_pwm1_width_storage[31:0] [31:24] \builder_csrbank3_width3_r case end - attribute \src "ls180.v:8926.2-8928.5" + attribute \src "ls180.v:8923.2-8925.5" switch \builder_csrbank3_width2_re - attribute \src "ls180.v:8926.6-8926.32" + attribute \src "ls180.v:8923.6-8923.32" case 1'1 assign $0\main_pwm1_width_storage[31:0] [23:16] \builder_csrbank3_width2_r case end - attribute \src "ls180.v:8929.2-8931.5" + attribute \src "ls180.v:8926.2-8928.5" switch \builder_csrbank3_width1_re - attribute \src "ls180.v:8929.6-8929.32" + attribute \src "ls180.v:8926.6-8926.32" case 1'1 assign $0\main_pwm1_width_storage[31:0] [15:8] \builder_csrbank3_width1_r case end - attribute \src "ls180.v:8932.2-8934.5" + attribute \src "ls180.v:8929.2-8931.5" switch \builder_csrbank3_width0_re - attribute \src "ls180.v:8932.6-8932.32" + attribute \src "ls180.v:8929.6-8929.32" case 1'1 assign $0\main_pwm1_width_storage[31:0] [7:0] \builder_csrbank3_width0_r case end - attribute \src "ls180.v:8936.2-8938.5" + attribute \src "ls180.v:8933.2-8935.5" switch \builder_csrbank3_period3_re - attribute \src "ls180.v:8936.6-8936.33" + attribute \src "ls180.v:8933.6-8933.33" case 1'1 assign $0\main_pwm1_period_storage[31:0] [31:24] \builder_csrbank3_period3_r case end - attribute \src "ls180.v:8939.2-8941.5" + attribute \src "ls180.v:8936.2-8938.5" switch \builder_csrbank3_period2_re - attribute \src "ls180.v:8939.6-8939.33" + attribute \src "ls180.v:8936.6-8936.33" case 1'1 assign $0\main_pwm1_period_storage[31:0] [23:16] \builder_csrbank3_period2_r case end - attribute \src "ls180.v:8942.2-8944.5" + attribute \src "ls180.v:8939.2-8941.5" switch \builder_csrbank3_period1_re - attribute \src "ls180.v:8942.6-8942.33" + attribute \src "ls180.v:8939.6-8939.33" case 1'1 assign $0\main_pwm1_period_storage[31:0] [15:8] \builder_csrbank3_period1_r case end - attribute \src "ls180.v:8945.2-8947.5" + attribute \src "ls180.v:8942.2-8944.5" switch \builder_csrbank3_period0_re - attribute \src "ls180.v:8945.6-8945.33" + attribute \src "ls180.v:8942.6-8942.33" case 1'1 assign $0\main_pwm1_period_storage[31:0] [7:0] \builder_csrbank3_period0_r case end - attribute \src "ls180.v:8950.2-8998.5" + attribute \src "ls180.v:8947.2-8995.5" switch \builder_csrbank4_sel - attribute \src "ls180.v:8950.6-8950.26" + attribute \src "ls180.v:8947.6-8947.26" case 1'1 - attribute \src "ls180.v:8951.3-8997.10" + attribute \src "ls180.v:8948.3-8994.10" switch \builder_interface4_bank_bus_adr [3:0] attribute \src "ls180.v:0.0-0.0" case 4'0000 @@ -125750,109 +125701,109 @@ module \ls180 end case end - attribute \src "ls180.v:8999.2-9001.5" + attribute \src "ls180.v:8996.2-8998.5" switch \builder_csrbank4_dma_base7_re - attribute \src "ls180.v:8999.6-8999.35" + attribute \src "ls180.v:8996.6-8996.35" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [63:56] \builder_csrbank4_dma_base7_r case end - attribute \src "ls180.v:9002.2-9004.5" + attribute \src "ls180.v:8999.2-9001.5" switch \builder_csrbank4_dma_base6_re - attribute \src "ls180.v:9002.6-9002.35" + attribute \src "ls180.v:8999.6-8999.35" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [55:48] \builder_csrbank4_dma_base6_r case end - attribute \src "ls180.v:9005.2-9007.5" + attribute \src "ls180.v:9002.2-9004.5" switch \builder_csrbank4_dma_base5_re - attribute \src "ls180.v:9005.6-9005.35" + attribute \src "ls180.v:9002.6-9002.35" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [47:40] \builder_csrbank4_dma_base5_r case end - attribute \src "ls180.v:9008.2-9010.5" + attribute \src "ls180.v:9005.2-9007.5" switch \builder_csrbank4_dma_base4_re - attribute \src "ls180.v:9008.6-9008.35" + attribute \src "ls180.v:9005.6-9005.35" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [39:32] \builder_csrbank4_dma_base4_r case end - attribute \src "ls180.v:9011.2-9013.5" + attribute \src "ls180.v:9008.2-9010.5" switch \builder_csrbank4_dma_base3_re - attribute \src "ls180.v:9011.6-9011.35" + attribute \src "ls180.v:9008.6-9008.35" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [31:24] \builder_csrbank4_dma_base3_r case end - attribute \src "ls180.v:9014.2-9016.5" + attribute \src "ls180.v:9011.2-9013.5" switch \builder_csrbank4_dma_base2_re - attribute \src "ls180.v:9014.6-9014.35" + attribute \src "ls180.v:9011.6-9011.35" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [23:16] \builder_csrbank4_dma_base2_r case end - attribute \src "ls180.v:9017.2-9019.5" + attribute \src "ls180.v:9014.2-9016.5" switch \builder_csrbank4_dma_base1_re - attribute \src "ls180.v:9017.6-9017.35" + attribute \src "ls180.v:9014.6-9014.35" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [15:8] \builder_csrbank4_dma_base1_r case end - attribute \src "ls180.v:9020.2-9022.5" + attribute \src "ls180.v:9017.2-9019.5" switch \builder_csrbank4_dma_base0_re - attribute \src "ls180.v:9020.6-9020.35" + attribute \src "ls180.v:9017.6-9017.35" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [7:0] \builder_csrbank4_dma_base0_r case end - attribute \src "ls180.v:9024.2-9026.5" + attribute \src "ls180.v:9021.2-9023.5" switch \builder_csrbank4_dma_length3_re - attribute \src "ls180.v:9024.6-9024.37" + attribute \src "ls180.v:9021.6-9021.37" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [31:24] \builder_csrbank4_dma_length3_r case end - attribute \src "ls180.v:9027.2-9029.5" + attribute \src "ls180.v:9024.2-9026.5" switch \builder_csrbank4_dma_length2_re - attribute \src "ls180.v:9027.6-9027.37" + attribute \src "ls180.v:9024.6-9024.37" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [23:16] \builder_csrbank4_dma_length2_r case end - attribute \src "ls180.v:9030.2-9032.5" + attribute \src "ls180.v:9027.2-9029.5" switch \builder_csrbank4_dma_length1_re - attribute \src "ls180.v:9030.6-9030.37" + attribute \src "ls180.v:9027.6-9027.37" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [15:8] \builder_csrbank4_dma_length1_r case end - attribute \src "ls180.v:9033.2-9035.5" + attribute \src "ls180.v:9030.2-9032.5" switch \builder_csrbank4_dma_length0_re - attribute \src "ls180.v:9033.6-9033.37" + attribute \src "ls180.v:9030.6-9030.37" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [7:0] \builder_csrbank4_dma_length0_r case end - attribute \src "ls180.v:9037.2-9039.5" + attribute \src "ls180.v:9034.2-9036.5" switch \builder_csrbank4_dma_enable0_re - attribute \src "ls180.v:9037.6-9037.37" + attribute \src "ls180.v:9034.6-9034.37" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] \builder_csrbank4_dma_enable0_r case end - attribute \src "ls180.v:9041.2-9043.5" + attribute \src "ls180.v:9038.2-9040.5" switch \builder_csrbank4_dma_loop0_re - attribute \src "ls180.v:9041.6-9041.35" + attribute \src "ls180.v:9038.6-9038.35" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] \builder_csrbank4_dma_loop0_r case end - attribute \src "ls180.v:9046.2-9148.5" + attribute \src "ls180.v:9043.2-9145.5" switch \builder_csrbank5_sel - attribute \src "ls180.v:9046.6-9046.26" + attribute \src "ls180.v:9043.6-9043.26" case 1'1 - attribute \src "ls180.v:9047.3-9147.10" + attribute \src "ls180.v:9044.3-9144.10" switch \builder_interface5_bank_bus_adr [5:0] attribute \src "ls180.v:0.0-0.0" case 6'000000 @@ -125957,109 +125908,109 @@ module \ls180 end case end - attribute \src "ls180.v:9149.2-9151.5" + attribute \src "ls180.v:9146.2-9148.5" switch \builder_csrbank5_cmd_argument3_re - attribute \src "ls180.v:9149.6-9149.39" + attribute \src "ls180.v:9146.6-9146.39" case 1'1 assign $0\main_sdcore_cmd_argument_storage[31:0] [31:24] \builder_csrbank5_cmd_argument3_r case end - attribute \src "ls180.v:9152.2-9154.5" + attribute \src "ls180.v:9149.2-9151.5" switch \builder_csrbank5_cmd_argument2_re - attribute \src "ls180.v:9152.6-9152.39" + attribute \src "ls180.v:9149.6-9149.39" case 1'1 assign $0\main_sdcore_cmd_argument_storage[31:0] [23:16] \builder_csrbank5_cmd_argument2_r case end - attribute \src "ls180.v:9155.2-9157.5" + attribute \src "ls180.v:9152.2-9154.5" switch \builder_csrbank5_cmd_argument1_re - attribute \src "ls180.v:9155.6-9155.39" + attribute \src "ls180.v:9152.6-9152.39" case 1'1 assign $0\main_sdcore_cmd_argument_storage[31:0] [15:8] \builder_csrbank5_cmd_argument1_r case end - attribute \src "ls180.v:9158.2-9160.5" + attribute \src "ls180.v:9155.2-9157.5" switch \builder_csrbank5_cmd_argument0_re - attribute \src "ls180.v:9158.6-9158.39" + attribute \src "ls180.v:9155.6-9155.39" case 1'1 assign $0\main_sdcore_cmd_argument_storage[31:0] [7:0] \builder_csrbank5_cmd_argument0_r case end - attribute \src "ls180.v:9162.2-9164.5" + attribute \src "ls180.v:9159.2-9161.5" switch \builder_csrbank5_cmd_command3_re - attribute \src "ls180.v:9162.6-9162.38" + attribute \src "ls180.v:9159.6-9159.38" case 1'1 assign $0\main_sdcore_cmd_command_storage[31:0] [31:24] \builder_csrbank5_cmd_command3_r case end - attribute \src "ls180.v:9165.2-9167.5" + attribute \src "ls180.v:9162.2-9164.5" switch \builder_csrbank5_cmd_command2_re - attribute \src "ls180.v:9165.6-9165.38" + attribute \src "ls180.v:9162.6-9162.38" case 1'1 assign $0\main_sdcore_cmd_command_storage[31:0] [23:16] \builder_csrbank5_cmd_command2_r case end - attribute \src "ls180.v:9168.2-9170.5" + attribute \src "ls180.v:9165.2-9167.5" switch \builder_csrbank5_cmd_command1_re - attribute \src "ls180.v:9168.6-9168.38" + attribute \src "ls180.v:9165.6-9165.38" case 1'1 assign $0\main_sdcore_cmd_command_storage[31:0] [15:8] \builder_csrbank5_cmd_command1_r case end - attribute \src "ls180.v:9171.2-9173.5" + attribute \src "ls180.v:9168.2-9170.5" switch \builder_csrbank5_cmd_command0_re - attribute \src "ls180.v:9171.6-9171.38" + attribute \src "ls180.v:9168.6-9168.38" case 1'1 assign $0\main_sdcore_cmd_command_storage[31:0] [7:0] \builder_csrbank5_cmd_command0_r case end - attribute \src "ls180.v:9175.2-9177.5" + attribute \src "ls180.v:9172.2-9174.5" switch \builder_csrbank5_block_length1_re - attribute \src "ls180.v:9175.6-9175.39" + attribute \src "ls180.v:9172.6-9172.39" case 1'1 assign $0\main_sdcore_block_length_storage[9:0] [9:8] \builder_csrbank5_block_length1_r case end - attribute \src "ls180.v:9178.2-9180.5" + attribute \src "ls180.v:9175.2-9177.5" switch \builder_csrbank5_block_length0_re - attribute \src "ls180.v:9178.6-9178.39" + attribute \src "ls180.v:9175.6-9175.39" case 1'1 assign $0\main_sdcore_block_length_storage[9:0] [7:0] \builder_csrbank5_block_length0_r case end - attribute \src "ls180.v:9182.2-9184.5" + attribute \src "ls180.v:9179.2-9181.5" switch \builder_csrbank5_block_count3_re - attribute \src "ls180.v:9182.6-9182.38" + attribute \src "ls180.v:9179.6-9179.38" case 1'1 assign $0\main_sdcore_block_count_storage[31:0] [31:24] \builder_csrbank5_block_count3_r case end - attribute \src "ls180.v:9185.2-9187.5" + attribute \src "ls180.v:9182.2-9184.5" switch \builder_csrbank5_block_count2_re - attribute \src "ls180.v:9185.6-9185.38" + attribute \src "ls180.v:9182.6-9182.38" case 1'1 assign $0\main_sdcore_block_count_storage[31:0] [23:16] \builder_csrbank5_block_count2_r case end - attribute \src "ls180.v:9188.2-9190.5" + attribute \src "ls180.v:9185.2-9187.5" switch \builder_csrbank5_block_count1_re - attribute \src "ls180.v:9188.6-9188.38" + attribute \src "ls180.v:9185.6-9185.38" case 1'1 assign $0\main_sdcore_block_count_storage[31:0] [15:8] \builder_csrbank5_block_count1_r case end - attribute \src "ls180.v:9191.2-9193.5" + attribute \src "ls180.v:9188.2-9190.5" switch \builder_csrbank5_block_count0_re - attribute \src "ls180.v:9191.6-9191.38" + attribute \src "ls180.v:9188.6-9188.38" case 1'1 assign $0\main_sdcore_block_count_storage[31:0] [7:0] \builder_csrbank5_block_count0_r case end - attribute \src "ls180.v:9196.2-9256.5" + attribute \src "ls180.v:9193.2-9253.5" switch \builder_csrbank6_sel - attribute \src "ls180.v:9196.6-9196.26" + attribute \src "ls180.v:9193.6-9193.26" case 1'1 - attribute \src "ls180.v:9197.3-9255.10" + attribute \src "ls180.v:9194.3-9252.10" switch \builder_interface6_bank_bus_adr [4:0] attribute \src "ls180.v:0.0-0.0" case 5'00000 @@ -126122,109 +126073,109 @@ module \ls180 end case end - attribute \src "ls180.v:9257.2-9259.5" + attribute \src "ls180.v:9254.2-9256.5" switch \builder_csrbank6_dma_base7_re - attribute \src "ls180.v:9257.6-9257.35" + attribute \src "ls180.v:9254.6-9254.35" case 1'1 assign $0\main_sdmem2block_dma_base_storage[63:0] [63:56] \builder_csrbank6_dma_base7_r case end - attribute \src "ls180.v:9260.2-9262.5" + attribute \src "ls180.v:9257.2-9259.5" switch \builder_csrbank6_dma_base6_re - attribute \src "ls180.v:9260.6-9260.35" + attribute \src "ls180.v:9257.6-9257.35" case 1'1 assign $0\main_sdmem2block_dma_base_storage[63:0] [55:48] \builder_csrbank6_dma_base6_r case end - attribute \src "ls180.v:9263.2-9265.5" + attribute \src "ls180.v:9260.2-9262.5" switch \builder_csrbank6_dma_base5_re - attribute \src "ls180.v:9263.6-9263.35" + attribute \src "ls180.v:9260.6-9260.35" case 1'1 assign $0\main_sdmem2block_dma_base_storage[63:0] [47:40] \builder_csrbank6_dma_base5_r case end - attribute \src "ls180.v:9266.2-9268.5" + attribute \src "ls180.v:9263.2-9265.5" switch \builder_csrbank6_dma_base4_re - attribute \src "ls180.v:9266.6-9266.35" + attribute \src "ls180.v:9263.6-9263.35" case 1'1 assign $0\main_sdmem2block_dma_base_storage[63:0] [39:32] \builder_csrbank6_dma_base4_r case end - attribute \src "ls180.v:9269.2-9271.5" + attribute \src "ls180.v:9266.2-9268.5" switch \builder_csrbank6_dma_base3_re - attribute \src "ls180.v:9269.6-9269.35" + attribute \src "ls180.v:9266.6-9266.35" case 1'1 assign $0\main_sdmem2block_dma_base_storage[63:0] [31:24] \builder_csrbank6_dma_base3_r case end - attribute \src "ls180.v:9272.2-9274.5" + attribute \src "ls180.v:9269.2-9271.5" switch \builder_csrbank6_dma_base2_re - attribute \src "ls180.v:9272.6-9272.35" + attribute \src "ls180.v:9269.6-9269.35" case 1'1 assign $0\main_sdmem2block_dma_base_storage[63:0] [23:16] \builder_csrbank6_dma_base2_r case end - attribute \src "ls180.v:9275.2-9277.5" + attribute \src "ls180.v:9272.2-9274.5" switch \builder_csrbank6_dma_base1_re - attribute \src "ls180.v:9275.6-9275.35" + attribute \src "ls180.v:9272.6-9272.35" case 1'1 assign $0\main_sdmem2block_dma_base_storage[63:0] [15:8] \builder_csrbank6_dma_base1_r case end - attribute \src "ls180.v:9278.2-9280.5" + attribute \src "ls180.v:9275.2-9277.5" switch \builder_csrbank6_dma_base0_re - attribute \src "ls180.v:9278.6-9278.35" + attribute \src "ls180.v:9275.6-9275.35" case 1'1 assign $0\main_sdmem2block_dma_base_storage[63:0] [7:0] \builder_csrbank6_dma_base0_r case end - attribute \src "ls180.v:9282.2-9284.5" + attribute \src "ls180.v:9279.2-9281.5" switch \builder_csrbank6_dma_length3_re - attribute \src "ls180.v:9282.6-9282.37" + attribute \src "ls180.v:9279.6-9279.37" case 1'1 assign $0\main_sdmem2block_dma_length_storage[31:0] [31:24] \builder_csrbank6_dma_length3_r case end - attribute \src "ls180.v:9285.2-9287.5" + attribute \src "ls180.v:9282.2-9284.5" switch \builder_csrbank6_dma_length2_re - attribute \src "ls180.v:9285.6-9285.37" + attribute \src "ls180.v:9282.6-9282.37" case 1'1 assign $0\main_sdmem2block_dma_length_storage[31:0] [23:16] \builder_csrbank6_dma_length2_r case end - attribute \src "ls180.v:9288.2-9290.5" + attribute \src "ls180.v:9285.2-9287.5" switch \builder_csrbank6_dma_length1_re - attribute \src "ls180.v:9288.6-9288.37" + attribute \src "ls180.v:9285.6-9285.37" case 1'1 assign $0\main_sdmem2block_dma_length_storage[31:0] [15:8] \builder_csrbank6_dma_length1_r case end - attribute \src "ls180.v:9291.2-9293.5" + attribute \src "ls180.v:9288.2-9290.5" switch \builder_csrbank6_dma_length0_re - attribute \src "ls180.v:9291.6-9291.37" + attribute \src "ls180.v:9288.6-9288.37" case 1'1 assign $0\main_sdmem2block_dma_length_storage[31:0] [7:0] \builder_csrbank6_dma_length0_r case end - attribute \src "ls180.v:9295.2-9297.5" + attribute \src "ls180.v:9292.2-9294.5" switch \builder_csrbank6_dma_enable0_re - attribute \src "ls180.v:9295.6-9295.37" + attribute \src "ls180.v:9292.6-9292.37" case 1'1 assign $0\main_sdmem2block_dma_enable_storage[0:0] \builder_csrbank6_dma_enable0_r case end - attribute \src "ls180.v:9299.2-9301.5" + attribute \src "ls180.v:9296.2-9298.5" switch \builder_csrbank6_dma_loop0_re - attribute \src "ls180.v:9299.6-9299.35" + attribute \src "ls180.v:9296.6-9296.35" case 1'1 assign $0\main_sdmem2block_dma_loop_storage[0:0] \builder_csrbank6_dma_loop0_r case end - attribute \src "ls180.v:9304.2-9319.5" + attribute \src "ls180.v:9301.2-9316.5" switch \builder_csrbank7_sel - attribute \src "ls180.v:9304.6-9304.26" + attribute \src "ls180.v:9301.6-9301.26" case 1'1 - attribute \src "ls180.v:9305.3-9318.10" + attribute \src "ls180.v:9302.3-9315.10" switch \builder_interface7_bank_bus_adr [1:0] attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -126242,25 +126193,25 @@ module \ls180 end case end - attribute \src "ls180.v:9320.2-9322.5" + attribute \src "ls180.v:9317.2-9319.5" switch \builder_csrbank7_clocker_divider1_re - attribute \src "ls180.v:9320.6-9320.42" + attribute \src "ls180.v:9317.6-9317.42" case 1'1 assign $0\main_sdphy_clocker_storage[8:0] [8] \builder_csrbank7_clocker_divider1_r case end - attribute \src "ls180.v:9323.2-9325.5" + attribute \src "ls180.v:9320.2-9322.5" switch \builder_csrbank7_clocker_divider0_re - attribute \src "ls180.v:9323.6-9323.42" + attribute \src "ls180.v:9320.6-9320.42" case 1'1 assign $0\main_sdphy_clocker_storage[8:0] [7:0] \builder_csrbank7_clocker_divider0_r case end - attribute \src "ls180.v:9328.2-9361.5" + attribute \src "ls180.v:9325.2-9358.5" switch \builder_csrbank8_sel - attribute \src "ls180.v:9328.6-9328.26" + attribute \src "ls180.v:9325.6-9325.26" case 1'1 - attribute \src "ls180.v:9329.3-9360.10" + attribute \src "ls180.v:9326.3-9357.10" switch \builder_interface8_bank_bus_adr [3:0] attribute \src "ls180.v:0.0-0.0" case 4'0000 @@ -126296,60 +126247,60 @@ module \ls180 end case end - attribute \src "ls180.v:9362.2-9364.5" + attribute \src "ls180.v:9359.2-9361.5" switch \builder_csrbank8_dfii_control0_re - attribute \src "ls180.v:9362.6-9362.39" + attribute \src "ls180.v:9359.6-9359.39" case 1'1 assign $0\main_sdram_storage[3:0] \builder_csrbank8_dfii_control0_r case end - attribute \src "ls180.v:9366.2-9368.5" + attribute \src "ls180.v:9363.2-9365.5" switch \builder_csrbank8_dfii_pi0_command0_re - attribute \src "ls180.v:9366.6-9366.43" + attribute \src "ls180.v:9363.6-9363.43" case 1'1 assign $0\main_sdram_command_storage[5:0] \builder_csrbank8_dfii_pi0_command0_r case end - attribute \src "ls180.v:9370.2-9372.5" + attribute \src "ls180.v:9367.2-9369.5" switch \builder_csrbank8_dfii_pi0_address1_re - attribute \src "ls180.v:9370.6-9370.43" + attribute \src "ls180.v:9367.6-9367.43" case 1'1 assign $0\main_sdram_address_storage[12:0] [12:8] \builder_csrbank8_dfii_pi0_address1_r case end - attribute \src "ls180.v:9373.2-9375.5" + attribute \src "ls180.v:9370.2-9372.5" switch \builder_csrbank8_dfii_pi0_address0_re - attribute \src "ls180.v:9373.6-9373.43" + attribute \src "ls180.v:9370.6-9370.43" case 1'1 assign $0\main_sdram_address_storage[12:0] [7:0] \builder_csrbank8_dfii_pi0_address0_r case end - attribute \src "ls180.v:9377.2-9379.5" + attribute \src "ls180.v:9374.2-9376.5" switch \builder_csrbank8_dfii_pi0_baddress0_re - attribute \src "ls180.v:9377.6-9377.44" + attribute \src "ls180.v:9374.6-9374.44" case 1'1 assign $0\main_sdram_baddress_storage[1:0] \builder_csrbank8_dfii_pi0_baddress0_r case end - attribute \src "ls180.v:9381.2-9383.5" + attribute \src "ls180.v:9378.2-9380.5" switch \builder_csrbank8_dfii_pi0_wrdata1_re - attribute \src "ls180.v:9381.6-9381.42" + attribute \src "ls180.v:9378.6-9378.42" case 1'1 assign $0\main_sdram_wrdata_storage[15:0] [15:8] \builder_csrbank8_dfii_pi0_wrdata1_r case end - attribute \src "ls180.v:9384.2-9386.5" + attribute \src "ls180.v:9381.2-9383.5" switch \builder_csrbank8_dfii_pi0_wrdata0_re - attribute \src "ls180.v:9384.6-9384.42" + attribute \src "ls180.v:9381.6-9381.42" case 1'1 assign $0\main_sdram_wrdata_storage[15:0] [7:0] \builder_csrbank8_dfii_pi0_wrdata0_r case end - attribute \src "ls180.v:9389.2-9413.5" + attribute \src "ls180.v:9386.2-9410.5" switch \builder_csrbank9_sel - attribute \src "ls180.v:9389.6-9389.26" + attribute \src "ls180.v:9386.6-9386.26" case 1'1 - attribute \src "ls180.v:9390.3-9412.10" + attribute \src "ls180.v:9387.3-9409.10" switch \builder_interface9_bank_bus_adr [2:0] attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -126376,46 +126327,46 @@ module \ls180 end case end - attribute \src "ls180.v:9414.2-9416.5" + attribute \src "ls180.v:9411.2-9413.5" switch \builder_csrbank9_control1_re - attribute \src "ls180.v:9414.6-9414.34" + attribute \src "ls180.v:9411.6-9411.34" case 1'1 assign $0\main_spi_master_control_storage[15:0] [15:8] \builder_csrbank9_control1_r case end - attribute \src "ls180.v:9417.2-9419.5" + attribute \src "ls180.v:9414.2-9416.5" switch \builder_csrbank9_control0_re - attribute \src "ls180.v:9417.6-9417.34" + attribute \src "ls180.v:9414.6-9414.34" case 1'1 assign $0\main_spi_master_control_storage[15:0] [7:0] \builder_csrbank9_control0_r case end - attribute \src "ls180.v:9421.2-9423.5" + attribute \src "ls180.v:9418.2-9420.5" switch \builder_csrbank9_mosi0_re - attribute \src "ls180.v:9421.6-9421.31" + attribute \src "ls180.v:9418.6-9418.31" case 1'1 assign $0\main_spi_master_mosi_storage[7:0] \builder_csrbank9_mosi0_r case end - attribute \src "ls180.v:9425.2-9427.5" + attribute \src "ls180.v:9422.2-9424.5" switch \builder_csrbank9_cs0_re - attribute \src "ls180.v:9425.6-9425.29" + attribute \src "ls180.v:9422.6-9422.29" case 1'1 assign $0\main_spi_master_cs_storage[0:0] \builder_csrbank9_cs0_r case end - attribute \src "ls180.v:9429.2-9431.5" + attribute \src "ls180.v:9426.2-9428.5" switch \builder_csrbank9_loopback0_re - attribute \src "ls180.v:9429.6-9429.35" + attribute \src "ls180.v:9426.6-9426.35" case 1'1 assign $0\main_spi_master_loopback_storage[0:0] \builder_csrbank9_loopback0_r case end - attribute \src "ls180.v:9434.2-9464.5" + attribute \src "ls180.v:9431.2-9461.5" switch \builder_csrbank10_sel - attribute \src "ls180.v:9434.6-9434.27" + attribute \src "ls180.v:9431.6-9431.27" case 1'1 - attribute \src "ls180.v:9435.3-9463.10" + attribute \src "ls180.v:9432.3-9460.10" switch \builder_interface10_bank_bus_adr [3:0] attribute \src "ls180.v:0.0-0.0" case 4'0000 @@ -126448,60 +126399,60 @@ module \ls180 end case end - attribute \src "ls180.v:9465.2-9467.5" + attribute \src "ls180.v:9462.2-9464.5" switch \builder_csrbank10_control1_re - attribute \src "ls180.v:9465.6-9465.35" + attribute \src "ls180.v:9462.6-9462.35" case 1'1 assign $0\libresocsim_control_storage[15:0] [15:8] \builder_csrbank10_control1_r case end - attribute \src "ls180.v:9468.2-9470.5" + attribute \src "ls180.v:9465.2-9467.5" switch \builder_csrbank10_control0_re - attribute \src "ls180.v:9468.6-9468.35" + attribute \src "ls180.v:9465.6-9465.35" case 1'1 assign $0\libresocsim_control_storage[15:0] [7:0] \builder_csrbank10_control0_r case end - attribute \src "ls180.v:9472.2-9474.5" + attribute \src "ls180.v:9469.2-9471.5" switch \builder_csrbank10_mosi0_re - attribute \src "ls180.v:9472.6-9472.32" + attribute \src "ls180.v:9469.6-9469.32" case 1'1 assign $0\libresocsim_mosi_storage[7:0] \builder_csrbank10_mosi0_r case end - attribute \src "ls180.v:9476.2-9478.5" + attribute \src "ls180.v:9473.2-9475.5" switch \builder_csrbank10_cs0_re - attribute \src "ls180.v:9476.6-9476.30" + attribute \src "ls180.v:9473.6-9473.30" case 1'1 assign $0\libresocsim_cs_storage[0:0] \builder_csrbank10_cs0_r case end - attribute \src "ls180.v:9480.2-9482.5" + attribute \src "ls180.v:9477.2-9479.5" switch \builder_csrbank10_loopback0_re - attribute \src "ls180.v:9480.6-9480.36" + attribute \src "ls180.v:9477.6-9477.36" case 1'1 assign $0\libresocsim_loopback_storage[0:0] \builder_csrbank10_loopback0_r case end - attribute \src "ls180.v:9484.2-9486.5" + attribute \src "ls180.v:9481.2-9483.5" switch \builder_csrbank10_clk_divider1_re - attribute \src "ls180.v:9484.6-9484.39" + attribute \src "ls180.v:9481.6-9481.39" case 1'1 assign $0\libresocsim_storage[15:0] [15:8] \builder_csrbank10_clk_divider1_r case end - attribute \src "ls180.v:9487.2-9489.5" + attribute \src "ls180.v:9484.2-9486.5" switch \builder_csrbank10_clk_divider0_re - attribute \src "ls180.v:9487.6-9487.39" + attribute \src "ls180.v:9484.6-9484.39" case 1'1 assign $0\libresocsim_storage[15:0] [7:0] \builder_csrbank10_clk_divider0_r case end - attribute \src "ls180.v:9492.2-9546.5" + attribute \src "ls180.v:9489.2-9543.5" switch \builder_csrbank11_sel - attribute \src "ls180.v:9492.6-9492.27" + attribute \src "ls180.v:9489.6-9489.27" case 1'1 - attribute \src "ls180.v:9493.3-9545.10" + attribute \src "ls180.v:9490.3-9542.10" switch \builder_interface11_bank_bus_adr [4:0] attribute \src "ls180.v:0.0-0.0" case 5'00000 @@ -126558,88 +126509,88 @@ module \ls180 end case end - attribute \src "ls180.v:9547.2-9549.5" + attribute \src "ls180.v:9544.2-9546.5" switch \builder_csrbank11_load3_re - attribute \src "ls180.v:9547.6-9547.32" + attribute \src "ls180.v:9544.6-9544.32" case 1'1 assign $0\main_libresocsim_load_storage[31:0] [31:24] \builder_csrbank11_load3_r case end - attribute \src "ls180.v:9550.2-9552.5" + attribute \src "ls180.v:9547.2-9549.5" switch \builder_csrbank11_load2_re - attribute \src "ls180.v:9550.6-9550.32" + attribute \src "ls180.v:9547.6-9547.32" case 1'1 assign $0\main_libresocsim_load_storage[31:0] [23:16] \builder_csrbank11_load2_r case end - attribute \src "ls180.v:9553.2-9555.5" + attribute \src "ls180.v:9550.2-9552.5" switch \builder_csrbank11_load1_re - attribute \src "ls180.v:9553.6-9553.32" + attribute \src "ls180.v:9550.6-9550.32" case 1'1 assign $0\main_libresocsim_load_storage[31:0] [15:8] \builder_csrbank11_load1_r case end - attribute \src "ls180.v:9556.2-9558.5" + attribute \src "ls180.v:9553.2-9555.5" switch \builder_csrbank11_load0_re - attribute \src "ls180.v:9556.6-9556.32" + attribute \src "ls180.v:9553.6-9553.32" case 1'1 assign $0\main_libresocsim_load_storage[31:0] [7:0] \builder_csrbank11_load0_r case end - attribute \src "ls180.v:9560.2-9562.5" + attribute \src "ls180.v:9557.2-9559.5" switch \builder_csrbank11_reload3_re - attribute \src "ls180.v:9560.6-9560.34" + attribute \src "ls180.v:9557.6-9557.34" case 1'1 assign $0\main_libresocsim_reload_storage[31:0] [31:24] \builder_csrbank11_reload3_r case end - attribute \src "ls180.v:9563.2-9565.5" + attribute \src "ls180.v:9560.2-9562.5" switch \builder_csrbank11_reload2_re - attribute \src "ls180.v:9563.6-9563.34" + attribute \src "ls180.v:9560.6-9560.34" case 1'1 assign $0\main_libresocsim_reload_storage[31:0] [23:16] \builder_csrbank11_reload2_r case end - attribute \src "ls180.v:9566.2-9568.5" + attribute \src "ls180.v:9563.2-9565.5" switch \builder_csrbank11_reload1_re - attribute \src "ls180.v:9566.6-9566.34" + attribute \src "ls180.v:9563.6-9563.34" case 1'1 assign $0\main_libresocsim_reload_storage[31:0] [15:8] \builder_csrbank11_reload1_r case end - attribute \src "ls180.v:9569.2-9571.5" + attribute \src "ls180.v:9566.2-9568.5" switch \builder_csrbank11_reload0_re - attribute \src "ls180.v:9569.6-9569.34" + attribute \src "ls180.v:9566.6-9566.34" case 1'1 assign $0\main_libresocsim_reload_storage[31:0] [7:0] \builder_csrbank11_reload0_r case end - attribute \src "ls180.v:9573.2-9575.5" + attribute \src "ls180.v:9570.2-9572.5" switch \builder_csrbank11_en0_re - attribute \src "ls180.v:9573.6-9573.30" + attribute \src "ls180.v:9570.6-9570.30" case 1'1 assign $0\main_libresocsim_en_storage[0:0] \builder_csrbank11_en0_r case end - attribute \src "ls180.v:9577.2-9579.5" + attribute \src "ls180.v:9574.2-9576.5" switch \builder_csrbank11_update_value0_re - attribute \src "ls180.v:9577.6-9577.40" + attribute \src "ls180.v:9574.6-9574.40" case 1'1 assign $0\main_libresocsim_update_value_storage[0:0] \builder_csrbank11_update_value0_r case end - attribute \src "ls180.v:9581.2-9583.5" + attribute \src "ls180.v:9578.2-9580.5" switch \builder_csrbank11_ev_enable0_re - attribute \src "ls180.v:9581.6-9581.37" + attribute \src "ls180.v:9578.6-9578.37" case 1'1 assign $0\main_libresocsim_eventmanager_storage[0:0] \builder_csrbank11_ev_enable0_r case end - attribute \src "ls180.v:9586.2-9613.5" + attribute \src "ls180.v:9583.2-9610.5" switch \builder_csrbank12_sel - attribute \src "ls180.v:9586.6-9586.27" + attribute \src "ls180.v:9583.6-9583.27" case 1'1 - attribute \src "ls180.v:9587.3-9612.10" + attribute \src "ls180.v:9584.3-9609.10" switch \builder_interface12_bank_bus_adr [2:0] attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -126669,18 +126620,18 @@ module \ls180 end case end - attribute \src "ls180.v:9614.2-9616.5" + attribute \src "ls180.v:9611.2-9613.5" switch \builder_csrbank12_ev_enable0_re - attribute \src "ls180.v:9614.6-9614.37" + attribute \src "ls180.v:9611.6-9611.37" case 1'1 assign $0\main_uart_eventmanager_storage[1:0] \builder_csrbank12_ev_enable0_r case end - attribute \src "ls180.v:9619.2-9634.5" + attribute \src "ls180.v:9616.2-9631.5" switch \builder_csrbank13_sel - attribute \src "ls180.v:9619.6-9619.27" + attribute \src "ls180.v:9616.6-9616.27" case 1'1 - attribute \src "ls180.v:9620.3-9633.10" + attribute \src "ls180.v:9617.3-9630.10" switch \builder_interface13_bank_bus_adr [1:0] attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -126698,37 +126649,37 @@ module \ls180 end case end - attribute \src "ls180.v:9635.2-9637.5" + attribute \src "ls180.v:9632.2-9634.5" switch \builder_csrbank13_tuning_word3_re - attribute \src "ls180.v:9635.6-9635.39" + attribute \src "ls180.v:9632.6-9632.39" case 1'1 assign $0\main_storage[31:0] [31:24] \builder_csrbank13_tuning_word3_r case end - attribute \src "ls180.v:9638.2-9640.5" + attribute \src "ls180.v:9635.2-9637.5" switch \builder_csrbank13_tuning_word2_re - attribute \src "ls180.v:9638.6-9638.39" + attribute \src "ls180.v:9635.6-9635.39" case 1'1 assign $0\main_storage[31:0] [23:16] \builder_csrbank13_tuning_word2_r case end - attribute \src "ls180.v:9641.2-9643.5" + attribute \src "ls180.v:9638.2-9640.5" switch \builder_csrbank13_tuning_word1_re - attribute \src "ls180.v:9641.6-9641.39" + attribute \src "ls180.v:9638.6-9638.39" case 1'1 assign $0\main_storage[31:0] [15:8] \builder_csrbank13_tuning_word1_r case end - attribute \src "ls180.v:9644.2-9646.5" + attribute \src "ls180.v:9641.2-9643.5" switch \builder_csrbank13_tuning_word0_re - attribute \src "ls180.v:9644.6-9644.39" + attribute \src "ls180.v:9641.6-9641.39" case 1'1 assign $0\main_storage[31:0] [7:0] \builder_csrbank13_tuning_word0_r case end - attribute \src "ls180.v:9648.2-9942.5" + attribute \src "ls180.v:9645.2-9938.5" switch \sys_rst_1 - attribute \src "ls180.v:9648.6-9648.15" + attribute \src "ls180.v:9645.6-9645.15" case 1'1 assign $0\main_libresocsim_reset_storage[0:0] 1'0 assign $0\main_libresocsim_reset_re[0:0] 1'0 @@ -126754,7 +126705,6 @@ module \ls180 assign $0\main_libresocsim_eventmanager_storage[0:0] 1'0 assign $0\main_libresocsim_eventmanager_re[0:0] 1'0 assign $0\main_libresocsim_value[31:0] 0 - assign $0\sdram_dm[1:0] 2'00 assign $0\main_dfi_p0_rddata_valid[0:0] 1'0 assign $0\main_rddata_en[2:0] 3'000 assign $0\main_sdram_storage[3:0] 4'0001 @@ -126865,7 +126815,7 @@ module \ls180 assign $0\main_spi_master_mosi_data[7:0] 8'00000000 assign $0\main_spi_master_mosi_sel[2:0] 3'000 assign $0\main_spi_master_miso_data[7:0] 8'00000000 - assign $0\main_dummy[42:0] 43'0000000000000000000000000000000000000000000 + assign $0\main_dummy[41:0] 42'000000000000000000000000000000000000000000 assign $0\pwm0[0:0] 1'0 assign $0\main_pwm0_enable_storage[0:0] 1'0 assign $0\main_pwm0_enable_re[0:0] 1'0 @@ -127026,7 +126976,6 @@ module \ls180 case end sync posedge \sys_clk_1 - update \sdram_dm $0\sdram_dm[1:0] update \spi_master_clk $0\spi_master_clk[0:0] update \spi_master_mosi $0\spi_master_mosi[0:0] update \spi_master_cs_n $0\spi_master_cs_n[0:0] @@ -127202,7 +127151,7 @@ module \ls180 update \main_spi_master_mosi_data $0\main_spi_master_mosi_data[7:0] update \main_spi_master_mosi_sel $0\main_spi_master_mosi_sel[2:0] update \main_spi_master_miso_data $0\main_spi_master_miso_data[7:0] - update \main_dummy $0\main_dummy[42:0] + update \main_dummy $0\main_dummy[41:0] update \main_pwm0_counter $0\main_pwm0_counter[31:0] update \main_pwm0_enable_storage $0\main_pwm0_enable_storage[0:0] update \main_pwm0_enable_re $0\main_pwm0_enable_re[0:0] @@ -127438,152 +127387,144 @@ module \ls180 update \builder_multiregimpl16_regs0 $0\builder_multiregimpl16_regs0[0:0] update \builder_multiregimpl16_regs1 $0\builder_multiregimpl16_regs1[0:0] end - attribute \src "ls180.v:736.5-736.49" - process $proc$ls180.v:736$3050 - assign { } { } - assign $1\main_sdram_choose_req_cmd_payload_ras[0:0] 1'0 - sync always - sync init - update \main_sdram_choose_req_cmd_payload_ras $1\main_sdram_choose_req_cmd_payload_ras[0:0] - end - attribute \src "ls180.v:737.5-737.48" - process $proc$ls180.v:737$3051 + attribute \src "ls180.v:736.5-736.48" + process $proc$ls180.v:736$3048 assign { } { } assign $1\main_sdram_choose_req_cmd_payload_we[0:0] 1'0 sync always sync init update \main_sdram_choose_req_cmd_payload_we $1\main_sdram_choose_req_cmd_payload_we[0:0] end - attribute \src "ls180.v:741.11-741.46" - process $proc$ls180.v:741$3052 + attribute \src "ls180.v:740.11-740.46" + process $proc$ls180.v:740$3049 assign { } { } assign $1\main_sdram_choose_req_valids[3:0] 4'0000 sync always sync init update \main_sdram_choose_req_valids $1\main_sdram_choose_req_valids[3:0] end - attribute \src "ls180.v:743.11-743.45" - process $proc$ls180.v:743$3053 + attribute \src "ls180.v:742.11-742.45" + process $proc$ls180.v:742$3050 assign { } { } assign $1\main_sdram_choose_req_grant[1:0] 2'00 sync always sync init update \main_sdram_choose_req_grant $1\main_sdram_choose_req_grant[1:0] end - attribute \src "ls180.v:745.12-745.36" - process $proc$ls180.v:745$3054 + attribute \src "ls180.v:744.12-744.36" + process $proc$ls180.v:744$3051 assign { } { } assign $0\main_sdram_nop_a[12:0] 13'0000000000000 sync always update \main_sdram_nop_a $0\main_sdram_nop_a[12:0] sync init end - attribute \src "ls180.v:746.11-746.35" - process $proc$ls180.v:746$3055 + attribute \src "ls180.v:745.11-745.35" + process $proc$ls180.v:745$3052 assign { } { } assign $0\main_sdram_nop_ba[1:0] 2'00 sync always update \main_sdram_nop_ba $0\main_sdram_nop_ba[1:0] sync init end - attribute \src "ls180.v:747.11-747.40" - process $proc$ls180.v:747$3056 + attribute \src "ls180.v:746.11-746.40" + process $proc$ls180.v:746$3053 assign { } { } assign $1\main_sdram_steerer_sel[1:0] 2'00 sync always sync init update \main_sdram_steerer_sel $1\main_sdram_steerer_sel[1:0] end - attribute \src "ls180.v:748.5-748.31" - process $proc$ls180.v:748$3057 + attribute \src "ls180.v:747.5-747.31" + process $proc$ls180.v:747$3054 assign { } { } assign $0\main_sdram_steerer0[0:0] 1'1 sync always update \main_sdram_steerer0 $0\main_sdram_steerer0[0:0] sync init end - attribute \src "ls180.v:749.5-749.31" - process $proc$ls180.v:749$3058 + attribute \src "ls180.v:748.5-748.31" + process $proc$ls180.v:748$3055 assign { } { } assign $0\main_sdram_steerer1[0:0] 1'1 sync always update \main_sdram_steerer1 $0\main_sdram_steerer1[0:0] sync init end - attribute \src "ls180.v:751.32-751.63" - process $proc$ls180.v:751$3059 + attribute \src "ls180.v:750.32-750.63" + process $proc$ls180.v:750$3056 assign { } { } assign $0\main_sdram_trrdcon_ready[0:0] 1'1 sync always update \main_sdram_trrdcon_ready $0\main_sdram_trrdcon_ready[0:0] sync init end - attribute \src "ls180.v:753.32-753.63" - process $proc$ls180.v:753$3060 + attribute \src "ls180.v:752.32-752.63" + process $proc$ls180.v:752$3057 assign { } { } assign $0\main_sdram_tfawcon_ready[0:0] 1'1 sync always update \main_sdram_tfawcon_ready $0\main_sdram_tfawcon_ready[0:0] sync init end - attribute \src "ls180.v:755.32-755.63" - process $proc$ls180.v:755$3061 + attribute \src "ls180.v:754.32-754.63" + process $proc$ls180.v:754$3058 assign { } { } assign $1\main_sdram_tccdcon_ready[0:0] 1'0 sync always sync init update \main_sdram_tccdcon_ready $1\main_sdram_tccdcon_ready[0:0] end - attribute \src "ls180.v:756.5-756.36" - process $proc$ls180.v:756$3062 + attribute \src "ls180.v:755.5-755.36" + process $proc$ls180.v:755$3059 assign { } { } assign $1\main_sdram_tccdcon_count[0:0] 1'0 sync always sync init update \main_sdram_tccdcon_count $1\main_sdram_tccdcon_count[0:0] end - attribute \src "ls180.v:758.32-758.63" - process $proc$ls180.v:758$3063 + attribute \src "ls180.v:757.32-757.63" + process $proc$ls180.v:757$3060 assign { } { } assign $1\main_sdram_twtrcon_ready[0:0] 1'0 sync always sync init update \main_sdram_twtrcon_ready $1\main_sdram_twtrcon_ready[0:0] end - attribute \src "ls180.v:759.11-759.42" - process $proc$ls180.v:759$3064 + attribute \src "ls180.v:758.11-758.42" + process $proc$ls180.v:758$3061 assign { } { } assign $1\main_sdram_twtrcon_count[2:0] 3'000 sync always sync init update \main_sdram_twtrcon_count $1\main_sdram_twtrcon_count[2:0] end - attribute \src "ls180.v:762.5-762.26" - process $proc$ls180.v:762$3065 + attribute \src "ls180.v:761.5-761.26" + process $proc$ls180.v:761$3062 assign { } { } assign $1\main_sdram_en0[0:0] 1'0 sync always sync init update \main_sdram_en0 $1\main_sdram_en0[0:0] end - attribute \src "ls180.v:764.11-764.34" - process $proc$ls180.v:764$3066 + attribute \src "ls180.v:763.11-763.34" + process $proc$ls180.v:763$3063 assign { } { } assign $1\main_sdram_time0[4:0] 5'00000 sync always sync init update \main_sdram_time0 $1\main_sdram_time0[4:0] end - attribute \src "ls180.v:765.5-765.26" - process $proc$ls180.v:765$3067 + attribute \src "ls180.v:764.5-764.26" + process $proc$ls180.v:764$3064 assign { } { } assign $1\main_sdram_en1[0:0] 1'0 sync always sync init update \main_sdram_en1 $1\main_sdram_en1[0:0] end - attribute \src "ls180.v:767.11-767.34" - process $proc$ls180.v:767$3068 + attribute \src "ls180.v:766.11-766.34" + process $proc$ls180.v:766$3065 assign { } { } assign $1\main_sdram_time1[3:0] 4'0000 sync always @@ -127591,695 +127532,695 @@ module \ls180 update \main_sdram_time1 $1\main_sdram_time1[3:0] end attribute \src "ls180.v:77.5-77.46" - process $proc$ls180.v:77$2775 + process $proc$ls180.v:77$2773 assign { } { } assign $1\main_libresocsim_libresoc_ibus_ack[0:0] 1'0 sync always sync init update \main_libresocsim_libresoc_ibus_ack $1\main_libresocsim_libresoc_ibus_ack[0:0] end - attribute \src "ls180.v:788.5-788.29" - process $proc$ls180.v:788$3069 + attribute \src "ls180.v:787.5-787.29" + process $proc$ls180.v:787$3066 assign { } { } assign $1\main_wb_sdram_ack[0:0] 1'0 sync always sync init update \main_wb_sdram_ack $1\main_wb_sdram_ack[0:0] end - attribute \src "ls180.v:792.5-792.29" - process $proc$ls180.v:792$3070 + attribute \src "ls180.v:791.5-791.29" + process $proc$ls180.v:791$3067 assign { } { } assign $0\main_wb_sdram_err[0:0] 1'0 sync always update \main_wb_sdram_err $0\main_wb_sdram_err[0:0] sync init end - attribute \src "ls180.v:793.12-793.40" - process $proc$ls180.v:793$3071 + attribute \src "ls180.v:792.12-792.40" + process $proc$ls180.v:792$3068 assign { } { } assign $1\main_litedram_wb_adr[29:0] 30'000000000000000000000000000000 sync always sync init update \main_litedram_wb_adr $1\main_litedram_wb_adr[29:0] end - attribute \src "ls180.v:794.12-794.42" - process $proc$ls180.v:794$3072 + attribute \src "ls180.v:793.12-793.42" + process $proc$ls180.v:793$3069 assign { } { } assign $1\main_litedram_wb_dat_w[15:0] 16'0000000000000000 sync always sync init update \main_litedram_wb_dat_w $1\main_litedram_wb_dat_w[15:0] end - attribute \src "ls180.v:796.11-796.38" - process $proc$ls180.v:796$3073 + attribute \src "ls180.v:795.11-795.38" + process $proc$ls180.v:795$3070 assign { } { } assign $1\main_litedram_wb_sel[1:0] 2'00 sync always sync init update \main_litedram_wb_sel $1\main_litedram_wb_sel[1:0] end - attribute \src "ls180.v:797.5-797.32" - process $proc$ls180.v:797$3074 + attribute \src "ls180.v:796.5-796.32" + process $proc$ls180.v:796$3071 assign { } { } assign $1\main_litedram_wb_cyc[0:0] 1'0 sync always sync init update \main_litedram_wb_cyc $1\main_litedram_wb_cyc[0:0] end - attribute \src "ls180.v:798.5-798.32" - process $proc$ls180.v:798$3075 + attribute \src "ls180.v:797.5-797.32" + process $proc$ls180.v:797$3072 assign { } { } assign $1\main_litedram_wb_stb[0:0] 1'0 sync always sync init update \main_litedram_wb_stb $1\main_litedram_wb_stb[0:0] end - attribute \src "ls180.v:800.5-800.31" - process $proc$ls180.v:800$3076 + attribute \src "ls180.v:799.5-799.31" + process $proc$ls180.v:799$3073 assign { } { } assign $1\main_litedram_wb_we[0:0] 1'0 sync always sync init update \main_litedram_wb_we $1\main_litedram_wb_we[0:0] end - attribute \src "ls180.v:801.5-801.31" - process $proc$ls180.v:801$3077 + attribute \src "ls180.v:800.5-800.31" + process $proc$ls180.v:800$3074 assign { } { } assign $1\main_converter_skip[0:0] 1'0 sync always sync init update \main_converter_skip $1\main_converter_skip[0:0] end - attribute \src "ls180.v:802.5-802.34" - process $proc$ls180.v:802$3078 + attribute \src "ls180.v:801.5-801.34" + process $proc$ls180.v:801$3075 assign { } { } assign $1\main_converter_counter[0:0] 1'0 sync always sync init update \main_converter_counter $1\main_converter_counter[0:0] end - attribute \src "ls180.v:804.12-804.40" - process $proc$ls180.v:804$3079 + attribute \src "ls180.v:803.12-803.40" + process $proc$ls180.v:803$3076 assign { } { } assign $1\main_converter_dat_r[31:0] 0 sync always sync init update \main_converter_dat_r $1\main_converter_dat_r[31:0] end - attribute \src "ls180.v:805.5-805.29" - process $proc$ls180.v:805$3080 + attribute \src "ls180.v:804.5-804.29" + process $proc$ls180.v:804$3077 assign { } { } assign $1\main_cmd_consumed[0:0] 1'0 sync always sync init update \main_cmd_consumed $1\main_cmd_consumed[0:0] end - attribute \src "ls180.v:806.5-806.31" - process $proc$ls180.v:806$3081 + attribute \src "ls180.v:805.5-805.31" + process $proc$ls180.v:805$3078 assign { } { } assign $1\main_wdata_consumed[0:0] 1'0 sync always sync init update \main_wdata_consumed $1\main_wdata_consumed[0:0] end - attribute \src "ls180.v:81.5-81.46" - process $proc$ls180.v:81$2776 + attribute \src "ls180.v:809.12-809.38" + process $proc$ls180.v:809$3079 assign { } { } - assign $0\main_libresocsim_libresoc_ibus_err[0:0] 1'0 + assign $1\main_storage[31:0] 9895604 sync always - update \main_libresocsim_libresoc_ibus_err $0\main_libresocsim_libresoc_ibus_err[0:0] sync init + update \main_storage $1\main_storage[31:0] end - attribute \src "ls180.v:810.12-810.38" - process $proc$ls180.v:810$3082 + attribute \src "ls180.v:81.5-81.46" + process $proc$ls180.v:81$2774 assign { } { } - assign $1\main_storage[31:0] 9895604 + assign $0\main_libresocsim_libresoc_ibus_err[0:0] 1'0 sync always + update \main_libresocsim_libresoc_ibus_err $0\main_libresocsim_libresoc_ibus_err[0:0] sync init - update \main_storage $1\main_storage[31:0] end - attribute \src "ls180.v:811.5-811.19" - process $proc$ls180.v:811$3083 + attribute \src "ls180.v:810.5-810.19" + process $proc$ls180.v:810$3080 assign { } { } assign $1\main_re[0:0] 1'0 sync always sync init update \main_re $1\main_re[0:0] end - attribute \src "ls180.v:813.5-813.27" - process $proc$ls180.v:813$3084 + attribute \src "ls180.v:812.5-812.27" + process $proc$ls180.v:812$3081 assign { } { } assign $1\main_sink_ready[0:0] 1'0 sync always sync init update \main_sink_ready $1\main_sink_ready[0:0] end - attribute \src "ls180.v:817.5-817.30" - process $proc$ls180.v:817$3085 + attribute \src "ls180.v:816.5-816.30" + process $proc$ls180.v:816$3082 assign { } { } assign $1\main_uart_clk_txen[0:0] 1'0 sync always sync init update \main_uart_clk_txen $1\main_uart_clk_txen[0:0] end - attribute \src "ls180.v:818.12-818.45" - process $proc$ls180.v:818$3086 + attribute \src "ls180.v:817.12-817.45" + process $proc$ls180.v:817$3083 assign { } { } assign $1\main_phase_accumulator_tx[31:0] 0 sync always sync init update \main_phase_accumulator_tx $1\main_phase_accumulator_tx[31:0] end - attribute \src "ls180.v:819.11-819.29" - process $proc$ls180.v:819$3087 + attribute \src "ls180.v:818.11-818.29" + process $proc$ls180.v:818$3084 assign { } { } assign $1\main_tx_reg[7:0] 8'00000000 sync always sync init update \main_tx_reg $1\main_tx_reg[7:0] end - attribute \src "ls180.v:820.11-820.34" - process $proc$ls180.v:820$3088 + attribute \src "ls180.v:819.11-819.34" + process $proc$ls180.v:819$3085 assign { } { } assign $1\main_tx_bitcount[3:0] 4'0000 sync always sync init update \main_tx_bitcount $1\main_tx_bitcount[3:0] end - attribute \src "ls180.v:821.5-821.24" - process $proc$ls180.v:821$3089 + attribute \src "ls180.v:820.5-820.24" + process $proc$ls180.v:820$3086 assign { } { } assign $1\main_tx_busy[0:0] 1'0 sync always sync init update \main_tx_busy $1\main_tx_busy[0:0] end - attribute \src "ls180.v:822.5-822.29" - process $proc$ls180.v:822$3090 + attribute \src "ls180.v:821.5-821.29" + process $proc$ls180.v:821$3087 assign { } { } assign $1\main_source_valid[0:0] 1'0 sync always sync init update \main_source_valid $1\main_source_valid[0:0] end - attribute \src "ls180.v:824.5-824.29" - process $proc$ls180.v:824$3091 + attribute \src "ls180.v:823.5-823.29" + process $proc$ls180.v:823$3088 assign { } { } assign $0\main_source_first[0:0] 1'0 sync always update \main_source_first $0\main_source_first[0:0] sync init end - attribute \src "ls180.v:825.5-825.28" - process $proc$ls180.v:825$3092 + attribute \src "ls180.v:824.5-824.28" + process $proc$ls180.v:824$3089 assign { } { } assign $0\main_source_last[0:0] 1'0 sync always update \main_source_last $0\main_source_last[0:0] sync init end - attribute \src "ls180.v:826.11-826.42" - process $proc$ls180.v:826$3093 + attribute \src "ls180.v:825.11-825.42" + process $proc$ls180.v:825$3090 assign { } { } assign $1\main_source_payload_data[7:0] 8'00000000 sync always sync init update \main_source_payload_data $1\main_source_payload_data[7:0] end - attribute \src "ls180.v:827.5-827.30" - process $proc$ls180.v:827$3094 + attribute \src "ls180.v:826.5-826.30" + process $proc$ls180.v:826$3091 assign { } { } assign $1\main_uart_clk_rxen[0:0] 1'0 sync always sync init update \main_uart_clk_rxen $1\main_uart_clk_rxen[0:0] end - attribute \src "ls180.v:828.12-828.45" - process $proc$ls180.v:828$3095 + attribute \src "ls180.v:827.12-827.45" + process $proc$ls180.v:827$3092 assign { } { } assign $1\main_phase_accumulator_rx[31:0] 0 sync always sync init update \main_phase_accumulator_rx $1\main_phase_accumulator_rx[31:0] end - attribute \src "ls180.v:830.5-830.21" - process $proc$ls180.v:830$3096 + attribute \src "ls180.v:829.5-829.21" + process $proc$ls180.v:829$3093 assign { } { } assign $1\main_rx_r[0:0] 1'0 sync always sync init update \main_rx_r $1\main_rx_r[0:0] end - attribute \src "ls180.v:831.11-831.29" - process $proc$ls180.v:831$3097 + attribute \src "ls180.v:830.11-830.29" + process $proc$ls180.v:830$3094 assign { } { } assign $1\main_rx_reg[7:0] 8'00000000 sync always sync init update \main_rx_reg $1\main_rx_reg[7:0] end - attribute \src "ls180.v:832.11-832.34" - process $proc$ls180.v:832$3098 + attribute \src "ls180.v:831.11-831.34" + process $proc$ls180.v:831$3095 assign { } { } assign $1\main_rx_bitcount[3:0] 4'0000 sync always sync init update \main_rx_bitcount $1\main_rx_bitcount[3:0] end - attribute \src "ls180.v:833.5-833.24" - process $proc$ls180.v:833$3099 + attribute \src "ls180.v:832.5-832.24" + process $proc$ls180.v:832$3096 assign { } { } assign $1\main_rx_busy[0:0] 1'0 sync always sync init update \main_rx_busy $1\main_rx_busy[0:0] end - attribute \src "ls180.v:844.5-844.32" - process $proc$ls180.v:844$3100 + attribute \src "ls180.v:843.5-843.32" + process $proc$ls180.v:843$3097 assign { } { } assign $1\main_uart_tx_pending[0:0] 1'0 sync always sync init update \main_uart_tx_pending $1\main_uart_tx_pending[0:0] end - attribute \src "ls180.v:846.5-846.30" - process $proc$ls180.v:846$3101 + attribute \src "ls180.v:845.5-845.30" + process $proc$ls180.v:845$3098 assign { } { } assign $1\main_uart_tx_clear[0:0] 1'0 sync always sync init update \main_uart_tx_clear $1\main_uart_tx_clear[0:0] end - attribute \src "ls180.v:847.5-847.36" - process $proc$ls180.v:847$3102 + attribute \src "ls180.v:846.5-846.36" + process $proc$ls180.v:846$3099 assign { } { } assign $1\main_uart_tx_old_trigger[0:0] 1'0 sync always sync init update \main_uart_tx_old_trigger $1\main_uart_tx_old_trigger[0:0] end - attribute \src "ls180.v:849.5-849.32" - process $proc$ls180.v:849$3103 + attribute \src "ls180.v:848.5-848.32" + process $proc$ls180.v:848$3100 assign { } { } assign $1\main_uart_rx_pending[0:0] 1'0 sync always sync init update \main_uart_rx_pending $1\main_uart_rx_pending[0:0] end - attribute \src "ls180.v:851.5-851.30" - process $proc$ls180.v:851$3104 + attribute \src "ls180.v:850.5-850.30" + process $proc$ls180.v:850$3101 assign { } { } assign $1\main_uart_rx_clear[0:0] 1'0 sync always sync init update \main_uart_rx_clear $1\main_uart_rx_clear[0:0] end - attribute \src "ls180.v:852.5-852.36" - process $proc$ls180.v:852$3105 + attribute \src "ls180.v:851.5-851.36" + process $proc$ls180.v:851$3102 assign { } { } assign $1\main_uart_rx_old_trigger[0:0] 1'0 sync always sync init update \main_uart_rx_old_trigger $1\main_uart_rx_old_trigger[0:0] end - attribute \src "ls180.v:856.11-856.49" - process $proc$ls180.v:856$3106 + attribute \src "ls180.v:855.11-855.49" + process $proc$ls180.v:855$3103 assign { } { } assign $1\main_uart_eventmanager_status_w[1:0] 2'00 sync always sync init update \main_uart_eventmanager_status_w $1\main_uart_eventmanager_status_w[1:0] end - attribute \src "ls180.v:860.11-860.50" - process $proc$ls180.v:860$3107 + attribute \src "ls180.v:859.11-859.50" + process $proc$ls180.v:859$3104 assign { } { } assign $1\main_uart_eventmanager_pending_w[1:0] 2'00 sync always sync init update \main_uart_eventmanager_pending_w $1\main_uart_eventmanager_pending_w[1:0] end - attribute \src "ls180.v:861.11-861.48" - process $proc$ls180.v:861$3108 + attribute \src "ls180.v:860.11-860.48" + process $proc$ls180.v:860$3105 assign { } { } assign $1\main_uart_eventmanager_storage[1:0] 2'00 sync always sync init update \main_uart_eventmanager_storage $1\main_uart_eventmanager_storage[1:0] end - attribute \src "ls180.v:862.5-862.37" - process $proc$ls180.v:862$3109 + attribute \src "ls180.v:861.5-861.37" + process $proc$ls180.v:861$3106 assign { } { } assign $1\main_uart_eventmanager_re[0:0] 1'0 sync always sync init update \main_uart_eventmanager_re $1\main_uart_eventmanager_re[0:0] end - attribute \src "ls180.v:879.5-879.40" - process $proc$ls180.v:879$3110 + attribute \src "ls180.v:878.5-878.40" + process $proc$ls180.v:878$3107 assign { } { } assign $0\main_uart_tx_fifo_sink_first[0:0] 1'0 sync always update \main_uart_tx_fifo_sink_first $0\main_uart_tx_fifo_sink_first[0:0] sync init end - attribute \src "ls180.v:880.5-880.39" - process $proc$ls180.v:880$3111 + attribute \src "ls180.v:879.5-879.39" + process $proc$ls180.v:879$3108 assign { } { } assign $0\main_uart_tx_fifo_sink_last[0:0] 1'0 sync always update \main_uart_tx_fifo_sink_last $0\main_uart_tx_fifo_sink_last[0:0] sync init end - attribute \src "ls180.v:888.5-888.38" - process $proc$ls180.v:888$3112 + attribute \src "ls180.v:887.5-887.38" + process $proc$ls180.v:887$3109 assign { } { } assign $1\main_uart_tx_fifo_readable[0:0] 1'0 sync always sync init update \main_uart_tx_fifo_readable $1\main_uart_tx_fifo_readable[0:0] end - attribute \src "ls180.v:895.11-895.42" - process $proc$ls180.v:895$3113 + attribute \src "ls180.v:894.11-894.42" + process $proc$ls180.v:894$3110 assign { } { } assign $1\main_uart_tx_fifo_level0[4:0] 5'00000 sync always sync init update \main_uart_tx_fifo_level0 $1\main_uart_tx_fifo_level0[4:0] end - attribute \src "ls180.v:896.5-896.37" - process $proc$ls180.v:896$3114 + attribute \src "ls180.v:895.5-895.37" + process $proc$ls180.v:895$3111 assign { } { } assign $0\main_uart_tx_fifo_replace[0:0] 1'0 sync always update \main_uart_tx_fifo_replace $0\main_uart_tx_fifo_replace[0:0] sync init end - attribute \src "ls180.v:897.11-897.43" - process $proc$ls180.v:897$3115 + attribute \src "ls180.v:896.11-896.43" + process $proc$ls180.v:896$3112 assign { } { } assign $1\main_uart_tx_fifo_produce[3:0] 4'0000 sync always sync init update \main_uart_tx_fifo_produce $1\main_uart_tx_fifo_produce[3:0] end - attribute \src "ls180.v:898.11-898.43" - process $proc$ls180.v:898$3116 + attribute \src "ls180.v:897.11-897.43" + process $proc$ls180.v:897$3113 assign { } { } assign $1\main_uart_tx_fifo_consume[3:0] 4'0000 sync always sync init update \main_uart_tx_fifo_consume $1\main_uart_tx_fifo_consume[3:0] end - attribute \src "ls180.v:899.11-899.46" - process $proc$ls180.v:899$3117 + attribute \src "ls180.v:898.11-898.46" + process $proc$ls180.v:898$3114 assign { } { } assign $1\main_uart_tx_fifo_wrport_adr[3:0] 4'0000 sync always sync init update \main_uart_tx_fifo_wrport_adr $1\main_uart_tx_fifo_wrport_adr[3:0] end - attribute \src "ls180.v:925.5-925.38" - process $proc$ls180.v:925$3118 + attribute \src "ls180.v:924.5-924.38" + process $proc$ls180.v:924$3115 assign { } { } assign $1\main_uart_rx_fifo_readable[0:0] 1'0 sync always sync init update \main_uart_rx_fifo_readable $1\main_uart_rx_fifo_readable[0:0] end - attribute \src "ls180.v:932.11-932.42" - process $proc$ls180.v:932$3119 + attribute \src "ls180.v:931.11-931.42" + process $proc$ls180.v:931$3116 assign { } { } assign $1\main_uart_rx_fifo_level0[4:0] 5'00000 sync always sync init update \main_uart_rx_fifo_level0 $1\main_uart_rx_fifo_level0[4:0] end - attribute \src "ls180.v:933.5-933.37" - process $proc$ls180.v:933$3120 + attribute \src "ls180.v:932.5-932.37" + process $proc$ls180.v:932$3117 assign { } { } assign $0\main_uart_rx_fifo_replace[0:0] 1'0 sync always update \main_uart_rx_fifo_replace $0\main_uart_rx_fifo_replace[0:0] sync init end - attribute \src "ls180.v:934.11-934.43" - process $proc$ls180.v:934$3121 + attribute \src "ls180.v:933.11-933.43" + process $proc$ls180.v:933$3118 assign { } { } assign $1\main_uart_rx_fifo_produce[3:0] 4'0000 sync always sync init update \main_uart_rx_fifo_produce $1\main_uart_rx_fifo_produce[3:0] end - attribute \src "ls180.v:935.11-935.43" - process $proc$ls180.v:935$3122 + attribute \src "ls180.v:934.11-934.43" + process $proc$ls180.v:934$3119 assign { } { } assign $1\main_uart_rx_fifo_consume[3:0] 4'0000 sync always sync init update \main_uart_rx_fifo_consume $1\main_uart_rx_fifo_consume[3:0] end - attribute \src "ls180.v:936.11-936.46" - process $proc$ls180.v:936$3123 + attribute \src "ls180.v:935.11-935.46" + process $proc$ls180.v:935$3120 assign { } { } assign $1\main_uart_rx_fifo_wrport_adr[3:0] 4'0000 sync always sync init update \main_uart_rx_fifo_wrport_adr $1\main_uart_rx_fifo_wrport_adr[3:0] end - attribute \src "ls180.v:951.5-951.27" - process $proc$ls180.v:951$3124 + attribute \src "ls180.v:950.5-950.27" + process $proc$ls180.v:950$3121 assign { } { } assign $0\main_uart_reset[0:0] 1'0 sync always update \main_uart_reset $0\main_uart_reset[0:0] sync init end - attribute \src "ls180.v:952.12-952.40" - process $proc$ls180.v:952$3125 + attribute \src "ls180.v:951.12-951.40" + process $proc$ls180.v:951$3122 assign { } { } assign $1\main_gpio_oe_storage[15:0] 16'0000000000000000 sync always sync init update \main_gpio_oe_storage $1\main_gpio_oe_storage[15:0] end - attribute \src "ls180.v:953.5-953.27" - process $proc$ls180.v:953$3126 + attribute \src "ls180.v:952.5-952.27" + process $proc$ls180.v:952$3123 assign { } { } assign $1\main_gpio_oe_re[0:0] 1'0 sync always sync init update \main_gpio_oe_re $1\main_gpio_oe_re[0:0] end - attribute \src "ls180.v:954.12-954.36" - process $proc$ls180.v:954$3127 + attribute \src "ls180.v:953.12-953.36" + process $proc$ls180.v:953$3124 assign { } { } assign $1\main_gpio_status[15:0] 16'0000000000000000 sync always sync init update \main_gpio_status $1\main_gpio_status[15:0] end - attribute \src "ls180.v:956.12-956.41" - process $proc$ls180.v:956$3128 + attribute \src "ls180.v:955.12-955.41" + process $proc$ls180.v:955$3125 assign { } { } assign $1\main_gpio_out_storage[15:0] 16'0000000000000000 sync always sync init update \main_gpio_out_storage $1\main_gpio_out_storage[15:0] end - attribute \src "ls180.v:957.5-957.28" - process $proc$ls180.v:957$3129 + attribute \src "ls180.v:956.5-956.28" + process $proc$ls180.v:956$3126 assign { } { } assign $1\main_gpio_out_re[0:0] 1'0 sync always sync init update \main_gpio_out_re $1\main_gpio_out_re[0:0] end - attribute \src "ls180.v:963.5-963.33" - process $proc$ls180.v:963$3130 + attribute \src "ls180.v:962.5-962.33" + process $proc$ls180.v:962$3127 assign { } { } assign $1\main_spi_master_done0[0:0] 1'0 sync always sync init update \main_spi_master_done0 $1\main_spi_master_done0[0:0] end - attribute \src "ls180.v:964.5-964.31" - process $proc$ls180.v:964$3131 + attribute \src "ls180.v:963.5-963.31" + process $proc$ls180.v:963$3128 assign { } { } assign $1\main_spi_master_irq[0:0] 1'0 sync always sync init update \main_spi_master_irq $1\main_spi_master_irq[0:0] end - attribute \src "ls180.v:966.11-966.38" - process $proc$ls180.v:966$3132 + attribute \src "ls180.v:965.11-965.38" + process $proc$ls180.v:965$3129 assign { } { } assign $1\main_spi_master_miso[7:0] 8'00000000 sync always sync init update \main_spi_master_miso $1\main_spi_master_miso[7:0] end - attribute \src "ls180.v:969.12-969.48" - process $proc$ls180.v:969$3133 + attribute \src "ls180.v:968.12-968.48" + process $proc$ls180.v:968$3130 assign { } { } assign $0\main_spi_master_clk_divider0[15:0] 16'0000000000000111 sync always update \main_spi_master_clk_divider0 $0\main_spi_master_clk_divider0[15:0] sync init end - attribute \src "ls180.v:970.5-970.34" - process $proc$ls180.v:970$3134 + attribute \src "ls180.v:969.5-969.34" + process $proc$ls180.v:969$3131 assign { } { } assign $1\main_spi_master_start1[0:0] 1'0 sync always sync init update \main_spi_master_start1 $1\main_spi_master_start1[0:0] end - attribute \src "ls180.v:972.12-972.51" - process $proc$ls180.v:972$3135 + attribute \src "ls180.v:971.12-971.51" + process $proc$ls180.v:971$3132 assign { } { } assign $1\main_spi_master_control_storage[15:0] 16'0000000000000000 sync always sync init update \main_spi_master_control_storage $1\main_spi_master_control_storage[15:0] end - attribute \src "ls180.v:973.5-973.38" - process $proc$ls180.v:973$3136 + attribute \src "ls180.v:972.5-972.38" + process $proc$ls180.v:972$3133 assign { } { } assign $1\main_spi_master_control_re[0:0] 1'0 sync always sync init update \main_spi_master_control_re $1\main_spi_master_control_re[0:0] end - attribute \src "ls180.v:977.11-977.46" - process $proc$ls180.v:977$3137 + attribute \src "ls180.v:976.11-976.46" + process $proc$ls180.v:976$3134 assign { } { } assign $1\main_spi_master_mosi_storage[7:0] 8'00000000 sync always sync init update \main_spi_master_mosi_storage $1\main_spi_master_mosi_storage[7:0] end - attribute \src "ls180.v:978.5-978.35" - process $proc$ls180.v:978$3138 + attribute \src "ls180.v:977.5-977.35" + process $proc$ls180.v:977$3135 assign { } { } assign $1\main_spi_master_mosi_re[0:0] 1'0 sync always sync init update \main_spi_master_mosi_re $1\main_spi_master_mosi_re[0:0] end - attribute \src "ls180.v:982.5-982.38" - process $proc$ls180.v:982$3139 + attribute \src "ls180.v:981.5-981.38" + process $proc$ls180.v:981$3136 assign { } { } assign $1\main_spi_master_cs_storage[0:0] 1'1 sync always sync init update \main_spi_master_cs_storage $1\main_spi_master_cs_storage[0:0] end - attribute \src "ls180.v:983.5-983.33" - process $proc$ls180.v:983$3140 + attribute \src "ls180.v:982.5-982.33" + process $proc$ls180.v:982$3137 assign { } { } assign $1\main_spi_master_cs_re[0:0] 1'0 sync always sync init update \main_spi_master_cs_re $1\main_spi_master_cs_re[0:0] end - attribute \src "ls180.v:984.5-984.44" - process $proc$ls180.v:984$3141 + attribute \src "ls180.v:983.5-983.44" + process $proc$ls180.v:983$3138 assign { } { } assign $1\main_spi_master_loopback_storage[0:0] 1'0 sync always sync init update \main_spi_master_loopback_storage $1\main_spi_master_loopback_storage[0:0] end - attribute \src "ls180.v:985.5-985.39" - process $proc$ls180.v:985$3142 + attribute \src "ls180.v:984.5-984.39" + process $proc$ls180.v:984$3139 assign { } { } assign $1\main_spi_master_loopback_re[0:0] 1'0 sync always sync init update \main_spi_master_loopback_re $1\main_spi_master_loopback_re[0:0] end - attribute \src "ls180.v:986.5-986.38" - process $proc$ls180.v:986$3143 + attribute \src "ls180.v:985.5-985.38" + process $proc$ls180.v:985$3140 assign { } { } assign $1\main_spi_master_clk_enable[0:0] 1'0 sync always sync init update \main_spi_master_clk_enable $1\main_spi_master_clk_enable[0:0] end - attribute \src "ls180.v:987.5-987.37" - process $proc$ls180.v:987$3144 + attribute \src "ls180.v:986.5-986.37" + process $proc$ls180.v:986$3141 assign { } { } assign $1\main_spi_master_cs_enable[0:0] 1'0 sync always sync init update \main_spi_master_cs_enable $1\main_spi_master_cs_enable[0:0] end - attribute \src "ls180.v:988.11-988.39" - process $proc$ls180.v:988$3145 + attribute \src "ls180.v:987.11-987.39" + process $proc$ls180.v:987$3142 assign { } { } assign $1\main_spi_master_count[2:0] 3'000 sync always sync init update \main_spi_master_count $1\main_spi_master_count[2:0] end - attribute \src "ls180.v:989.5-989.38" - process $proc$ls180.v:989$3146 + attribute \src "ls180.v:988.5-988.38" + process $proc$ls180.v:988$3143 assign { } { } assign $1\main_spi_master_mosi_latch[0:0] 1'0 sync always sync init update \main_spi_master_mosi_latch $1\main_spi_master_mosi_latch[0:0] end - attribute \src "ls180.v:990.5-990.38" - process $proc$ls180.v:990$3147 + attribute \src "ls180.v:989.5-989.38" + process $proc$ls180.v:989$3144 assign { } { } assign $1\main_spi_master_miso_latch[0:0] 1'0 sync always sync init update \main_spi_master_miso_latch $1\main_spi_master_miso_latch[0:0] end - attribute \src "ls180.v:991.12-991.48" - process $proc$ls180.v:991$3148 + attribute \src "ls180.v:990.12-990.48" + process $proc$ls180.v:990$3145 assign { } { } assign $1\main_spi_master_clk_divider1[15:0] 16'0000000000000000 sync always sync init update \main_spi_master_clk_divider1 $1\main_spi_master_clk_divider1[15:0] end - attribute \src "ls180.v:994.11-994.43" - process $proc$ls180.v:994$3149 + attribute \src "ls180.v:993.11-993.43" + process $proc$ls180.v:993$3146 assign { } { } assign $1\main_spi_master_mosi_data[7:0] 8'00000000 sync always sync init update \main_spi_master_mosi_data $1\main_spi_master_mosi_data[7:0] end - attribute \src "ls180.v:995.11-995.42" - process $proc$ls180.v:995$3150 + attribute \src "ls180.v:994.11-994.42" + process $proc$ls180.v:994$3147 assign { } { } assign $1\main_spi_master_mosi_sel[2:0] 3'000 sync always sync init update \main_spi_master_mosi_sel $1\main_spi_master_mosi_sel[2:0] end - attribute \src "ls180.v:996.11-996.43" - process $proc$ls180.v:996$3151 + attribute \src "ls180.v:995.11-995.43" + process $proc$ls180.v:995$3148 assign { } { } assign $1\main_spi_master_miso_data[7:0] 8'00000000 sync always sync init update \main_spi_master_miso_data $1\main_spi_master_miso_data[7:0] end - attribute \src "ls180.v:998.12-998.30" - process $proc$ls180.v:998$3152 + attribute \src "ls180.v:997.12-997.30" + process $proc$ls180.v:997$3149 assign { } { } - assign $1\main_dummy[42:0] 43'0000000000000000000000000000000000000000000 + assign $1\main_dummy[41:0] 42'000000000000000000000000000000000000000000 sync always sync init - update \main_dummy $1\main_dummy[42:0] + update \main_dummy $1\main_dummy[41:0] end - attribute \src "ls180.v:9981.1-9991.4" - process $proc$ls180.v:9981$2684 + attribute \src "ls180.v:9977.1-9987.4" + process $proc$ls180.v:9977$2682 assign { } { } assign { } { } assign { } { } @@ -128293,69 +128234,94 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0$memwr$\mem$ls180.v:9989$4_ADDR[6:0]$2694 7'xxxxxxx - assign $0$memwr$\mem$ls180.v:9989$4_DATA[31:0]$2695 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:9989$4_EN[31:0]$2696 0 - assign $0$memwr$\mem$ls180.v:9987$3_ADDR[6:0]$2691 7'xxxxxxx - assign $0$memwr$\mem$ls180.v:9987$3_DATA[31:0]$2692 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:9987$3_EN[31:0]$2693 0 - assign $0$memwr$\mem$ls180.v:9985$2_ADDR[6:0]$2688 7'xxxxxxx - assign $0$memwr$\mem$ls180.v:9985$2_DATA[31:0]$2689 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:9985$2_EN[31:0]$2690 0 - assign $0$memwr$\mem$ls180.v:9983$1_ADDR[6:0]$2685 7'xxxxxxx - assign $0$memwr$\mem$ls180.v:9983$1_DATA[31:0]$2686 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:9983$1_EN[31:0]$2687 0 + assign $0$memwr$\mem$ls180.v:9985$4_ADDR[6:0]$2692 7'xxxxxxx + assign $0$memwr$\mem$ls180.v:9985$4_DATA[31:0]$2693 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:9985$4_EN[31:0]$2694 0 + assign $0$memwr$\mem$ls180.v:9983$3_ADDR[6:0]$2689 7'xxxxxxx + assign $0$memwr$\mem$ls180.v:9983$3_DATA[31:0]$2690 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:9983$3_EN[31:0]$2691 0 + assign $0$memwr$\mem$ls180.v:9981$2_ADDR[6:0]$2686 7'xxxxxxx + assign $0$memwr$\mem$ls180.v:9981$2_DATA[31:0]$2687 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:9981$2_EN[31:0]$2688 0 + assign $0$memwr$\mem$ls180.v:9979$1_ADDR[6:0]$2683 7'xxxxxxx + assign $0$memwr$\mem$ls180.v:9979$1_DATA[31:0]$2684 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:9979$1_EN[31:0]$2685 0 assign $0\memadr[6:0] \main_libresocsim_adr - attribute \src "ls180.v:9982.2-9983.65" + attribute \src "ls180.v:9978.2-9979.65" switch \main_libresocsim_we [0] - attribute \src "ls180.v:9982.6-9982.28" + attribute \src "ls180.v:9978.6-9978.28" case 1'1 - assign $0$memwr$\mem$ls180.v:9983$1_ADDR[6:0]$2685 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:9983$1_DATA[31:0]$2686 { 24'000000000000000000000000 \main_libresocsim_dat_w [7:0] } - assign $0$memwr$\mem$ls180.v:9983$1_EN[31:0]$2687 255 + assign $0$memwr$\mem$ls180.v:9979$1_ADDR[6:0]$2683 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:9979$1_DATA[31:0]$2684 { 24'000000000000000000000000 \main_libresocsim_dat_w [7:0] } + assign $0$memwr$\mem$ls180.v:9979$1_EN[31:0]$2685 255 case end - attribute \src "ls180.v:9984.2-9985.67" + attribute \src "ls180.v:9980.2-9981.67" switch \main_libresocsim_we [1] - attribute \src "ls180.v:9984.6-9984.28" + attribute \src "ls180.v:9980.6-9980.28" case 1'1 - assign $0$memwr$\mem$ls180.v:9985$2_ADDR[6:0]$2688 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:9985$2_DATA[31:0]$2689 { 16'0000000000000000 \main_libresocsim_dat_w [15:8] 8'xxxxxxxx } - assign $0$memwr$\mem$ls180.v:9985$2_EN[31:0]$2690 65280 + assign $0$memwr$\mem$ls180.v:9981$2_ADDR[6:0]$2686 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:9981$2_DATA[31:0]$2687 { 16'0000000000000000 \main_libresocsim_dat_w [15:8] 8'xxxxxxxx } + assign $0$memwr$\mem$ls180.v:9981$2_EN[31:0]$2688 65280 case end - attribute \src "ls180.v:9986.2-9987.69" + attribute \src "ls180.v:9982.2-9983.69" switch \main_libresocsim_we [2] - attribute \src "ls180.v:9986.6-9986.28" + attribute \src "ls180.v:9982.6-9982.28" case 1'1 - assign $0$memwr$\mem$ls180.v:9987$3_ADDR[6:0]$2691 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:9987$3_DATA[31:0]$2692 { 8'00000000 \main_libresocsim_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } - assign $0$memwr$\mem$ls180.v:9987$3_EN[31:0]$2693 16711680 + assign $0$memwr$\mem$ls180.v:9983$3_ADDR[6:0]$2689 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:9983$3_DATA[31:0]$2690 { 8'00000000 \main_libresocsim_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:9983$3_EN[31:0]$2691 16711680 case end - attribute \src "ls180.v:9988.2-9989.69" + attribute \src "ls180.v:9984.2-9985.69" switch \main_libresocsim_we [3] - attribute \src "ls180.v:9988.6-9988.28" + attribute \src "ls180.v:9984.6-9984.28" case 1'1 - assign $0$memwr$\mem$ls180.v:9989$4_ADDR[6:0]$2694 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:9989$4_DATA[31:0]$2695 { \main_libresocsim_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem$ls180.v:9989$4_EN[31:0]$2696 32'11111111000000000000000000000000 + assign $0$memwr$\mem$ls180.v:9985$4_ADDR[6:0]$2692 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:9985$4_DATA[31:0]$2693 { \main_libresocsim_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:9985$4_EN[31:0]$2694 32'11111111000000000000000000000000 case end sync posedge \sys_clk_1 update \memadr $0\memadr[6:0] - update $memwr$\mem$ls180.v:9983$1_ADDR $0$memwr$\mem$ls180.v:9983$1_ADDR[6:0]$2685 - update $memwr$\mem$ls180.v:9983$1_DATA $0$memwr$\mem$ls180.v:9983$1_DATA[31:0]$2686 - update $memwr$\mem$ls180.v:9983$1_EN $0$memwr$\mem$ls180.v:9983$1_EN[31:0]$2687 - update $memwr$\mem$ls180.v:9985$2_ADDR $0$memwr$\mem$ls180.v:9985$2_ADDR[6:0]$2688 - update $memwr$\mem$ls180.v:9985$2_DATA $0$memwr$\mem$ls180.v:9985$2_DATA[31:0]$2689 - update $memwr$\mem$ls180.v:9985$2_EN $0$memwr$\mem$ls180.v:9985$2_EN[31:0]$2690 - update $memwr$\mem$ls180.v:9987$3_ADDR $0$memwr$\mem$ls180.v:9987$3_ADDR[6:0]$2691 - update $memwr$\mem$ls180.v:9987$3_DATA $0$memwr$\mem$ls180.v:9987$3_DATA[31:0]$2692 - update $memwr$\mem$ls180.v:9987$3_EN $0$memwr$\mem$ls180.v:9987$3_EN[31:0]$2693 - update $memwr$\mem$ls180.v:9989$4_ADDR $0$memwr$\mem$ls180.v:9989$4_ADDR[6:0]$2694 - update $memwr$\mem$ls180.v:9989$4_DATA $0$memwr$\mem$ls180.v:9989$4_DATA[31:0]$2695 - update $memwr$\mem$ls180.v:9989$4_EN $0$memwr$\mem$ls180.v:9989$4_EN[31:0]$2696 + update $memwr$\mem$ls180.v:9979$1_ADDR $0$memwr$\mem$ls180.v:9979$1_ADDR[6:0]$2683 + update $memwr$\mem$ls180.v:9979$1_DATA $0$memwr$\mem$ls180.v:9979$1_DATA[31:0]$2684 + update $memwr$\mem$ls180.v:9979$1_EN $0$memwr$\mem$ls180.v:9979$1_EN[31:0]$2685 + update $memwr$\mem$ls180.v:9981$2_ADDR $0$memwr$\mem$ls180.v:9981$2_ADDR[6:0]$2686 + update $memwr$\mem$ls180.v:9981$2_DATA $0$memwr$\mem$ls180.v:9981$2_DATA[31:0]$2687 + update $memwr$\mem$ls180.v:9981$2_EN $0$memwr$\mem$ls180.v:9981$2_EN[31:0]$2688 + update $memwr$\mem$ls180.v:9983$3_ADDR $0$memwr$\mem$ls180.v:9983$3_ADDR[6:0]$2689 + update $memwr$\mem$ls180.v:9983$3_DATA $0$memwr$\mem$ls180.v:9983$3_DATA[31:0]$2690 + update $memwr$\mem$ls180.v:9983$3_EN $0$memwr$\mem$ls180.v:9983$3_EN[31:0]$2691 + update $memwr$\mem$ls180.v:9985$4_ADDR $0$memwr$\mem$ls180.v:9985$4_ADDR[6:0]$2692 + update $memwr$\mem$ls180.v:9985$4_DATA $0$memwr$\mem$ls180.v:9985$4_DATA[31:0]$2693 + update $memwr$\mem$ls180.v:9985$4_EN $0$memwr$\mem$ls180.v:9985$4_EN[31:0]$2694 + end + attribute \src "ls180.v:9997.1-10001.4" + process $proc$ls180.v:9997$2696 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage$ls180.v:9999$5_ADDR[2:0]$2697 3'xxx + assign $0$memwr$\storage$ls180.v:9999$5_DATA[24:0]$2698 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage$ls180.v:9999$5_EN[24:0]$2699 25'0000000000000000000000000 + assign $0\memdat[24:0] $memrd$\storage$ls180.v:10000$2700_DATA + attribute \src "ls180.v:9998.2-9999.129" + switch \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:9998.6-9998.60" + case 1'1 + assign $0$memwr$\storage$ls180.v:9999$5_ADDR[2:0]$2697 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage$ls180.v:9999$5_DATA[24:0]$2698 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage$ls180.v:9999$5_EN[24:0]$2699 25'1111111111111111111111111 + case + end + sync posedge \sys_clk_1 + update \memdat $0\memdat[24:0] + update $memwr$\storage$ls180.v:9999$5_ADDR $0$memwr$\storage$ls180.v:9999$5_ADDR[2:0]$2697 + update $memwr$\storage$ls180.v:9999$5_DATA $0$memwr$\storage$ls180.v:9999$5_DATA[24:0]$2698 + update $memwr$\storage$ls180.v:9999$5_EN $0$memwr$\storage$ls180.v:9999$5_EN[24:0]$2699 end connect \main_libresocsim_libresoc_reset \main_libresocsim_reset connect \uart_tx \main_libresocsim_libresoc_constraintmanager1_uart0_tx @@ -128379,21 +128345,21 @@ module \ls180 connect \main_sdcore_sink_sink_last \main_sdmem2block_source_source_last0 connect \main_sdcore_sink_sink_payload_data \main_sdmem2block_source_source_payload_data0 connect \main_libresocsim_bus_error \builder_error - connect \main_libresocsim_converter0_reset $not$ls180.v:2725$14_Y + connect \main_libresocsim_converter0_reset $not$ls180.v:2726$14_Y connect \main_libresocsim_libresoc_ibus_dat_r { \main_libresocsim_interface0_converted_interface_dat_r \main_libresocsim_converter0_dat_r [63:32] } - connect \main_libresocsim_converter1_reset $not$ls180.v:2785$25_Y + connect \main_libresocsim_converter1_reset $not$ls180.v:2786$25_Y connect \main_libresocsim_libresoc_dbus_dat_r { \main_libresocsim_interface1_converted_interface_dat_r \main_libresocsim_converter1_dat_r [63:32] } - connect \main_libresocsim_converter2_reset $not$ls180.v:2845$36_Y + connect \main_libresocsim_converter2_reset $not$ls180.v:2846$36_Y connect \main_libresocsim_libresoc_jtag_wb_dat_r { \main_libresocsim_interface2_converted_interface_dat_r \main_libresocsim_converter2_dat_r [63:32] } connect \main_libresocsim_reset \main_libresocsim_reset_re connect \main_libresocsim_bus_errors_status \main_libresocsim_bus_errors connect \main_libresocsim_adr \main_libresocsim_ram_bus_adr [6:0] connect \main_libresocsim_ram_bus_dat_r \main_libresocsim_dat_r connect \main_libresocsim_dat_w \main_libresocsim_ram_bus_dat_w - connect \main_libresocsim_zero_trigger $ne$ls180.v:2917$60_Y + connect \main_libresocsim_zero_trigger $ne$ls180.v:2918$60_Y connect \main_libresocsim_eventmanager_status_w \main_libresocsim_zero_status connect \main_libresocsim_eventmanager_pending_w \main_libresocsim_zero_pending - connect \main_libresocsim_irq $and$ls180.v:2926$63_Y + connect \main_libresocsim_irq $and$ls180.v:2927$63_Y connect \main_libresocsim_zero_status \main_libresocsim_zero_trigger connect \sys_clk_1 \sys_clk connect \por_clk \sys_clk @@ -128435,8 +128401,8 @@ module \ls180 connect \main_sdram_inti_p0_reset_n \main_sdram_reset_n connect \main_sdram_inti_p0_address \main_sdram_address_storage connect \main_sdram_inti_p0_bank \main_sdram_baddress_storage - connect \main_sdram_inti_p0_wrdata_en $and$ls180.v:3045$71_Y - connect \main_sdram_inti_p0_rddata_en $and$ls180.v:3046$72_Y + connect \main_sdram_inti_p0_wrdata_en $and$ls180.v:3041$70_Y + connect \main_sdram_inti_p0_rddata_en $and$ls180.v:3042$71_Y connect \main_sdram_inti_p0_wrdata \main_sdram_wrdata_storage connect \main_sdram_inti_p0_wrdata_mask 2'00 connect \main_sdram_bankmachine0_req_valid \main_sdram_interface_bank0_valid @@ -128467,14 +128433,14 @@ module \ls180 connect \main_sdram_interface_bank3_lock \main_sdram_bankmachine3_req_lock connect \main_sdram_interface_bank3_wdata_ready \main_sdram_bankmachine3_req_wdata_ready connect \main_sdram_interface_bank3_rdata_valid \main_sdram_bankmachine3_req_rdata_valid - connect \main_sdram_timer_wait $not$ls180.v:3077$73_Y + connect \main_sdram_timer_wait $not$ls180.v:3073$72_Y connect \main_sdram_postponer_req_i \main_sdram_timer_done0 connect \main_sdram_wants_refresh \main_sdram_postponer_req_o - connect \main_sdram_timer_done1 $eq$ls180.v:3080$74_Y + connect \main_sdram_timer_done1 $eq$ls180.v:3076$73_Y connect \main_sdram_timer_done0 \main_sdram_timer_done1 connect \main_sdram_timer_count0 \main_sdram_timer_count1 - connect \main_sdram_sequencer_start1 $or$ls180.v:3083$76_Y - connect \main_sdram_sequencer_done0 $and$ls180.v:3084$78_Y + connect \main_sdram_sequencer_start1 $or$ls180.v:3079$75_Y + connect \main_sdram_sequencer_done0 $and$ls180.v:3080$77_Y connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine0_req_valid connect \main_sdram_bankmachine0_req_ready \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine0_req_we @@ -128485,13 +128451,13 @@ module \ls180 connect \main_sdram_bankmachine0_cmd_buffer_sink_last \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last connect \main_sdram_bankmachine0_cmd_buffer_sink_payload_we \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we connect \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr - connect \main_sdram_bankmachine0_cmd_buffer_source_ready $or$ls180.v:3126$80_Y - connect \main_sdram_bankmachine0_req_lock $or$ls180.v:3127$81_Y - connect \main_sdram_bankmachine0_row_hit $eq$ls180.v:3128$82_Y + connect \main_sdram_bankmachine0_cmd_buffer_source_ready $or$ls180.v:3122$79_Y + connect \main_sdram_bankmachine0_req_lock $or$ls180.v:3123$80_Y + connect \main_sdram_bankmachine0_row_hit $eq$ls180.v:3124$81_Y connect \main_sdram_bankmachine0_cmd_payload_ba 2'00 - connect \main_sdram_bankmachine0_twtpcon_valid $and$ls180.v:3138$87_Y - connect \main_sdram_bankmachine0_trccon_valid $and$ls180.v:3139$89_Y - connect \main_sdram_bankmachine0_trascon_valid $and$ls180.v:3140$91_Y + connect \main_sdram_bankmachine0_twtpcon_valid $and$ls180.v:3134$86_Y + connect \main_sdram_bankmachine0_trccon_valid $and$ls180.v:3135$88_Y + connect \main_sdram_bankmachine0_trascon_valid $and$ls180.v:3136$90_Y connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din { \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we } connect { \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable @@ -128507,13 +128473,13 @@ module \ls180 connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we $and$ls180.v:3172$99_Y - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read $and$ls180.v:3173$100_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we $and$ls180.v:3168$98_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read $and$ls180.v:3169$99_Y connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine0_cmd_buffer_lookahead_consume connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable $ne$ls180.v:3176$101_Y - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable $ne$ls180.v:3177$102_Y - connect \main_sdram_bankmachine0_cmd_buffer_sink_ready $or$ls180.v:3178$104_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable $ne$ls180.v:3172$100_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable $ne$ls180.v:3173$101_Y + connect \main_sdram_bankmachine0_cmd_buffer_sink_ready $or$ls180.v:3174$103_Y connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine1_req_valid connect \main_sdram_bankmachine1_req_ready \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine1_req_we @@ -128524,13 +128490,13 @@ module \ls180 connect \main_sdram_bankmachine1_cmd_buffer_sink_last \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last connect \main_sdram_bankmachine1_cmd_buffer_sink_payload_we \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we connect \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr - connect \main_sdram_bankmachine1_cmd_buffer_source_ready $or$ls180.v:3283$110_Y - connect \main_sdram_bankmachine1_req_lock $or$ls180.v:3284$111_Y - connect \main_sdram_bankmachine1_row_hit $eq$ls180.v:3285$112_Y + connect \main_sdram_bankmachine1_cmd_buffer_source_ready $or$ls180.v:3279$109_Y + connect \main_sdram_bankmachine1_req_lock $or$ls180.v:3280$110_Y + connect \main_sdram_bankmachine1_row_hit $eq$ls180.v:3281$111_Y connect \main_sdram_bankmachine1_cmd_payload_ba 2'01 - connect \main_sdram_bankmachine1_twtpcon_valid $and$ls180.v:3295$117_Y - connect \main_sdram_bankmachine1_trccon_valid $and$ls180.v:3296$119_Y - connect \main_sdram_bankmachine1_trascon_valid $and$ls180.v:3297$121_Y + connect \main_sdram_bankmachine1_twtpcon_valid $and$ls180.v:3291$116_Y + connect \main_sdram_bankmachine1_trccon_valid $and$ls180.v:3292$118_Y + connect \main_sdram_bankmachine1_trascon_valid $and$ls180.v:3293$120_Y connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din { \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we } connect { \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable @@ -128546,13 +128512,13 @@ module \ls180 connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we $and$ls180.v:3329$129_Y - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read $and$ls180.v:3330$130_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we $and$ls180.v:3325$128_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read $and$ls180.v:3326$129_Y connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine1_cmd_buffer_lookahead_consume connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable $ne$ls180.v:3333$131_Y - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable $ne$ls180.v:3334$132_Y - connect \main_sdram_bankmachine1_cmd_buffer_sink_ready $or$ls180.v:3335$134_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable $ne$ls180.v:3329$130_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable $ne$ls180.v:3330$131_Y + connect \main_sdram_bankmachine1_cmd_buffer_sink_ready $or$ls180.v:3331$133_Y connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine2_req_valid connect \main_sdram_bankmachine2_req_ready \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine2_req_we @@ -128563,13 +128529,13 @@ module \ls180 connect \main_sdram_bankmachine2_cmd_buffer_sink_last \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last connect \main_sdram_bankmachine2_cmd_buffer_sink_payload_we \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we connect \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr - connect \main_sdram_bankmachine2_cmd_buffer_source_ready $or$ls180.v:3440$140_Y - connect \main_sdram_bankmachine2_req_lock $or$ls180.v:3441$141_Y - connect \main_sdram_bankmachine2_row_hit $eq$ls180.v:3442$142_Y + connect \main_sdram_bankmachine2_cmd_buffer_source_ready $or$ls180.v:3436$139_Y + connect \main_sdram_bankmachine2_req_lock $or$ls180.v:3437$140_Y + connect \main_sdram_bankmachine2_row_hit $eq$ls180.v:3438$141_Y connect \main_sdram_bankmachine2_cmd_payload_ba 2'10 - connect \main_sdram_bankmachine2_twtpcon_valid $and$ls180.v:3452$147_Y - connect \main_sdram_bankmachine2_trccon_valid $and$ls180.v:3453$149_Y - connect \main_sdram_bankmachine2_trascon_valid $and$ls180.v:3454$151_Y + connect \main_sdram_bankmachine2_twtpcon_valid $and$ls180.v:3448$146_Y + connect \main_sdram_bankmachine2_trccon_valid $and$ls180.v:3449$148_Y + connect \main_sdram_bankmachine2_trascon_valid $and$ls180.v:3450$150_Y connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din { \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we } connect { \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable @@ -128585,13 +128551,13 @@ module \ls180 connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we $and$ls180.v:3486$159_Y - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read $and$ls180.v:3487$160_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we $and$ls180.v:3482$158_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read $and$ls180.v:3483$159_Y connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine2_cmd_buffer_lookahead_consume connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable $ne$ls180.v:3490$161_Y - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable $ne$ls180.v:3491$162_Y - connect \main_sdram_bankmachine2_cmd_buffer_sink_ready $or$ls180.v:3492$164_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable $ne$ls180.v:3486$160_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable $ne$ls180.v:3487$161_Y + connect \main_sdram_bankmachine2_cmd_buffer_sink_ready $or$ls180.v:3488$163_Y connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine3_req_valid connect \main_sdram_bankmachine3_req_ready \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine3_req_we @@ -128602,13 +128568,13 @@ module \ls180 connect \main_sdram_bankmachine3_cmd_buffer_sink_last \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last connect \main_sdram_bankmachine3_cmd_buffer_sink_payload_we \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we connect \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr - connect \main_sdram_bankmachine3_cmd_buffer_source_ready $or$ls180.v:3597$170_Y - connect \main_sdram_bankmachine3_req_lock $or$ls180.v:3598$171_Y - connect \main_sdram_bankmachine3_row_hit $eq$ls180.v:3599$172_Y + connect \main_sdram_bankmachine3_cmd_buffer_source_ready $or$ls180.v:3593$169_Y + connect \main_sdram_bankmachine3_req_lock $or$ls180.v:3594$170_Y + connect \main_sdram_bankmachine3_row_hit $eq$ls180.v:3595$171_Y connect \main_sdram_bankmachine3_cmd_payload_ba 2'11 - connect \main_sdram_bankmachine3_twtpcon_valid $and$ls180.v:3609$177_Y - connect \main_sdram_bankmachine3_trccon_valid $and$ls180.v:3610$179_Y - connect \main_sdram_bankmachine3_trascon_valid $and$ls180.v:3611$181_Y + connect \main_sdram_bankmachine3_twtpcon_valid $and$ls180.v:3605$176_Y + connect \main_sdram_bankmachine3_trccon_valid $and$ls180.v:3606$178_Y + connect \main_sdram_bankmachine3_trascon_valid $and$ls180.v:3607$180_Y connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din { \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we } connect { \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable @@ -128624,32 +128590,32 @@ module \ls180 connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we $and$ls180.v:3643$189_Y - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read $and$ls180.v:3644$190_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we $and$ls180.v:3639$188_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read $and$ls180.v:3640$189_Y connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine3_cmd_buffer_lookahead_consume connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable $ne$ls180.v:3647$191_Y - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable $ne$ls180.v:3648$192_Y - connect \main_sdram_bankmachine3_cmd_buffer_sink_ready $or$ls180.v:3649$194_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable $ne$ls180.v:3643$190_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable $ne$ls180.v:3644$191_Y + connect \main_sdram_bankmachine3_cmd_buffer_sink_ready $or$ls180.v:3645$193_Y connect \main_sdram_choose_req_want_cmds 1'1 - connect \main_sdram_trrdcon_valid $and$ls180.v:3745$205_Y - connect \main_sdram_tfawcon_valid $and$ls180.v:3746$211_Y - connect \main_sdram_ras_allowed $and$ls180.v:3747$212_Y - connect \main_sdram_tccdcon_valid $and$ls180.v:3748$215_Y + connect \main_sdram_trrdcon_valid $and$ls180.v:3741$204_Y + connect \main_sdram_tfawcon_valid $and$ls180.v:3742$210_Y + connect \main_sdram_ras_allowed $and$ls180.v:3743$211_Y + connect \main_sdram_tccdcon_valid $and$ls180.v:3744$214_Y connect \main_sdram_cas_allowed \main_sdram_tccdcon_ready - connect \main_sdram_twtrcon_valid $and$ls180.v:3750$217_Y - connect \main_sdram_read_available $or$ls180.v:3751$224_Y - connect \main_sdram_write_available $or$ls180.v:3752$231_Y - connect \main_sdram_max_time0 $eq$ls180.v:3753$232_Y - connect \main_sdram_max_time1 $eq$ls180.v:3754$233_Y + connect \main_sdram_twtrcon_valid $and$ls180.v:3746$216_Y + connect \main_sdram_read_available $or$ls180.v:3747$223_Y + connect \main_sdram_write_available $or$ls180.v:3748$230_Y + connect \main_sdram_max_time0 $eq$ls180.v:3749$231_Y + connect \main_sdram_max_time1 $eq$ls180.v:3750$232_Y connect \main_sdram_bankmachine0_refresh_req \main_sdram_cmd_valid connect \main_sdram_bankmachine1_refresh_req \main_sdram_cmd_valid connect \main_sdram_bankmachine2_refresh_req \main_sdram_cmd_valid connect \main_sdram_bankmachine3_refresh_req \main_sdram_cmd_valid - connect \main_sdram_go_to_refresh $and$ls180.v:3759$236_Y + connect \main_sdram_go_to_refresh $and$ls180.v:3755$235_Y connect \main_sdram_interface_rdata \main_sdram_dfi_p0_rddata connect \main_sdram_dfi_p0_wrdata \main_sdram_interface_wdata - connect \main_sdram_dfi_p0_wrdata_mask $not$ls180.v:3762$237_Y + connect \main_sdram_dfi_p0_wrdata_mask $not$ls180.v:3758$236_Y connect \main_sdram_choose_cmd_request \main_sdram_choose_cmd_valids connect \main_sdram_choose_cmd_cmd_valid \builder_comb_rhs_array_muxed0 connect \main_sdram_choose_cmd_cmd_payload_a \builder_comb_rhs_array_muxed1 @@ -128657,7 +128623,7 @@ module \ls180 connect \main_sdram_choose_cmd_cmd_payload_is_read \builder_comb_rhs_array_muxed3 connect \main_sdram_choose_cmd_cmd_payload_is_write \builder_comb_rhs_array_muxed4 connect \main_sdram_choose_cmd_cmd_payload_is_cmd \builder_comb_rhs_array_muxed5 - connect \main_sdram_choose_cmd_ce $or$ls180.v:3795$295_Y + connect \main_sdram_choose_cmd_ce $or$ls180.v:3791$294_Y connect \main_sdram_choose_req_request \main_sdram_choose_req_valids connect \main_sdram_choose_req_cmd_valid \builder_comb_rhs_array_muxed6 connect \main_sdram_choose_req_cmd_payload_a \builder_comb_rhs_array_muxed7 @@ -128665,31 +128631,31 @@ module \ls180 connect \main_sdram_choose_req_cmd_payload_is_read \builder_comb_rhs_array_muxed9 connect \main_sdram_choose_req_cmd_payload_is_write \builder_comb_rhs_array_muxed10 connect \main_sdram_choose_req_cmd_payload_is_cmd \builder_comb_rhs_array_muxed11 - connect \main_sdram_choose_req_ce $or$ls180.v:3864$381_Y + connect \main_sdram_choose_req_ce $or$ls180.v:3860$380_Y connect \main_sdram_dfi_p0_reset_n 1'1 connect \main_sdram_dfi_p0_cke \main_sdram_steerer0 connect \main_sdram_dfi_p0_odt \main_sdram_steerer1 - connect \builder_roundrobin0_request $and$ls180.v:3941$413_Y - connect \builder_roundrobin0_ce $and$ls180.v:3942$416_Y + connect \builder_roundrobin0_request $and$ls180.v:3937$412_Y + connect \builder_roundrobin0_ce $and$ls180.v:3938$415_Y connect \main_sdram_interface_bank0_addr \builder_comb_rhs_array_muxed12 connect \main_sdram_interface_bank0_we \builder_comb_rhs_array_muxed13 connect \main_sdram_interface_bank0_valid \builder_comb_rhs_array_muxed14 - connect \builder_roundrobin1_request $and$ls180.v:3946$429_Y - connect \builder_roundrobin1_ce $and$ls180.v:3947$432_Y + connect \builder_roundrobin1_request $and$ls180.v:3942$428_Y + connect \builder_roundrobin1_ce $and$ls180.v:3943$431_Y connect \main_sdram_interface_bank1_addr \builder_comb_rhs_array_muxed15 connect \main_sdram_interface_bank1_we \builder_comb_rhs_array_muxed16 connect \main_sdram_interface_bank1_valid \builder_comb_rhs_array_muxed17 - connect \builder_roundrobin2_request $and$ls180.v:3951$445_Y - connect \builder_roundrobin2_ce $and$ls180.v:3952$448_Y + connect \builder_roundrobin2_request $and$ls180.v:3947$444_Y + connect \builder_roundrobin2_ce $and$ls180.v:3948$447_Y connect \main_sdram_interface_bank2_addr \builder_comb_rhs_array_muxed18 connect \main_sdram_interface_bank2_we \builder_comb_rhs_array_muxed19 connect \main_sdram_interface_bank2_valid \builder_comb_rhs_array_muxed20 - connect \builder_roundrobin3_request $and$ls180.v:3956$461_Y - connect \builder_roundrobin3_ce $and$ls180.v:3957$464_Y + connect \builder_roundrobin3_request $and$ls180.v:3952$460_Y + connect \builder_roundrobin3_ce $and$ls180.v:3953$463_Y connect \main_sdram_interface_bank3_addr \builder_comb_rhs_array_muxed21 connect \main_sdram_interface_bank3_we \builder_comb_rhs_array_muxed22 connect \main_sdram_interface_bank3_valid \builder_comb_rhs_array_muxed23 - connect \main_port_cmd_ready $or$ls180.v:3961$528_Y + connect \main_port_cmd_ready $or$ls180.v:3957$527_Y connect \main_port_wdata_ready \builder_new_master_wdata_ready connect \main_port_rdata_valid \builder_new_master_rdata_valid3 connect \main_port_rdata_payload_data \main_sdram_interface_rdata @@ -128697,22 +128663,22 @@ module \ls180 connect \builder_roundrobin1_grant 1'0 connect \builder_roundrobin2_grant 1'0 connect \builder_roundrobin3_grant 1'0 - connect \main_converter_reset $not$ls180.v:3983$530_Y + connect \main_converter_reset $not$ls180.v:3979$529_Y connect \main_wb_sdram_dat_r { \main_litedram_wb_dat_r \main_converter_dat_r [31:16] } - connect \main_port_cmd_payload_addr $sub$ls180.v:4043$541_Y [23:0] + connect \main_port_cmd_payload_addr $sub$ls180.v:4039$540_Y [23:0] connect \main_port_cmd_payload_we \main_litedram_wb_we connect \main_port_wdata_payload_data \main_litedram_wb_dat_w connect \main_port_wdata_payload_we \main_litedram_wb_sel connect \main_litedram_wb_dat_r \main_port_rdata_payload_data - connect \main_port_flush $not$ls180.v:4048$542_Y - connect \main_port_cmd_last $not$ls180.v:4049$543_Y - connect \main_port_cmd_valid $and$ls180.v:4050$546_Y - connect \main_port_wdata_valid $and$ls180.v:4051$550_Y - connect \main_port_rdata_ready $and$ls180.v:4052$553_Y - connect \main_litedram_wb_ack $and$ls180.v:4053$558_Y - connect \main_ack_cmd $or$ls180.v:4054$560_Y - connect \main_ack_wdata $or$ls180.v:4055$562_Y - connect \main_ack_rdata $and$ls180.v:4056$563_Y + connect \main_port_flush $not$ls180.v:4044$541_Y + connect \main_port_cmd_last $not$ls180.v:4045$542_Y + connect \main_port_cmd_valid $and$ls180.v:4046$545_Y + connect \main_port_wdata_valid $and$ls180.v:4047$549_Y + connect \main_port_rdata_ready $and$ls180.v:4048$552_Y + connect \main_litedram_wb_ack $and$ls180.v:4049$557_Y + connect \main_ack_cmd $or$ls180.v:4050$559_Y + connect \main_ack_wdata $or$ls180.v:4051$561_Y + connect \main_ack_rdata $and$ls180.v:4052$562_Y connect \main_uart_uart_sink_valid \main_source_valid connect \main_source_ready \main_uart_uart_sink_ready connect \main_uart_uart_sink_first \main_source_first @@ -128725,25 +128691,25 @@ module \ls180 connect \main_sink_payload_data \main_uart_uart_source_payload_data connect \main_uart_tx_fifo_sink_valid \main_uart_rxtx_re connect \main_uart_tx_fifo_sink_payload_data \main_uart_rxtx_r - connect \main_uart_txfull_status $not$ls180.v:4069$564_Y - connect \main_uart_txempty_status $not$ls180.v:4070$565_Y + connect \main_uart_txfull_status $not$ls180.v:4065$563_Y + connect \main_uart_txempty_status $not$ls180.v:4066$564_Y connect \main_uart_uart_source_valid \main_uart_tx_fifo_source_valid connect \main_uart_tx_fifo_source_ready \main_uart_uart_source_ready connect \main_uart_uart_source_first \main_uart_tx_fifo_source_first connect \main_uart_uart_source_last \main_uart_tx_fifo_source_last connect \main_uart_uart_source_payload_data \main_uart_tx_fifo_source_payload_data - connect \main_uart_tx_trigger $not$ls180.v:4076$566_Y + connect \main_uart_tx_trigger $not$ls180.v:4072$565_Y connect \main_uart_rx_fifo_sink_valid \main_uart_uart_sink_valid connect \main_uart_uart_sink_ready \main_uart_rx_fifo_sink_ready connect \main_uart_rx_fifo_sink_first \main_uart_uart_sink_first connect \main_uart_rx_fifo_sink_last \main_uart_uart_sink_last connect \main_uart_rx_fifo_sink_payload_data \main_uart_uart_sink_payload_data - connect \main_uart_rxempty_status $not$ls180.v:4082$567_Y - connect \main_uart_rxfull_status $not$ls180.v:4083$568_Y + connect \main_uart_rxempty_status $not$ls180.v:4078$566_Y + connect \main_uart_rxfull_status $not$ls180.v:4079$567_Y connect \main_uart_rxtx_w \main_uart_rx_fifo_source_payload_data - connect \main_uart_rx_fifo_source_ready $or$ls180.v:4085$570_Y - connect \main_uart_rx_trigger $not$ls180.v:4086$571_Y - connect \main_uart_irq $or$ls180.v:4109$580_Y + connect \main_uart_rx_fifo_source_ready $or$ls180.v:4081$569_Y + connect \main_uart_rx_trigger $not$ls180.v:4082$570_Y + connect \main_uart_irq $or$ls180.v:4105$579_Y connect \main_uart_tx_status \main_uart_tx_trigger connect \main_uart_rx_status \main_uart_rx_trigger connect \main_uart_tx_fifo_syncfifo_din { \main_uart_tx_fifo_fifo_in_last \main_uart_tx_fifo_fifo_in_first \main_uart_tx_fifo_fifo_in_payload_data } @@ -128758,16 +128724,16 @@ module \ls180 connect \main_uart_tx_fifo_source_last \main_uart_tx_fifo_fifo_out_last connect \main_uart_tx_fifo_source_payload_data \main_uart_tx_fifo_fifo_out_payload_data connect \main_uart_tx_fifo_re \main_uart_tx_fifo_source_ready - connect \main_uart_tx_fifo_syncfifo_re $and$ls180.v:4124$583_Y - connect \main_uart_tx_fifo_level1 $add$ls180.v:4125$584_Y + connect \main_uart_tx_fifo_syncfifo_re $and$ls180.v:4120$582_Y + connect \main_uart_tx_fifo_level1 $add$ls180.v:4121$583_Y connect \main_uart_tx_fifo_wrport_dat_w \main_uart_tx_fifo_syncfifo_din - connect \main_uart_tx_fifo_wrport_we $and$ls180.v:4135$588_Y - connect \main_uart_tx_fifo_do_read $and$ls180.v:4136$589_Y + connect \main_uart_tx_fifo_wrport_we $and$ls180.v:4131$587_Y + connect \main_uart_tx_fifo_do_read $and$ls180.v:4132$588_Y connect \main_uart_tx_fifo_rdport_adr \main_uart_tx_fifo_consume connect \main_uart_tx_fifo_syncfifo_dout \main_uart_tx_fifo_rdport_dat_r connect \main_uart_tx_fifo_rdport_re \main_uart_tx_fifo_do_read - connect \main_uart_tx_fifo_syncfifo_writable $ne$ls180.v:4140$590_Y - connect \main_uart_tx_fifo_syncfifo_readable $ne$ls180.v:4141$591_Y + connect \main_uart_tx_fifo_syncfifo_writable $ne$ls180.v:4136$589_Y + connect \main_uart_tx_fifo_syncfifo_readable $ne$ls180.v:4137$590_Y connect \main_uart_rx_fifo_syncfifo_din { \main_uart_rx_fifo_fifo_in_last \main_uart_rx_fifo_fifo_in_first \main_uart_rx_fifo_fifo_in_payload_data } connect { \main_uart_rx_fifo_fifo_out_last \main_uart_rx_fifo_fifo_out_first \main_uart_rx_fifo_fifo_out_payload_data } \main_uart_rx_fifo_syncfifo_dout connect \main_uart_rx_fifo_sink_ready \main_uart_rx_fifo_syncfifo_writable @@ -128780,16 +128746,16 @@ module \ls180 connect \main_uart_rx_fifo_source_last \main_uart_rx_fifo_fifo_out_last connect \main_uart_rx_fifo_source_payload_data \main_uart_rx_fifo_fifo_out_payload_data connect \main_uart_rx_fifo_re \main_uart_rx_fifo_source_ready - connect \main_uart_rx_fifo_syncfifo_re $and$ls180.v:4154$594_Y - connect \main_uart_rx_fifo_level1 $add$ls180.v:4155$595_Y + connect \main_uart_rx_fifo_syncfifo_re $and$ls180.v:4150$593_Y + connect \main_uart_rx_fifo_level1 $add$ls180.v:4151$594_Y connect \main_uart_rx_fifo_wrport_dat_w \main_uart_rx_fifo_syncfifo_din - connect \main_uart_rx_fifo_wrport_we $and$ls180.v:4165$599_Y - connect \main_uart_rx_fifo_do_read $and$ls180.v:4166$600_Y + connect \main_uart_rx_fifo_wrport_we $and$ls180.v:4161$598_Y + connect \main_uart_rx_fifo_do_read $and$ls180.v:4162$599_Y connect \main_uart_rx_fifo_rdport_adr \main_uart_rx_fifo_consume connect \main_uart_rx_fifo_syncfifo_dout \main_uart_rx_fifo_rdport_dat_r connect \main_uart_rx_fifo_rdport_re \main_uart_rx_fifo_do_read - connect \main_uart_rx_fifo_syncfifo_writable $ne$ls180.v:4170$601_Y - connect \main_uart_rx_fifo_syncfifo_readable $ne$ls180.v:4171$602_Y + connect \main_uart_rx_fifo_syncfifo_writable $ne$ls180.v:4166$600_Y + connect \main_uart_rx_fifo_syncfifo_readable $ne$ls180.v:4167$601_Y connect \main_gpio_pads_i \main_libresocsim_libresoc_constraintmanager0_gpio0_i connect \main_libresocsim_libresoc_constraintmanager0_gpio0_o \main_gpio_pads_o connect \main_libresocsim_libresoc_constraintmanager0_gpio0_oe \main_gpio_pads_oe @@ -128802,14 +128768,14 @@ module \ls180 connect \main_spi_master_miso_status \main_spi_master_miso connect \main_spi_master_cs \main_spi_master_cs_storage connect \main_spi_master_loopback \main_spi_master_loopback_storage - connect \main_spi_master_clk_rise $eq$ls180.v:4184$604_Y - connect \main_spi_master_clk_fall $eq$ls180.v:4185$606_Y + connect \main_spi_master_clk_rise $eq$ls180.v:4180$603_Y + connect \main_spi_master_clk_fall $eq$ls180.v:4181$605_Y connect \main_sdphy_status 1'0 - connect \main_sdphy_sdpads_clk $or$ls180.v:4236$614_Y - connect \main_sdphy_sdpads_cmd_oe $or$ls180.v:4237$618_Y - connect \main_sdphy_sdpads_cmd_o $or$ls180.v:4238$622_Y - connect \main_sdphy_sdpads_data_oe $or$ls180.v:4239$626_Y - connect \main_sdphy_sdpads_data_o $or$ls180.v:4240$630_Y + connect \main_sdphy_sdpads_clk $or$ls180.v:4232$613_Y + connect \main_sdphy_sdpads_cmd_oe $or$ls180.v:4233$617_Y + connect \main_sdphy_sdpads_cmd_o $or$ls180.v:4234$621_Y + connect \main_sdphy_sdpads_data_oe $or$ls180.v:4235$625_Y + connect \main_sdphy_sdpads_data_o $or$ls180.v:4236$629_Y connect \main_sdphy_init_pads_out_ready \main_sdphy_clocker_ce connect \main_sdphy_cmdw_pads_out_ready \main_sdphy_clocker_ce connect \main_sdphy_cmdr_pads_out_ready \main_sdphy_clocker_ce @@ -128830,8 +128796,8 @@ module \ls180 connect \main_sdphy_datar_pads_in_pads_in_valid \main_sdphy_clocker_ce connect \main_sdphy_datar_pads_in_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i connect \main_sdphy_datar_pads_in_pads_in_payload_data_i \main_sdphy_sdpads_data_i - connect \main_sdphy_clocker_stop $or$ls180.v:4261$631_Y - connect \main_sdphy_clocker_ce $and$ls180.v:4291$634_Y + connect \main_sdphy_clocker_stop $or$ls180.v:4257$630_Y + connect \main_sdphy_clocker_ce $and$ls180.v:4287$633_Y connect \main_sdphy_cmdr_cmdr_pads_in_valid \main_sdphy_cmdr_pads_in_pads_in_valid connect \main_sdphy_cmdr_pads_in_pads_in_ready \main_sdphy_cmdr_cmdr_pads_in_ready connect \main_sdphy_cmdr_cmdr_pads_in_first \main_sdphy_cmdr_pads_in_pads_in_first @@ -128843,8 +128809,8 @@ module \ls180 connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_i \main_sdphy_cmdr_pads_in_pads_in_payload_data_i connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_o \main_sdphy_cmdr_pads_in_pads_in_payload_data_o connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_oe \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe - connect \main_sdphy_cmdr_cmdr_start $eq$ls180.v:4414$644_Y - connect \main_sdphy_cmdr_cmdr_converter_sink_valid $and$ls180.v:4415$646_Y + connect \main_sdphy_cmdr_cmdr_start $eq$ls180.v:4410$643_Y + connect \main_sdphy_cmdr_cmdr_converter_sink_valid $and$ls180.v:4411$645_Y connect \main_sdphy_cmdr_cmdr_converter_sink_payload_data \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i connect \main_sdphy_cmdr_cmdr_buf_sink_valid \main_sdphy_cmdr_cmdr_source_source_valid1 connect \main_sdphy_cmdr_cmdr_source_source_ready1 \main_sdphy_cmdr_cmdr_buf_sink_ready @@ -128861,10 +128827,10 @@ module \ls180 connect \main_sdphy_cmdr_cmdr_source_source_first1 \main_sdphy_cmdr_cmdr_converter_source_first connect \main_sdphy_cmdr_cmdr_source_source_last1 \main_sdphy_cmdr_cmdr_converter_source_last connect \main_sdphy_cmdr_cmdr_source_source_payload_data1 \main_sdphy_cmdr_cmdr_converter_source_payload_data - connect \main_sdphy_cmdr_cmdr_converter_sink_ready $or$ls180.v:4432$648_Y + connect \main_sdphy_cmdr_cmdr_converter_sink_ready $or$ls180.v:4428$647_Y connect \main_sdphy_cmdr_cmdr_converter_source_valid \main_sdphy_cmdr_cmdr_converter_strobe_all - connect \main_sdphy_cmdr_cmdr_converter_load_part $and$ls180.v:4434$649_Y - connect \main_sdphy_cmdr_cmdr_buf_sink_ready $or$ls180.v:4435$651_Y + connect \main_sdphy_cmdr_cmdr_converter_load_part $and$ls180.v:4430$648_Y + connect \main_sdphy_cmdr_cmdr_buf_sink_ready $or$ls180.v:4431$650_Y connect \main_sdphy_dataw_crcr_pads_in_valid \main_sdphy_dataw_pads_in_pads_in_valid connect \main_sdphy_dataw_pads_in_pads_in_ready \main_sdphy_dataw_crcr_pads_in_ready connect \main_sdphy_dataw_crcr_pads_in_first \main_sdphy_dataw_pads_in_pads_in_first @@ -128876,8 +128842,8 @@ module \ls180 connect \main_sdphy_dataw_crcr_pads_in_payload_data_i \main_sdphy_dataw_pads_in_pads_in_payload_data_i connect \main_sdphy_dataw_crcr_pads_in_payload_data_o \main_sdphy_dataw_pads_in_pads_in_payload_data_o connect \main_sdphy_dataw_crcr_pads_in_payload_data_oe \main_sdphy_dataw_pads_in_pads_in_payload_data_oe - connect \main_sdphy_dataw_crcr_start $eq$ls180.v:4541$666_Y - connect \main_sdphy_dataw_crcr_converter_sink_valid $and$ls180.v:4542$667_Y + connect \main_sdphy_dataw_crcr_start $eq$ls180.v:4537$665_Y + connect \main_sdphy_dataw_crcr_converter_sink_valid $and$ls180.v:4538$666_Y connect \main_sdphy_dataw_crcr_converter_sink_payload_data \main_sdphy_dataw_crcr_pads_in_payload_data_i [0] connect \main_sdphy_dataw_crcr_buf_sink_valid \main_sdphy_dataw_crcr_source_source_valid1 connect \main_sdphy_dataw_crcr_source_source_ready1 \main_sdphy_dataw_crcr_buf_sink_ready @@ -128894,10 +128860,10 @@ module \ls180 connect \main_sdphy_dataw_crcr_source_source_first1 \main_sdphy_dataw_crcr_converter_source_first connect \main_sdphy_dataw_crcr_source_source_last1 \main_sdphy_dataw_crcr_converter_source_last connect \main_sdphy_dataw_crcr_source_source_payload_data1 \main_sdphy_dataw_crcr_converter_source_payload_data - connect \main_sdphy_dataw_crcr_converter_sink_ready $or$ls180.v:4559$669_Y + connect \main_sdphy_dataw_crcr_converter_sink_ready $or$ls180.v:4555$668_Y connect \main_sdphy_dataw_crcr_converter_source_valid \main_sdphy_dataw_crcr_converter_strobe_all - connect \main_sdphy_dataw_crcr_converter_load_part $and$ls180.v:4561$670_Y - connect \main_sdphy_dataw_crcr_buf_sink_ready $or$ls180.v:4562$672_Y + connect \main_sdphy_dataw_crcr_converter_load_part $and$ls180.v:4557$669_Y + connect \main_sdphy_dataw_crcr_buf_sink_ready $or$ls180.v:4558$671_Y connect \main_sdphy_datar_datar_pads_in_valid \main_sdphy_datar_pads_in_pads_in_valid connect \main_sdphy_datar_pads_in_pads_in_ready \main_sdphy_datar_datar_pads_in_ready connect \main_sdphy_datar_datar_pads_in_first \main_sdphy_datar_pads_in_pads_in_first @@ -128909,8 +128875,8 @@ module \ls180 connect \main_sdphy_datar_datar_pads_in_payload_data_i \main_sdphy_datar_pads_in_pads_in_payload_data_i connect \main_sdphy_datar_datar_pads_in_payload_data_o \main_sdphy_datar_pads_in_pads_in_payload_data_o connect \main_sdphy_datar_datar_pads_in_payload_data_oe \main_sdphy_datar_pads_in_pads_in_payload_data_oe - connect \main_sdphy_datar_datar_start $eq$ls180.v:4675$681_Y - connect \main_sdphy_datar_datar_converter_sink_valid $and$ls180.v:4676$682_Y + connect \main_sdphy_datar_datar_start $eq$ls180.v:4671$680_Y + connect \main_sdphy_datar_datar_converter_sink_valid $and$ls180.v:4672$681_Y connect \main_sdphy_datar_datar_converter_sink_payload_data \main_sdphy_datar_datar_pads_in_payload_data_i connect \main_sdphy_datar_datar_buf_sink_valid \main_sdphy_datar_datar_source_source_valid1 connect \main_sdphy_datar_datar_source_source_ready1 \main_sdphy_datar_datar_buf_sink_ready @@ -128927,10 +128893,10 @@ module \ls180 connect \main_sdphy_datar_datar_source_source_first1 \main_sdphy_datar_datar_converter_source_first connect \main_sdphy_datar_datar_source_source_last1 \main_sdphy_datar_datar_converter_source_last connect \main_sdphy_datar_datar_source_source_payload_data1 \main_sdphy_datar_datar_converter_source_payload_data - connect \main_sdphy_datar_datar_converter_sink_ready $or$ls180.v:4693$684_Y + connect \main_sdphy_datar_datar_converter_sink_ready $or$ls180.v:4689$683_Y connect \main_sdphy_datar_datar_converter_source_valid \main_sdphy_datar_datar_converter_strobe_all - connect \main_sdphy_datar_datar_converter_load_part $and$ls180.v:4695$685_Y - connect \main_sdphy_datar_datar_buf_sink_ready $or$ls180.v:4696$687_Y + connect \main_sdphy_datar_datar_converter_load_part $and$ls180.v:4691$684_Y + connect \main_sdphy_datar_datar_buf_sink_ready $or$ls180.v:4692$686_Y connect \main_sdcore_crc16_inserter_sink_valid \main_sdcore_sink_sink_valid connect \main_sdcore_sink_sink_ready \main_sdcore_crc16_inserter_sink_ready connect \main_sdcore_crc16_inserter_sink_first \main_sdcore_sink_sink_first @@ -128944,88 +128910,88 @@ module \ls180 connect \main_sdcore_cmd_type \main_sdcore_cmd_command_storage [1:0] connect \main_sdcore_data_type \main_sdcore_cmd_command_storage [6:5] connect \main_sdcore_cmd_event_status { 1'0 \main_sdcore_cmd_timeout \main_sdcore_cmd_error \main_sdcore_cmd_done } - connect \main_sdcore_data_event_status { $not$ls180.v:4812$702_Y \main_sdcore_data_timeout \main_sdcore_data_error \main_sdcore_data_done } + connect \main_sdcore_data_event_status { $not$ls180.v:4808$701_Y \main_sdcore_data_timeout \main_sdcore_data_error \main_sdcore_data_done } connect \main_sdcore_crc7_inserter_val { 2'01 \main_sdcore_cmd_command_storage [13:8] \main_sdcore_cmd_argument_storage } connect \main_sdcore_crc7_inserter_clr 1'1 connect \main_sdcore_crc7_inserter_enable 1'1 - connect \main_sdcore_crc7_inserter_crcreg1 { \main_sdcore_crc7_inserter_crcreg0 [5:3] $xor$ls180.v:4816$705_Y \main_sdcore_crc7_inserter_crcreg0 [1:0] $xor$ls180.v:4816$703_Y } - connect \main_sdcore_crc7_inserter_crcreg2 { \main_sdcore_crc7_inserter_crcreg1 [5:3] $xor$ls180.v:4817$708_Y \main_sdcore_crc7_inserter_crcreg1 [1:0] $xor$ls180.v:4817$706_Y } - connect \main_sdcore_crc7_inserter_crcreg3 { \main_sdcore_crc7_inserter_crcreg2 [5:3] $xor$ls180.v:4818$711_Y \main_sdcore_crc7_inserter_crcreg2 [1:0] $xor$ls180.v:4818$709_Y } - connect \main_sdcore_crc7_inserter_crcreg4 { \main_sdcore_crc7_inserter_crcreg3 [5:3] $xor$ls180.v:4819$714_Y \main_sdcore_crc7_inserter_crcreg3 [1:0] $xor$ls180.v:4819$712_Y } - connect \main_sdcore_crc7_inserter_crcreg5 { \main_sdcore_crc7_inserter_crcreg4 [5:3] $xor$ls180.v:4820$717_Y \main_sdcore_crc7_inserter_crcreg4 [1:0] $xor$ls180.v:4820$715_Y } - connect \main_sdcore_crc7_inserter_crcreg6 { \main_sdcore_crc7_inserter_crcreg5 [5:3] $xor$ls180.v:4821$720_Y \main_sdcore_crc7_inserter_crcreg5 [1:0] $xor$ls180.v:4821$718_Y } - connect \main_sdcore_crc7_inserter_crcreg7 { \main_sdcore_crc7_inserter_crcreg6 [5:3] $xor$ls180.v:4822$723_Y \main_sdcore_crc7_inserter_crcreg6 [1:0] $xor$ls180.v:4822$721_Y } - connect \main_sdcore_crc7_inserter_crcreg8 { \main_sdcore_crc7_inserter_crcreg7 [5:3] $xor$ls180.v:4823$726_Y \main_sdcore_crc7_inserter_crcreg7 [1:0] $xor$ls180.v:4823$724_Y } - connect \main_sdcore_crc7_inserter_crcreg9 { \main_sdcore_crc7_inserter_crcreg8 [5:3] $xor$ls180.v:4824$729_Y \main_sdcore_crc7_inserter_crcreg8 [1:0] $xor$ls180.v:4824$727_Y } - connect \main_sdcore_crc7_inserter_crcreg10 { \main_sdcore_crc7_inserter_crcreg9 [5:3] $xor$ls180.v:4825$732_Y \main_sdcore_crc7_inserter_crcreg9 [1:0] $xor$ls180.v:4825$730_Y } - connect \main_sdcore_crc7_inserter_crcreg11 { \main_sdcore_crc7_inserter_crcreg10 [5:3] $xor$ls180.v:4826$735_Y \main_sdcore_crc7_inserter_crcreg10 [1:0] $xor$ls180.v:4826$733_Y } - connect \main_sdcore_crc7_inserter_crcreg12 { \main_sdcore_crc7_inserter_crcreg11 [5:3] $xor$ls180.v:4827$738_Y \main_sdcore_crc7_inserter_crcreg11 [1:0] $xor$ls180.v:4827$736_Y } - connect \main_sdcore_crc7_inserter_crcreg13 { \main_sdcore_crc7_inserter_crcreg12 [5:3] $xor$ls180.v:4828$741_Y \main_sdcore_crc7_inserter_crcreg12 [1:0] $xor$ls180.v:4828$739_Y } - connect \main_sdcore_crc7_inserter_crcreg14 { \main_sdcore_crc7_inserter_crcreg13 [5:3] $xor$ls180.v:4829$744_Y \main_sdcore_crc7_inserter_crcreg13 [1:0] $xor$ls180.v:4829$742_Y } - connect \main_sdcore_crc7_inserter_crcreg15 { \main_sdcore_crc7_inserter_crcreg14 [5:3] $xor$ls180.v:4830$747_Y \main_sdcore_crc7_inserter_crcreg14 [1:0] $xor$ls180.v:4830$745_Y } - connect \main_sdcore_crc7_inserter_crcreg16 { \main_sdcore_crc7_inserter_crcreg15 [5:3] $xor$ls180.v:4831$750_Y \main_sdcore_crc7_inserter_crcreg15 [1:0] $xor$ls180.v:4831$748_Y } - connect \main_sdcore_crc7_inserter_crcreg17 { \main_sdcore_crc7_inserter_crcreg16 [5:3] $xor$ls180.v:4832$753_Y \main_sdcore_crc7_inserter_crcreg16 [1:0] $xor$ls180.v:4832$751_Y } - connect \main_sdcore_crc7_inserter_crcreg18 { \main_sdcore_crc7_inserter_crcreg17 [5:3] $xor$ls180.v:4833$756_Y \main_sdcore_crc7_inserter_crcreg17 [1:0] $xor$ls180.v:4833$754_Y } - connect \main_sdcore_crc7_inserter_crcreg19 { \main_sdcore_crc7_inserter_crcreg18 [5:3] $xor$ls180.v:4834$759_Y \main_sdcore_crc7_inserter_crcreg18 [1:0] $xor$ls180.v:4834$757_Y } - connect \main_sdcore_crc7_inserter_crcreg20 { \main_sdcore_crc7_inserter_crcreg19 [5:3] $xor$ls180.v:4835$762_Y \main_sdcore_crc7_inserter_crcreg19 [1:0] $xor$ls180.v:4835$760_Y } - connect \main_sdcore_crc7_inserter_crcreg21 { \main_sdcore_crc7_inserter_crcreg20 [5:3] $xor$ls180.v:4836$765_Y \main_sdcore_crc7_inserter_crcreg20 [1:0] $xor$ls180.v:4836$763_Y } - connect \main_sdcore_crc7_inserter_crcreg22 { \main_sdcore_crc7_inserter_crcreg21 [5:3] $xor$ls180.v:4837$768_Y \main_sdcore_crc7_inserter_crcreg21 [1:0] $xor$ls180.v:4837$766_Y } - connect \main_sdcore_crc7_inserter_crcreg23 { \main_sdcore_crc7_inserter_crcreg22 [5:3] $xor$ls180.v:4838$771_Y \main_sdcore_crc7_inserter_crcreg22 [1:0] $xor$ls180.v:4838$769_Y } - connect \main_sdcore_crc7_inserter_crcreg24 { \main_sdcore_crc7_inserter_crcreg23 [5:3] $xor$ls180.v:4839$774_Y \main_sdcore_crc7_inserter_crcreg23 [1:0] $xor$ls180.v:4839$772_Y } - connect \main_sdcore_crc7_inserter_crcreg25 { \main_sdcore_crc7_inserter_crcreg24 [5:3] $xor$ls180.v:4840$777_Y \main_sdcore_crc7_inserter_crcreg24 [1:0] $xor$ls180.v:4840$775_Y } - connect \main_sdcore_crc7_inserter_crcreg26 { \main_sdcore_crc7_inserter_crcreg25 [5:3] $xor$ls180.v:4841$780_Y \main_sdcore_crc7_inserter_crcreg25 [1:0] $xor$ls180.v:4841$778_Y } - connect \main_sdcore_crc7_inserter_crcreg27 { \main_sdcore_crc7_inserter_crcreg26 [5:3] $xor$ls180.v:4842$783_Y \main_sdcore_crc7_inserter_crcreg26 [1:0] $xor$ls180.v:4842$781_Y } - connect \main_sdcore_crc7_inserter_crcreg28 { \main_sdcore_crc7_inserter_crcreg27 [5:3] $xor$ls180.v:4843$786_Y \main_sdcore_crc7_inserter_crcreg27 [1:0] $xor$ls180.v:4843$784_Y } - connect \main_sdcore_crc7_inserter_crcreg29 { \main_sdcore_crc7_inserter_crcreg28 [5:3] $xor$ls180.v:4844$789_Y \main_sdcore_crc7_inserter_crcreg28 [1:0] $xor$ls180.v:4844$787_Y } - connect \main_sdcore_crc7_inserter_crcreg30 { \main_sdcore_crc7_inserter_crcreg29 [5:3] $xor$ls180.v:4845$792_Y \main_sdcore_crc7_inserter_crcreg29 [1:0] $xor$ls180.v:4845$790_Y } - connect \main_sdcore_crc7_inserter_crcreg31 { \main_sdcore_crc7_inserter_crcreg30 [5:3] $xor$ls180.v:4846$795_Y \main_sdcore_crc7_inserter_crcreg30 [1:0] $xor$ls180.v:4846$793_Y } - connect \main_sdcore_crc7_inserter_crcreg32 { \main_sdcore_crc7_inserter_crcreg31 [5:3] $xor$ls180.v:4847$798_Y \main_sdcore_crc7_inserter_crcreg31 [1:0] $xor$ls180.v:4847$796_Y } - connect \main_sdcore_crc7_inserter_crcreg33 { \main_sdcore_crc7_inserter_crcreg32 [5:3] $xor$ls180.v:4848$801_Y \main_sdcore_crc7_inserter_crcreg32 [1:0] $xor$ls180.v:4848$799_Y } - connect \main_sdcore_crc7_inserter_crcreg34 { \main_sdcore_crc7_inserter_crcreg33 [5:3] $xor$ls180.v:4849$804_Y \main_sdcore_crc7_inserter_crcreg33 [1:0] $xor$ls180.v:4849$802_Y } - connect \main_sdcore_crc7_inserter_crcreg35 { \main_sdcore_crc7_inserter_crcreg34 [5:3] $xor$ls180.v:4850$807_Y \main_sdcore_crc7_inserter_crcreg34 [1:0] $xor$ls180.v:4850$805_Y } - connect \main_sdcore_crc7_inserter_crcreg36 { \main_sdcore_crc7_inserter_crcreg35 [5:3] $xor$ls180.v:4851$810_Y \main_sdcore_crc7_inserter_crcreg35 [1:0] $xor$ls180.v:4851$808_Y } - connect \main_sdcore_crc7_inserter_crcreg37 { \main_sdcore_crc7_inserter_crcreg36 [5:3] $xor$ls180.v:4852$813_Y \main_sdcore_crc7_inserter_crcreg36 [1:0] $xor$ls180.v:4852$811_Y } - connect \main_sdcore_crc7_inserter_crcreg38 { \main_sdcore_crc7_inserter_crcreg37 [5:3] $xor$ls180.v:4853$816_Y \main_sdcore_crc7_inserter_crcreg37 [1:0] $xor$ls180.v:4853$814_Y } - connect \main_sdcore_crc7_inserter_crcreg39 { \main_sdcore_crc7_inserter_crcreg38 [5:3] $xor$ls180.v:4854$819_Y \main_sdcore_crc7_inserter_crcreg38 [1:0] $xor$ls180.v:4854$817_Y } - connect \main_sdcore_crc7_inserter_crcreg40 { \main_sdcore_crc7_inserter_crcreg39 [5:3] $xor$ls180.v:4855$822_Y \main_sdcore_crc7_inserter_crcreg39 [1:0] $xor$ls180.v:4855$820_Y } + connect \main_sdcore_crc7_inserter_crcreg1 { \main_sdcore_crc7_inserter_crcreg0 [5:3] $xor$ls180.v:4812$704_Y \main_sdcore_crc7_inserter_crcreg0 [1:0] $xor$ls180.v:4812$702_Y } + connect \main_sdcore_crc7_inserter_crcreg2 { \main_sdcore_crc7_inserter_crcreg1 [5:3] $xor$ls180.v:4813$707_Y \main_sdcore_crc7_inserter_crcreg1 [1:0] $xor$ls180.v:4813$705_Y } + connect \main_sdcore_crc7_inserter_crcreg3 { \main_sdcore_crc7_inserter_crcreg2 [5:3] $xor$ls180.v:4814$710_Y \main_sdcore_crc7_inserter_crcreg2 [1:0] $xor$ls180.v:4814$708_Y } + connect \main_sdcore_crc7_inserter_crcreg4 { \main_sdcore_crc7_inserter_crcreg3 [5:3] $xor$ls180.v:4815$713_Y \main_sdcore_crc7_inserter_crcreg3 [1:0] $xor$ls180.v:4815$711_Y } + connect \main_sdcore_crc7_inserter_crcreg5 { \main_sdcore_crc7_inserter_crcreg4 [5:3] $xor$ls180.v:4816$716_Y \main_sdcore_crc7_inserter_crcreg4 [1:0] $xor$ls180.v:4816$714_Y } + connect \main_sdcore_crc7_inserter_crcreg6 { \main_sdcore_crc7_inserter_crcreg5 [5:3] $xor$ls180.v:4817$719_Y \main_sdcore_crc7_inserter_crcreg5 [1:0] $xor$ls180.v:4817$717_Y } + connect \main_sdcore_crc7_inserter_crcreg7 { \main_sdcore_crc7_inserter_crcreg6 [5:3] $xor$ls180.v:4818$722_Y \main_sdcore_crc7_inserter_crcreg6 [1:0] $xor$ls180.v:4818$720_Y } + connect \main_sdcore_crc7_inserter_crcreg8 { \main_sdcore_crc7_inserter_crcreg7 [5:3] $xor$ls180.v:4819$725_Y \main_sdcore_crc7_inserter_crcreg7 [1:0] $xor$ls180.v:4819$723_Y } + connect \main_sdcore_crc7_inserter_crcreg9 { \main_sdcore_crc7_inserter_crcreg8 [5:3] $xor$ls180.v:4820$728_Y \main_sdcore_crc7_inserter_crcreg8 [1:0] $xor$ls180.v:4820$726_Y } + connect \main_sdcore_crc7_inserter_crcreg10 { \main_sdcore_crc7_inserter_crcreg9 [5:3] $xor$ls180.v:4821$731_Y \main_sdcore_crc7_inserter_crcreg9 [1:0] $xor$ls180.v:4821$729_Y } + connect \main_sdcore_crc7_inserter_crcreg11 { \main_sdcore_crc7_inserter_crcreg10 [5:3] $xor$ls180.v:4822$734_Y \main_sdcore_crc7_inserter_crcreg10 [1:0] $xor$ls180.v:4822$732_Y } + connect \main_sdcore_crc7_inserter_crcreg12 { \main_sdcore_crc7_inserter_crcreg11 [5:3] $xor$ls180.v:4823$737_Y \main_sdcore_crc7_inserter_crcreg11 [1:0] $xor$ls180.v:4823$735_Y } + connect \main_sdcore_crc7_inserter_crcreg13 { \main_sdcore_crc7_inserter_crcreg12 [5:3] $xor$ls180.v:4824$740_Y \main_sdcore_crc7_inserter_crcreg12 [1:0] $xor$ls180.v:4824$738_Y } + connect \main_sdcore_crc7_inserter_crcreg14 { \main_sdcore_crc7_inserter_crcreg13 [5:3] $xor$ls180.v:4825$743_Y \main_sdcore_crc7_inserter_crcreg13 [1:0] $xor$ls180.v:4825$741_Y } + connect \main_sdcore_crc7_inserter_crcreg15 { \main_sdcore_crc7_inserter_crcreg14 [5:3] $xor$ls180.v:4826$746_Y \main_sdcore_crc7_inserter_crcreg14 [1:0] $xor$ls180.v:4826$744_Y } + connect \main_sdcore_crc7_inserter_crcreg16 { \main_sdcore_crc7_inserter_crcreg15 [5:3] $xor$ls180.v:4827$749_Y \main_sdcore_crc7_inserter_crcreg15 [1:0] $xor$ls180.v:4827$747_Y } + connect \main_sdcore_crc7_inserter_crcreg17 { \main_sdcore_crc7_inserter_crcreg16 [5:3] $xor$ls180.v:4828$752_Y \main_sdcore_crc7_inserter_crcreg16 [1:0] $xor$ls180.v:4828$750_Y } + connect \main_sdcore_crc7_inserter_crcreg18 { \main_sdcore_crc7_inserter_crcreg17 [5:3] $xor$ls180.v:4829$755_Y \main_sdcore_crc7_inserter_crcreg17 [1:0] $xor$ls180.v:4829$753_Y } + connect \main_sdcore_crc7_inserter_crcreg19 { \main_sdcore_crc7_inserter_crcreg18 [5:3] $xor$ls180.v:4830$758_Y \main_sdcore_crc7_inserter_crcreg18 [1:0] $xor$ls180.v:4830$756_Y } + connect \main_sdcore_crc7_inserter_crcreg20 { \main_sdcore_crc7_inserter_crcreg19 [5:3] $xor$ls180.v:4831$761_Y \main_sdcore_crc7_inserter_crcreg19 [1:0] $xor$ls180.v:4831$759_Y } + connect \main_sdcore_crc7_inserter_crcreg21 { \main_sdcore_crc7_inserter_crcreg20 [5:3] $xor$ls180.v:4832$764_Y \main_sdcore_crc7_inserter_crcreg20 [1:0] $xor$ls180.v:4832$762_Y } + connect \main_sdcore_crc7_inserter_crcreg22 { \main_sdcore_crc7_inserter_crcreg21 [5:3] $xor$ls180.v:4833$767_Y \main_sdcore_crc7_inserter_crcreg21 [1:0] $xor$ls180.v:4833$765_Y } + connect \main_sdcore_crc7_inserter_crcreg23 { \main_sdcore_crc7_inserter_crcreg22 [5:3] $xor$ls180.v:4834$770_Y \main_sdcore_crc7_inserter_crcreg22 [1:0] $xor$ls180.v:4834$768_Y } + connect \main_sdcore_crc7_inserter_crcreg24 { \main_sdcore_crc7_inserter_crcreg23 [5:3] $xor$ls180.v:4835$773_Y \main_sdcore_crc7_inserter_crcreg23 [1:0] $xor$ls180.v:4835$771_Y } + connect \main_sdcore_crc7_inserter_crcreg25 { \main_sdcore_crc7_inserter_crcreg24 [5:3] $xor$ls180.v:4836$776_Y \main_sdcore_crc7_inserter_crcreg24 [1:0] $xor$ls180.v:4836$774_Y } + connect \main_sdcore_crc7_inserter_crcreg26 { \main_sdcore_crc7_inserter_crcreg25 [5:3] $xor$ls180.v:4837$779_Y \main_sdcore_crc7_inserter_crcreg25 [1:0] $xor$ls180.v:4837$777_Y } + connect \main_sdcore_crc7_inserter_crcreg27 { \main_sdcore_crc7_inserter_crcreg26 [5:3] $xor$ls180.v:4838$782_Y \main_sdcore_crc7_inserter_crcreg26 [1:0] $xor$ls180.v:4838$780_Y } + connect \main_sdcore_crc7_inserter_crcreg28 { \main_sdcore_crc7_inserter_crcreg27 [5:3] $xor$ls180.v:4839$785_Y \main_sdcore_crc7_inserter_crcreg27 [1:0] $xor$ls180.v:4839$783_Y } + connect \main_sdcore_crc7_inserter_crcreg29 { \main_sdcore_crc7_inserter_crcreg28 [5:3] $xor$ls180.v:4840$788_Y \main_sdcore_crc7_inserter_crcreg28 [1:0] $xor$ls180.v:4840$786_Y } + connect \main_sdcore_crc7_inserter_crcreg30 { \main_sdcore_crc7_inserter_crcreg29 [5:3] $xor$ls180.v:4841$791_Y \main_sdcore_crc7_inserter_crcreg29 [1:0] $xor$ls180.v:4841$789_Y } + connect \main_sdcore_crc7_inserter_crcreg31 { \main_sdcore_crc7_inserter_crcreg30 [5:3] $xor$ls180.v:4842$794_Y \main_sdcore_crc7_inserter_crcreg30 [1:0] $xor$ls180.v:4842$792_Y } + connect \main_sdcore_crc7_inserter_crcreg32 { \main_sdcore_crc7_inserter_crcreg31 [5:3] $xor$ls180.v:4843$797_Y \main_sdcore_crc7_inserter_crcreg31 [1:0] $xor$ls180.v:4843$795_Y } + connect \main_sdcore_crc7_inserter_crcreg33 { \main_sdcore_crc7_inserter_crcreg32 [5:3] $xor$ls180.v:4844$800_Y \main_sdcore_crc7_inserter_crcreg32 [1:0] $xor$ls180.v:4844$798_Y } + connect \main_sdcore_crc7_inserter_crcreg34 { \main_sdcore_crc7_inserter_crcreg33 [5:3] $xor$ls180.v:4845$803_Y \main_sdcore_crc7_inserter_crcreg33 [1:0] $xor$ls180.v:4845$801_Y } + connect \main_sdcore_crc7_inserter_crcreg35 { \main_sdcore_crc7_inserter_crcreg34 [5:3] $xor$ls180.v:4846$806_Y \main_sdcore_crc7_inserter_crcreg34 [1:0] $xor$ls180.v:4846$804_Y } + connect \main_sdcore_crc7_inserter_crcreg36 { \main_sdcore_crc7_inserter_crcreg35 [5:3] $xor$ls180.v:4847$809_Y \main_sdcore_crc7_inserter_crcreg35 [1:0] $xor$ls180.v:4847$807_Y } + connect \main_sdcore_crc7_inserter_crcreg37 { \main_sdcore_crc7_inserter_crcreg36 [5:3] $xor$ls180.v:4848$812_Y \main_sdcore_crc7_inserter_crcreg36 [1:0] $xor$ls180.v:4848$810_Y } + connect \main_sdcore_crc7_inserter_crcreg38 { \main_sdcore_crc7_inserter_crcreg37 [5:3] $xor$ls180.v:4849$815_Y \main_sdcore_crc7_inserter_crcreg37 [1:0] $xor$ls180.v:4849$813_Y } + connect \main_sdcore_crc7_inserter_crcreg39 { \main_sdcore_crc7_inserter_crcreg38 [5:3] $xor$ls180.v:4850$818_Y \main_sdcore_crc7_inserter_crcreg38 [1:0] $xor$ls180.v:4850$816_Y } + connect \main_sdcore_crc7_inserter_crcreg40 { \main_sdcore_crc7_inserter_crcreg39 [5:3] $xor$ls180.v:4851$821_Y \main_sdcore_crc7_inserter_crcreg39 [1:0] $xor$ls180.v:4851$819_Y } connect \main_sdcore_crc16_inserter_crc0_val { \main_sdcore_crc16_inserter_sink_payload_data [4] \main_sdcore_crc16_inserter_sink_payload_data [0] } - connect \main_sdcore_crc16_inserter_crc0_clr $and$ls180.v:4865$825_Y - connect \main_sdcore_crc16_inserter_crc0_enable $and$ls180.v:4866$826_Y + connect \main_sdcore_crc16_inserter_crc0_clr $and$ls180.v:4861$824_Y + connect \main_sdcore_crc16_inserter_crc0_enable $and$ls180.v:4862$825_Y connect \main_sdcore_crc16_inserter_crc1_val { \main_sdcore_crc16_inserter_sink_payload_data [5] \main_sdcore_crc16_inserter_sink_payload_data [1] } - connect \main_sdcore_crc16_inserter_crc1_clr $and$ls180.v:4868$828_Y - connect \main_sdcore_crc16_inserter_crc1_enable $and$ls180.v:4869$829_Y + connect \main_sdcore_crc16_inserter_crc1_clr $and$ls180.v:4864$827_Y + connect \main_sdcore_crc16_inserter_crc1_enable $and$ls180.v:4865$828_Y connect \main_sdcore_crc16_inserter_crc2_val { \main_sdcore_crc16_inserter_sink_payload_data [6] \main_sdcore_crc16_inserter_sink_payload_data [2] } - connect \main_sdcore_crc16_inserter_crc2_clr $and$ls180.v:4871$831_Y - connect \main_sdcore_crc16_inserter_crc2_enable $and$ls180.v:4872$832_Y + connect \main_sdcore_crc16_inserter_crc2_clr $and$ls180.v:4867$830_Y + connect \main_sdcore_crc16_inserter_crc2_enable $and$ls180.v:4868$831_Y connect \main_sdcore_crc16_inserter_crc3_val { \main_sdcore_crc16_inserter_sink_payload_data [7] \main_sdcore_crc16_inserter_sink_payload_data [3] } - connect \main_sdcore_crc16_inserter_crc3_clr $and$ls180.v:4874$834_Y - connect \main_sdcore_crc16_inserter_crc3_enable $and$ls180.v:4875$835_Y - connect \main_sdcore_crc16_inserter_crc0_crcreg1 { \main_sdcore_crc16_inserter_crc0_crcreg0 [14:12] $xor$ls180.v:4876$840_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [10:5] $xor$ls180.v:4876$838_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [3:0] $xor$ls180.v:4876$836_Y } - connect \main_sdcore_crc16_inserter_crc0_crcreg2 { \main_sdcore_crc16_inserter_crc0_crcreg1 [14:12] $xor$ls180.v:4877$845_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [10:5] $xor$ls180.v:4877$843_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [3:0] $xor$ls180.v:4877$841_Y } - connect \main_sdcore_crc16_inserter_crc1_crcreg1 { \main_sdcore_crc16_inserter_crc1_crcreg0 [14:12] $xor$ls180.v:4886$851_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [10:5] $xor$ls180.v:4886$849_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [3:0] $xor$ls180.v:4886$847_Y } - connect \main_sdcore_crc16_inserter_crc1_crcreg2 { \main_sdcore_crc16_inserter_crc1_crcreg1 [14:12] $xor$ls180.v:4887$856_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [10:5] $xor$ls180.v:4887$854_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [3:0] $xor$ls180.v:4887$852_Y } - connect \main_sdcore_crc16_inserter_crc2_crcreg1 { \main_sdcore_crc16_inserter_crc2_crcreg0 [14:12] $xor$ls180.v:4896$862_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [10:5] $xor$ls180.v:4896$860_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [3:0] $xor$ls180.v:4896$858_Y } - connect \main_sdcore_crc16_inserter_crc2_crcreg2 { \main_sdcore_crc16_inserter_crc2_crcreg1 [14:12] $xor$ls180.v:4897$867_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [10:5] $xor$ls180.v:4897$865_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [3:0] $xor$ls180.v:4897$863_Y } - connect \main_sdcore_crc16_inserter_crc3_crcreg1 { \main_sdcore_crc16_inserter_crc3_crcreg0 [14:12] $xor$ls180.v:4906$873_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [10:5] $xor$ls180.v:4906$871_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [3:0] $xor$ls180.v:4906$869_Y } - connect \main_sdcore_crc16_inserter_crc3_crcreg2 { \main_sdcore_crc16_inserter_crc3_crcreg1 [14:12] $xor$ls180.v:4907$878_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [10:5] $xor$ls180.v:4907$876_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [3:0] $xor$ls180.v:4907$874_Y } + connect \main_sdcore_crc16_inserter_crc3_clr $and$ls180.v:4870$833_Y + connect \main_sdcore_crc16_inserter_crc3_enable $and$ls180.v:4871$834_Y + connect \main_sdcore_crc16_inserter_crc0_crcreg1 { \main_sdcore_crc16_inserter_crc0_crcreg0 [14:12] $xor$ls180.v:4872$839_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [10:5] $xor$ls180.v:4872$837_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [3:0] $xor$ls180.v:4872$835_Y } + connect \main_sdcore_crc16_inserter_crc0_crcreg2 { \main_sdcore_crc16_inserter_crc0_crcreg1 [14:12] $xor$ls180.v:4873$844_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [10:5] $xor$ls180.v:4873$842_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [3:0] $xor$ls180.v:4873$840_Y } + connect \main_sdcore_crc16_inserter_crc1_crcreg1 { \main_sdcore_crc16_inserter_crc1_crcreg0 [14:12] $xor$ls180.v:4882$850_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [10:5] $xor$ls180.v:4882$848_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [3:0] $xor$ls180.v:4882$846_Y } + connect \main_sdcore_crc16_inserter_crc1_crcreg2 { \main_sdcore_crc16_inserter_crc1_crcreg1 [14:12] $xor$ls180.v:4883$855_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [10:5] $xor$ls180.v:4883$853_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [3:0] $xor$ls180.v:4883$851_Y } + connect \main_sdcore_crc16_inserter_crc2_crcreg1 { \main_sdcore_crc16_inserter_crc2_crcreg0 [14:12] $xor$ls180.v:4892$861_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [10:5] $xor$ls180.v:4892$859_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [3:0] $xor$ls180.v:4892$857_Y } + connect \main_sdcore_crc16_inserter_crc2_crcreg2 { \main_sdcore_crc16_inserter_crc2_crcreg1 [14:12] $xor$ls180.v:4893$866_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [10:5] $xor$ls180.v:4893$864_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [3:0] $xor$ls180.v:4893$862_Y } + connect \main_sdcore_crc16_inserter_crc3_crcreg1 { \main_sdcore_crc16_inserter_crc3_crcreg0 [14:12] $xor$ls180.v:4902$872_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [10:5] $xor$ls180.v:4902$870_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [3:0] $xor$ls180.v:4902$868_Y } + connect \main_sdcore_crc16_inserter_crc3_crcreg2 { \main_sdcore_crc16_inserter_crc3_crcreg1 [14:12] $xor$ls180.v:4903$877_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [10:5] $xor$ls180.v:4903$875_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [3:0] $xor$ls180.v:4903$873_Y } connect \main_sdcore_crc16_checker_crc0_val { \main_sdcore_crc16_checker_val [7] \main_sdcore_crc16_checker_val [3] } - connect \main_sdcore_crc16_checker_crc0_enable $and$ls180.v:5003$894_Y + connect \main_sdcore_crc16_checker_crc0_enable $and$ls180.v:4999$893_Y connect \main_sdcore_crc16_checker_crc1_val { \main_sdcore_crc16_checker_val [6] \main_sdcore_crc16_checker_val [2] } - connect \main_sdcore_crc16_checker_crc1_enable $and$ls180.v:5013$897_Y + connect \main_sdcore_crc16_checker_crc1_enable $and$ls180.v:5009$896_Y connect \main_sdcore_crc16_checker_crc2_val { \main_sdcore_crc16_checker_val [5] \main_sdcore_crc16_checker_val [1] } - connect \main_sdcore_crc16_checker_crc2_enable $and$ls180.v:5023$900_Y + connect \main_sdcore_crc16_checker_crc2_enable $and$ls180.v:5019$899_Y connect \main_sdcore_crc16_checker_crc3_val { \main_sdcore_crc16_checker_val [4] \main_sdcore_crc16_checker_val [0] } - connect \main_sdcore_crc16_checker_crc3_enable $and$ls180.v:5033$903_Y + connect \main_sdcore_crc16_checker_crc3_enable $and$ls180.v:5029$902_Y connect \main_sdcore_crc16_checker_source_payload_data \main_sdcore_crc16_checker_val connect \main_sdcore_crc16_checker_source_last \main_sdcore_crc16_checker_sink_last - connect \main_sdcore_crc16_checker_crc0_crcreg1 { \main_sdcore_crc16_checker_crc0_crcreg0 [14:12] $xor$ls180.v:5058$915_Y \main_sdcore_crc16_checker_crc0_crcreg0 [10:5] $xor$ls180.v:5058$913_Y \main_sdcore_crc16_checker_crc0_crcreg0 [3:0] $xor$ls180.v:5058$911_Y } - connect \main_sdcore_crc16_checker_crc0_crcreg2 { \main_sdcore_crc16_checker_crc0_crcreg1 [14:12] $xor$ls180.v:5059$920_Y \main_sdcore_crc16_checker_crc0_crcreg1 [10:5] $xor$ls180.v:5059$918_Y \main_sdcore_crc16_checker_crc0_crcreg1 [3:0] $xor$ls180.v:5059$916_Y } - connect \main_sdcore_crc16_checker_crc1_crcreg1 { \main_sdcore_crc16_checker_crc1_crcreg0 [14:12] $xor$ls180.v:5068$926_Y \main_sdcore_crc16_checker_crc1_crcreg0 [10:5] $xor$ls180.v:5068$924_Y \main_sdcore_crc16_checker_crc1_crcreg0 [3:0] $xor$ls180.v:5068$922_Y } - connect \main_sdcore_crc16_checker_crc1_crcreg2 { \main_sdcore_crc16_checker_crc1_crcreg1 [14:12] $xor$ls180.v:5069$931_Y \main_sdcore_crc16_checker_crc1_crcreg1 [10:5] $xor$ls180.v:5069$929_Y \main_sdcore_crc16_checker_crc1_crcreg1 [3:0] $xor$ls180.v:5069$927_Y } - connect \main_sdcore_crc16_checker_crc2_crcreg1 { \main_sdcore_crc16_checker_crc2_crcreg0 [14:12] $xor$ls180.v:5078$937_Y \main_sdcore_crc16_checker_crc2_crcreg0 [10:5] $xor$ls180.v:5078$935_Y \main_sdcore_crc16_checker_crc2_crcreg0 [3:0] $xor$ls180.v:5078$933_Y } - connect \main_sdcore_crc16_checker_crc2_crcreg2 { \main_sdcore_crc16_checker_crc2_crcreg1 [14:12] $xor$ls180.v:5079$942_Y \main_sdcore_crc16_checker_crc2_crcreg1 [10:5] $xor$ls180.v:5079$940_Y \main_sdcore_crc16_checker_crc2_crcreg1 [3:0] $xor$ls180.v:5079$938_Y } - connect \main_sdcore_crc16_checker_crc3_crcreg1 { \main_sdcore_crc16_checker_crc3_crcreg0 [14:12] $xor$ls180.v:5088$948_Y \main_sdcore_crc16_checker_crc3_crcreg0 [10:5] $xor$ls180.v:5088$946_Y \main_sdcore_crc16_checker_crc3_crcreg0 [3:0] $xor$ls180.v:5088$944_Y } - connect \main_sdcore_crc16_checker_crc3_crcreg2 { \main_sdcore_crc16_checker_crc3_crcreg1 [14:12] $xor$ls180.v:5089$953_Y \main_sdcore_crc16_checker_crc3_crcreg1 [10:5] $xor$ls180.v:5089$951_Y \main_sdcore_crc16_checker_crc3_crcreg1 [3:0] $xor$ls180.v:5089$949_Y } + connect \main_sdcore_crc16_checker_crc0_crcreg1 { \main_sdcore_crc16_checker_crc0_crcreg0 [14:12] $xor$ls180.v:5054$914_Y \main_sdcore_crc16_checker_crc0_crcreg0 [10:5] $xor$ls180.v:5054$912_Y \main_sdcore_crc16_checker_crc0_crcreg0 [3:0] $xor$ls180.v:5054$910_Y } + connect \main_sdcore_crc16_checker_crc0_crcreg2 { \main_sdcore_crc16_checker_crc0_crcreg1 [14:12] $xor$ls180.v:5055$919_Y \main_sdcore_crc16_checker_crc0_crcreg1 [10:5] $xor$ls180.v:5055$917_Y \main_sdcore_crc16_checker_crc0_crcreg1 [3:0] $xor$ls180.v:5055$915_Y } + connect \main_sdcore_crc16_checker_crc1_crcreg1 { \main_sdcore_crc16_checker_crc1_crcreg0 [14:12] $xor$ls180.v:5064$925_Y \main_sdcore_crc16_checker_crc1_crcreg0 [10:5] $xor$ls180.v:5064$923_Y \main_sdcore_crc16_checker_crc1_crcreg0 [3:0] $xor$ls180.v:5064$921_Y } + connect \main_sdcore_crc16_checker_crc1_crcreg2 { \main_sdcore_crc16_checker_crc1_crcreg1 [14:12] $xor$ls180.v:5065$930_Y \main_sdcore_crc16_checker_crc1_crcreg1 [10:5] $xor$ls180.v:5065$928_Y \main_sdcore_crc16_checker_crc1_crcreg1 [3:0] $xor$ls180.v:5065$926_Y } + connect \main_sdcore_crc16_checker_crc2_crcreg1 { \main_sdcore_crc16_checker_crc2_crcreg0 [14:12] $xor$ls180.v:5074$936_Y \main_sdcore_crc16_checker_crc2_crcreg0 [10:5] $xor$ls180.v:5074$934_Y \main_sdcore_crc16_checker_crc2_crcreg0 [3:0] $xor$ls180.v:5074$932_Y } + connect \main_sdcore_crc16_checker_crc2_crcreg2 { \main_sdcore_crc16_checker_crc2_crcreg1 [14:12] $xor$ls180.v:5075$941_Y \main_sdcore_crc16_checker_crc2_crcreg1 [10:5] $xor$ls180.v:5075$939_Y \main_sdcore_crc16_checker_crc2_crcreg1 [3:0] $xor$ls180.v:5075$937_Y } + connect \main_sdcore_crc16_checker_crc3_crcreg1 { \main_sdcore_crc16_checker_crc3_crcreg0 [14:12] $xor$ls180.v:5084$947_Y \main_sdcore_crc16_checker_crc3_crcreg0 [10:5] $xor$ls180.v:5084$945_Y \main_sdcore_crc16_checker_crc3_crcreg0 [3:0] $xor$ls180.v:5084$943_Y } + connect \main_sdcore_crc16_checker_crc3_crcreg2 { \main_sdcore_crc16_checker_crc3_crcreg1 [14:12] $xor$ls180.v:5085$952_Y \main_sdcore_crc16_checker_crc3_crcreg1 [10:5] $xor$ls180.v:5085$950_Y \main_sdcore_crc16_checker_crc3_crcreg1 [3:0] $xor$ls180.v:5085$948_Y } connect \main_sdblock2mem_fifo_sink_valid \main_sdblock2mem_sink_sink_valid0 connect \main_sdblock2mem_sink_sink_ready0 \main_sdblock2mem_fifo_sink_ready connect \main_sdblock2mem_fifo_sink_first \main_sdblock2mem_sink_sink_first @@ -129054,20 +129020,20 @@ module \ls180 connect \main_sdblock2mem_fifo_source_payload_data \main_sdblock2mem_fifo_fifo_out_payload_data connect \main_sdblock2mem_fifo_syncfifo_re \main_sdblock2mem_fifo_source_ready connect \main_sdblock2mem_fifo_wrport_dat_w \main_sdblock2mem_fifo_syncfifo_din - connect \main_sdblock2mem_fifo_wrport_we $and$ls180.v:5325$983_Y - connect \main_sdblock2mem_fifo_do_read $and$ls180.v:5326$984_Y + connect \main_sdblock2mem_fifo_wrport_we $and$ls180.v:5321$982_Y + connect \main_sdblock2mem_fifo_do_read $and$ls180.v:5322$983_Y connect \main_sdblock2mem_fifo_rdport_adr \main_sdblock2mem_fifo_consume connect \main_sdblock2mem_fifo_syncfifo_dout \main_sdblock2mem_fifo_rdport_dat_r - connect \main_sdblock2mem_fifo_syncfifo_writable $ne$ls180.v:5329$985_Y - connect \main_sdblock2mem_fifo_syncfifo_readable $ne$ls180.v:5330$986_Y + connect \main_sdblock2mem_fifo_syncfifo_writable $ne$ls180.v:5325$984_Y + connect \main_sdblock2mem_fifo_syncfifo_readable $ne$ls180.v:5326$985_Y connect \main_sdblock2mem_source_source_valid \main_sdblock2mem_converter_source_valid connect \main_sdblock2mem_converter_source_ready \main_sdblock2mem_source_source_ready connect \main_sdblock2mem_source_source_first \main_sdblock2mem_converter_source_first connect \main_sdblock2mem_source_source_last \main_sdblock2mem_converter_source_last connect \main_sdblock2mem_source_source_payload_data \main_sdblock2mem_converter_source_payload_data - connect \main_sdblock2mem_converter_sink_ready $or$ls180.v:5336$988_Y + connect \main_sdblock2mem_converter_sink_ready $or$ls180.v:5332$987_Y connect \main_sdblock2mem_converter_source_valid \main_sdblock2mem_converter_strobe_all - connect \main_sdblock2mem_converter_load_part $and$ls180.v:5338$989_Y + connect \main_sdblock2mem_converter_load_part $and$ls180.v:5334$988_Y connect \main_interface0_bus_stb \main_sdblock2mem_sink_sink_valid1 connect \main_interface0_bus_cyc \main_sdblock2mem_sink_sink_valid1 connect \main_interface0_bus_we 1'1 @@ -129077,7 +129043,7 @@ module \ls180 connect \main_sdblock2mem_sink_sink_ready1 \main_interface0_bus_ack connect \main_sdblock2mem_wishbonedmawriter_base \main_sdblock2mem_wishbonedmawriter_base_storage [33:2] connect \main_sdblock2mem_wishbonedmawriter_length { 2'00 \main_sdblock2mem_wishbonedmawriter_length_storage [31:2] } - connect \main_sdblock2mem_wishbonedmawriter_reset $not$ls180.v:5348$990_Y + connect \main_sdblock2mem_wishbonedmawriter_reset $not$ls180.v:5344$989_Y connect \main_sdmem2block_converter_sink_valid \main_sdmem2block_dma_source_valid connect \main_sdmem2block_dma_source_ready \main_sdmem2block_converter_sink_ready connect \main_sdmem2block_converter_sink_first \main_sdmem2block_dma_source_first @@ -129096,18 +129062,18 @@ module \ls180 connect \main_sdmem2block_dma_base \main_sdmem2block_dma_base_storage [33:2] connect \main_sdmem2block_dma_length { 2'00 \main_sdmem2block_dma_length_storage [31:2] } connect \main_sdmem2block_dma_offset_status \main_sdmem2block_dma_offset - connect \main_sdmem2block_dma_reset $not$ls180.v:5407$997_Y + connect \main_sdmem2block_dma_reset $not$ls180.v:5403$996_Y connect \main_sdmem2block_source_source_valid1 \main_sdmem2block_converter_source_valid connect \main_sdmem2block_converter_source_ready \main_sdmem2block_source_source_ready1 connect \main_sdmem2block_source_source_first1 \main_sdmem2block_converter_source_first connect \main_sdmem2block_source_source_last1 \main_sdmem2block_converter_source_last connect \main_sdmem2block_source_source_payload_data1 \main_sdmem2block_converter_source_payload_data - connect \main_sdmem2block_converter_first $eq$ls180.v:5488$1005_Y - connect \main_sdmem2block_converter_last $eq$ls180.v:5489$1006_Y + connect \main_sdmem2block_converter_first $eq$ls180.v:5484$1004_Y + connect \main_sdmem2block_converter_last $eq$ls180.v:5485$1005_Y connect \main_sdmem2block_converter_source_valid \main_sdmem2block_converter_sink_valid - connect \main_sdmem2block_converter_source_first $and$ls180.v:5491$1007_Y - connect \main_sdmem2block_converter_source_last $and$ls180.v:5492$1008_Y - connect \main_sdmem2block_converter_sink_ready $and$ls180.v:5493$1009_Y + connect \main_sdmem2block_converter_source_first $and$ls180.v:5487$1006_Y + connect \main_sdmem2block_converter_source_last $and$ls180.v:5488$1007_Y + connect \main_sdmem2block_converter_sink_ready $and$ls180.v:5489$1008_Y connect \main_sdmem2block_converter_source_payload_valid_token_count \main_sdmem2block_converter_last connect \main_sdmem2block_fifo_syncfifo_din { \main_sdmem2block_fifo_fifo_in_last \main_sdmem2block_fifo_fifo_in_first \main_sdmem2block_fifo_fifo_in_payload_data } connect { \main_sdmem2block_fifo_fifo_out_last \main_sdmem2block_fifo_fifo_out_first \main_sdmem2block_fifo_fifo_out_payload_data } \main_sdmem2block_fifo_syncfifo_dout @@ -129122,12 +129088,12 @@ module \ls180 connect \main_sdmem2block_fifo_source_payload_data \main_sdmem2block_fifo_fifo_out_payload_data connect \main_sdmem2block_fifo_syncfifo_re \main_sdmem2block_fifo_source_ready connect \main_sdmem2block_fifo_wrport_dat_w \main_sdmem2block_fifo_syncfifo_din - connect \main_sdmem2block_fifo_wrport_we $and$ls180.v:5533$1014_Y - connect \main_sdmem2block_fifo_do_read $and$ls180.v:5534$1015_Y + connect \main_sdmem2block_fifo_wrport_we $and$ls180.v:5529$1013_Y + connect \main_sdmem2block_fifo_do_read $and$ls180.v:5530$1014_Y connect \main_sdmem2block_fifo_rdport_adr \main_sdmem2block_fifo_consume connect \main_sdmem2block_fifo_syncfifo_dout \main_sdmem2block_fifo_rdport_dat_r - connect \main_sdmem2block_fifo_syncfifo_writable $ne$ls180.v:5537$1016_Y - connect \main_sdmem2block_fifo_syncfifo_readable $ne$ls180.v:5538$1017_Y + connect \main_sdmem2block_fifo_syncfifo_writable $ne$ls180.v:5533$1015_Y + connect \main_sdmem2block_fifo_syncfifo_readable $ne$ls180.v:5534$1016_Y connect \libresocsim_start0 \libresocsim_start1 connect \libresocsim_length0 \libresocsim_length1 connect \libresocsim_mosi \libresocsim_mosi_storage @@ -129135,8 +129101,8 @@ module \ls180 connect \libresocsim_miso_status \libresocsim_miso connect \libresocsim_cs \libresocsim_cs_storage connect \libresocsim_loopback \libresocsim_loopback_storage - connect \libresocsim_clk_rise $eq$ls180.v:5546$1019_Y - connect \libresocsim_clk_fall $eq$ls180.v:5547$1021_Y + connect \libresocsim_clk_rise $eq$ls180.v:5542$1018_Y + connect \libresocsim_clk_fall $eq$ls180.v:5543$1020_Y connect \libresocsim_clk_divider0 \libresocsim_storage connect \builder_shared_adr \builder_comb_rhs_array_muxed24 [29:0] connect \builder_shared_dat_w \builder_comb_rhs_array_muxed25 @@ -129151,16 +129117,16 @@ module \ls180 connect \main_libresocsim_interface2_converted_interface_dat_r \builder_shared_dat_r connect \main_interface0_bus_dat_r \builder_shared_dat_r connect \main_interface1_bus_dat_r \builder_shared_dat_r - connect \main_libresocsim_interface0_converted_interface_ack $and$ls180.v:5648$1031_Y - connect \main_libresocsim_interface1_converted_interface_ack $and$ls180.v:5649$1033_Y - connect \main_libresocsim_interface2_converted_interface_ack $and$ls180.v:5650$1035_Y - connect \main_interface0_bus_ack $and$ls180.v:5651$1037_Y - connect \main_interface1_bus_ack $and$ls180.v:5652$1039_Y - connect \main_libresocsim_interface0_converted_interface_err $and$ls180.v:5653$1041_Y - connect \main_libresocsim_interface1_converted_interface_err $and$ls180.v:5654$1043_Y - connect \main_libresocsim_interface2_converted_interface_err $and$ls180.v:5655$1045_Y - connect \main_interface0_bus_err $and$ls180.v:5656$1047_Y - connect \main_interface1_bus_err $and$ls180.v:5657$1049_Y + connect \main_libresocsim_interface0_converted_interface_ack $and$ls180.v:5644$1030_Y + connect \main_libresocsim_interface1_converted_interface_ack $and$ls180.v:5645$1032_Y + connect \main_libresocsim_interface2_converted_interface_ack $and$ls180.v:5646$1034_Y + connect \main_interface0_bus_ack $and$ls180.v:5647$1036_Y + connect \main_interface1_bus_ack $and$ls180.v:5648$1038_Y + connect \main_libresocsim_interface0_converted_interface_err $and$ls180.v:5649$1040_Y + connect \main_libresocsim_interface1_converted_interface_err $and$ls180.v:5650$1042_Y + connect \main_libresocsim_interface2_converted_interface_err $and$ls180.v:5651$1044_Y + connect \main_interface0_bus_err $and$ls180.v:5652$1046_Y + connect \main_interface1_bus_err $and$ls180.v:5653$1048_Y connect \builder_request { \main_interface1_bus_cyc \main_interface0_bus_cyc \main_libresocsim_interface2_converted_interface_cyc \main_libresocsim_interface1_converted_interface_cyc \main_libresocsim_interface0_converted_interface_cyc } connect \main_libresocsim_ram_bus_adr \builder_shared_adr connect \main_libresocsim_ram_bus_dat_w \builder_shared_dat_w @@ -129197,42 +129163,42 @@ module \ls180 connect \builder_libresocsim_wishbone_we \builder_shared_we connect \builder_libresocsim_wishbone_cti \builder_shared_cti connect \builder_libresocsim_wishbone_bte \builder_shared_bte - connect \main_libresocsim_ram_bus_cyc $and$ls180.v:5702$1056_Y - connect \main_libresocsim_libresoc_xics_icp_cyc $and$ls180.v:5703$1057_Y - connect \main_libresocsim_libresoc_xics_ics_cyc $and$ls180.v:5704$1058_Y - connect \main_wb_sdram_cyc $and$ls180.v:5705$1059_Y - connect \builder_libresocsim_wishbone_cyc $and$ls180.v:5706$1060_Y - connect \builder_shared_err $or$ls180.v:5707$1064_Y - connect \builder_wait $and$ls180.v:5708$1067_Y - connect \builder_done $eq$ls180.v:5721$1082_Y - connect \builder_csrbank0_sel $eq$ls180.v:5722$1083_Y + connect \main_libresocsim_ram_bus_cyc $and$ls180.v:5698$1055_Y + connect \main_libresocsim_libresoc_xics_icp_cyc $and$ls180.v:5699$1056_Y + connect \main_libresocsim_libresoc_xics_ics_cyc $and$ls180.v:5700$1057_Y + connect \main_wb_sdram_cyc $and$ls180.v:5701$1058_Y + connect \builder_libresocsim_wishbone_cyc $and$ls180.v:5702$1059_Y + connect \builder_shared_err $or$ls180.v:5703$1063_Y + connect \builder_wait $and$ls180.v:5704$1066_Y + connect \builder_done $eq$ls180.v:5717$1081_Y + connect \builder_csrbank0_sel $eq$ls180.v:5718$1082_Y connect \builder_csrbank0_reset0_r \builder_interface0_bank_bus_dat_w [0] - connect \builder_csrbank0_reset0_re $and$ls180.v:5724$1086_Y - connect \builder_csrbank0_reset0_we $and$ls180.v:5725$1090_Y + connect \builder_csrbank0_reset0_re $and$ls180.v:5720$1085_Y + connect \builder_csrbank0_reset0_we $and$ls180.v:5721$1089_Y connect \builder_csrbank0_scratch3_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_scratch3_re $and$ls180.v:5727$1093_Y - connect \builder_csrbank0_scratch3_we $and$ls180.v:5728$1097_Y + connect \builder_csrbank0_scratch3_re $and$ls180.v:5723$1092_Y + connect \builder_csrbank0_scratch3_we $and$ls180.v:5724$1096_Y connect \builder_csrbank0_scratch2_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_scratch2_re $and$ls180.v:5730$1100_Y - connect \builder_csrbank0_scratch2_we $and$ls180.v:5731$1104_Y + connect \builder_csrbank0_scratch2_re $and$ls180.v:5726$1099_Y + connect \builder_csrbank0_scratch2_we $and$ls180.v:5727$1103_Y connect \builder_csrbank0_scratch1_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_scratch1_re $and$ls180.v:5733$1107_Y - connect \builder_csrbank0_scratch1_we $and$ls180.v:5734$1111_Y + connect \builder_csrbank0_scratch1_re $and$ls180.v:5729$1106_Y + connect \builder_csrbank0_scratch1_we $and$ls180.v:5730$1110_Y connect \builder_csrbank0_scratch0_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_scratch0_re $and$ls180.v:5736$1114_Y - connect \builder_csrbank0_scratch0_we $and$ls180.v:5737$1118_Y + connect \builder_csrbank0_scratch0_re $and$ls180.v:5732$1113_Y + connect \builder_csrbank0_scratch0_we $and$ls180.v:5733$1117_Y connect \builder_csrbank0_bus_errors3_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_bus_errors3_re $and$ls180.v:5739$1121_Y - connect \builder_csrbank0_bus_errors3_we $and$ls180.v:5740$1125_Y + connect \builder_csrbank0_bus_errors3_re $and$ls180.v:5735$1120_Y + connect \builder_csrbank0_bus_errors3_we $and$ls180.v:5736$1124_Y connect \builder_csrbank0_bus_errors2_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_bus_errors2_re $and$ls180.v:5742$1128_Y - connect \builder_csrbank0_bus_errors2_we $and$ls180.v:5743$1132_Y + connect \builder_csrbank0_bus_errors2_re $and$ls180.v:5738$1127_Y + connect \builder_csrbank0_bus_errors2_we $and$ls180.v:5739$1131_Y connect \builder_csrbank0_bus_errors1_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_bus_errors1_re $and$ls180.v:5745$1135_Y - connect \builder_csrbank0_bus_errors1_we $and$ls180.v:5746$1139_Y + connect \builder_csrbank0_bus_errors1_re $and$ls180.v:5741$1134_Y + connect \builder_csrbank0_bus_errors1_we $and$ls180.v:5742$1138_Y connect \builder_csrbank0_bus_errors0_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_bus_errors0_re $and$ls180.v:5748$1142_Y - connect \builder_csrbank0_bus_errors0_we $and$ls180.v:5749$1146_Y + connect \builder_csrbank0_bus_errors0_re $and$ls180.v:5744$1141_Y + connect \builder_csrbank0_bus_errors0_we $and$ls180.v:5745$1145_Y connect \builder_csrbank0_reset0_w \main_libresocsim_reset_storage connect \builder_csrbank0_scratch3_w \main_libresocsim_scratch_storage [31:24] connect \builder_csrbank0_scratch2_w \main_libresocsim_scratch_storage [23:16] @@ -129243,25 +129209,25 @@ module \ls180 connect \builder_csrbank0_bus_errors1_w \main_libresocsim_bus_errors_status [15:8] connect \builder_csrbank0_bus_errors0_w \main_libresocsim_bus_errors_status [7:0] connect \main_libresocsim_bus_errors_we \builder_csrbank0_bus_errors0_we - connect \builder_csrbank1_sel $eq$ls180.v:5760$1147_Y + connect \builder_csrbank1_sel $eq$ls180.v:5756$1146_Y connect \builder_csrbank1_oe1_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_oe1_re $and$ls180.v:5762$1150_Y - connect \builder_csrbank1_oe1_we $and$ls180.v:5763$1154_Y + connect \builder_csrbank1_oe1_re $and$ls180.v:5758$1149_Y + connect \builder_csrbank1_oe1_we $and$ls180.v:5759$1153_Y connect \builder_csrbank1_oe0_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_oe0_re $and$ls180.v:5765$1157_Y - connect \builder_csrbank1_oe0_we $and$ls180.v:5766$1161_Y + connect \builder_csrbank1_oe0_re $and$ls180.v:5761$1156_Y + connect \builder_csrbank1_oe0_we $and$ls180.v:5762$1160_Y connect \builder_csrbank1_in1_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_in1_re $and$ls180.v:5768$1164_Y - connect \builder_csrbank1_in1_we $and$ls180.v:5769$1168_Y + connect \builder_csrbank1_in1_re $and$ls180.v:5764$1163_Y + connect \builder_csrbank1_in1_we $and$ls180.v:5765$1167_Y connect \builder_csrbank1_in0_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_in0_re $and$ls180.v:5771$1171_Y - connect \builder_csrbank1_in0_we $and$ls180.v:5772$1175_Y + connect \builder_csrbank1_in0_re $and$ls180.v:5767$1170_Y + connect \builder_csrbank1_in0_we $and$ls180.v:5768$1174_Y connect \builder_csrbank1_out1_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_out1_re $and$ls180.v:5774$1178_Y - connect \builder_csrbank1_out1_we $and$ls180.v:5775$1182_Y + connect \builder_csrbank1_out1_re $and$ls180.v:5770$1177_Y + connect \builder_csrbank1_out1_we $and$ls180.v:5771$1181_Y connect \builder_csrbank1_out0_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_out0_re $and$ls180.v:5777$1185_Y - connect \builder_csrbank1_out0_we $and$ls180.v:5778$1189_Y + connect \builder_csrbank1_out0_re $and$ls180.v:5773$1184_Y + connect \builder_csrbank1_out0_we $and$ls180.v:5774$1188_Y connect \builder_csrbank1_oe1_w \main_gpio_oe_storage [15:8] connect \builder_csrbank1_oe0_w \main_gpio_oe_storage [7:0] connect \builder_csrbank1_in1_w \main_gpio_status [15:8] @@ -129269,34 +129235,34 @@ module \ls180 connect \main_gpio_we \builder_csrbank1_in0_we connect \builder_csrbank1_out1_w \main_gpio_out_storage [15:8] connect \builder_csrbank1_out0_w \main_gpio_out_storage [7:0] - connect \builder_csrbank2_sel $eq$ls180.v:5786$1190_Y + connect \builder_csrbank2_sel $eq$ls180.v:5782$1189_Y connect \builder_csrbank2_enable0_r \builder_interface2_bank_bus_dat_w [0] - connect \builder_csrbank2_enable0_re $and$ls180.v:5788$1193_Y - connect \builder_csrbank2_enable0_we $and$ls180.v:5789$1197_Y + connect \builder_csrbank2_enable0_re $and$ls180.v:5784$1192_Y + connect \builder_csrbank2_enable0_we $and$ls180.v:5785$1196_Y connect \builder_csrbank2_width3_r \builder_interface2_bank_bus_dat_w - connect \builder_csrbank2_width3_re $and$ls180.v:5791$1200_Y - connect \builder_csrbank2_width3_we $and$ls180.v:5792$1204_Y + connect \builder_csrbank2_width3_re $and$ls180.v:5787$1199_Y + connect \builder_csrbank2_width3_we $and$ls180.v:5788$1203_Y connect \builder_csrbank2_width2_r \builder_interface2_bank_bus_dat_w - connect \builder_csrbank2_width2_re $and$ls180.v:5794$1207_Y - connect \builder_csrbank2_width2_we $and$ls180.v:5795$1211_Y + connect \builder_csrbank2_width2_re $and$ls180.v:5790$1206_Y + connect \builder_csrbank2_width2_we $and$ls180.v:5791$1210_Y connect \builder_csrbank2_width1_r \builder_interface2_bank_bus_dat_w - connect \builder_csrbank2_width1_re $and$ls180.v:5797$1214_Y - connect \builder_csrbank2_width1_we $and$ls180.v:5798$1218_Y + connect \builder_csrbank2_width1_re $and$ls180.v:5793$1213_Y + connect \builder_csrbank2_width1_we $and$ls180.v:5794$1217_Y connect \builder_csrbank2_width0_r \builder_interface2_bank_bus_dat_w - connect \builder_csrbank2_width0_re $and$ls180.v:5800$1221_Y - connect \builder_csrbank2_width0_we $and$ls180.v:5801$1225_Y + connect \builder_csrbank2_width0_re $and$ls180.v:5796$1220_Y + connect \builder_csrbank2_width0_we $and$ls180.v:5797$1224_Y connect \builder_csrbank2_period3_r \builder_interface2_bank_bus_dat_w - connect \builder_csrbank2_period3_re $and$ls180.v:5803$1228_Y - connect \builder_csrbank2_period3_we $and$ls180.v:5804$1232_Y + connect \builder_csrbank2_period3_re $and$ls180.v:5799$1227_Y + connect \builder_csrbank2_period3_we $and$ls180.v:5800$1231_Y connect \builder_csrbank2_period2_r \builder_interface2_bank_bus_dat_w - connect \builder_csrbank2_period2_re $and$ls180.v:5806$1235_Y - connect \builder_csrbank2_period2_we $and$ls180.v:5807$1239_Y + connect \builder_csrbank2_period2_re $and$ls180.v:5802$1234_Y + connect \builder_csrbank2_period2_we $and$ls180.v:5803$1238_Y connect \builder_csrbank2_period1_r \builder_interface2_bank_bus_dat_w - connect \builder_csrbank2_period1_re $and$ls180.v:5809$1242_Y - connect \builder_csrbank2_period1_we $and$ls180.v:5810$1246_Y + connect \builder_csrbank2_period1_re $and$ls180.v:5805$1241_Y + connect \builder_csrbank2_period1_we $and$ls180.v:5806$1245_Y connect \builder_csrbank2_period0_r \builder_interface2_bank_bus_dat_w - connect \builder_csrbank2_period0_re $and$ls180.v:5812$1249_Y - connect \builder_csrbank2_period0_we $and$ls180.v:5813$1253_Y + connect \builder_csrbank2_period0_re $and$ls180.v:5808$1248_Y + connect \builder_csrbank2_period0_we $and$ls180.v:5809$1252_Y connect \builder_csrbank2_enable0_w \main_pwm0_enable_storage connect \builder_csrbank2_width3_w \main_pwm0_width_storage [31:24] connect \builder_csrbank2_width2_w \main_pwm0_width_storage [23:16] @@ -129306,34 +129272,34 @@ module \ls180 connect \builder_csrbank2_period2_w \main_pwm0_period_storage [23:16] connect \builder_csrbank2_period1_w \main_pwm0_period_storage [15:8] connect \builder_csrbank2_period0_w \main_pwm0_period_storage [7:0] - connect \builder_csrbank3_sel $eq$ls180.v:5823$1254_Y + connect \builder_csrbank3_sel $eq$ls180.v:5819$1253_Y connect \builder_csrbank3_enable0_r \builder_interface3_bank_bus_dat_w [0] - connect \builder_csrbank3_enable0_re $and$ls180.v:5825$1257_Y - connect \builder_csrbank3_enable0_we $and$ls180.v:5826$1261_Y + connect \builder_csrbank3_enable0_re $and$ls180.v:5821$1256_Y + connect \builder_csrbank3_enable0_we $and$ls180.v:5822$1260_Y connect \builder_csrbank3_width3_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_width3_re $and$ls180.v:5828$1264_Y - connect \builder_csrbank3_width3_we $and$ls180.v:5829$1268_Y + connect \builder_csrbank3_width3_re $and$ls180.v:5824$1263_Y + connect \builder_csrbank3_width3_we $and$ls180.v:5825$1267_Y connect \builder_csrbank3_width2_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_width2_re $and$ls180.v:5831$1271_Y - connect \builder_csrbank3_width2_we $and$ls180.v:5832$1275_Y + connect \builder_csrbank3_width2_re $and$ls180.v:5827$1270_Y + connect \builder_csrbank3_width2_we $and$ls180.v:5828$1274_Y connect \builder_csrbank3_width1_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_width1_re $and$ls180.v:5834$1278_Y - connect \builder_csrbank3_width1_we $and$ls180.v:5835$1282_Y + connect \builder_csrbank3_width1_re $and$ls180.v:5830$1277_Y + connect \builder_csrbank3_width1_we $and$ls180.v:5831$1281_Y connect \builder_csrbank3_width0_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_width0_re $and$ls180.v:5837$1285_Y - connect \builder_csrbank3_width0_we $and$ls180.v:5838$1289_Y + connect \builder_csrbank3_width0_re $and$ls180.v:5833$1284_Y + connect \builder_csrbank3_width0_we $and$ls180.v:5834$1288_Y connect \builder_csrbank3_period3_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_period3_re $and$ls180.v:5840$1292_Y - connect \builder_csrbank3_period3_we $and$ls180.v:5841$1296_Y + connect \builder_csrbank3_period3_re $and$ls180.v:5836$1291_Y + connect \builder_csrbank3_period3_we $and$ls180.v:5837$1295_Y connect \builder_csrbank3_period2_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_period2_re $and$ls180.v:5843$1299_Y - connect \builder_csrbank3_period2_we $and$ls180.v:5844$1303_Y + connect \builder_csrbank3_period2_re $and$ls180.v:5839$1298_Y + connect \builder_csrbank3_period2_we $and$ls180.v:5840$1302_Y connect \builder_csrbank3_period1_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_period1_re $and$ls180.v:5846$1306_Y - connect \builder_csrbank3_period1_we $and$ls180.v:5847$1310_Y + connect \builder_csrbank3_period1_re $and$ls180.v:5842$1305_Y + connect \builder_csrbank3_period1_we $and$ls180.v:5843$1309_Y connect \builder_csrbank3_period0_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_period0_re $and$ls180.v:5849$1313_Y - connect \builder_csrbank3_period0_we $and$ls180.v:5850$1317_Y + connect \builder_csrbank3_period0_re $and$ls180.v:5845$1312_Y + connect \builder_csrbank3_period0_we $and$ls180.v:5846$1316_Y connect \builder_csrbank3_enable0_w \main_pwm1_enable_storage connect \builder_csrbank3_width3_w \main_pwm1_width_storage [31:24] connect \builder_csrbank3_width2_w \main_pwm1_width_storage [23:16] @@ -129343,52 +129309,52 @@ module \ls180 connect \builder_csrbank3_period2_w \main_pwm1_period_storage [23:16] connect \builder_csrbank3_period1_w \main_pwm1_period_storage [15:8] connect \builder_csrbank3_period0_w \main_pwm1_period_storage [7:0] - connect \builder_csrbank4_sel $eq$ls180.v:5860$1318_Y + connect \builder_csrbank4_sel $eq$ls180.v:5856$1317_Y connect \builder_csrbank4_dma_base7_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_dma_base7_re $and$ls180.v:5862$1321_Y - connect \builder_csrbank4_dma_base7_we $and$ls180.v:5863$1325_Y + connect \builder_csrbank4_dma_base7_re $and$ls180.v:5858$1320_Y + connect \builder_csrbank4_dma_base7_we $and$ls180.v:5859$1324_Y connect \builder_csrbank4_dma_base6_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_dma_base6_re $and$ls180.v:5865$1328_Y - connect \builder_csrbank4_dma_base6_we $and$ls180.v:5866$1332_Y + connect \builder_csrbank4_dma_base6_re $and$ls180.v:5861$1327_Y + connect \builder_csrbank4_dma_base6_we $and$ls180.v:5862$1331_Y connect \builder_csrbank4_dma_base5_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_dma_base5_re $and$ls180.v:5868$1335_Y - connect \builder_csrbank4_dma_base5_we $and$ls180.v:5869$1339_Y + connect \builder_csrbank4_dma_base5_re $and$ls180.v:5864$1334_Y + connect \builder_csrbank4_dma_base5_we $and$ls180.v:5865$1338_Y connect \builder_csrbank4_dma_base4_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_dma_base4_re $and$ls180.v:5871$1342_Y - connect \builder_csrbank4_dma_base4_we $and$ls180.v:5872$1346_Y + connect \builder_csrbank4_dma_base4_re $and$ls180.v:5867$1341_Y + connect \builder_csrbank4_dma_base4_we $and$ls180.v:5868$1345_Y connect \builder_csrbank4_dma_base3_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_dma_base3_re $and$ls180.v:5874$1349_Y - connect \builder_csrbank4_dma_base3_we $and$ls180.v:5875$1353_Y + connect \builder_csrbank4_dma_base3_re $and$ls180.v:5870$1348_Y + connect \builder_csrbank4_dma_base3_we $and$ls180.v:5871$1352_Y connect \builder_csrbank4_dma_base2_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_dma_base2_re $and$ls180.v:5877$1356_Y - connect \builder_csrbank4_dma_base2_we $and$ls180.v:5878$1360_Y + connect \builder_csrbank4_dma_base2_re $and$ls180.v:5873$1355_Y + connect \builder_csrbank4_dma_base2_we $and$ls180.v:5874$1359_Y connect \builder_csrbank4_dma_base1_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_dma_base1_re $and$ls180.v:5880$1363_Y - connect \builder_csrbank4_dma_base1_we $and$ls180.v:5881$1367_Y + connect \builder_csrbank4_dma_base1_re $and$ls180.v:5876$1362_Y + connect \builder_csrbank4_dma_base1_we $and$ls180.v:5877$1366_Y connect \builder_csrbank4_dma_base0_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_dma_base0_re $and$ls180.v:5883$1370_Y - connect \builder_csrbank4_dma_base0_we $and$ls180.v:5884$1374_Y + connect \builder_csrbank4_dma_base0_re $and$ls180.v:5879$1369_Y + connect \builder_csrbank4_dma_base0_we $and$ls180.v:5880$1373_Y connect \builder_csrbank4_dma_length3_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_dma_length3_re $and$ls180.v:5886$1377_Y - connect \builder_csrbank4_dma_length3_we $and$ls180.v:5887$1381_Y + connect \builder_csrbank4_dma_length3_re $and$ls180.v:5882$1376_Y + connect \builder_csrbank4_dma_length3_we $and$ls180.v:5883$1380_Y connect \builder_csrbank4_dma_length2_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_dma_length2_re $and$ls180.v:5889$1384_Y - connect \builder_csrbank4_dma_length2_we $and$ls180.v:5890$1388_Y + connect \builder_csrbank4_dma_length2_re $and$ls180.v:5885$1383_Y + connect \builder_csrbank4_dma_length2_we $and$ls180.v:5886$1387_Y connect \builder_csrbank4_dma_length1_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_dma_length1_re $and$ls180.v:5892$1391_Y - connect \builder_csrbank4_dma_length1_we $and$ls180.v:5893$1395_Y + connect \builder_csrbank4_dma_length1_re $and$ls180.v:5888$1390_Y + connect \builder_csrbank4_dma_length1_we $and$ls180.v:5889$1394_Y connect \builder_csrbank4_dma_length0_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_dma_length0_re $and$ls180.v:5895$1398_Y - connect \builder_csrbank4_dma_length0_we $and$ls180.v:5896$1402_Y + connect \builder_csrbank4_dma_length0_re $and$ls180.v:5891$1397_Y + connect \builder_csrbank4_dma_length0_we $and$ls180.v:5892$1401_Y connect \builder_csrbank4_dma_enable0_r \builder_interface4_bank_bus_dat_w [0] - connect \builder_csrbank4_dma_enable0_re $and$ls180.v:5898$1405_Y - connect \builder_csrbank4_dma_enable0_we $and$ls180.v:5899$1409_Y + connect \builder_csrbank4_dma_enable0_re $and$ls180.v:5894$1404_Y + connect \builder_csrbank4_dma_enable0_we $and$ls180.v:5895$1408_Y connect \builder_csrbank4_dma_done_r \builder_interface4_bank_bus_dat_w [0] - connect \builder_csrbank4_dma_done_re $and$ls180.v:5901$1412_Y - connect \builder_csrbank4_dma_done_we $and$ls180.v:5902$1416_Y + connect \builder_csrbank4_dma_done_re $and$ls180.v:5897$1411_Y + connect \builder_csrbank4_dma_done_we $and$ls180.v:5898$1415_Y connect \builder_csrbank4_dma_loop0_r \builder_interface4_bank_bus_dat_w [0] - connect \builder_csrbank4_dma_loop0_re $and$ls180.v:5904$1419_Y - connect \builder_csrbank4_dma_loop0_we $and$ls180.v:5905$1423_Y + connect \builder_csrbank4_dma_loop0_re $and$ls180.v:5900$1418_Y + connect \builder_csrbank4_dma_loop0_we $and$ls180.v:5901$1422_Y connect \builder_csrbank4_dma_base7_w \main_sdblock2mem_wishbonedmawriter_base_storage [63:56] connect \builder_csrbank4_dma_base6_w \main_sdblock2mem_wishbonedmawriter_base_storage [55:48] connect \builder_csrbank4_dma_base5_w \main_sdblock2mem_wishbonedmawriter_base_storage [47:40] @@ -129405,106 +129371,106 @@ module \ls180 connect \builder_csrbank4_dma_done_w \main_sdblock2mem_wishbonedmawriter_status connect \main_sdblock2mem_wishbonedmawriter_we \builder_csrbank4_dma_done_we connect \builder_csrbank4_dma_loop0_w \main_sdblock2mem_wishbonedmawriter_loop_storage - connect \builder_csrbank5_sel $eq$ls180.v:5922$1424_Y + connect \builder_csrbank5_sel $eq$ls180.v:5918$1423_Y connect \builder_csrbank5_cmd_argument3_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_cmd_argument3_re $and$ls180.v:5924$1427_Y - connect \builder_csrbank5_cmd_argument3_we $and$ls180.v:5925$1431_Y + connect \builder_csrbank5_cmd_argument3_re $and$ls180.v:5920$1426_Y + connect \builder_csrbank5_cmd_argument3_we $and$ls180.v:5921$1430_Y connect \builder_csrbank5_cmd_argument2_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_cmd_argument2_re $and$ls180.v:5927$1434_Y - connect \builder_csrbank5_cmd_argument2_we $and$ls180.v:5928$1438_Y + connect \builder_csrbank5_cmd_argument2_re $and$ls180.v:5923$1433_Y + connect \builder_csrbank5_cmd_argument2_we $and$ls180.v:5924$1437_Y connect \builder_csrbank5_cmd_argument1_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_cmd_argument1_re $and$ls180.v:5930$1441_Y - connect \builder_csrbank5_cmd_argument1_we $and$ls180.v:5931$1445_Y + connect \builder_csrbank5_cmd_argument1_re $and$ls180.v:5926$1440_Y + connect \builder_csrbank5_cmd_argument1_we $and$ls180.v:5927$1444_Y connect \builder_csrbank5_cmd_argument0_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_cmd_argument0_re $and$ls180.v:5933$1448_Y - connect \builder_csrbank5_cmd_argument0_we $and$ls180.v:5934$1452_Y + connect \builder_csrbank5_cmd_argument0_re $and$ls180.v:5929$1447_Y + connect \builder_csrbank5_cmd_argument0_we $and$ls180.v:5930$1451_Y connect \builder_csrbank5_cmd_command3_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_cmd_command3_re $and$ls180.v:5936$1455_Y - connect \builder_csrbank5_cmd_command3_we $and$ls180.v:5937$1459_Y + connect \builder_csrbank5_cmd_command3_re $and$ls180.v:5932$1454_Y + connect \builder_csrbank5_cmd_command3_we $and$ls180.v:5933$1458_Y connect \builder_csrbank5_cmd_command2_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_cmd_command2_re $and$ls180.v:5939$1462_Y - connect \builder_csrbank5_cmd_command2_we $and$ls180.v:5940$1466_Y + connect \builder_csrbank5_cmd_command2_re $and$ls180.v:5935$1461_Y + connect \builder_csrbank5_cmd_command2_we $and$ls180.v:5936$1465_Y connect \builder_csrbank5_cmd_command1_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_cmd_command1_re $and$ls180.v:5942$1469_Y - connect \builder_csrbank5_cmd_command1_we $and$ls180.v:5943$1473_Y + connect \builder_csrbank5_cmd_command1_re $and$ls180.v:5938$1468_Y + connect \builder_csrbank5_cmd_command1_we $and$ls180.v:5939$1472_Y connect \builder_csrbank5_cmd_command0_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_cmd_command0_re $and$ls180.v:5945$1476_Y - connect \builder_csrbank5_cmd_command0_we $and$ls180.v:5946$1480_Y + connect \builder_csrbank5_cmd_command0_re $and$ls180.v:5941$1475_Y + connect \builder_csrbank5_cmd_command0_we $and$ls180.v:5942$1479_Y connect \main_sdcore_cmd_send_r \builder_interface5_bank_bus_dat_w [0] - connect \main_sdcore_cmd_send_re $and$ls180.v:5948$1483_Y - connect \main_sdcore_cmd_send_we $and$ls180.v:5949$1487_Y + connect \main_sdcore_cmd_send_re $and$ls180.v:5944$1482_Y + connect \main_sdcore_cmd_send_we $and$ls180.v:5945$1486_Y connect \builder_csrbank5_cmd_response15_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_cmd_response15_re $and$ls180.v:5951$1490_Y - connect \builder_csrbank5_cmd_response15_we $and$ls180.v:5952$1494_Y + connect \builder_csrbank5_cmd_response15_re $and$ls180.v:5947$1489_Y + connect \builder_csrbank5_cmd_response15_we $and$ls180.v:5948$1493_Y connect \builder_csrbank5_cmd_response14_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_cmd_response14_re $and$ls180.v:5954$1497_Y - connect \builder_csrbank5_cmd_response14_we $and$ls180.v:5955$1501_Y + connect \builder_csrbank5_cmd_response14_re $and$ls180.v:5950$1496_Y + connect \builder_csrbank5_cmd_response14_we $and$ls180.v:5951$1500_Y connect \builder_csrbank5_cmd_response13_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_cmd_response13_re $and$ls180.v:5957$1504_Y - connect \builder_csrbank5_cmd_response13_we $and$ls180.v:5958$1508_Y + connect \builder_csrbank5_cmd_response13_re $and$ls180.v:5953$1503_Y + connect \builder_csrbank5_cmd_response13_we $and$ls180.v:5954$1507_Y connect \builder_csrbank5_cmd_response12_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_cmd_response12_re $and$ls180.v:5960$1511_Y - connect \builder_csrbank5_cmd_response12_we $and$ls180.v:5961$1515_Y + connect \builder_csrbank5_cmd_response12_re $and$ls180.v:5956$1510_Y + connect \builder_csrbank5_cmd_response12_we $and$ls180.v:5957$1514_Y connect \builder_csrbank5_cmd_response11_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_cmd_response11_re $and$ls180.v:5963$1518_Y - connect \builder_csrbank5_cmd_response11_we $and$ls180.v:5964$1522_Y + connect \builder_csrbank5_cmd_response11_re $and$ls180.v:5959$1517_Y + connect \builder_csrbank5_cmd_response11_we $and$ls180.v:5960$1521_Y connect \builder_csrbank5_cmd_response10_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_cmd_response10_re $and$ls180.v:5966$1525_Y - connect \builder_csrbank5_cmd_response10_we $and$ls180.v:5967$1529_Y + connect \builder_csrbank5_cmd_response10_re $and$ls180.v:5962$1524_Y + connect \builder_csrbank5_cmd_response10_we $and$ls180.v:5963$1528_Y connect \builder_csrbank5_cmd_response9_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_cmd_response9_re $and$ls180.v:5969$1532_Y - connect \builder_csrbank5_cmd_response9_we $and$ls180.v:5970$1536_Y + connect \builder_csrbank5_cmd_response9_re $and$ls180.v:5965$1531_Y + connect \builder_csrbank5_cmd_response9_we $and$ls180.v:5966$1535_Y connect \builder_csrbank5_cmd_response8_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_cmd_response8_re $and$ls180.v:5972$1539_Y - connect \builder_csrbank5_cmd_response8_we $and$ls180.v:5973$1543_Y + connect \builder_csrbank5_cmd_response8_re $and$ls180.v:5968$1538_Y + connect \builder_csrbank5_cmd_response8_we $and$ls180.v:5969$1542_Y connect \builder_csrbank5_cmd_response7_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_cmd_response7_re $and$ls180.v:5975$1546_Y - connect \builder_csrbank5_cmd_response7_we $and$ls180.v:5976$1550_Y + connect \builder_csrbank5_cmd_response7_re $and$ls180.v:5971$1545_Y + connect \builder_csrbank5_cmd_response7_we $and$ls180.v:5972$1549_Y connect \builder_csrbank5_cmd_response6_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_cmd_response6_re $and$ls180.v:5978$1553_Y - connect \builder_csrbank5_cmd_response6_we $and$ls180.v:5979$1557_Y + connect \builder_csrbank5_cmd_response6_re $and$ls180.v:5974$1552_Y + connect \builder_csrbank5_cmd_response6_we $and$ls180.v:5975$1556_Y connect \builder_csrbank5_cmd_response5_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_cmd_response5_re $and$ls180.v:5981$1560_Y - connect \builder_csrbank5_cmd_response5_we $and$ls180.v:5982$1564_Y + connect \builder_csrbank5_cmd_response5_re $and$ls180.v:5977$1559_Y + connect \builder_csrbank5_cmd_response5_we $and$ls180.v:5978$1563_Y connect \builder_csrbank5_cmd_response4_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_cmd_response4_re $and$ls180.v:5984$1567_Y - connect \builder_csrbank5_cmd_response4_we $and$ls180.v:5985$1571_Y + connect \builder_csrbank5_cmd_response4_re $and$ls180.v:5980$1566_Y + connect \builder_csrbank5_cmd_response4_we $and$ls180.v:5981$1570_Y connect \builder_csrbank5_cmd_response3_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_cmd_response3_re $and$ls180.v:5987$1574_Y - connect \builder_csrbank5_cmd_response3_we $and$ls180.v:5988$1578_Y + connect \builder_csrbank5_cmd_response3_re $and$ls180.v:5983$1573_Y + connect \builder_csrbank5_cmd_response3_we $and$ls180.v:5984$1577_Y connect \builder_csrbank5_cmd_response2_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_cmd_response2_re $and$ls180.v:5990$1581_Y - connect \builder_csrbank5_cmd_response2_we $and$ls180.v:5991$1585_Y + connect \builder_csrbank5_cmd_response2_re $and$ls180.v:5986$1580_Y + connect \builder_csrbank5_cmd_response2_we $and$ls180.v:5987$1584_Y connect \builder_csrbank5_cmd_response1_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_cmd_response1_re $and$ls180.v:5993$1588_Y - connect \builder_csrbank5_cmd_response1_we $and$ls180.v:5994$1592_Y + connect \builder_csrbank5_cmd_response1_re $and$ls180.v:5989$1587_Y + connect \builder_csrbank5_cmd_response1_we $and$ls180.v:5990$1591_Y connect \builder_csrbank5_cmd_response0_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_cmd_response0_re $and$ls180.v:5996$1595_Y - connect \builder_csrbank5_cmd_response0_we $and$ls180.v:5997$1599_Y + connect \builder_csrbank5_cmd_response0_re $and$ls180.v:5992$1594_Y + connect \builder_csrbank5_cmd_response0_we $and$ls180.v:5993$1598_Y connect \builder_csrbank5_cmd_event_r \builder_interface5_bank_bus_dat_w [3:0] - connect \builder_csrbank5_cmd_event_re $and$ls180.v:5999$1602_Y - connect \builder_csrbank5_cmd_event_we $and$ls180.v:6000$1606_Y + connect \builder_csrbank5_cmd_event_re $and$ls180.v:5995$1601_Y + connect \builder_csrbank5_cmd_event_we $and$ls180.v:5996$1605_Y connect \builder_csrbank5_data_event_r \builder_interface5_bank_bus_dat_w [3:0] - connect \builder_csrbank5_data_event_re $and$ls180.v:6002$1609_Y - connect \builder_csrbank5_data_event_we $and$ls180.v:6003$1613_Y + connect \builder_csrbank5_data_event_re $and$ls180.v:5998$1608_Y + connect \builder_csrbank5_data_event_we $and$ls180.v:5999$1612_Y connect \builder_csrbank5_block_length1_r \builder_interface5_bank_bus_dat_w [1:0] - connect \builder_csrbank5_block_length1_re $and$ls180.v:6005$1616_Y - connect \builder_csrbank5_block_length1_we $and$ls180.v:6006$1620_Y + connect \builder_csrbank5_block_length1_re $and$ls180.v:6001$1615_Y + connect \builder_csrbank5_block_length1_we $and$ls180.v:6002$1619_Y connect \builder_csrbank5_block_length0_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_block_length0_re $and$ls180.v:6008$1623_Y - connect \builder_csrbank5_block_length0_we $and$ls180.v:6009$1627_Y + connect \builder_csrbank5_block_length0_re $and$ls180.v:6004$1622_Y + connect \builder_csrbank5_block_length0_we $and$ls180.v:6005$1626_Y connect \builder_csrbank5_block_count3_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_block_count3_re $and$ls180.v:6011$1630_Y - connect \builder_csrbank5_block_count3_we $and$ls180.v:6012$1634_Y + connect \builder_csrbank5_block_count3_re $and$ls180.v:6007$1629_Y + connect \builder_csrbank5_block_count3_we $and$ls180.v:6008$1633_Y connect \builder_csrbank5_block_count2_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_block_count2_re $and$ls180.v:6014$1637_Y - connect \builder_csrbank5_block_count2_we $and$ls180.v:6015$1641_Y + connect \builder_csrbank5_block_count2_re $and$ls180.v:6010$1636_Y + connect \builder_csrbank5_block_count2_we $and$ls180.v:6011$1640_Y connect \builder_csrbank5_block_count1_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_block_count1_re $and$ls180.v:6017$1644_Y - connect \builder_csrbank5_block_count1_we $and$ls180.v:6018$1648_Y + connect \builder_csrbank5_block_count1_re $and$ls180.v:6013$1643_Y + connect \builder_csrbank5_block_count1_we $and$ls180.v:6014$1647_Y connect \builder_csrbank5_block_count0_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_block_count0_re $and$ls180.v:6020$1651_Y - connect \builder_csrbank5_block_count0_we $and$ls180.v:6021$1655_Y + connect \builder_csrbank5_block_count0_re $and$ls180.v:6016$1650_Y + connect \builder_csrbank5_block_count0_we $and$ls180.v:6017$1654_Y connect \builder_csrbank5_cmd_argument3_w \main_sdcore_cmd_argument_storage [31:24] connect \builder_csrbank5_cmd_argument2_w \main_sdcore_cmd_argument_storage [23:16] connect \builder_csrbank5_cmd_argument1_w \main_sdcore_cmd_argument_storage [15:8] @@ -129540,64 +129506,64 @@ module \ls180 connect \builder_csrbank5_block_count2_w \main_sdcore_block_count_storage [23:16] connect \builder_csrbank5_block_count1_w \main_sdcore_block_count_storage [15:8] connect \builder_csrbank5_block_count0_w \main_sdcore_block_count_storage [7:0] - connect \builder_csrbank6_sel $eq$ls180.v:6057$1656_Y + connect \builder_csrbank6_sel $eq$ls180.v:6053$1655_Y connect \builder_csrbank6_dma_base7_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_dma_base7_re $and$ls180.v:6059$1659_Y - connect \builder_csrbank6_dma_base7_we $and$ls180.v:6060$1663_Y + connect \builder_csrbank6_dma_base7_re $and$ls180.v:6055$1658_Y + connect \builder_csrbank6_dma_base7_we $and$ls180.v:6056$1662_Y connect \builder_csrbank6_dma_base6_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_dma_base6_re $and$ls180.v:6062$1666_Y - connect \builder_csrbank6_dma_base6_we $and$ls180.v:6063$1670_Y + connect \builder_csrbank6_dma_base6_re $and$ls180.v:6058$1665_Y + connect \builder_csrbank6_dma_base6_we $and$ls180.v:6059$1669_Y connect \builder_csrbank6_dma_base5_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_dma_base5_re $and$ls180.v:6065$1673_Y - connect \builder_csrbank6_dma_base5_we $and$ls180.v:6066$1677_Y + connect \builder_csrbank6_dma_base5_re $and$ls180.v:6061$1672_Y + connect \builder_csrbank6_dma_base5_we $and$ls180.v:6062$1676_Y connect \builder_csrbank6_dma_base4_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_dma_base4_re $and$ls180.v:6068$1680_Y - connect \builder_csrbank6_dma_base4_we $and$ls180.v:6069$1684_Y + connect \builder_csrbank6_dma_base4_re $and$ls180.v:6064$1679_Y + connect \builder_csrbank6_dma_base4_we $and$ls180.v:6065$1683_Y connect \builder_csrbank6_dma_base3_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_dma_base3_re $and$ls180.v:6071$1687_Y - connect \builder_csrbank6_dma_base3_we $and$ls180.v:6072$1691_Y + connect \builder_csrbank6_dma_base3_re $and$ls180.v:6067$1686_Y + connect \builder_csrbank6_dma_base3_we $and$ls180.v:6068$1690_Y connect \builder_csrbank6_dma_base2_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_dma_base2_re $and$ls180.v:6074$1694_Y - connect \builder_csrbank6_dma_base2_we $and$ls180.v:6075$1698_Y + connect \builder_csrbank6_dma_base2_re $and$ls180.v:6070$1693_Y + connect \builder_csrbank6_dma_base2_we $and$ls180.v:6071$1697_Y connect \builder_csrbank6_dma_base1_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_dma_base1_re $and$ls180.v:6077$1701_Y - connect \builder_csrbank6_dma_base1_we $and$ls180.v:6078$1705_Y + connect \builder_csrbank6_dma_base1_re $and$ls180.v:6073$1700_Y + connect \builder_csrbank6_dma_base1_we $and$ls180.v:6074$1704_Y connect \builder_csrbank6_dma_base0_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_dma_base0_re $and$ls180.v:6080$1708_Y - connect \builder_csrbank6_dma_base0_we $and$ls180.v:6081$1712_Y + connect \builder_csrbank6_dma_base0_re $and$ls180.v:6076$1707_Y + connect \builder_csrbank6_dma_base0_we $and$ls180.v:6077$1711_Y connect \builder_csrbank6_dma_length3_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_dma_length3_re $and$ls180.v:6083$1715_Y - connect \builder_csrbank6_dma_length3_we $and$ls180.v:6084$1719_Y + connect \builder_csrbank6_dma_length3_re $and$ls180.v:6079$1714_Y + connect \builder_csrbank6_dma_length3_we $and$ls180.v:6080$1718_Y connect \builder_csrbank6_dma_length2_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_dma_length2_re $and$ls180.v:6086$1722_Y - connect \builder_csrbank6_dma_length2_we $and$ls180.v:6087$1726_Y + connect \builder_csrbank6_dma_length2_re $and$ls180.v:6082$1721_Y + connect \builder_csrbank6_dma_length2_we $and$ls180.v:6083$1725_Y connect \builder_csrbank6_dma_length1_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_dma_length1_re $and$ls180.v:6089$1729_Y - connect \builder_csrbank6_dma_length1_we $and$ls180.v:6090$1733_Y + connect \builder_csrbank6_dma_length1_re $and$ls180.v:6085$1728_Y + connect \builder_csrbank6_dma_length1_we $and$ls180.v:6086$1732_Y connect \builder_csrbank6_dma_length0_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_dma_length0_re $and$ls180.v:6092$1736_Y - connect \builder_csrbank6_dma_length0_we $and$ls180.v:6093$1740_Y + connect \builder_csrbank6_dma_length0_re $and$ls180.v:6088$1735_Y + connect \builder_csrbank6_dma_length0_we $and$ls180.v:6089$1739_Y connect \builder_csrbank6_dma_enable0_r \builder_interface6_bank_bus_dat_w [0] - connect \builder_csrbank6_dma_enable0_re $and$ls180.v:6095$1743_Y - connect \builder_csrbank6_dma_enable0_we $and$ls180.v:6096$1747_Y + connect \builder_csrbank6_dma_enable0_re $and$ls180.v:6091$1742_Y + connect \builder_csrbank6_dma_enable0_we $and$ls180.v:6092$1746_Y connect \builder_csrbank6_dma_done_r \builder_interface6_bank_bus_dat_w [0] - connect \builder_csrbank6_dma_done_re $and$ls180.v:6098$1750_Y - connect \builder_csrbank6_dma_done_we $and$ls180.v:6099$1754_Y + connect \builder_csrbank6_dma_done_re $and$ls180.v:6094$1749_Y + connect \builder_csrbank6_dma_done_we $and$ls180.v:6095$1753_Y connect \builder_csrbank6_dma_loop0_r \builder_interface6_bank_bus_dat_w [0] - connect \builder_csrbank6_dma_loop0_re $and$ls180.v:6101$1757_Y - connect \builder_csrbank6_dma_loop0_we $and$ls180.v:6102$1761_Y + connect \builder_csrbank6_dma_loop0_re $and$ls180.v:6097$1756_Y + connect \builder_csrbank6_dma_loop0_we $and$ls180.v:6098$1760_Y connect \builder_csrbank6_dma_offset3_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_dma_offset3_re $and$ls180.v:6104$1764_Y - connect \builder_csrbank6_dma_offset3_we $and$ls180.v:6105$1768_Y + connect \builder_csrbank6_dma_offset3_re $and$ls180.v:6100$1763_Y + connect \builder_csrbank6_dma_offset3_we $and$ls180.v:6101$1767_Y connect \builder_csrbank6_dma_offset2_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_dma_offset2_re $and$ls180.v:6107$1771_Y - connect \builder_csrbank6_dma_offset2_we $and$ls180.v:6108$1775_Y + connect \builder_csrbank6_dma_offset2_re $and$ls180.v:6103$1770_Y + connect \builder_csrbank6_dma_offset2_we $and$ls180.v:6104$1774_Y connect \builder_csrbank6_dma_offset1_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_dma_offset1_re $and$ls180.v:6110$1778_Y - connect \builder_csrbank6_dma_offset1_we $and$ls180.v:6111$1782_Y + connect \builder_csrbank6_dma_offset1_re $and$ls180.v:6106$1777_Y + connect \builder_csrbank6_dma_offset1_we $and$ls180.v:6107$1781_Y connect \builder_csrbank6_dma_offset0_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_dma_offset0_re $and$ls180.v:6113$1785_Y - connect \builder_csrbank6_dma_offset0_we $and$ls180.v:6114$1789_Y + connect \builder_csrbank6_dma_offset0_re $and$ls180.v:6109$1784_Y + connect \builder_csrbank6_dma_offset0_we $and$ls180.v:6110$1788_Y connect \builder_csrbank6_dma_base7_w \main_sdmem2block_dma_base_storage [63:56] connect \builder_csrbank6_dma_base6_w \main_sdmem2block_dma_base_storage [55:48] connect \builder_csrbank6_dma_base5_w \main_sdmem2block_dma_base_storage [47:40] @@ -129619,54 +129585,54 @@ module \ls180 connect \builder_csrbank6_dma_offset1_w \main_sdmem2block_dma_offset_status [15:8] connect \builder_csrbank6_dma_offset0_w \main_sdmem2block_dma_offset_status [7:0] connect \main_sdmem2block_dma_offset_we \builder_csrbank6_dma_offset0_we - connect \builder_csrbank7_sel $eq$ls180.v:6136$1790_Y + connect \builder_csrbank7_sel $eq$ls180.v:6132$1789_Y connect \builder_csrbank7_card_detect_r \builder_interface7_bank_bus_dat_w [0] - connect \builder_csrbank7_card_detect_re $and$ls180.v:6138$1793_Y - connect \builder_csrbank7_card_detect_we $and$ls180.v:6139$1797_Y + connect \builder_csrbank7_card_detect_re $and$ls180.v:6134$1792_Y + connect \builder_csrbank7_card_detect_we $and$ls180.v:6135$1796_Y connect \builder_csrbank7_clocker_divider1_r \builder_interface7_bank_bus_dat_w [0] - connect \builder_csrbank7_clocker_divider1_re $and$ls180.v:6141$1800_Y - connect \builder_csrbank7_clocker_divider1_we $and$ls180.v:6142$1804_Y + connect \builder_csrbank7_clocker_divider1_re $and$ls180.v:6137$1799_Y + connect \builder_csrbank7_clocker_divider1_we $and$ls180.v:6138$1803_Y connect \builder_csrbank7_clocker_divider0_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_clocker_divider0_re $and$ls180.v:6144$1807_Y - connect \builder_csrbank7_clocker_divider0_we $and$ls180.v:6145$1811_Y + connect \builder_csrbank7_clocker_divider0_re $and$ls180.v:6140$1806_Y + connect \builder_csrbank7_clocker_divider0_we $and$ls180.v:6141$1810_Y connect \main_sdphy_init_initialize_r \builder_interface7_bank_bus_dat_w [0] - connect \main_sdphy_init_initialize_re $and$ls180.v:6147$1814_Y - connect \main_sdphy_init_initialize_we $and$ls180.v:6148$1818_Y + connect \main_sdphy_init_initialize_re $and$ls180.v:6143$1813_Y + connect \main_sdphy_init_initialize_we $and$ls180.v:6144$1817_Y connect \builder_csrbank7_card_detect_w \main_sdphy_status connect \main_sdphy_we \builder_csrbank7_card_detect_we connect \builder_csrbank7_clocker_divider1_w \main_sdphy_clocker_storage [8] connect \builder_csrbank7_clocker_divider0_w \main_sdphy_clocker_storage [7:0] - connect \builder_csrbank8_sel $eq$ls180.v:6153$1819_Y + connect \builder_csrbank8_sel $eq$ls180.v:6149$1818_Y connect \builder_csrbank8_dfii_control0_r \builder_interface8_bank_bus_dat_w [3:0] - connect \builder_csrbank8_dfii_control0_re $and$ls180.v:6155$1822_Y - connect \builder_csrbank8_dfii_control0_we $and$ls180.v:6156$1826_Y + connect \builder_csrbank8_dfii_control0_re $and$ls180.v:6151$1821_Y + connect \builder_csrbank8_dfii_control0_we $and$ls180.v:6152$1825_Y connect \builder_csrbank8_dfii_pi0_command0_r \builder_interface8_bank_bus_dat_w [5:0] - connect \builder_csrbank8_dfii_pi0_command0_re $and$ls180.v:6158$1829_Y - connect \builder_csrbank8_dfii_pi0_command0_we $and$ls180.v:6159$1833_Y + connect \builder_csrbank8_dfii_pi0_command0_re $and$ls180.v:6154$1828_Y + connect \builder_csrbank8_dfii_pi0_command0_we $and$ls180.v:6155$1832_Y connect \main_sdram_command_issue_r \builder_interface8_bank_bus_dat_w [0] - connect \main_sdram_command_issue_re $and$ls180.v:6161$1836_Y - connect \main_sdram_command_issue_we $and$ls180.v:6162$1840_Y + connect \main_sdram_command_issue_re $and$ls180.v:6157$1835_Y + connect \main_sdram_command_issue_we $and$ls180.v:6158$1839_Y connect \builder_csrbank8_dfii_pi0_address1_r \builder_interface8_bank_bus_dat_w [4:0] - connect \builder_csrbank8_dfii_pi0_address1_re $and$ls180.v:6164$1843_Y - connect \builder_csrbank8_dfii_pi0_address1_we $and$ls180.v:6165$1847_Y + connect \builder_csrbank8_dfii_pi0_address1_re $and$ls180.v:6160$1842_Y + connect \builder_csrbank8_dfii_pi0_address1_we $and$ls180.v:6161$1846_Y connect \builder_csrbank8_dfii_pi0_address0_r \builder_interface8_bank_bus_dat_w - connect \builder_csrbank8_dfii_pi0_address0_re $and$ls180.v:6167$1850_Y - connect \builder_csrbank8_dfii_pi0_address0_we $and$ls180.v:6168$1854_Y + connect \builder_csrbank8_dfii_pi0_address0_re $and$ls180.v:6163$1849_Y + connect \builder_csrbank8_dfii_pi0_address0_we $and$ls180.v:6164$1853_Y connect \builder_csrbank8_dfii_pi0_baddress0_r \builder_interface8_bank_bus_dat_w [1:0] - connect \builder_csrbank8_dfii_pi0_baddress0_re $and$ls180.v:6170$1857_Y - connect \builder_csrbank8_dfii_pi0_baddress0_we $and$ls180.v:6171$1861_Y + connect \builder_csrbank8_dfii_pi0_baddress0_re $and$ls180.v:6166$1856_Y + connect \builder_csrbank8_dfii_pi0_baddress0_we $and$ls180.v:6167$1860_Y connect \builder_csrbank8_dfii_pi0_wrdata1_r \builder_interface8_bank_bus_dat_w - connect \builder_csrbank8_dfii_pi0_wrdata1_re $and$ls180.v:6173$1864_Y - connect \builder_csrbank8_dfii_pi0_wrdata1_we $and$ls180.v:6174$1868_Y + connect \builder_csrbank8_dfii_pi0_wrdata1_re $and$ls180.v:6169$1863_Y + connect \builder_csrbank8_dfii_pi0_wrdata1_we $and$ls180.v:6170$1867_Y connect \builder_csrbank8_dfii_pi0_wrdata0_r \builder_interface8_bank_bus_dat_w - connect \builder_csrbank8_dfii_pi0_wrdata0_re $and$ls180.v:6176$1871_Y - connect \builder_csrbank8_dfii_pi0_wrdata0_we $and$ls180.v:6177$1875_Y + connect \builder_csrbank8_dfii_pi0_wrdata0_re $and$ls180.v:6172$1870_Y + connect \builder_csrbank8_dfii_pi0_wrdata0_we $and$ls180.v:6173$1874_Y connect \builder_csrbank8_dfii_pi0_rddata1_r \builder_interface8_bank_bus_dat_w - connect \builder_csrbank8_dfii_pi0_rddata1_re $and$ls180.v:6179$1878_Y - connect \builder_csrbank8_dfii_pi0_rddata1_we $and$ls180.v:6180$1882_Y + connect \builder_csrbank8_dfii_pi0_rddata1_re $and$ls180.v:6175$1877_Y + connect \builder_csrbank8_dfii_pi0_rddata1_we $and$ls180.v:6176$1881_Y connect \builder_csrbank8_dfii_pi0_rddata0_r \builder_interface8_bank_bus_dat_w - connect \builder_csrbank8_dfii_pi0_rddata0_re $and$ls180.v:6182$1885_Y - connect \builder_csrbank8_dfii_pi0_rddata0_we $and$ls180.v:6183$1889_Y + connect \builder_csrbank8_dfii_pi0_rddata0_re $and$ls180.v:6178$1884_Y + connect \builder_csrbank8_dfii_pi0_rddata0_we $and$ls180.v:6179$1888_Y connect \main_sdram_sel \main_sdram_storage [0] connect \main_sdram_cke \main_sdram_storage [1] connect \main_sdram_odt \main_sdram_storage [2] @@ -129681,28 +129647,28 @@ module \ls180 connect \builder_csrbank8_dfii_pi0_rddata1_w \main_sdram_status [15:8] connect \builder_csrbank8_dfii_pi0_rddata0_w \main_sdram_status [7:0] connect \main_sdram_we \builder_csrbank8_dfii_pi0_rddata0_we - connect \builder_csrbank9_sel $eq$ls180.v:6198$1890_Y + connect \builder_csrbank9_sel $eq$ls180.v:6194$1889_Y connect \builder_csrbank9_control1_r \builder_interface9_bank_bus_dat_w - connect \builder_csrbank9_control1_re $and$ls180.v:6200$1893_Y - connect \builder_csrbank9_control1_we $and$ls180.v:6201$1897_Y + connect \builder_csrbank9_control1_re $and$ls180.v:6196$1892_Y + connect \builder_csrbank9_control1_we $and$ls180.v:6197$1896_Y connect \builder_csrbank9_control0_r \builder_interface9_bank_bus_dat_w - connect \builder_csrbank9_control0_re $and$ls180.v:6203$1900_Y - connect \builder_csrbank9_control0_we $and$ls180.v:6204$1904_Y + connect \builder_csrbank9_control0_re $and$ls180.v:6199$1899_Y + connect \builder_csrbank9_control0_we $and$ls180.v:6200$1903_Y connect \builder_csrbank9_status_r \builder_interface9_bank_bus_dat_w [0] - connect \builder_csrbank9_status_re $and$ls180.v:6206$1907_Y - connect \builder_csrbank9_status_we $and$ls180.v:6207$1911_Y + connect \builder_csrbank9_status_re $and$ls180.v:6202$1906_Y + connect \builder_csrbank9_status_we $and$ls180.v:6203$1910_Y connect \builder_csrbank9_mosi0_r \builder_interface9_bank_bus_dat_w - connect \builder_csrbank9_mosi0_re $and$ls180.v:6209$1914_Y - connect \builder_csrbank9_mosi0_we $and$ls180.v:6210$1918_Y + connect \builder_csrbank9_mosi0_re $and$ls180.v:6205$1913_Y + connect \builder_csrbank9_mosi0_we $and$ls180.v:6206$1917_Y connect \builder_csrbank9_miso_r \builder_interface9_bank_bus_dat_w - connect \builder_csrbank9_miso_re $and$ls180.v:6212$1921_Y - connect \builder_csrbank9_miso_we $and$ls180.v:6213$1925_Y + connect \builder_csrbank9_miso_re $and$ls180.v:6208$1920_Y + connect \builder_csrbank9_miso_we $and$ls180.v:6209$1924_Y connect \builder_csrbank9_cs0_r \builder_interface9_bank_bus_dat_w [0] - connect \builder_csrbank9_cs0_re $and$ls180.v:6215$1928_Y - connect \builder_csrbank9_cs0_we $and$ls180.v:6216$1932_Y + connect \builder_csrbank9_cs0_re $and$ls180.v:6211$1927_Y + connect \builder_csrbank9_cs0_we $and$ls180.v:6212$1931_Y connect \builder_csrbank9_loopback0_r \builder_interface9_bank_bus_dat_w [0] - connect \builder_csrbank9_loopback0_re $and$ls180.v:6218$1935_Y - connect \builder_csrbank9_loopback0_we $and$ls180.v:6219$1939_Y + connect \builder_csrbank9_loopback0_re $and$ls180.v:6214$1934_Y + connect \builder_csrbank9_loopback0_we $and$ls180.v:6215$1938_Y connect \main_spi_master_length1 \main_spi_master_control_storage [15:8] connect \builder_csrbank9_control1_w \main_spi_master_control_storage [15:8] connect \builder_csrbank9_control0_w \main_spi_master_control_storage [7:0] @@ -129715,34 +129681,34 @@ module \ls180 connect \main_spi_master_sel \main_spi_master_cs_storage connect \builder_csrbank9_cs0_w \main_spi_master_cs_storage connect \builder_csrbank9_loopback0_w \main_spi_master_loopback_storage - connect \builder_csrbank10_sel $eq$ls180.v:6238$1941_Y + connect \builder_csrbank10_sel $eq$ls180.v:6234$1940_Y connect \builder_csrbank10_control1_r \builder_interface10_bank_bus_dat_w - connect \builder_csrbank10_control1_re $and$ls180.v:6240$1944_Y - connect \builder_csrbank10_control1_we $and$ls180.v:6241$1948_Y + connect \builder_csrbank10_control1_re $and$ls180.v:6236$1943_Y + connect \builder_csrbank10_control1_we $and$ls180.v:6237$1947_Y connect \builder_csrbank10_control0_r \builder_interface10_bank_bus_dat_w - connect \builder_csrbank10_control0_re $and$ls180.v:6243$1951_Y - connect \builder_csrbank10_control0_we $and$ls180.v:6244$1955_Y + connect \builder_csrbank10_control0_re $and$ls180.v:6239$1950_Y + connect \builder_csrbank10_control0_we $and$ls180.v:6240$1954_Y connect \builder_csrbank10_status_r \builder_interface10_bank_bus_dat_w [0] - connect \builder_csrbank10_status_re $and$ls180.v:6246$1958_Y - connect \builder_csrbank10_status_we $and$ls180.v:6247$1962_Y + connect \builder_csrbank10_status_re $and$ls180.v:6242$1957_Y + connect \builder_csrbank10_status_we $and$ls180.v:6243$1961_Y connect \builder_csrbank10_mosi0_r \builder_interface10_bank_bus_dat_w - connect \builder_csrbank10_mosi0_re $and$ls180.v:6249$1965_Y - connect \builder_csrbank10_mosi0_we $and$ls180.v:6250$1969_Y + connect \builder_csrbank10_mosi0_re $and$ls180.v:6245$1964_Y + connect \builder_csrbank10_mosi0_we $and$ls180.v:6246$1968_Y connect \builder_csrbank10_miso_r \builder_interface10_bank_bus_dat_w - connect \builder_csrbank10_miso_re $and$ls180.v:6252$1972_Y - connect \builder_csrbank10_miso_we $and$ls180.v:6253$1976_Y + connect \builder_csrbank10_miso_re $and$ls180.v:6248$1971_Y + connect \builder_csrbank10_miso_we $and$ls180.v:6249$1975_Y connect \builder_csrbank10_cs0_r \builder_interface10_bank_bus_dat_w [0] - connect \builder_csrbank10_cs0_re $and$ls180.v:6255$1979_Y - connect \builder_csrbank10_cs0_we $and$ls180.v:6256$1983_Y + connect \builder_csrbank10_cs0_re $and$ls180.v:6251$1978_Y + connect \builder_csrbank10_cs0_we $and$ls180.v:6252$1982_Y connect \builder_csrbank10_loopback0_r \builder_interface10_bank_bus_dat_w [0] - connect \builder_csrbank10_loopback0_re $and$ls180.v:6258$1986_Y - connect \builder_csrbank10_loopback0_we $and$ls180.v:6259$1990_Y + connect \builder_csrbank10_loopback0_re $and$ls180.v:6254$1985_Y + connect \builder_csrbank10_loopback0_we $and$ls180.v:6255$1989_Y connect \builder_csrbank10_clk_divider1_r \builder_interface10_bank_bus_dat_w - connect \builder_csrbank10_clk_divider1_re $and$ls180.v:6261$1993_Y - connect \builder_csrbank10_clk_divider1_we $and$ls180.v:6262$1997_Y + connect \builder_csrbank10_clk_divider1_re $and$ls180.v:6257$1992_Y + connect \builder_csrbank10_clk_divider1_we $and$ls180.v:6258$1996_Y connect \builder_csrbank10_clk_divider0_r \builder_interface10_bank_bus_dat_w - connect \builder_csrbank10_clk_divider0_re $and$ls180.v:6264$2000_Y - connect \builder_csrbank10_clk_divider0_we $and$ls180.v:6265$2004_Y + connect \builder_csrbank10_clk_divider0_re $and$ls180.v:6260$1999_Y + connect \builder_csrbank10_clk_divider0_we $and$ls180.v:6261$2003_Y connect \libresocsim_length1 \libresocsim_control_storage [15:8] connect \builder_csrbank10_control1_w \libresocsim_control_storage [15:8] connect \builder_csrbank10_control0_w \libresocsim_control_storage [7:0] @@ -129757,58 +129723,58 @@ module \ls180 connect \builder_csrbank10_loopback0_w \libresocsim_loopback_storage connect \builder_csrbank10_clk_divider1_w \libresocsim_storage [15:8] connect \builder_csrbank10_clk_divider0_w \libresocsim_storage [7:0] - connect \builder_csrbank11_sel $eq$ls180.v:6286$2006_Y + connect \builder_csrbank11_sel $eq$ls180.v:6282$2005_Y connect \builder_csrbank11_load3_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_load3_re $and$ls180.v:6288$2009_Y - connect \builder_csrbank11_load3_we $and$ls180.v:6289$2013_Y + connect \builder_csrbank11_load3_re $and$ls180.v:6284$2008_Y + connect \builder_csrbank11_load3_we $and$ls180.v:6285$2012_Y connect \builder_csrbank11_load2_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_load2_re $and$ls180.v:6291$2016_Y - connect \builder_csrbank11_load2_we $and$ls180.v:6292$2020_Y + connect \builder_csrbank11_load2_re $and$ls180.v:6287$2015_Y + connect \builder_csrbank11_load2_we $and$ls180.v:6288$2019_Y connect \builder_csrbank11_load1_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_load1_re $and$ls180.v:6294$2023_Y - connect \builder_csrbank11_load1_we $and$ls180.v:6295$2027_Y + connect \builder_csrbank11_load1_re $and$ls180.v:6290$2022_Y + connect \builder_csrbank11_load1_we $and$ls180.v:6291$2026_Y connect \builder_csrbank11_load0_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_load0_re $and$ls180.v:6297$2030_Y - connect \builder_csrbank11_load0_we $and$ls180.v:6298$2034_Y + connect \builder_csrbank11_load0_re $and$ls180.v:6293$2029_Y + connect \builder_csrbank11_load0_we $and$ls180.v:6294$2033_Y connect \builder_csrbank11_reload3_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_reload3_re $and$ls180.v:6300$2037_Y - connect \builder_csrbank11_reload3_we $and$ls180.v:6301$2041_Y + connect \builder_csrbank11_reload3_re $and$ls180.v:6296$2036_Y + connect \builder_csrbank11_reload3_we $and$ls180.v:6297$2040_Y connect \builder_csrbank11_reload2_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_reload2_re $and$ls180.v:6303$2044_Y - connect \builder_csrbank11_reload2_we $and$ls180.v:6304$2048_Y + connect \builder_csrbank11_reload2_re $and$ls180.v:6299$2043_Y + connect \builder_csrbank11_reload2_we $and$ls180.v:6300$2047_Y connect \builder_csrbank11_reload1_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_reload1_re $and$ls180.v:6306$2051_Y - connect \builder_csrbank11_reload1_we $and$ls180.v:6307$2055_Y + connect \builder_csrbank11_reload1_re $and$ls180.v:6302$2050_Y + connect \builder_csrbank11_reload1_we $and$ls180.v:6303$2054_Y connect \builder_csrbank11_reload0_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_reload0_re $and$ls180.v:6309$2058_Y - connect \builder_csrbank11_reload0_we $and$ls180.v:6310$2062_Y + connect \builder_csrbank11_reload0_re $and$ls180.v:6305$2057_Y + connect \builder_csrbank11_reload0_we $and$ls180.v:6306$2061_Y connect \builder_csrbank11_en0_r \builder_interface11_bank_bus_dat_w [0] - connect \builder_csrbank11_en0_re $and$ls180.v:6312$2065_Y - connect \builder_csrbank11_en0_we $and$ls180.v:6313$2069_Y + connect \builder_csrbank11_en0_re $and$ls180.v:6308$2064_Y + connect \builder_csrbank11_en0_we $and$ls180.v:6309$2068_Y connect \builder_csrbank11_update_value0_r \builder_interface11_bank_bus_dat_w [0] - connect \builder_csrbank11_update_value0_re $and$ls180.v:6315$2072_Y - connect \builder_csrbank11_update_value0_we $and$ls180.v:6316$2076_Y + connect \builder_csrbank11_update_value0_re $and$ls180.v:6311$2071_Y + connect \builder_csrbank11_update_value0_we $and$ls180.v:6312$2075_Y connect \builder_csrbank11_value3_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_value3_re $and$ls180.v:6318$2079_Y - connect \builder_csrbank11_value3_we $and$ls180.v:6319$2083_Y + connect \builder_csrbank11_value3_re $and$ls180.v:6314$2078_Y + connect \builder_csrbank11_value3_we $and$ls180.v:6315$2082_Y connect \builder_csrbank11_value2_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_value2_re $and$ls180.v:6321$2086_Y - connect \builder_csrbank11_value2_we $and$ls180.v:6322$2090_Y + connect \builder_csrbank11_value2_re $and$ls180.v:6317$2085_Y + connect \builder_csrbank11_value2_we $and$ls180.v:6318$2089_Y connect \builder_csrbank11_value1_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_value1_re $and$ls180.v:6324$2093_Y - connect \builder_csrbank11_value1_we $and$ls180.v:6325$2097_Y + connect \builder_csrbank11_value1_re $and$ls180.v:6320$2092_Y + connect \builder_csrbank11_value1_we $and$ls180.v:6321$2096_Y connect \builder_csrbank11_value0_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_value0_re $and$ls180.v:6327$2100_Y - connect \builder_csrbank11_value0_we $and$ls180.v:6328$2104_Y + connect \builder_csrbank11_value0_re $and$ls180.v:6323$2099_Y + connect \builder_csrbank11_value0_we $and$ls180.v:6324$2103_Y connect \main_libresocsim_eventmanager_status_r \builder_interface11_bank_bus_dat_w [0] - connect \main_libresocsim_eventmanager_status_re $and$ls180.v:6330$2107_Y - connect \main_libresocsim_eventmanager_status_we $and$ls180.v:6331$2111_Y + connect \main_libresocsim_eventmanager_status_re $and$ls180.v:6326$2106_Y + connect \main_libresocsim_eventmanager_status_we $and$ls180.v:6327$2110_Y connect \main_libresocsim_eventmanager_pending_r \builder_interface11_bank_bus_dat_w [0] - connect \main_libresocsim_eventmanager_pending_re $and$ls180.v:6333$2114_Y - connect \main_libresocsim_eventmanager_pending_we $and$ls180.v:6334$2118_Y + connect \main_libresocsim_eventmanager_pending_re $and$ls180.v:6329$2113_Y + connect \main_libresocsim_eventmanager_pending_we $and$ls180.v:6330$2117_Y connect \builder_csrbank11_ev_enable0_r \builder_interface11_bank_bus_dat_w [0] - connect \builder_csrbank11_ev_enable0_re $and$ls180.v:6336$2121_Y - connect \builder_csrbank11_ev_enable0_we $and$ls180.v:6337$2125_Y + connect \builder_csrbank11_ev_enable0_re $and$ls180.v:6332$2120_Y + connect \builder_csrbank11_ev_enable0_we $and$ls180.v:6333$2124_Y connect \builder_csrbank11_load3_w \main_libresocsim_load_storage [31:24] connect \builder_csrbank11_load2_w \main_libresocsim_load_storage [23:16] connect \builder_csrbank11_load1_w \main_libresocsim_load_storage [15:8] @@ -129825,31 +129791,31 @@ module \ls180 connect \builder_csrbank11_value0_w \main_libresocsim_value_status [7:0] connect \main_libresocsim_value_we \builder_csrbank11_value0_we connect \builder_csrbank11_ev_enable0_w \main_libresocsim_eventmanager_storage - connect \builder_csrbank12_sel $eq$ls180.v:6354$2126_Y + connect \builder_csrbank12_sel $eq$ls180.v:6350$2125_Y connect \main_uart_rxtx_r \builder_interface12_bank_bus_dat_w - connect \main_uart_rxtx_re $and$ls180.v:6356$2129_Y - connect \main_uart_rxtx_we $and$ls180.v:6357$2133_Y + connect \main_uart_rxtx_re $and$ls180.v:6352$2128_Y + connect \main_uart_rxtx_we $and$ls180.v:6353$2132_Y connect \builder_csrbank12_txfull_r \builder_interface12_bank_bus_dat_w [0] - connect \builder_csrbank12_txfull_re $and$ls180.v:6359$2136_Y - connect \builder_csrbank12_txfull_we $and$ls180.v:6360$2140_Y + connect \builder_csrbank12_txfull_re $and$ls180.v:6355$2135_Y + connect \builder_csrbank12_txfull_we $and$ls180.v:6356$2139_Y connect \builder_csrbank12_rxempty_r \builder_interface12_bank_bus_dat_w [0] - connect \builder_csrbank12_rxempty_re $and$ls180.v:6362$2143_Y - connect \builder_csrbank12_rxempty_we $and$ls180.v:6363$2147_Y + connect \builder_csrbank12_rxempty_re $and$ls180.v:6358$2142_Y + connect \builder_csrbank12_rxempty_we $and$ls180.v:6359$2146_Y connect \main_uart_eventmanager_status_r \builder_interface12_bank_bus_dat_w [1:0] - connect \main_uart_eventmanager_status_re $and$ls180.v:6365$2150_Y - connect \main_uart_eventmanager_status_we $and$ls180.v:6366$2154_Y + connect \main_uart_eventmanager_status_re $and$ls180.v:6361$2149_Y + connect \main_uart_eventmanager_status_we $and$ls180.v:6362$2153_Y connect \main_uart_eventmanager_pending_r \builder_interface12_bank_bus_dat_w [1:0] - connect \main_uart_eventmanager_pending_re $and$ls180.v:6368$2157_Y - connect \main_uart_eventmanager_pending_we $and$ls180.v:6369$2161_Y + connect \main_uart_eventmanager_pending_re $and$ls180.v:6364$2156_Y + connect \main_uart_eventmanager_pending_we $and$ls180.v:6365$2160_Y connect \builder_csrbank12_ev_enable0_r \builder_interface12_bank_bus_dat_w [1:0] - connect \builder_csrbank12_ev_enable0_re $and$ls180.v:6371$2164_Y - connect \builder_csrbank12_ev_enable0_we $and$ls180.v:6372$2168_Y + connect \builder_csrbank12_ev_enable0_re $and$ls180.v:6367$2163_Y + connect \builder_csrbank12_ev_enable0_we $and$ls180.v:6368$2167_Y connect \builder_csrbank12_txempty_r \builder_interface12_bank_bus_dat_w [0] - connect \builder_csrbank12_txempty_re $and$ls180.v:6374$2171_Y - connect \builder_csrbank12_txempty_we $and$ls180.v:6375$2175_Y + connect \builder_csrbank12_txempty_re $and$ls180.v:6370$2170_Y + connect \builder_csrbank12_txempty_we $and$ls180.v:6371$2174_Y connect \builder_csrbank12_rxfull_r \builder_interface12_bank_bus_dat_w [0] - connect \builder_csrbank12_rxfull_re $and$ls180.v:6377$2178_Y - connect \builder_csrbank12_rxfull_we $and$ls180.v:6378$2182_Y + connect \builder_csrbank12_rxfull_re $and$ls180.v:6373$2177_Y + connect \builder_csrbank12_rxfull_we $and$ls180.v:6374$2181_Y connect \builder_csrbank12_txfull_w \main_uart_txfull_status connect \main_uart_txfull_we \builder_csrbank12_txfull_we connect \builder_csrbank12_rxempty_w \main_uart_rxempty_status @@ -129859,19 +129825,19 @@ module \ls180 connect \main_uart_txempty_we \builder_csrbank12_txempty_we connect \builder_csrbank12_rxfull_w \main_uart_rxfull_status connect \main_uart_rxfull_we \builder_csrbank12_rxfull_we - connect \builder_csrbank13_sel $eq$ls180.v:6388$2183_Y + connect \builder_csrbank13_sel $eq$ls180.v:6384$2182_Y connect \builder_csrbank13_tuning_word3_r \builder_interface13_bank_bus_dat_w - connect \builder_csrbank13_tuning_word3_re $and$ls180.v:6390$2186_Y - connect \builder_csrbank13_tuning_word3_we $and$ls180.v:6391$2190_Y + connect \builder_csrbank13_tuning_word3_re $and$ls180.v:6386$2185_Y + connect \builder_csrbank13_tuning_word3_we $and$ls180.v:6387$2189_Y connect \builder_csrbank13_tuning_word2_r \builder_interface13_bank_bus_dat_w - connect \builder_csrbank13_tuning_word2_re $and$ls180.v:6393$2193_Y - connect \builder_csrbank13_tuning_word2_we $and$ls180.v:6394$2197_Y + connect \builder_csrbank13_tuning_word2_re $and$ls180.v:6389$2192_Y + connect \builder_csrbank13_tuning_word2_we $and$ls180.v:6390$2196_Y connect \builder_csrbank13_tuning_word1_r \builder_interface13_bank_bus_dat_w - connect \builder_csrbank13_tuning_word1_re $and$ls180.v:6396$2200_Y - connect \builder_csrbank13_tuning_word1_we $and$ls180.v:6397$2204_Y + connect \builder_csrbank13_tuning_word1_re $and$ls180.v:6392$2199_Y + connect \builder_csrbank13_tuning_word1_we $and$ls180.v:6393$2203_Y connect \builder_csrbank13_tuning_word0_r \builder_interface13_bank_bus_dat_w - connect \builder_csrbank13_tuning_word0_re $and$ls180.v:6399$2207_Y - connect \builder_csrbank13_tuning_word0_we $and$ls180.v:6400$2211_Y + connect \builder_csrbank13_tuning_word0_re $and$ls180.v:6395$2206_Y + connect \builder_csrbank13_tuning_word0_we $and$ls180.v:6396$2210_Y connect \builder_csrbank13_tuning_word3_w \main_storage [31:24] connect \builder_csrbank13_tuning_word2_w \main_storage [23:16] connect \builder_csrbank13_tuning_word1_w \main_storage [15:8] @@ -129922,7 +129888,7 @@ module \ls180 connect \builder_interface11_bank_bus_dat_w \builder_csr_interconnect_dat_w connect \builder_interface12_bank_bus_dat_w \builder_csr_interconnect_dat_w connect \builder_interface13_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_csr_interconnect_dat_r $or$ls180.v:6451$2224_Y + connect \builder_csr_interconnect_dat_r $or$ls180.v:6447$2223_Y connect \sdrio_clk \sys_clk_1 connect \sdrio_clk_1 \sys_clk_1 connect \sdrio_clk_2 \sys_clk_1 @@ -129977,6 +129943,8 @@ module \ls180 connect \sdrio_clk_51 \sys_clk_1 connect \sdrio_clk_52 \sys_clk_1 connect \sdrio_clk_53 \sys_clk_1 + connect \sdrio_clk_54 \sys_clk_1 + connect \sdrio_clk_55 \sys_clk_1 connect \main_rx \builder_multiregimpl0_regs1 connect \main_pwm0_enable \main_pwm0_enable_storage connect \main_pwm0_width \main_pwm0_width_storage @@ -129984,8 +129952,6 @@ module \ls180 connect \main_pwm1_enable \main_pwm1_enable_storage connect \main_pwm1_width \main_pwm1_width_storage connect \main_pwm1_period \main_pwm1_period_storage - connect \sdrio_clk_54 \sys_clk_1 - connect \sdrio_clk_55 \sys_clk_1 connect \sdrio_clk_56 \sys_clk_1 connect \sdrio_clk_57 \sys_clk_1 connect \sdrio_clk_58 \sys_clk_1 @@ -129997,23 +129963,25 @@ module \ls180 connect \sdrio_clk_64 \sys_clk_1 connect \sdrio_clk_65 \sys_clk_1 connect \sdrio_clk_66 \sys_clk_1 - connect \main_libresocsim_dat_r $memrd$\mem$ls180.v:9993$2697_DATA + connect \sdrio_clk_67 \sys_clk_1 + connect \sdrio_clk_68 \sys_clk_1 + connect \main_libresocsim_dat_r $memrd$\mem$ls180.v:9989$2695_DATA connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r \memdat - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage$ls180.v:10011$2704_DATA + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage$ls180.v:10007$2702_DATA connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r \memdat_1 - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_1$ls180.v:10025$2711_DATA + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_1$ls180.v:10021$2709_DATA connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r \memdat_2 - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_2$ls180.v:10039$2718_DATA + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_2$ls180.v:10035$2716_DATA connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r \memdat_3 - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_3$ls180.v:10053$2725_DATA + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_3$ls180.v:10049$2723_DATA connect \main_uart_tx_fifo_wrport_dat_r \memdat_4 connect \main_uart_tx_fifo_rdport_dat_r \memdat_5 connect \main_uart_rx_fifo_wrport_dat_r \memdat_6 connect \main_uart_rx_fifo_rdport_dat_r \memdat_7 connect \main_sdblock2mem_fifo_wrport_dat_r \memdat_8 - connect \main_sdblock2mem_fifo_rdport_dat_r $memrd$\storage_6$ls180.v:10101$2746_DATA + connect \main_sdblock2mem_fifo_rdport_dat_r $memrd$\storage_6$ls180.v:10097$2744_DATA connect \main_sdmem2block_fifo_wrport_dat_r \memdat_9 - connect \main_sdmem2block_fifo_rdport_dat_r $memrd$\storage_7$ls180.v:10115$2753_DATA + connect \main_sdmem2block_fifo_rdport_dat_r $memrd$\storage_7$ls180.v:10111$2751_DATA end attribute \src "libresoc.v:44585.1-44669.10" attribute \cells_not_processed 1 @@ -134061,9 +134029,9 @@ module \test_issuer wire output 8 \TAP_bus__tdo attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" wire input 10 \TAP_bus__tms - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:93" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:94" wire \bigendian_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:93" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:94" wire \bigendian_i$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:90" wire output 5 \busy_o @@ -134362,7 +134330,7 @@ module \test_issuer wire \core_rego_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire \core_rego_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:102" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:103" wire \core_reset_i attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -134602,9 +134570,9 @@ module \test_issuer wire \core_spro_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire \core_spro_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:101" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:102" wire \core_stopped_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:103" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:104" wire \core_terminate_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:102" wire width 3 \core_xer_in @@ -134614,7 +134582,7 @@ module \test_issuer wire \core_xer_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:103" wire \core_xer_out$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:98" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:99" wire \corebusy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" wire \coresync_clk @@ -135469,9 +135437,9 @@ module \test_issuer wire \issue__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire \issue__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:97" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:98" wire \issue_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:96" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:97" wire \ivalid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:62" wire \jtag_dmi0_ack_o @@ -135541,9 +135509,9 @@ module \test_issuer wire \pc_ok_delay$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:150" wire \por_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:92" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:93" wire width 32 \raw_insn_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:92" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:93" wire width 32 \raw_insn_i$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:151" wire input 7 \rst