From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 3 Oct 2019 17:45:53 +0000 (-0700)
Subject: Disable equiv check for ice40 latches
X-Git-Tag: working-ls180~1001^2~2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bd5889640bbcbb11c80360893fcf17d9399cef8a;p=yosys.git

Disable equiv check for ice40 latches
---

diff --git a/tests/ice40/latches.ys b/tests/ice40/latches.ys
index f3562559e..708734e44 100644
--- a/tests/ice40/latches.ys
+++ b/tests/ice40/latches.ys
@@ -1,14 +1,11 @@
 read_verilog latches.v
-design -save read
 
 proc
-async2sync # converts latches to a 'sync' variant clocked by a 'super'-clock
 flatten
-synth_ice40
-equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+# Can't run any sort of equivalence check because latches are blown to LUTs
+#equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
 
-design -load read
+#design -load preopt
 synth_ice40
 cd top
 select -assert-count 4 t:SB_LUT4