From: lkcl <lkcl@web>
Date: Fri, 6 May 2022 12:20:38 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2377
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bd67bdc509a10a1eb5691d5edbe1003620b19945;p=libreriscv.git

---

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index 75a532aa8..cd6215fa7 100644
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -536,8 +536,15 @@ and apply deterministic nested loop schedules to more than just registers
 
 OpenCAPI is a deterministic high-performance, high-bandwidth, low-latency
 cache-coherent Memory-access Protocol that is integrated into IBM's Supercomputing-class POWER9 and POWER10 processors. POWER10 *only*
-has OpenCAPI interfaces, and requires an OpenCAPI-to-DDR4/5 Bridge PHY
+has OpenCAPI Memory interfaces, and requires an OpenCAPI-to-DDR4/5 Bridge PHY
 to connect to standard DIMMs.
 
+Extra-V appears to be a remarkable research project that, by leveraging
+OpenCAPI, assuming that the map of edges in any given arbitrary data graph
+could be kept by the main CPU in-memory, could distribute and delegate
+a limited-capability deterministic node-walking schedule actually right down into the memory itself (on the other side of that L1-4 cache barrier),
+where, thanks to the OpenCAPI Standard, many of the nightmare problems
+of other more explicit parallel processing paradigms disappear.
+
 **Snitch**