From: lkcl <lkcl@web>
Date: Mon, 10 Apr 2023 08:53:43 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls012_v1~42
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bd69450ff610c2d8131e68e2236d66831ba3fd18;p=libreriscv.git

---

diff --git a/openpower/sv/rfc/ls012.mdwn b/openpower/sv/rfc/ls012.mdwn
index 57461df9c..9ee2012f2 100644
--- a/openpower/sv/rfc/ls012.mdwn
+++ b/openpower/sv/rfc/ls012.mdwn
@@ -240,8 +240,9 @@ as just one example.
 These LUT2/3 operations are high cost high reward. Outlined in
 [[sv/bitmanip]], the simplest ones already exist in PackedSIMD VSX:
 `xxeval`.  The same reasoning applies as to fclass: SFFS needs to be
-stand-alone on its own merits and not "punished" should an implementor
-choose not to implement any aspect of PackedSIMD VSX.
+stand-alone on its own merits and should an implementor
+choose not to implement any aspect of PackedSIMD VSX the performance
+of their product should not be penalised for making that decision.
 
 With Predication being such a high priority in GPUs and HPC, CR Field
 variants of Ternary and Binary LUT instructions were considered high