From: Luke Kenneth Casson Leighton Date: Mon, 6 Apr 2020 16:42:47 +0000 (+0000) Subject: experimenting with positions X-Git-Tag: partial-core-ls180-gdsii~143 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bd6b78003c0cc6579fbad73593e69f2714f3a770;p=soclayout.git experimenting with positions --- diff --git a/experiments7/doAlu16.py b/experiments7/doAlu16.py index 15fbd26..aa9dbda 100755 --- a/experiments7/doAlu16.py +++ b/experiments7/doAlu16.py @@ -25,7 +25,7 @@ def coriolis_setup(): cfg.misc_verboseLevel1 = True cfg.misc_verboseLevel2 = True cfg.etesian_effort = 2 - cfg.etesian_spaceMargin = "20.0%" + cfg.etesian_spaceMargin = "10.0%" cfg.etesian_aspectRatio = "100.0%" cfg.etesian_uniformDensity = True cfg.anabatic_edgeLenght = 24 @@ -94,15 +94,16 @@ class ALU16(Module): ])) + 2*v_margin # experiment, over-ride - width = 1300 + width = 1310 height = 370 self.ab = Box(0, 0, self.to_dbu(width), self.to_dbu(height)) add_wid = self.from_dbu(add.ab.getWidth()) sub_ht = self.from_dbu(sub.ab.getHeight()) - self.place_submodule(add, h_margin, v_margin+add_wid) - self.place_submodule(sub, width-sub.ab_width-h_margin+sub_ht-45, + + self.place_submodule(add, 25, v_margin+add_wid) + self.place_submodule(sub, width-sub.ab_width-h_margin+sub_ht-35, v_margin) # TODO: replace with some form of lazy evaluation? @@ -128,8 +129,8 @@ class ALU16(Module): self.to_dbu((width+self.ab_width)/2 + h_margin), self.to_dbu(height - v_margin) ) - self.ab = Box(self.to_dbu(450), self.to_dbu(15), - self.to_dbu(835), self.to_dbu(370)) + self.ab = Box(self.to_dbu(475), self.to_dbu(10), + self.to_dbu(840), self.to_dbu(360)) self.place() # place only # then route (globally) @@ -181,7 +182,7 @@ def ScriptMain(editor=None, **kwargs): alu16 = ALU16( 'alu16', editor, submodules=[add, sub], north_pins=[ - {'net': 'o({})', 'x': 500.0, 'delta': 10.0, 'repeat': BIT_WIDTH}, + {'net': 'o({})', 'x': 500.0, 'delta': 20.0, 'repeat': BIT_WIDTH}, {'net': 'op'}, ], south_pins=[