From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 27 Mar 2022 12:21:25 +0000 (+0100)
Subject: add link to Winbond HyperRAM model
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bd757fe5177e000680d16cd08f48d91072cfa22e;p=ls2.git

add link to Winbond HyperRAM model
---

diff --git a/hyperram_model/README.txt b/hyperram_model/README.txt
index f2cf555..0718cbc 100644
--- a/hyperram_model/README.txt
+++ b/hyperram_model/README.txt
@@ -1,12 +1,18 @@
 1) download the Cypress HyperRAM Model
    http://www.cypress.com/verilog/s27kl0641-verilog
-2) install icarus verilog
-3) run ./runhyperramsim.sh
+2) download the Winbond HyperRAM Model
+   https://www.winbond.com/resource-files/W956x8MBY_verilog_p.zip
+3) install icarus verilog
+4) run ./runhyperramsim.sh
 
 Cypress HyperRAM Model files are
 Copyright (C) 2015 Spansion, LLC.
 (no explicit license found, but they are available publicly for download)
 
+Winbond HyperRAM Model files are
+Copyright C 2019 Winbond Electronics Corp. All rights reserved.
+(no explicit license found, but they are available publicly for download)
+
 hbc_*.v files from https://github.com/gtjennings1/HyperBUS are
 Copyright 2017 Gnarly Grey LLC and have been released under this
 license by Gnarly Grey: