From: Michael Nolan <mtnolan2640@gmail.com>
Date: Wed, 6 May 2020 18:23:20 +0000 (-0400)
Subject: Re-enable test_mtcrf
X-Git-Tag: div_pipeline~1364
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bd75cff581ce8e55dd819ef9d497261130df9e04;p=soc.git

Re-enable test_mtcrf
---

diff --git a/src/soc/decoder/isa/test_caller.py b/src/soc/decoder/isa/test_caller.py
index 5f029570..21364340 100644
--- a/src/soc/decoder/isa/test_caller.py
+++ b/src/soc/decoder/isa/test_caller.py
@@ -131,7 +131,6 @@ class DecoderTestCase(FHDLTestCase):
 
 
 
-    @unittest.skip("broken")  # FIXME
     def test_mtcrf(self):
         for i in range(4):
             # 0x7654 gives expected (3+4) (2+4) (1+4) (0+4) for i=3,2,1,0