From: Luke Kenneth Casson Leighton Date: Wed, 22 Jul 2020 19:18:30 +0000 (+0100) Subject: set additional MSR bits according to v3.0B spec when trap occurs X-Git-Tag: semi_working_ecp5~613 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bd75d340d2ac47f9d02a0cff6547838f13f77a2f;p=soc.git set additional MSR bits according to v3.0B spec when trap occurs --- diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py index 33aae8d3..9d3008ba 100644 --- a/src/soc/decoder/isa/caller.py +++ b/src/soc/decoder/isa/caller.py @@ -353,12 +353,22 @@ class ISACaller: # in figure 66 p1065 V3.0B and the table figure 65 p1063 set these # bits appropriately. however it turns out that *for now* in all # cases (all trap_addrs) the exact same thing is needed. - self.msr[MSRb.SF] = 1 - self.msr[MSRb.EE] = 0 - self.msr[MSRb.PR] = 0 self.msr[MSRb.IR] = 0 self.msr[MSRb.DR] = 0 + self.msr[MSRb.FE0] = 0 + self.msr[MSRb.FE1] = 0 + self.msr[MSRb.EE] = 0 self.msr[MSRb.RI] = 0 + self.msr[MSRb.SF] = 1 + self.msr[MSRb.TM] = 0 + self.msr[MSRb.VEC] = 0 + self.msr[MSRb.VSX] = 0 + self.msr[MSRb.PR] = 0 + self.msr[MSRb.FP] = 0 + self.msr[MSRb.PMM] = 0 + self.msr[MSRb.TEs] = 0 + self.msr[MSRb.TEe] = 0 + self.msr[MSRb.UND] = 0 self.msr[MSRb.LE] = 1 def memassign(self, ea, sz, val):