From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 22 Jul 2019 17:49:50 +0000 (+0100)
Subject: more random experimenting
X-Git-Tag: ls180-24jan2020~765
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bd7b46e1ac553b544ee278c0f95754f10be26da3;p=ieee754fpu.git

more random experimenting
---

diff --git a/src/ieee754/fpdiv/div0.py b/src/ieee754/fpdiv/div0.py
index 7b1d24f4..1174d01b 100644
--- a/src/ieee754/fpdiv/div0.py
+++ b/src/ieee754/fpdiv/div0.py
@@ -65,15 +65,15 @@ class FPDivStage0Mod(Elaboratable):
             am0 = Signal(len(self.i.a.m)+3, reset_less=True)
             bm0 = Signal(len(self.i.b.m)+3, reset_less=True)
             m.d.comb += [
-                         am0.eq(Cat(0, 0, self.i.a.m, 0)),
-                         bm0.eq(Cat(0, 0, self.i.b.m, 0)),
+                         am0.eq(Cat(0,0,0,self.i.a.m, 0)),
+                         bm0.eq(Cat(0,0,0,self.i.b.m, 0)),
                          #am0.eq(0x392),
                          #bm0.eq(0x1110),
                         ]
 
             m.d.comb += [self.o.z.e.eq(self.i.a.e - self.i.b.e + 1),
                          self.o.z.s.eq(self.i.a.s ^ self.i.b.s),
-                         self.o.dividend[len(self.i.a.m):].eq(am0), # TODO: check
+                         self.o.dividend[len(self.i.a.m)+3:].eq(am0), # TODO: check
                          self.o.divisor_radicand.eq(bm0), # TODO: check
                          self.o.operation.eq(Const(0)) # TODO check: DIV
                 ]
diff --git a/src/ieee754/fpdiv/div2.py b/src/ieee754/fpdiv/div2.py
index ddc6f905..0261528b 100644
--- a/src/ieee754/fpdiv/div2.py
+++ b/src/ieee754/fpdiv/div2.py
@@ -63,15 +63,15 @@ class FPDivStage2Mod(FPState, Elaboratable):
         with m.If(~self.i.out_do_z):
             mw = self.o.z.m_width
             # TODO: compensate for answer being in range 0.49999 to 1.99998
-            pl = len(self.i.quotient_root) + len(self.i.remainder)
+            pl = len(self.i.quotient_root) + 1
             pt = Signal(pl, reset_less=True)
-            m.d.comb += pt.eq(Cat(self.i.remainder, self.i.quotient_root))
+            m.d.comb += pt.eq(Cat(0, self.i.quotient_root))
             p = Signal(pl-1, reset_less=True) # drop top bit
             with m.If(self.i.quotient_root[-1]):
-                m.d.comb += p.eq(pt)
+                m.d.comb += p.eq(pt[1:])
             with m.Else():
                 # get 1 bit of extra accuracy if the mantissa top bit is zero
-                m.d.comb += p.eq(pt << 1)
+                m.d.comb += p.eq(pt)
                 m.d.comb += self.o.z.e.eq(self.i.z.e-1)
 
             # TODO: use p here instead of quotient_root, direct.
@@ -82,7 +82,7 @@ class FPDivStage2Mod(FPState, Elaboratable):
                 self.o.of.m0.eq(p[-mw]), # copy of LSB
                 self.o.of.guard.eq(p[-mw-1]),
                 self.o.of.round_bit.eq(p[-mw-2]),
-                self.o.of.sticky.eq(p[:-mw-2].bool())
+                self.o.of.sticky.eq(p[:-mw-2].bool() | self.i.remainder.bool())
             ]
 
         m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
diff --git a/src/ieee754/fpdiv/pipeline.py b/src/ieee754/fpdiv/pipeline.py
index b265bd18..119db0f5 100644
--- a/src/ieee754/fpdiv/pipeline.py
+++ b/src/ieee754/fpdiv/pipeline.py
@@ -159,10 +159,10 @@ class FPDIVMuxInOut(ReservationStations):
         fmt = FPFormat.standard(width)
         log2_radix = 2
 
-        # ...4 extra bits on the mantissa: MSB is zero, MSB-1 is 1
-        # then there is guard and round at the LSB end.
+        # ...5 extra bits on the mantissa: MSB is zero, MSB-1 is 1
+        # then there is guard, round and sticky at the LSB end.
         # also: round up to nearest radix
-        fmt.m_width = roundup(fmt.m_width + 4, log2_radix)
+        fmt.m_width = roundup(fmt.m_width + 5, log2_radix)
 
         cfg = DivPipeCoreConfig(fmt.m_width, fmt.fraction_width, log2_radix)