From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 30 Sep 2019 19:34:28 +0000 (-0700)
Subject: Use derived module
X-Git-Tag: working-ls180~881^2^2~199
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bd8356799aaee629b747984fd01d3ef4d1182a27;p=yosys.git

Use derived module
---

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 616aca074..6907ccecc 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -808,6 +808,11 @@ struct XAigerWriter
 			int box_count = 0;
 			for (auto cell : box_list) {
 				RTLIL::Module* box_module = module->design->module(cell->type);
+				if (box_module->get_bool_attribute("\\abc9_flop")) {
+					auto derived_name = box_module->derive(module->design, cell->parameters);
+					box_module = module->design->module(derived_name);
+				}
+
 				int box_inputs = 0, box_outputs = 0;
 				Cell *holes_cell = nullptr;
 				if (box_module->get_bool_attribute("\\whitebox")) {
@@ -858,28 +863,6 @@ struct XAigerWriter
 					}
 				}
 
-				if (box_module->get_bool_attribute("\\abc9_flop")) {
-					log_assert(holes_cell);
-					IdString port_name = "\\$currQ";
-					Wire* w = box_module->wire(port_name);
-					SigSpec rhs = cell->getPort(port_name);
-					log_assert(GetSize(w) == GetSize(rhs));
-					SigSpec port_wire;
-					Wire *holes_wire;
-					for (int i = 0; i < GetSize(w); i++) {
-						box_inputs++;
-						holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
-						if (!holes_wire) {
-							holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
-							holes_wire->port_input = true;
-							holes_wire->port_id = port_id++;
-							holes_module->ports.push_back(holes_wire->name);
-						}
-						port_wire.append(holes_wire);
-					}
-					holes_cell->setPort(w->name, port_wire);
-				}
-
 				write_h_buffer(box_inputs);
 				write_h_buffer(box_outputs);
 				write_h_buffer(box_module->attributes.at("\\abc_box_id").as_int());