From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 13 Dec 2021 12:55:03 +0000 (+0000)
Subject: add msr to MMU Op Subset record
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bdaeccaeec3b376e6750c608ab8040596641a0a1;p=soc.git

add msr to MMU Op Subset record
---

diff --git a/src/soc/fu/mmu/mmu_input_record.py b/src/soc/fu/mmu/mmu_input_record.py
index 079c2e9f..54256ca5 100644
--- a/src/soc/fu/mmu/mmu_input_record.py
+++ b/src/soc/fu/mmu/mmu_input_record.py
@@ -14,6 +14,7 @@ class CompMMUOpSubset(CompOpSubsetBase):
                   ('fn_unit', Function),
                   ('insn', 32),
                   ('nia', 64), # for instruction fault (MMU PTE lookup)
+                  ('msr', 64), # ditto, to set priv_mode etc.
                   ('zero_a', 1),
                   )
         super().__init__(layout, name=name)