From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Thu, 13 Feb 2014 21:45:27 +0000 (+0100)
Subject: dvisampler: replace parity with sof
X-Git-Tag: 24jan2021_ls180~2743
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bdb47e7977fb018d458b90960e299fd2998edba1;p=litex.git

dvisampler: replace parity with sof
---

diff --git a/misoclib/dvisampler/analysis.py b/misoclib/dvisampler/analysis.py
index 7005afbd..05d26880 100644
--- a/misoclib/dvisampler/analysis.py
+++ b/misoclib/dvisampler/analysis.py
@@ -116,7 +116,7 @@ class FrameExtraction(Module, AutoCSR):
 		self.b = Signal(8)
 
 		# in sys clock domain
-		word_layout = [("parity", 1), ("pixels", word_width)]
+		word_layout = [("sof", 1), ("pixels", word_width)]
 		self.frame = Source(word_layout)
 		self.busy = Signal()
 
@@ -159,11 +159,12 @@ class FrameExtraction(Module, AutoCSR):
 			fifo.din.pixels.eq(cur_word),
 			fifo.we.eq(cur_word_valid)
 		]
-		new_frame_r = Signal()
-		self.sync.pix += [
-			If(new_frame_r, fifo.din.parity.eq(~fifo.din.parity)),
-			new_frame_r.eq(new_frame)
-		]
+		self.sync.pix += \
+			If(new_frame,
+				fifo.din.sof.eq(1)
+			).Elif(cur_word_valid,
+				fifo.din.sof.eq(0)
+			)
 		self.comb += [
 			self.frame.stb.eq(fifo.readable),
 			self.frame.payload.eq(fifo.dout),
@@ -196,10 +197,9 @@ class FrameExtraction(Module, AutoCSR):
 			self._r_overflow.w.eq(sys_overflow & ~overflow_mask),
 			self.overflow_reset.i.eq(self._r_overflow.re)
 		]
-		self.sync += [
+		self.sync += \
 			If(self._r_overflow.re,
 				overflow_mask.eq(1)
 			).Elif(self.overflow_reset_ack.o,
 				overflow_mask.eq(0)
 			)
-		]
diff --git a/misoclib/dvisampler/dma.py b/misoclib/dvisampler/dma.py
index 412b718f..114a5397 100644
--- a/misoclib/dvisampler/dma.py
+++ b/misoclib/dvisampler/dma.py
@@ -64,19 +64,13 @@ class DMA(Module):
 		alignment_bits = bits_for(bus_dw//8) - 1
 
 		fifo_word_width = 24*bus_dw//32
-		self.frame = Sink([("parity", 1), ("pixels", fifo_word_width)])
+		self.frame = Sink([("sof", 1), ("pixels", fifo_word_width)])
 		self._r_frame_size = CSRStorage(bus_aw + alignment_bits, alignment_bits=alignment_bits)
 		self.submodules._slot_array = _SlotArray(nslots, bus_aw, alignment_bits)
 		self.ev = self._slot_array.ev
 
 		###
 
-		# start of frame detection
-		sof = Signal()
-		parity_r = Signal()
-		self.sync += If(self.frame.stb & self.frame.ack, parity_r.eq(self.frame.payload.parity))
-		self.comb += sof.eq(parity_r ^ self.frame.payload.parity)
-
 		# address generator + maximum memory word count to prevent DMA buffer overrun
 		reset_words = Signal()
 		count_word = Signal()
@@ -122,8 +116,8 @@ class DMA(Module):
 
 		fsm.act("WAIT_SOF",
 			reset_words.eq(1),
-			self.frame.ack.eq(~self._slot_array.address_valid | ~sof),
-			If(self._slot_array.address_valid & sof & self.frame.stb, NextState("TRANSFER_PIXELS"))
+			self.frame.ack.eq(~self._slot_array.address_valid | ~self.frame.payload.sof),
+			If(self._slot_array.address_valid & self.frame.payload.sof & self.frame.stb, NextState("TRANSFER_PIXELS"))
 		)
 		fsm.act("TRANSFER_PIXELS",
 			self.frame.ack.eq(self._bus_accessor.address_data.ack),