From: Michael Nolan <mtnolan2640@gmail.com>
Date: Mon, 10 Feb 2020 16:27:42 +0000 (-0500)
Subject: Fix line length
X-Git-Tag: ls180-24jan2020~201
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bdb8390f014463ab5c534841fb17839547a7a83c;p=ieee754fpu.git

Fix line length
---

diff --git a/src/ieee754/part/test/test_partsig.py b/src/ieee754/part/test/test_partsig.py
index b209aec1..699a34f9 100644
--- a/src/ieee754/part/test/test_partsig.py
+++ b/src/ieee754/part/test/test_partsig.py
@@ -149,7 +149,8 @@ class TestPartitionPoints(unittest.TestCase):
                         c_outval = (yield getattr(module,
                                                   "%s_carry_out" % mod_attr))
                         msg = f"{msg_prefix}: 0x{a:X} + 0x{b:X}" + \
-                            f" => 0x{carry_result:X} != 0x{c_outval:X} ({mod_attr})"
+                            f" => 0x{carry_result:X} != 0x{c_outval:X}" + \
+                            " ({mod_attr})"
                         self.assertEqual(carry_result, c_outval, msg)
 
             for (test_fn, mod_attr) in ((test_add_fn, "add"),